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Digital IC Terminology

Current and voltage parameters


Fan-Out
Propagation delays
Power requirements
Noise immunity
Invalid voltage levels
Current-sourcing and current-sinking action
IC Packages
Common IC packages (Courtesy of Texas Instruments)
Voltage Parameters:

§ VIH(min): high-level input voltage

§ VIL(max): low-level input voltage

§ VOH(min): high-level output voltage

§ VOL(max): low-level output voltage


Current Parameters
• IIH(min): high-level input current, the current that flows into an

input when a specified high-level voltage is applied to that input.

• IIL(max): low-level input current

• IOH(min): high-level output current

• IOL(max): low-level output current


Power Requirements
Every IC needs a certain amount of electrical power to operate.
Ø

Vcc (TTL)
Ø

VDD(MOS)
Ø

Power dissipation determined by Icc and Vcc.


Ø

Average Icc(avg)= (ICCH + ICCL)/2


Ø

PD(avg) = Icc(avg) x Vcc


Ø

Power Dissipation :-

Power dissipation is the amount of heat (in milliwatts) that the IC


dissipates in the form of heat.
ICCH and ICCL

ICCL – current from supply when all outputs are low


ICCH – current from supply when all outputs are high
Propagation delays

Measured between 50% points on inputs and outputs


DC noise margins

Noise margins – amount of “noise” a signal can tolerate going from an outp
an input.
Currents and voltages in the two
logic states

O – output
I – input
H – high
L - low
Comparison of current-sourcing
and current-sinking actions
Logic Families
• RTL : Resistor transistor logic

• DTL : Diode transistor Logic

• TTL: Transistor-transistor logic

• ECL: Emitter-coupled logic.

• IIL : Integrated injection logic.

• MOS ICs: Metal-oxide-semiconductor ICs.


Diode Logic (DL)

In Diode logic, all the logic is implemented with the use of resistors and diodes

The purpose of the diodes is to perform OR and AND operations.


• Diodes can also be used as a logical switch

oThe disadvantage of Diodes is that they tend to degrade the signals quickly.

oDiodes also cannot work for multiple stages, only one stage at a time.

oThe diodes also cannot perform the NOT operation which limits their functionality.
Resistor-Transistor Logic (RTL)
üIn resistor-transistor logic, all the logic is implemented with the use of transistors
and resistors
üResistor-Transistor gates are not very expensive and are very simple to
construct.
ü RTL gates can be used as amplifiers as well to amplify small signals.

ü The drawback in using RTL gates is that they draw a great amount of current
from the power supply.

üThey are used in slower applications, but cannot be used in today's computers as
they cannot switch at high speeds.
1. If any input is high the corresponding transistor is driven into
saturation
2. This causes output as low
3. If all input are low at 0.2v all transistors are cutoff because
Diode Transistor Logic (DTL)
ØIn Diode-transistor logic, all the logic is implemented with the use of diodes
and transistors.

ØDTL has some advantages over DL and RTL. As the diodes can perform AND
and OR operations but along with a transistor the output signal can be amplified

ØThe switching speed of the transistor is limited due to the input resistor to
transistor.

DTL was used in early vacuum tube computers.


Ø
Y=(A.B.C)’

If all the inputs are high the transistor is driven into saturation
region
The voltage at Y equal to VBE plus the two diode drops across D4
& D5.
8-2 The Transistor-Transistor-Logic
(TTL) Logic Family
The NAND gate is a basic TTL circuit.
8-2 The TTL Logic Family
TTL circuits have a similar structure
The input will be the cathode of a PN junction
A HIGH input will turn off the junction and only a leakage
current is generated in Q1 (Q2 and Q4 turn on).
A LOW input turns on the junction and a relatively large current
is generated through Q1 (Q2 and Q4 turn off).
Most TTL circuits have some type of totem-pole output
configuration
TTL
NAND
gate in its
two output
states
TTL NAND gate with output low
TTL NAND gate with output high
Flow of Current in TTL Output State

Figure 8-9 (a) When the TTL output is in the LOW state, Q4 acts as a current sink, deriving its current from the load. (b) In the output
HIGH state, Q3 acts as a current source, providing current to the load gate.
TTL NOR gate circuit
Q2 and Q4
added to
TTL
inverter

is high only when A and B are low.


case both Q1 and Q2 are on, Q3 and Q4 are off, and Q6 if off.
wise, if A or B is high, Q6 is on and output is low.
TTL NOR gate circuit
Q2 and Q4
added to
TTL
inverter

hen A is high, Q3 and Q6 is on, and output is low


hen B is high, Q4 and Q6 is on, and output is low
TTL NOR gate circuit
Q2 and Q4
added to
TTL
inverter

ut is high only when A and B are low.


s case both Q1 and Q2 are on, Q3 and Q4 are off, and Q6 is off.
8-3 TTL Data Sheets
First line of TTL ICs was the 54/74 series
54 series operates over a wider temperature range
Same numbering system, prefix indicates manufacturer
SN – Texas Instruments
DM – National Semiconductor
S – Signetics
DM7402, SN7402, S7402 all perform the same function
Data sheets contain electrical characteristics, switching
characteristics, and recommended operating conditions.
Emitter Coupled Logic (ECL)
This logic is used in applications with high speed environment.
v

ECL is considered to be one of the best because there is a very low propagation
v

delay.

The logic levels for ECL are normally -0.9V for high logic and -1.6 for low logic.
v

The design of ECL consists of termination resistors which allows the signals to
v

propagate with very low reflection.


Data sheet
for the
74ALS00
NAND gate
IC(Courtesy of Texas Instruments)
8-4 TTL Series Characteristics
Standard 74 series TTL has evolved into other series:
Standard TTL, 74 series
Schottky TTL, 74S series
Low power Schottky TTL, 74LS series (LS-TTL)
Advanced Schottky TTL, 74AS series (AS-TTL)
Advanced low power Schottky TTL, 74ALS series
74F fast TTL
Refer to Table 8-6 for a comparison between the series
characteristics
Ronald Tocci/Neal Widmer/Gregory
Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved..
Schottky-clamped Transistor
(a) Schottky-clamped transistor;
(b) basic NAND gate in S-TTL
series
(c) Schottky diode has a smaller
junction voltage than the
transistor
(d) currently will be shunted from
the transistor when it goes into
reverse bias preventing the
transistor from going into
saturation
(e) fewer carriers will be present in
the transistor and it will switch
faster.
8-5 TTL Loading and Fan Out
Fan out refers to the load drive capability of an IC
output
A TTL output has a limit on how much current it can sink in the
LOW state
A TTL output has a limit on how much current it can source in
the HIGH state.
Exceeding these currents will result in output voltage levels
outside specified ranges

Ronald Tocci/Neal Widmer/Gregory


Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved..
8-5 TTL Loading and Fan Out
Determining fan out
Add the IIH for all inputs connected to an output. The sum must
be less than the output IOH specification.
Add the IIL for all inputs connected to an output. The sum must
be less than the output IOL specification.

Ronald Tocci/Neal Widmer/Gregory


Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved..
Currents when a TTL output is
driving several inputs
8-6 Other TTL Characteristics

Unconnected (floating) inputs


Unused inputs
Tied together inputs
Biasing TTL inputs low
Current transients

Ronald Tocci/Neal Widmer/Gregory


Moss Copyright ©2007 by Pearson Education, Inc.
Digital Systems: Principles and Columbus, OH 43235
Applications, 10e All rights reserved..
Three ways to handle unused logic
inputs
Determining TTL Loads

Determine the load that gate 1 is driving, the 74LS devices have IIH = 20uA, and IIL
= 0.4mA.

Leakage
• •Gates 2 and 3 have
currents. one input transistor.
Each input •Gate 4 uses a
Calculating fan-out

Max fan-out of LS to standard TTL (low) = IOL(max) / IIL(max) = 8mA / |-1.6mA| = 5



(max fan-out low).
•Max fan-out of LS to standard TTL (high) = IOH(max) / IIH(max) = |-.4mA| / 40uA = 10(max fan-out high)

•Maximum fan-out is limited by lowest fan-out, 5 in this case.

•Maximum sink (implies low output) current = fan-out x IL = 5 x -1.6 mA = -8.0mA.


Max fan-out when low = IOL(max) / IIL(max)

= 8mA/|-.4mA| = 20 (max fan-out low for 74AS devices.
•Max fan-out when high = IOH(max) / IIH(max) =

|-0.4mA| / 20uA = 20 (max fan-out high for 74AS devices.


•Maximum fan-out is limited by lowest fan-out.
Driving Different Families

ermine max currents that can be supplied and sunk


ermine current needed

• Max sink current for LS device in low state, fan-out x IIL = 20 x -0.4mA =
-8mA.

Max supply current for LS device in high state, , fan-out x IOH = 20 x -0.4mA = -8mA.

Magnitude of current needed by load should be less than magnitude of max sink or source current.

Figure 8-56 Problems 8-11 and 8-13.

Calculating Propagation Delay Time


TTL Characteristic When Switching
from LOW to HIGH

• When a totem pole TTL output goes from LOW to HIGH, a


high amplitude current spike is drawn from the VCC supply
(because Q4 and Q3 are both on for a short time).
8-7 MOS Technology

Metal Oxide Semiconductor Field Effect


Transistors (MOSFETs)
Simple and cheap to fabricate
Consume very little power
More circuit elements are possible
Susceptible to static electricity damage
8-7 MOS Technology

Schematic symbols for P and N channel


enhancement MOSFETs.
8-7 MOS Technology: N-channel
MOSFET

N-channel
MOSFET used as a
switch: (a) symbol;
(b) circuit model;
(c) N-MOS inverter
operation.
P-channel MOSFET

P-channel
MOSFET used as
a switch: (a)
symbol; (b)
circuit model for
OFF and ON; (c)
P-MOS inverter
circuit.
8-8 Complementary MOS Logic
The CMOS family uses both P and N channel
MOSFETs
Faster
Consumes less power
More complex fabrication
CMOS Inverter (Figure 8-22)
CMOS NAND gate (Figure 8-23)
CMOS NOR gate (Figure 8-24)
CMOS INVERTER
CMOS NAND gate
CMOS NOR gate
8-9 CMOS Series Characteristics

CMOS devices compete directly with TTL


Pin compatible
Functionally equivalent
Electrically compatible
4000/1400 series
74C series
74HC/HCT (high-speed CMOS)
74AC/ACT (advanced CMOS)
74AHC/AHCT (advanced high-speed CMOS)
BiCMOS 5-volt logic
Fan out
Switching speed
Unused inputs
Loads Act Like Capacitors

Figure 8-26 Each CMOS input adds


to the total load capacitance seen by the
driving gate’s output.
Current spikes when switching (charging a capacitive load)

Figure 8-25 Current spikes are drawn from the VDD supply each time the output switches from LOW to HIGH. This is due mainly to the
charging current of the load capacitance.
8-10 Low Voltage Technology
CMOS family:
74LVC (low voltage CMOS)
74ALVC (advanced low voltage CMOS)
74LV (low voltage)
74AVC (advanced very low voltage CMOS)
74AUC (advanced ultra-low voltage CMOS)
74AUP (advanced ultra-low power)
74CBT (cross bar technology)
74CBTLV (cross bar technology low voltage)
74GTLP (gunning transceiver logic plus)
74SSTV (stub series terminated logic)
74TVC (translation voltage clamp)
8-10 Low Voltage Technology

BiCMOS family:
74LVT (low voltage BiCMOS technology)
74ALVT (advanced low voltage BiCMOS
technology)
74ALB (advanced low voltage BiCMOS)
74VME (VERSA Module Eurocard)
Voltage-level comparison
8-11 Open Collector/Open Drain Outputs

Conventional CMOS outputs and TTL totem pole


outputs should never be connected to the same point.
Open-collector/open-drain outputs
Open-collector/open-drain buffer/drivers
IEEE/ANSI symbols for open collector/drain outputs
Open collector gates – no
internal load

Figure 8-30 (a) Open-


collector TTL circuit; (b)
with external pull-up
resistor.
Cannot Connect Outputs of Typical
Gates Together

Figure 8-29 Totem-pole outputs tied together can


produce harmful current through Q4.
Open-collector gates are useful for
driving high-current loads
Figure 8-32 An open-
collector buffer/driver drives a
high-current, high-voltage load.
Can connect open-collector to form
an AND gate

Figure 8-31 Wired-AND


operation using open-collector gates.
8-12 Tristate (Three-State) Logic
Outputs
Three states are possible: HIGH, LOW, and high
impedance.
Advantages of tristate devices
Tristate buffers
Tristate ICs
IEEE/ANSI symbol for tristate outputs
Hi-Z state is an open circuit

Figure 8-35 Three output conditions of tristate.


Tri-state operation

Figure 8-37 (a) Tristate buffers used


to connect several signals to a common
bus; (b) conditions for transmitting B to
the bus.
Problem 8-31. Bidirectional transceiver
8-15 CMOS Transmission Gate
(Bilateral Switch)
Acts as a single pole, single throw switch
Controlled by an input logic level
Passes signals in both directions
Signals applied to the input can be analog or digital
Input must be between 0 and VDD volts.
CMOS bilateral switch
(transmission gate)

Both devices
on or both off
Figure 8-45 Example 8-12: 74HC4016 bilateral switches used to switch an analog signal to two different outputs.
Problem 8-37. Determine the waveform at X assuming Ron = 200Ω
Problem 8-14
Figure 8-57 Problem 8-14. The master reset is active-high and is activated by a push-button switch. Resistor R is used to hold MR LOW
while the switch is open. (a) What is the maximum value that can be used for R? (b) Repeat if using a 74ALS193

Make this voltage < VIL(max) to remain a logic 0


b. 8.16 Will each clock waveform below reliably trigger a 74LS112 flip

(a) No. The amplitude is less than VIL.


(b) No. Tp of 10ns is less than tw(H) = 20ns minimum (from data sheet)
(c) tw(L) not given. However, fmax (from data sheet) is given as 30MHz. Therefore, Tmin =
1/fmax = 33.3ns.

tw(L)min = Tmin - tw(H)min or 33.3ns – 20ns = 13.3ns.


tw(L) (actual) is less than tw(L)min, so the answer is no.
. 8.19 Which of the following are advantages that CMOS generally h
?

(a) Greater packing density, yes – MOS devices are


smaller
(b) Higher speed, no
(c) Greater fan-out, yes – inputs to gates are capacitors
(d) Lower output impedance, no – MOS rout~1000ohms
(e) Simpler fabrication structure, yes
(f) More suited to VLSI, yes – greater packing density
(g) Lower PD (below 1Mhz), yes, - MOS essentially an
open circuit when off
(h) Transistors as only circuit element, yes
(i) Lower input capacitance, no – input structure is a
capacitor
. 8.20 Which of the following operating conditions will probably result
st average PD for a CMOS logic system?
(a) VDD = 5V, switching frequency = 1MHz
(b) VDD = 5V, switching frequency = 10kHz
(c) VDD = 10V, switching frequency = 10kHz

Power drain generally increases with, an increase in VDD and frequency; therefore, (b) is
probably has the lowest average PD.

P = VI, increase in V, increase in P

I = V/R, increase in f, decrease in R (of capacitive load), increase in I (current spike)


Prob. 8.22 Calculate the Noise Margins when a
74HC gate drives a standard 74LS input.

Noise margins: VNL = VIL – VOL, VNH = VOH – VIH

VNL = VIL(LS) – VOL(HC) = 0.8V – 0.1V = 0.7V


VNH = VOH(HC) – VIH(LS) = 4.9V – 2.0V = 2.9V
Prob. 8.23 What will cause latch-up in a CMOS
IC?

Latch-up can be triggered by high-voltage spikes or ringing at


the device inputs and outputs. When latch-up occurs, a larger
current flows and may damage the device. Clamping diodes
can be used externally, or a regulated power supply.

CMOS cross-section
Prob. 8.27 Determine the logic expression for
output X.

Output of wired-AND is (AB)’


(CD)’ (EF)’

X = ((AB)’ (CD)’ (EF)’)’


Prob. 8.28 Which of the following would be most
likely to destroy a TTL while it is switching from
HIGH to LOW?.
(a) Tying the output to 5V

(b) Tying the output to ground

(c) Applying an input of 7V

(d) Tying the output to another TTL output


Prob. 8.29 (a) What will be the voltage of the
7406 output when Q = 0?
(b) Find Rs if Vf = 2.4V at If = 20mA for the
diode.

(a) 5V since the 7406 has an open collector and Q4 is


off.

(a) Voltage across Rs = 5V – Vf – VOL = 5 – 2.4 – 0.4 =


2.2V.
NMOS Circuits

Outputs obtained
by using the inputs
to either “pull-up”
the network to
VDD, or “pull-
down”
E. John, S. Yamashita, D. Markovic, andto ground.
Y. Kado, CMOS Circuits, in Digital Design and
Fabrication, Ed. V. G. Oklobdzija , CRC Press 2008, eBook ISBN: 978-0-8493-8604-6.
ass Transistor/Transmission Gate Lo

Inputs as well as VDD and ground are steered to the


output.

• Simple and fast.

• Complex functions can be implemented with a


ass Transistor/Transmission Gate Lo

Simple pass transistor only passes one logic level


well.

•Using NMOS and PMOS in parallel allows both logic


levels to pass well.

• CMOS transmission gate operates as a bi-directional


ass Transistor/Transmission Gate Lo

• Can be used to realize logic gates and functions.

For a XOR gate, when both A and B are low, the top

TG in on and bottom is off; output is A (0). Similarly


for other conditions.
Sequential CMOS Logic Circuits

uential circuits depend on current and previous values of the

put is stored as a state variable.

uit consists of combinational logic and memory.


Sequential CMOS Logic Circuits

When CLK = 0, output remains the same due to


feedback loop.

When CLK = 1, Q = D, and the data is accepted


continually.

Operates as a latch when CLK = 1; positive-level


sensing.

Positive-level sensing D-latch using


transmission gates and inverters
Sequential CMOS Logic Circuits

Positive and negative sensing latches


can be
combined to form an edge-triggered
flip-flop.

•When CLK = 0, the latches are


isolated from
each other. The positive latch
(rightmost latch) holds the previous
value and the negative latch follows
the input.
Positive edge-triggered D flip-flo
When CLK transitions to 1, the

negative latch holds the value of D at


Sequential CMOS Logic Circuits

MOS implementation of the positive-edge triggered D flip-flop (18 transisto


Dynamic Logic Circuits

Use the capacitive input of the MOSFET to store a charge


and remember the value for later use.

• Output decays with time unless it is periodically refreshed.

•Dynamic logic gates are used to decrease complexity,


increase speed, and lower power dissipation.

Basic design eliminates one of the switch networks from the


CMOS logic circuits (almost 50% reduction).


Dynamic Logic Circuits

Dynamic logic circuits have two-phase


operation, a precharge and evaluation


phase.

•When CLK = 0, PMOS is on and


NMOS is off and the load capacitance
is charged to VDD.

No conducting path between between


VDD and ground for this precharge


phase eliminates a static current.

Evaluation phase starts when CLK = 1.


The PMOS is off and NMOS is on.


Dynamic Logic Circuits

When CLK = 0, PMOS is on and NMOS is off and the load


capacitance is charged to VDD.

When CLK = 1, (a) discharges when AB = 1, (b) discharges when


A + B = 1, and (c) discharges when ABC + D = 1.


Low-Voltage Design

Four sources of power dissipation in CMOS VLSI design


Silicon on Insulator

Suited for low-parasitic capacitance, and operation on low supply


voltage.

• Copper line and low-permittivity layer between wiring layers..


Silicon on Insulator

Improved SOI MOS transistor


MOS transistor SOI MOS transistor
•A MOSFET is formed on a thin SOI layer over a buried oxide (BOX)
layer.

• The entire MOSFET is enclosed in a silicon oxide layer.

• The process technology is similar to conventional CMOS technology.

• Low capacitance near source/drain leads to high-speed operation.


Silicon on Insulator

In a conventional device, the drain junction capacitance consists


of a capacitance between the drain and the substrate.

In SOI structures, the capacitance between drain and substrate


consists of a series capacitance. The BOX capacitance has a


dielectric constant 1/3 smaller than Si.
Silicon on Insulator

The threshold voltage of the MOSFET is a function of the source-


substrate voltage – body effect.

In SOI structures (unlike the conventional case), the body is


floating so there is no body effect.


BiCMOS
CMOS is limited by speed

ECL is 2 to 5 times faster than CMOS but ECL has high power
consumption which makes VLSI difficult

BiCMOS combines the high-density integration of MOS logic with


the current-driving capabilities of bipolar transistors
BiCMOS Inverter

Similar to a CMOS gate


with a current amplifier as


an output stage

When input is HIGH, M1 is


on causing Q1 to conduct,
while M2 and Q2 are off.
The results is a LOW output.

When input is LOW, M2 is


on causing Q2 to conduct,
while M1 and Q1 are off.
The results is a HIGH
output.
BiCMOS Inverter
•When input is HIGH
(output is LOW), current in
M2 is multiplied by β in Q2
resulting in more current at
the output and faster
operation than CMOS.

Similar to CMOS but better


capacitance-driving
capabilities.

Has substantial speed


advantage over CMOS gates


when driving large
BiCMOS
• Similar to CMOS but better capacitance-driving capabilities.

CMOS is better for driving small loads because of the added


complexity of BiCMOS. BiCMOS is better for driving large


capacitive loads such as gate arrays and memories.

•The use of BiCMOS in ICs like ALUs is not likely because of


the complexity of BiCMOS.

• Built-in voltages like VBE(on) do not scale, which limits the range of supply voltages
that can be used.

• The non-scalability of built-in voltages is one of the most important deficiencies of bipolar technology.

• BiCMOS probably not used with supply voltages under 3V.


8-14 The ECL Digital IC Family
o Emitter coupled logic – increased switching speed.
o Basic ECL circuit
o ECL OR/NOR gate
o ECL characteristics
n Very fast switching, typical propagation delay is 360 ps
n -0.8 V logic 1, -1.7 V logic 0
n Noise margins approximately 150 mV
n Output complement is produced, eliminating need for inverters
n Typical fan out is 25
n Typical power dissipation is 25 mW
n Current flow remains constant, eliminating noise spikes
ECL Circuitry

ECL Inverter

Current switches from one


side to the other

S, Muroga, Emitter-Coupled Logic, in Logic Design


Ed. W.-K., Chen , CRC Press 2003, eBook ISBN: 978-0-203-
01015-0, DOI: 10.1201/9780203010150.ch13

Figure 8-41 (a) Basic ECL circuit;


(b) with addition of Current amplifiers
emitter followers.
Emitter-Coupled Logic (ECL)

F = (X + Y + Z)’ F=X+Y+Z

• .The basis of the gate is a differential amplifier.


Current flows to -4V through the transistor with the base grounded or one of the input transistors.

Current is amplified by emitter-follower amplifiers.


The basic gate is the NOR/OR gate.


50Ω resistors only used for protecting transistors from large current, and can often be eliminated

Emitter-Coupled Logic (ECL)

•.When a high voltage is applied to an


input X, Y, or Z, it turns on the
corresponding transistor. Currently
flows through it making its collector
have a low voltage, and therefore one
output of the gate low. Current will
not flow through Tr and its collector
will be high, as well as its
corresponding output.

•When all input voltages are low, the


corresponding transistors are off and
the corresponding output is high.
Current flows through Tr and its
Emitter-Coupled Logic (ECL)

When the emitter circuits are connected together they may form

a wired-OR circuit; also called emitter-dotting.

If both transistors T1 and T2 are off, the output is low;


otherwise, the output is high.


Emitter-Coupled Logic (ECL)

• An OR gate can be eliminated simply by connecting two outputs.

Once an output has been connected to another emitter, it does not


retain its original logic function.


Emitter-Coupled Logic (ECL)

If an emitter follower circuit is repeated, then the corresponding


outputs can be connected independently.


Emitter-Coupled Logic (ECL)

Design of a logic network with ECL

Procedure:
•Design a network for given logic function and its complement using NOR gates

without considering fan-in or fan-out restrictions. Use a minimum number of NOR


gates.

Reduce the number of input connections to each gate by providing Wired-Ors, or by


using OR-outputs of other gates.

Repeat for the OR network and choose the “best” one.



Emitter-Coupled Logic (ECL)

The use of OR outputs and wired-Ors generally reduces the


number of connections or fan-ins (input transistors), and
connections lengths, thus saving chip area.

OR network NOR network


Emitter-Coupled Logic (ECL)

Series gating

(a) x’ at collector when x is at base


(b) consider two transistors: one with x and one with y at base
(c) series gating results in OR function: x’ + y’ = (xy)’
Emitter-Coupled Logic (ECL)

Series
gating

create a structure where the complement of minterms are available at collec


Emitter-Coupled Logic (ECL)

Logic functions in ECL can often be made with fewer transistors


than CMOS

Full-adder using series gating, and wired-OR connections in ECL