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at Behavioral Level
Lecture outline
1. review the architecture, chip layout, pin definition
2. instruction set
3. 8085 Verilog models
4. 8085 Verilog test bench.
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S0, S1 (Output) READY (Input)
Data Bus Status. Encoded status of the bus cycle: If Ready is high during a read or write cycle, it indicates that the memory
or peripheral is ready to send or receive data.
S1 S0 If Ready is low, the CPU will wait for Ready to go high before
0 0 HALT completing the read or write cycle.
0 1 WRITE
1 0 READ
1 1 FETCH HOLD (Input)
RD (Output 3state) HOLD; indicates that another Master is requesting the use of the Address
and Data Buses. The CPU, upon receiving the Hold request. will relinquish
READ; indicates the selected memory or I/O device is to be read the use of buses as soon as the completion of the current machine cycle.
and that the Data Bus is available for the data transfer. Internal processing can continue. The processor can regain the buses only
3stated during Hold and Halt. after the Hold is removed.
When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines
WR (Output 3state) are 3stated.
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HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request Trap interrupt is a nonmaskable restart interrupt.
and that it will relinquish thebuses in the next clock cycle. It is recognized at the same time as INTR.
HLDA goes low after the Hold request is removed. It is unaffected by any mask or Interrupt Enable.
The CPU takes the buses one half clock cycle after HLDA goes low. It has the highest priority of any interrupt.
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IO/M (Output) module s85; // simulation testbench module
IO/M indicates whether the Read/Write is to memory or l/O reg [8:1] dflags;
Tristated during Hold and Halt modes. initial dflags = 0;
// diag flags:
// 1 = printmem
RESET OUT (Output)
// 2 = dump state at end
// 3 = test reset control
Indicates CPU is being reset. Can be used as a system RESET.
// 4 = monitor the transmit and receive lines
The signal is synchronized to the processor clock.
wire s0, ale, rxd, txd, clock;
X1, X2 (Input)
tri[7:0] ad, a;
Crystal or R/C network connections to set the internal clock generator tri1 read, write, iomout;
X1 can also be an external clock input instead of a crystal.
The input frequency is divided by 2 to give the internal operating frequency. reg trap, rst7p5, rst6p5, rst5p5,
intr, ready, nreset, hold, pclock;
CLK (Output)
module intel_8085a
//instantiate the clock (clock, x2, resetff, sodff, sid, trap,
osc timebase(clock); rst7p5, rst6p5, rst5p5, intr, intaff,
ad, a, s0, aleff, writeout, readout, s1,
//instantiate the RAM module iomout, ready, nreset,
ram85a r0(ale, ad, a, write, read, iomout); clockff, hldaff, hold);
initial output
begin resetff, sodff, intaff, s0, aleff,
$write("\n"); writeout, readout, s1, iomout, clockff, hldaff;
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reg[15:0]
pc, // program counter intaff, // interrupt acknowledge
sp, // stack pointer trapff, // trap interrupt request
addr; // address output trapi, // trap execution for RIM instruction (RIM:read interrupt mask)
inte, // previous state of interrupt enable flag
reg[8:0] int, // interrupt acknowledge in progress
intmask; // interrupt mask and status validint, // interrupt pending
haltff, // halt request
reg[7:0] resetff, // reset output
acc, // accumulator clockff, // clock output
regb, // general sodff, // serial output data
regc, // general read, // read request signal
regd, // general write, // write request signal
rege, // general iomff, // i/o memory select
regh, // general acontrol, // address output control
regl, // general dcontrol, // data output control
ir, // instruction s, // data source control
data; // data output cs, // sign condition code
reg cz, // zero condition code
aleff, // address latch enable cac, // aux carry condition code
s0ff, // status line 0 cp, // parity condition code
s1ff, // status line 1 cc; // carry condition code
hldaff, // hold acknowledge
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holdff, // internal hold
4
LDA addr //load accumulator direct
(A) Å ((byte 3) (byte 2)) MOV M, r //store r in memory
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/* increment register and memory contents */
/* move register and memory immediate */ task inr;
task movi; case(ir[5:3])
begin 0: doinc(regb); // INR B
case(ir[5:3]) 1: doinc(regc); // INR C
0: memread(regb, pc); // MVI B, -- 2: doinc(regd); // INR D
1: memread(regc, pc); // MVI C, -- 3: doinc(rege); // INR E
2: memread(regd, pc); // MVI D, -- 4: doinc(regh); // INR H
3: memread(rege, pc); // MVI E, -- 5: doinc(regl); // INR L
4: memread(regh, pc); // MVI H, -- 6: // INR M
5: memread(regl, pc); // MVI L, -- begin
6: // MVI M, -- ; ((H)(L)) <-- (byte 2) memread(data, {regh, regl});
begin doinc(data);
memread(data, pc); memwrite(data, {regh, regl});
memwrite(data, {regh, regl}); end
end
7: doinc(acc); // INR A
7: memread(acc, pc); // MVI A endcase
endcase endtask
pc = pc + 1;
end
endtask
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6: // STA
begin
adread(ra); /* memory read */ @(posedge clock)
memwrite(acc, ra); task memread; dcontrol = 0;
end output[7:0] rdata; if(int)
7: // LDA input[15:0] raddr; intaff = 0;
begin begin else
adread(ra); @(posedge clock) read = 0;
memread(acc, ra); addr = raddr; @(posedge clock)
end s = 0; ready_hold;
endcase acontrol = 1; checkint;
endtask dcontrol = 1;
iomff = int; @(posedge clock)
/* fetch address from pc+1, pc+2 */
s0ff = int; intaff = 1;
task adread;
s1ff = 1; read = 1;
output[15:0] address;
aleff = 1; rdata = ad;
begin
@(posedge clock) if(holdff) holdit;
memread(address[7:0], pc);
aleff = 0; end
pc = pc + 1;
endtask
memread(address[15:8], pc);
if(!int) pc = pc + 1; // if interrupt is not true, pc = pc+1
end
endtask 25 26
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7
RLC rotate accumulator left
(CY) ÅA7; A0 ÅA7; An+1 Å An SBI data subtract immediate with borrow
5: // XRA XRI
2: // SUB SUI
/* operate on accumulator */ begin
begin
task doacci; acc = acc ^ sr;
{cac, null4} = acc - sr;
input[7:0] sr; cac = 0;
{cc, acc} = {1'b0, acc} - sr;
reg[3:0] null4; cc = 0;
calpsz(acc);
reg[7:0] null8; calpsz(acc);
end
case(ir[5:3]) end
0: // ADD ADI
3: // SBB SBI
begin 6: // ORA ORI
begin
{cac, null4} = acc + sr; begin
{cac, null4} = acc - sr - cc;
{cc, acc} = {1'b0, acc} + sr; acc = acc | sr;
{cc, acc} = {1'b0, acc} - sr - cc;
calpsz(acc); cac = 0;
calpsz(acc);
end cc = 0;
end
calpsz(acc);
1: // ADC ACI end
4: // ANA ANI
begin
begin
{cac, null4} = acc + sr + cc; 7: // CMP CPI
acc = acc & sr;
{cc, acc} = {1'b0, acc} + sr + cc; begin
cac = 1;
calpsz(acc); {cac, null4} = acc - sr;
cc = 0;
end {cc, null8} = {1'b0, acc} - sr;
calpsz(acc);
calpsz(null8);
end
end
endcase
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endtask
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/* rotate acc and special instructions */ 3: // RAR
task racc_spec; {acc, cc} = {cc, acc};
case(ir[5:3])
0: // RLC 4: // DAA, decimal adjust
begin begin
acc = {acc[6:0], acc[7]}; if((acc[3:0] > 9) || cac) acc = acc + 6;
cc = acc[7]; if((acc[7:4] > 9) || cc) {cc, acc} = {1'b0, acc} + 'h60;
end end
1: // RRC 5: // CMA
begin acc = ~acc;
acc = {acc[0], acc[7:1]};
cc = acc[0]; 6: // STC
end cc = 1;
2: // RAL 7: // CMC
{cc, acc} = {acc, cc}; cc = ~cc;
endcase
endtask
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