TITLE

 Topic:

You need to measure because…

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 (Humorous)
Topic: Lessons Learned from Test
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Speaker: Charles Hymowitz
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Image
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Topic:
 By Charles Hymowitz, Steve Sandler
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Picotest
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AEi Systems
 Test is sending a wake up call
 Are you listening?

 What will you learn?

o How Test Supports the Design Process

o Pessimistic Thought Process

o Test Saves Time/Money

o Some Humorous Stories

Optimize  Measure-Model-Simulate-Measure PDN Interrogation in a USB Stick

SPEAKER
Charles Hymowitz
VP Sales & Marketing, Picotest
charles@picotest.com | www.picotest.com | @CEHymowitz
LinkedIn Group: Power Integrity for Distributed Systems

Charles is a technologist, marketer, and business executive with

over 30 years of experience in the EE services and EDA software
markets. Charles is the VP of Sales & Marketing for Picotest.com,
Modeling service provider and manufacturer of test equipment for power
supply and power integrity applications. Charles has also been
Simulation Chairman and CEO of AEi Systems, LLC a company specializing in
WCCA Worst Case Circuit Analysis. In 1985, Charles co-founded Intusoft,
a leading SPICE EDA software developer.
Test
Test’s Relationship to Design
Tired of hearing there isn’t
enough time?
 Reference Designs – Are They Really? I am more tired of hearing “we
need to rev the board”
 Model Validation – Hey, someone’s got to do it
 Model Development – A Necessary Evil?
 Design Centering – Can we please decide
“What is Nominal?”
 Datasheet Confirmation – So you didn’t
know these were “marketing” brochures?
Bad or Inadequate Reference Designs
And you thought you could
 Many reference designs are use just it as it. Modifications
are often necessary
limited in their applicability
 OOPS!?! – Part has no external
 Weak points are left unstated compensation

 Applicability to your specs is

not always obvious
 Documentation?
Bad or Inadequate Reference Designs - Regulator
Prepare to mod the EVM
 “Reference” Design
 Needed Board Mods
o Some manufacturers seem
allergic to good test
connects/50 ohms
 Testing Revealed
 Oscillated out of the box
 “Oh, it likes low ESR caps!”
 Bad or Inadequate Reference Designs - VRM
Be prepared to develop your own
 Model Needed for PDN Analysis test boards and get the test data you
need for your application
Output Impedance, V OUT = 1.0V, ILOAD = 4A
10.00

-10.00
Zout, dBΩ

-30.00 10 0

10 -1
-50.00

TR1
10 -2
-70.00 10 -3
1.00E+02 1.00E+03 1.00E+04 1.00E+05 1.00E+06 1.00E+07
10 -4
frequency, Hz
10 -5
102 103 104 105 106 107
Magnitude f/Hz
TR1: |Mag(Gain)| OFF : |Mag(Gain)|

Well the Bode Plots look ok

NO LOAD : |Mag(Gain)| 100mA : |Mag(Gain)|
200mA no Cin : |Mag(Gain)| 200mA Cin : |Mag(Gain)|
Model Validation
0.15Ω @ 100MHz
Confirm
 Many models are bad Vendor
Curves!
 Many models are awful
 Models don’t have all characteristics
 Models don’t have tolerances
0.32Ω @ 100MHz
 Models don’t have documentation

 How do you know what you have without test?

Model Validation

 Lessons Learned from our WCCA Class

 Model Fidelity And Accuracy Is In Your Hands
 Test All The Models You Use
 Correlate The Performance
 Everything must be modeled appropriately!

 It’s VERY easy to get into trouble and not know it!
Model Validation – A Regulator

 Requested vendor data for correlation

 Bode Plot didn’t look right – Over-driven
 Gap in the data
 Correlation revealed problem below 1A
Bode Plot 0dB Bandwidth
 Test data didn’t match vs. Attenuation vs. Load Resistor
(3.3 Vout, 100 ohm Injection Resistor)
Load Resistor
 Model needed to be fixed Bench Sims
Atten 15 ohms 100 ohms 330 ohms
IOUT Phase Gain Phase Gain
(A) Margin Margin Margin Margin -20dB 6 kHz 969 Hz 355 Hz
0.1 101 -24.4 71.17155 28.64675 -40dB 70 kHz 9.3 kHz 3.28 kHz
That doesn’t match at all! 1.0 67.5831 -16.5258 69.74625 18.77656 -60dB 99 kHz 44.6 kHz 20.03 kHz
2.0 68.7299 -15.5546 65.472 15.89438 -67dB 100 kHz 46.8 kHz 21.49 kHz
Model Validation – a Bead Vendor model (blue)
vs measurement (red)

 Bead Model
 Low frequency match was poor - what does
that mean?

Vendor model (blue)

vs measurement (red)
Model Validation
 DOUBLE DIPPING
 Our capacitor test vs. vendor model -
showed how the model was wrong
with the mounting included where it
should not have been
Mount included
(Used with SPICE Simulator) C
 The mount has to be removed for
A
printed circuit board simulation P
because the EM simulator will
M
automatically account for it
Mount removed
O
U
 If we include it in the model or the N
Used with PCB EM model T
measurement it will be included
twice!
Model Validation “I said I make the parts. I didn’t say I
know how to test them”
Wait. What?
220uF Aluminum Polymer

1 mΩ - 225 Ω > 105 dB

Impedance, Ohms
1-port reflection

2-port shunt thru

1 Ω - 2 kΩ > 66 dB
Model Development - Capacitors
 Distributed decoupling capacitors reduce the high
frequency inductance of the power planes,
minimizing the voltage noise
 The high fidelity model shown here requires half as
many decoupling capacitors as the RLC model!

R-L-C Model

Measured
Model Development - VRMs
Measured values for L, Ri and f
 PDN Analysis DCM model MOSFET
requires a good VRM
model
 The data isn’t in the Measured L values
datasheet; You must
test
 Output impedance,
Parameters and FITTED
PSRR and Gain LM25116 ramp equation
 GFS is Fundamental to Stability and Current Limit
8.00
7.00 y = 8.7258x - 15.402
R² = 0.9995
6.00 LM25116 EVAL
LOAD CURRENT

5.00
4.00
Slope=PGfs
3.00
2.00
1.00
NOTE THAT THIS IS SIGNIFICANTLY The measured value of Ri is 12% higher
DIFFERENT THAN THE DATASHEET!
than expected due to DC PCB resistance
0.00
despite the very short connections
1.700 1.900 2.100 2.300 2.500 2.700
VCOMP

“Oh, you noticed that too”

Design Centering- What is Nominal?
Many VRMs have
resonant input or
output planes,
especially when
multiple ceramic
capacitors are used

Where did all the

noise come from?
 Design Centering- What is Nominal?
 PDN Test data - Doing all via software? We did it all in software.
No time for test..
 Many unknown: Board, Package, Die
models, Dynamic currents, Tolerances

https://www.cst.com/Content/Events/Downloads/euc2015/7-2-2-Edoardo-Genovese.pdf
Design Centering- What is Nominal?
 There are a myriad of key parameters
Sim
BW = 17.6k Hz , PM = 88.0 degrees
Measurement

without nominal values (ESR in BW = 17.8k Hz, PM = 86.4 degrees

capacitors)

 Stability is one of the most important

Measurement
x = 279k , GM = 22.3 dB
3
parameters Sim
x = 311k , GM = 23.6 dB 2

Sim SM = 52.6 degrees

 But the nominal is often unknown
1

Measurement SM = 53.2 degrees

10
12
4
 Even when the bode plot looks great you 100 1k
1
10k
Frequency
100k 1Meg 10Meg

can have poor stability

Simulation 42.9 degrees
Measurement 50.9 degrees

100m

 Step loading can be challenging 10m

Impedance doesn’t lie
1m
Datasheet Confirmation and Filling in Holes
Clock Jitter - Missing Power Supply Data
 What is not apparent, and is often not
included in the datasheet, is the sensitivity
to power supply noise
 The bright trace shows the result of
including noise from the power supply
 This noise also highlights an internal power
rail resonance at approximately 2MHz
 Noise in this range can greatly degrade the
clock jitter performance
 This sensitivity would not be seen from Phase noise of a
the datasheet
precision reference clock
Why does the power supply matter?
Lessons Learned

 At the end of the day, you need to make

GOOD measurements AND interpret
them correctly

 Papers & Application Notes

https://www.picotest.com/blog/
 charles@picotest.com
Thank you!
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QUESTIONS?