James Bond Email: bond.007@gmail.

com

ACADEMIC DETAILS

Motilal Nehru National Institute of Technology, Allahabad-India Current CPI-8.77

B.Tech in Electronics and Communication Engineering (2012-Present)
DAV Public School, Delhi- India Percentage-94.60%
All India Senior School Certificate Examination (2012)
Kerala Model School, Delhi- India Percentage- 90.40%
Indian Certificate for Secondary School Examination (2010)

TECHNICAL SKILLS AND INTERESTS

 Areas of Interest: Digital Design, Data Structures, Computer Architecture

 Languages used: Verilog HDL, C
 IDEs used: Xilinx ISE, NetBeans, MATLAB
 Relevant Courses: Data Structures, Digital Electronics, Computer Architecture

PROJECTS

1.Design of reconfigurable architecture for adaptive modulation schemes for mobile communication
MNNIT, Allahabad July 2016-Present

 Design and Implementation of Adaptive Modulator system using Verilog HDL on Spartan 3e FPGA kit. Analysis carried out on
MATLAB.
 Implemented CORDIC algorithm to generate sine and cosine functions on Verilog HDL.
 Exposure: Digital Design, Analog Design, Communication Systems, Verilog HDL.

2.Implementation of convolution operation using Verilog HDL

MNNIT, Allahabad August 2014-December 2014

 The design was made to evaluate the convolution of 2 sequences of fixed length by evaluating the convolution as the
intermediate step.
 PS2 keyboard and VGA monitor were interfaced as input and output devices.
 Radix 2 FFT algorithm was implemented.
 Exposure: Digital Design, Signal Processing, Hardware interfacing with FPGA, Verilog HDL.

3.Implementation of 32 bit FPR ALU using Verilog HDL

IIT(BHU), Varanasi January 2015-February 2015

 32-bit pipelined floating point unit was designed using Verilog HDL and simulated on ISim simulator.
 IEEE 734 standard was implemented for floating point addition, multiplication and subtraction.
 Instructions were queued in stored in reverse polish notation for cascaded operat ion.
 Exposure: Digital Design, Verilog HDL, Computer Architecture, Data Structures.

ACHIEVEMENT

 Received Merit Scholarship for being in the top 10% in Electronics and Communication Engineering Department, MNNIT in 2013-14
and 2014-15 session.
 Runner up at FPGA Design event at IIT(BHU) in 2015.
 Winner at FPGA Design event at MNNIT, Allahabad in 2014.
 Best Speaker at debate organized by Indian Institute of Metals, Jamshedpur Chapter. Gave a talk on “Efficient metal extraction
methodologies” at the Annual General Meeting of IIM at Kolkata in 2011.

HOBBIES
 Debating  Public Speaking

PERSONAL DETAILS
 Date of Birth- 1st March, 1994  Contact Number-+91- 9000000000