James Bond Email:bond.007@gmail.

com

ACADEMIC DETAILS

Motilal Nehru National Institute of Technology, Allahabad,India July 2012-Present

B.Tech in Electronics and Communication Engineering (Current CPI 8.77)
DAV Public School , Delhi- India 2012
All India Senior School Certificate Examination (Percentage:94.60%)
Kerala Model School, Delhi- India 2010
Indian Certificate for Secondary School Examination (Percentage: 90.40%)

TECHNICAL SKILLS AND INTERESTS

 Areas Of Interests: Digital Design, Data Structures, Computer Architecture

 Languages/HDL used: Verilog HDL, C
 IDEs used: Xilinx ISE, NetBeans, MatLab
 Relevant Courses: Data Structures, Digital Electronics, Computer Architecture

PROJECTS

1.Design of reconfigurable architecture for adaptive modulation schemes for mobile communication
MNNIT, Allahabad,India July 2016-Present

 Design and Implementation of Adaptive Modulator system using Verilog HDL on Spartan 3e FPGA kit. Analysis
carried out on MatLab.
 Implemented CORDIC algorithm to generate sine and cosine functions on Verilog HDL.
 Exposure: Digital Design, Analog Design, Communication Systems, Verilog HDL

2.Implementation of convolution operation using Verilog HDL

MNNIT, Allahabad,India August 2014-December 2014

 The design was made to evaluate the convolution of 2 sequences of fixed length by evaluating the convolution
as the intermediate step.
 PS2 keyboard and VGA monitor were interfaced as input and output devices.
 Radix 2 FFT algorithm was implemented.
 Exposure: Digital Design, Signal Processing, Hardware interfacing with FPGA, Verilog HDL

3.Implementation of 32 bit FPR ALU using Verilog HDL

IIT(BHU), Varanasi,India January 2015-February 2015

 32 bit floating point unit was designed using Verilog HDL and simulated on ISim simulator.
 IEEE 734 standard was implemented for floating point addition, multiplication and subtraction.
 3 stage pipelined system was developed.
 Instructions were queued in stored in reverse polish notation for cascaded operat ion.
 Exposure: Digital Design, Verilog HDL, Computer Architecture, Data Structures

ACHEIVEMENTS

 Received Merit Scholarship for being in the top 10% in ECED,MNNIT in 2013-14 and 2014-15 session.
 Runner up at FPGA Design event at IIT(BHU) in 2015.
 Winner at FPGA Deign even at MNNIT,Allahabad in 2014.
 Best Speaker at debate organized by Indian Institute of Metals, Jamshedpur Chapter. Was invited to give a talk at their
AGM held in Kolkata.

PERSONAL DETAILS

 Nationality-Indian  Date of Birth- 1st March 1994

 Gender- Male  Contact Number-+91-9000000000