Microprocessor and Microcontroller

MICROPROCESSOR AND MICROCONTROLLER

Unit 1:
1.1 RISC and CISC Architectures
RISC and CISC are the two different types of processor
architectures. RISC stands for Reduced Instruction Set Computer and
CISC stands for Complex Instruction Set Computer.
 RISC processors use single clock to execute an instruction whereas, CISC
processors use multiple clocks for execution.
 Memory-to-memory access is used for data manipulations is RISC processors.
In CISC processors, intermediate registers are used for data manipulation.
 In RISC processors, single word instructions are given as inputs. In CISC
processors, instructions of variable lengths are given as input, based upon the
task to be performed.
 As the instruction set is reduced in RISC processors, compilers can be simple.
Compliers need to be complex as the instruction set is complex.
 Both RISC and CISC processor find their applications in different computing
machines.
 Almost all the flagship mobile available in the mobile market today are
embedding RISC processors.
 Apple was the first company to implement RISC processors for mobile
computations.

The following is the tabulated comparison between the RISC and CISC processor.
Aspect RISC CISC

Acronym Reduced Instruction Set Computer Complex Instruction Set Computer

Instruction set Reduced Complex

Compiler design Easy to design Hard to design

Hardware/Software Stresses more on software Stresses more on hardware

Memory management Memory-to-memory operations Register-to-register operations

Code size High in code size Less in code size

Clocking Single clock is used Multiple clocks are used

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Instruction length Single word instruction Variable length instruction

Pipelining Pipelining is the major feature Doesn’t support pipelining

1.2 Harvard and Von Neumann Memory Architectures

There are basically two types of digital computer architectures. The first one is called Von Neumann
architecture and later Harvard architecture was adopted for designing digital computers.

Harvard architecture has separate data and instruction busses, allowing transfers
to be performed simultaneously on both busses. Von Neumann architecture has
only one bus which is used for both data transfers and instruction fetches, and
therefore data transfers and instruction fetches must be scheduled - they cannot be
performed at the same time.

Von Neumann Architecture (Princeton Architecture):

 It is named after the mathematician and early computer scientist John Von Neumann.
 The computer has single storage system (memory) for storing data as well as program to be
executed.
 Processor needs two clock cycles to complete an instruction. Pipelining the instructions is not
possible with this architecture.
 In the first clock cycle the processor gets the instruction from memory and decodes it. In the next
clock cycle the required data is taken from memory. For each instruction this cycle repeats and hence
needs two cycles to complete an instruction.
 This is a relatively older architecture and was replaced by Harvard architecture.

Harvard Architecture:

 The name is originated from "Harvard Mark I" a relay based old computer.

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 The computer has two separate memories for storing data and program.
 Processor can complete an instruction in one cycle if appropriate pipelining strategies
are implemented.
 In the first stage of pipeline the instruction to be executed can be taken from program
memory. In the second stage of pipeline data is taken from the data memory using the decoded
instruction or address.
 Most of the modern computing architectures are based on Harvard architecture. But the
number of stages in the pipeline varies from system to system.

1.3 History of Microprocessors

A microprocessor is a computer processor that incorporates the functions of a computer's central
processing unit (CPU) on a single integrated circuit (IC), or at most a few integrated circuits. The
microprocessor is a multipurpose, programmable device that accepts digital data as input, processes
it according to instructions stored in its memory, and provides results as output. It is an example of
sequential digital logic, as it has internal memory. Microprocessors operate on numbers and symbols
represented in the binary numeral system.

The integration of a whole CPU onto a single chip or on a few chips greatly reduced the cost of
processing power. The integrated circuit processor was produced in large numbers by highly
automated processes, so unit cost was low. Single-chip processors increase reliability as there are
many fewer electrical connections to fail. As microprocessor designs get faster, the cost of
manufacturing a chip (with smaller components built on a semiconductor chip the same size)
generally stays the same.

Before microprocessors, small computers had been implemented using racks of circuit boards with
many medium- and small-scale integrated circuits. Microprocessors integrated this into one or a
few large-scale ICs. Continued increases in microprocessor capacity have since rendered other
forms of computers almost completely obsolete, with one or more microprocessors used in
everything from the smallest embedded systems and handheld devices to the
largest mainframes and supercomputers.

As integrated circuit technology advanced, it was feasible to manufacture more and more complex
processors on a single chip. The size of data objects became larger; allowing more transistors on a
chip allowed word sizes to increase from 4- and 8-bit words up to today's64-bit words. Additional
features were added to the processor architecture; more on-chip registers sped up programs, and
complex instructions could be used to make more compact programs. Floating-point arithmetic, for
example, was often not available on 8-bit microprocessors, but had to be carried out in software.

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Integration of the floating point unit first as a separate integrated circuit and then as part of the same
microprocessor chip, sped up floating point calculations.

History of few Microprocessors : 8085 :

4004 : Introduced in 1976.
Introduced in 1971. It was also 8-bit µP.
It was the first microprocessor by Intel. Its clock speed was 3 MHz.
It was a 4-bit µP. Its data bus is 8-bit and address bus is 16-
bit.
Its clock speed was 740KHz.
It had 6,500 transistors.
It had 2,300 transistors.
Could execute 7,69,230 instructions per
It could execute around 60,000 instructions
second.
per second.
4040 : Almost similar to 4004 , introduced It could access 64 KB of memory.
in 1974. It had 246 instructions.
8008: Over 100 million copies were sold.
Introduced in 1972. 8086 :
It was first 8-bit µP. Introduced in 1978.
Its clock speed was 500 KHz. It was first 16-bit µP.
Could execute 50,000 instructions per Its clock speed is 4.77 MHz, 8 MHz and 10
second. MHz, depending on the version.
8080: Its data bus is 16-bit and address bus is 20-
bit.
Introduced in 1974.
It had 29,000 transistors.
It was also 8-bit µP.
Could execute 2.5 million instructions per
Its clock speed was 2 MHz.
second.
It had 6,000 transistors.
It could access 1 MB of memory.
Was 10 times faster than 8008.
It had 22,000 instructions.
Could execute 5,00,000 instructions per
It had Multiply and Divide instructions.
second

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To know about other processors refer :

http://www.eazynotes.com/notes/microprocessor/slides/history-of-microprocessors.pdf

1.4 - 8086 Microprocessor

Features of 8086 Microprocessor

1) 8086 has 16-bit ALU; this means 16-bit numbers are directly processed by 8086.
2) It has 16-bit data bus, so it can read data or write data to memory or I/O ports either 16
bits or 8 bits at a time.
3) It has 20 address lines, so it can address up to 220 i.e. 1048576 = 1Mbytes of memory
(words i.e. 16 bit numbers are stored in consecutive memory locations). Due to the
1Mbytes memory size multiprogramming is made feasible as well as several
multiprogramming features have been incorporated in 8086 design.
4) 8086 includes few features, which enhance multiprocessing capability (it can be used
with math coprocessors like 8087, I/O processor 8089 etc.
5) Operates on +5v supply and single phase (single line) clock frequency.(Clock is generated
by separate peripheral chip 8284).

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6) 8086 comes with different versions. 8086 runs at 5 MHz, 8086-2 runs at 8 MHz, 8086-1
runs at 10 MHz.
7) It comes in 40-pin configuration having around 29,000 transistors in its circuitry.
8) It has multiplexed address and data bus like 8085 due to which the pin count is reduced
considerably
9) Higher Throughput (Speed). This is achieved by a concept called pipelining.
1.4.1 Architecture of 8086
The 8086 ("eighty eighty-six") is a 16-bit microprocessor chip designed by Intel between early 1976
and mid-1978. The architecture is shown below.

The 8086 CPU is divided into two independent functional units:

 Bus Interface Unit (BIU)
 Execution Unit (EU)

Bus Interface Unit (BIU)

The function of BIU is to:

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 Fetch the instruction or data from memory.

 Write the data to memory.
 Write the data to the port.
 Read data from the port.

Instruction Queue

1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead to
time from memory.
2. All six bytes are then held in first in first out 6 byte register called instruction queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution operation of EU,
which improves the speed execution of the instruction.

Execution Unit (EU)

The functions of execution unit are:

 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A decoder in EU
decodes the instruction fetched memory to generate different internal or external control
signals required to perform the operation. EU has 16-bit ALU, which can perform arithmetic and
logical operations on 8-bit as well as 16-bit.

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to
have AX, BX, CX, and DX.
1. AX Register: AX register is also known as accumulator register that stores operands for
arithmetic operation like divided, rotate.
2. BX Register: This register is mainly used as a base register. It holds the starting base location
of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop
counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Segment Registers

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Additional registers called segment registers generate memory address when combined with
other in the microprocessor. In 8086 microprocessor, memory is divided into 4 segments as
follow:
1. Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the
Data Segment by an offset address or the content of other register that holds the offset
address.
3. Stack Segment (SS): SS defined the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold
the destination data.

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in below fig :

Flags Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the type of
the result, and to determine conditions to transfer control to other parts of the program.
8086 has 9 flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags

Conditional Flags :
Conditional flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:

 Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic. It is
also used in multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit
to D4 is AF flag. This is not a general-purpose flag, it is used internally by the processor to
perform Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the
Parity Flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.

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 Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set.
 Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF indicates
that the result has exceeded the capacity of machine.

Control Flags :
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:

1. Trap Flag (TP):

 It is used for single step control.
 It allows user to execute one instruction of a program at a time for debugging.
 When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
 It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
3. Direction Flag (DF):
 It is used in string operation.
 If it is set, string bytes are accessed from higher memory address to lower
memory address.
 When it is reset, the string bytes are accessed from lower memory address to
higher memory address.

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Pin Description of 8086

AD0 - AD15 (I/O): Address Data Bus

These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1)
and data during T2, T3 and T4 clock cycles. A0 is analogous to BHE for the lower byte of the
data bus, pins D0-D7. A0 bit is Low during T1 state when a byte is to be transferred on the
lower portion of the bus in memory or I/O operations. 8-bit oriented devices tied to the lower
half would normally use A0 to condition chip select functions. These lines are active high and
float to tri-state during interrupt acknowledge and local bus "Hold acknowledge".

A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

During T1 state these lines are the four most significant address lines for memory operations.
During I/O operations these lines are low. During memory and I/O operations, status
information is available on these lines during T2, T3, and T4 states.S5: The status of the
interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is
indicated through this bus.

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S6:

When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock
period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of the
status bus.
S3 & S4:

Lines are decoded as follows:

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which
segment register generates the segment portion of the 8086 address. Thus by decoding these
lines and using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one
Mega per segment) of memory can be accesses. This feature also provides a degree of
protection by preventing write operations to one segment from erroneously overlapping into
another segment and destroying information in that segment.

BHE /S7 (O): Bus High Enable/Status

During T1 state the BHE should be used to enable data onto the most significant half of the data
bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally
use BHE to control chip select functions. BHE is Low during T1 state of read, write and interrupt
acknowledge cycles when a byte is to be transferred on the high portion of the bus.
The S7 status information is available during T2, T3 and T4 states. The signal is active Low and
floats to 3-state during "hold" state. This pin is Low during T1 state for the first interrupt
acknowledge cycle.

RD (O): READ

The Read strobe indicates that the processor is performing a memory or I/O read cycle. This
signal is active low during T2 and T3 states and the Two states of any read cycle. This signal
floats to tri-state in "hold acknowledge cycle".

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TEST

TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues.
Otherwise the processor waits in an "idle" state. This input is synchronized internally during
each clock cycle on the leading edge of CLK.

INTR : Interrupt Request

It is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt acknowledge operation. A subroutine
is vectored to via an interrupt vector look up table located in system memory. It can be
internally masked by software resetting the interrupt enable bit INTR is internally synchronized.
This signal is active HIGH.

NMI : Non-Muskable Interrupt

An edge triggered input, causes a type-2 interrupt. A subroutine is vectored to via the interrupt
vector look up table located in system memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current
instruction. This input is internally synchronized.

Reset

Reset causes the processor to immediately terminate its present activity. To be recognised, the
signal must be active high for at least four clock cycles, except after power-on which requires a
50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all zeros.
It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET pin, the 8086
will fetch its next instruction from the 20 bit physical address FFFF0H. The reset signal to 8086
can be generated by the 8284. (Clock generation chip). To guarantee reset from power-up, the
reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached the minimum
supply voltage of 4.5V.

Ready

Ready is the acknowledgement from the addressed memory or I/O device that it will complete
the data transfer. The READY signal from memory or I/O is synchronized by the 8284 clock
generator to form READY. This signal is active HIGH. The 8086 READY input is not synchronized.
Correct operation is not guaranteed if the setup and hold times are not met.

CLK : Clock

Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33%
duty cycle to provide optimized internal timing. Minimum frequency of 2 MHz is required, since

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the design of 8086 processors incorporates dynamic cells. The maximum clock frequencies of
the 8086-4, 8086 and 8086-2 are4MHz, 5MHz and 8MHz respectively.
Since the 8086 does not have on-chip clock generation circuitry, and 8284 clock generator chip
must be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency
3 times the 8086 internal frequency. The 8284 clock generation chip is used to generate READY,
RESET and CLK.

MN/MX (I): Maximum / Minimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded
to generate all the bus control signals.
Minimum Mode Pins The following 8 pins function descriptions are for the 8086 in minimum
mode; MN/ MX = 1. The corresponding 8 pins function descriptions for maximum mode is
explained later.

M/IO : Status line

This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it
accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a
bus cycle and remains valid until the final T4 of the cycle. M/IO floats to 3 - state OFF during
local bus "hold acknowledge".

WR : Write

Indicates that the processor is performing a write memory or write IO cycle, depending on the
state of the M /IOsignal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW, and
floats to 3-state OFF during local bus "hold acknowledge ".

INTA : Interrupt Acknowledge

It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and
T4 of each interrupt acknowledge cycle.

ALE : Address Latch Enable

ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an
active high pulse during T1 of any bus cycle. ALE signal is never floated.

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DT/ R : DATA Transmit/Receive

In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus
"hold acknowledge".

DEN : Data Enable

It is provided as an output enable for the 8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and IO access. It will be low beginning with
T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the
middle of T4. It floats to tri-state off during local bus "hold acknowledge".

HOLD & HLDA (I/O): Hold and Hold Acknowledge

Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged,
HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA (HIGH)
as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue of
HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as being
Low, the processor will lower the HLDA and when the processor needs to run another cycle, it
will again drive the local bus and control lines.
Maximum Mode The following pins function descriptions are for the 8086/8088 systems in
maximum mode (i.e.. MN/MX = 0). Only the pins which are unique to maximum mode are
described below.

S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during
T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all
memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used to
indicate the beginning of a bus cycle. These status lines are encoded as shown in table.
S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access1 0 1 Read memory

1 1 0 Write memory

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1 1 1 Passive State

QS0, QS1 (O): Queue – Status

Queue Status is valid during the clock cycle after which the queue operation is performed. QS0,
QS1 provide status to allow external tracking of the internal 8086 instruction queue. The
condition of queue status is shown in table.
Queue status allows external devices like In-circuit Emulators or special instruction set
extension co-processors to track the CPU instruction execution. Since instructions are executed
from the 8086 internal queue, the queue status is presented each CPU clock cycle and is not
related to the bus cycle activity. This mechanism allows (1) A processor to detect execution of a
ESCAPE instruction which directs the co- processor to perform a specific task and (2) An in-
circuit Emulator to trap execution of a specific memory location.
QS1 QS1 Characteristics

0 0 No operation

0 1 First byte of opcode from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

LOCK (O)

It indicates to another system bus master, not to gain control of the system bus while LOCK is
active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active
until the completion of the instruction. This signal is active Low and floats to tri-state OFF
during 'hold acknowledge'. Example:
LOCK XCHG reg., Memory ; Register is any register and memory GT0
; is the address of the semaphore.

RQ/GT0 and RQ/GT1 (I/O): Request/Grant

These pins are used by other processors in a multi processor organization. Local bus masters of
other processors force the processor to release the local bus at the end of the processors
current bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they
may be left un-connected.

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Assembler Directives
 DB: Define Byte: The DB directive is used to reserve byte or bytes of memory
locations in the available memory.
 DW: Define Word: The DW directive serves the same purposes as the DB
directive, but it makes the assembler reserves the number of memory words
(16bit) instead of bytes.
 DQ: Define Quadword: This directive is used to direct the assembler to
reserve 4 words (8bytes) of memory for the specified variable and may initialize it
with the specified values.
 DT: Define Ten Bytes: The DT directive directs the assembler to define the
specified variable requiring 10-bytes for its storage and initialize the 10-bytes
with the specified values.
 ASSUME: Assume Logical Segment Name: The ASSUME directive is used
to inform the assembler, the names of the logical segments to be assumed for
different segments used in the program.
 END: END Of Program: The END directive marks the end of an assembly
language program.
 ENDP: END Of Procedure: The ENDP directive is used to indicate the end of
a procedure.

PROCEDURE STAR
:

STAR ENDP //indicates the end of procedure STAR

 ENDS: END Of Segment: This directive marks the end of a logical

segment.

DATA SEGMENT

DATA ENDS //indicates the end of segment DATA

 EVEN: Align On Even Memory Address: The EVEN directive updates the
location counter to the next even address, if the current location counter contents
are not even, and assigns the following routine or variable or constant to that
address. If the content of the location counter is already even, then the procedure
will be assigned with the same address.

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 EQU: Equate: The directive EQU is used to assign a label with a value or
symbol. The use of this directive is just to reduce the recurrence of the numerical
values or constants in the program code.

constant EQU 0500H

 EXTERN: External and PUBLIC: Public: The directive EXTERN informs

the assembler that the names, procedures and labels declared after this directive
have already been defined in some other assembly language module.

 GROUP: Group the Related Segments: This directive is used to form logical
groups of segments with similar purpose or type.

PROGRAM GROUP CODE, DATA, STACK //this statement directs

the loader/linker to prepare an EXE file such that CODE, DATA, STACK segment must
lie within a 64byte memory segment that is named as PROGRAM

 LENGTH: Byte Length Of A Label: This directive is used to refer to the

length of a data array or a string. Not available in MASM.
 LOCAL: The label, variables, constants or procedures declared LOCAL in a
module are to be used only by that particular module.
 OFFSET: Offset Of A Label: When the assembler comes across the OFFSET
operator along with a label, it first computes the 16-bit displacement of the
particular label, and replaces the string ‘OFFSET LABEL’ by the computed
displacement.
 ORG: Origin: The ORG directive directs the assembler to start the memory
allotment for the particular segment, block or code from the declared address in
the ORG statement.
 PROC: Procedure: The PROC directive marks the start of a named procedure
in the statement. Also the types FAR and NEAR specifies the type of the
procedure.
 PTR: Pointer: The POINTER operator is used to declare the type of a label,
variable or memory operand. The operator PTR is prefixed by either BYTE (8-bit
quantity) orWORD (16-bit quantity).
 SEGMENT: Logical Segment: The SEGMENT directive marks the starting of
a logical segment. The started segment is also assigned a name, i.e. label, by this
statement.

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 SHORT: The SHORT operator indicates the assembler that only one byte is
required to code the displacement for a jump. This method of specifying jump
address saves memory.

 TYPE: The TYPE operator directs the assembler to decide the data type of the
specified label and replaces the TYPE label by the decided data type.
 GLOBAL: The labels, variables, constants or procedures
declared GLOBAL may be used by other modules of the program.

 FAR PTR: This directive indicates the assembler that the label
following FAR PTR is not available within the same segment and the address of
the bit is of 32 bits i.e. 2 bytes offset followed by 2 bytes.

 NEAR PTR: This directive indicates that the label following NEAR PTR is in
the same segment and need only 16 bit i.e. 2 byte offset to address it. A NEAR
PTR label is considered as default if a label is not preceded by NEAR PTR or FAR
PTR.

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Instruction Set
Students refer to
http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html

or

study the instructions that I have taught in the class.

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