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JEDEC STYLE TO-247
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SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
4-335 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRFP350
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
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IRFP350
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 16A, VGS = 0V (Figure 13) - - 1.6 V
Reverse Recovery Time trr TJ = 150oC, ISD = 15A, dISD/dt = 100A/µs 270 - 1300 ns
Reverse Recovered Charge QRR TJ = 150oC, ISD = 15A, dISD/dt = 100A/µs 1.7 - 8.1 µC
NOTES:
2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 40V, starting TJ = 25oC, L = 5.66mH, RG = 50Ω, peak IAS = 15A.
1.2 20
POWER DISSIPATION MULTIPLIER
1.0
16
ID , DRAIN CURRENT (A)
0.8
12
0.6
8
0.4
4
0.2
0 0
0 50 100 150 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
1
ZθJC, NORMALIZED TRANSIENT
0.5
THERMAL IMPEDANCE
0.2
0.1 0.1
0.05 PDM
0.02
0.01
t1
10-2 t2 t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC +TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10
t1 , RECTANGULAR PULSE DURATION (S)
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IRFP350
103 25
OPERATION IN THIS
REGION IS LIMITED VGS = 6.0V
BY rDS(ON) VGS = 10V
PULSE DURATION = 80µs
20
ID, DRAIN CURRENT (A)
10
10ms
VGS = 5.0V
1
5
TC = 25oC DC
VGS = 4.0V
TJ = MAX RATED VGS = 4.5V
SINGLE PULSE
0.1 0
1 10 102 103 0 40 80 120 160 200
VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)
25
PULSE DURATION = 80µs 102
VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VGS = 6.0V VDS = 2 x VGS
20
ID, DRAIN CURRENT (A)
10
15 VGS = 5.5V
TJ = 150oC TJ = 25oC
10
VGS = 5.0V 1
5
VGS = 4.0V
VGS = 4.5V
0 0.1
0 2 4 6 8 10 0 2 4 6 8 10
VDS , DRAIN TO SOURCE VOLTAGE (V) VSD , GATE TO SOURCE VOLTAGE (V)
0.75 2.5
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE
0.60 2.0
ON RESISTANCE VOLTAGE
ON RESISTANCE
0.15 0.5
0 0
0 13 26 39 52 65 -60 -40 -20 0 20 40 60 80 100 120 140 160
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)
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IRFP350
1.25 5000
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE
CRSS = CGD
COSS ≈ CDS + CGS
1.15 4000
BREAKDOWN VOLTAGE
C, CAPACITANCE (pF)
1.05 3000 CISS
0.95 2000
COSS
0.75 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 1 2 5 10 2 5 102
TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
25 102
PULSE DURATION = 80µs PULSE DURATION = 80µs
ISD, SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
gfs, TRANSCONDUCTANCE (S)
VDS = 2 x VGS
20
TJ = 25oC
10
15
TJ = 150oC TJ = 25oC
10
TJ = 150oC 1
0 0.1
0 5 10 15 20 25 0 0.4 0.8 1.2 1.6 2.0
ID , DRAIN CURRENT (A) VSD , SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE
20
ID = 16A
VGS, GATE TO SOURCE VOLTAGE (V)
16
VDS = 80V
12
VDS = 200V
VDS = 320V
8
0
0 30 60 90 120 150
Qg , GATE CHARGE (nC)
4-339
IRFP350
VDS
BVDSS
L tP
VDS
tP
0V IAS
0
0.01Ω
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
tON tOFF
td(ON) td(OFF)
tr tf
RL VDS
90% 90%
+
VDD 10% 10%
RG 0
-
DUT 90%
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
VDD
D
VDS
G DUT
0
IG(REF) S
0
VDS IG(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
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IRFP350
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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