System Verilog Assertions-3

by: Anand S Moghe

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 System Verilog Assertions

• Sequences in System Verilog Assertions:

• A sequence is a temporal expression which describes the behavior of signals

over a period of time. Suppose we write a property, and use it in an assertion
statement as follows:

property P6;
@(posedge clk)
sig1 |-> ##2(sig2 && sig3) ##1 !sig2 ##1 !sig3;
endproperty

Assertion will look like this:

label_1: assert property P6;

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 System Verilog Assertions

Now define two sequences as follows:

sequence S1;
##2(sig2 && sig3); // notice that there is no clock
endsequence

sequence S2;
!sig2 ##1 !sig3; // notice that there is no clock
endsequence

Property P6 can now be re-written using sequences S1, S2 as:

property P6;
@(posedge clk)
sig1 |-> S1 ##1 S2; // S1 and S2 make use of P6 clock. ##n always
endproperty // works wrt a clock edge.

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 System Verilog Assertions

• A sequence can be instantiated by another sequence.

• Parameters can be passed to sequences. This enables the same sequence

definition to be used in different situations and different conditions and
properties.

Example of sequence being used in the property definition:

sequence S6(x,y); // sequence with arguments (parameters)
##1x ##2y; // semicolon is required
endsequence

property P7;
@(posedge clk)
data1 |-> S6(sig1, sig2);
endproperty

label_2: assert property P7;

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 System Verilog Assertions

• Question: Can two parameterized sequences be used in different

properties at the same time?
Ans: Yes, they can be used. Example of their usage at the same time in
two different checks is shown below.

Parameterized property

property P9(z,m,n);
@(posedge clk)
z |->S6 (m, n); // sequence S6 is as defined above
endproperty

chk8: assert property P9(data1, sig1, sig2); // one set of

// parameters

chk9: assert property P9(data2, sig4, sig5); // diff set of

// parameters

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 System Verilog Assertions
• It is possible to write a property purely in terms of seq. that are defined.

sequence s1(x, y, z);

x ##y z; // after x is true, then ##y cycles later z is true.
endsequence

sequence s2 (a, b);

##a b; // semicolon required
endsequence

property p1(p,q,r,s,t);
@(posedge clk)
s1(p,q,r) |-> s2(s,t);
endproperty

In the above case if we write :

chk1: assert property (P1(sig1, 1, sig2, 4, out1) );

This is equivalent to:

@(posedge clk)
(sig1 ##1 sig2) |-> (##4 out1);
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 System Verilog Assertions
• System Verilog also provides the means to use operators on the sequences, as
shown in the examples below. Examples using the sequence operators
and, within and throughout are given below.

The and operator:

=====================
sequence s1;
##1 sig1;
endsequence

sequence s2;
##2 sig2 ##3 sig4;
endsequence

property p1;
@(posedge clk)
data1 |-> s1 and s2;
endproperty

chkn: assert property (p1);

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 System Verilog Assertions
• The within operator:
=====================
sequence s3;
sig1 ##1 sig2;
endsequence

sequence s4;
sig3 ##8 sig4;
endsequence

propery p1;
@(posedge clk)
in1 |-> s3 within s4;
Endproperty

The within construct in the example above allows the definition of a sequence
contained within another sequence.

The starting matching point of s3 must happen after the starting matching point of
s4. The ending matching point of s3 must happen before the ending matching point
of s4.
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 System Verilog Assertions
• The througout operator:

=================
sequence s31;
( ##1 (!a&&!b) ##1 (c[->3]) ##1 (a&&b) );
endsequence

property p31;
@(posedge clk) $fell(start) |-> (!start) throughout s31;
endproperty

chk31: assert property(p31);

=================
(expression) throughout (sequence definition)

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 System Verilog Assertions
• The througout operator:

(expression) throughout (sequence definition)

Property p31 above checks the following.

a. The check starts when signal "start" has a falling edge.

b. It tests the expression: ((!a&&!b) ##1 (c[->3]) ##1 (a&&b)).
c. The sequence s31 checks that between the falling edge of signals "a" and "b,"
and the rising edge of signals "a" and "b," signal "c" should repeat itself 3 times
continuously or intermittently,
d. During the entire test expression, signal "start" should always be low

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 System Verilog Assertions
Success 1 –
• The antecedent of the property succeeds on clock cycle 3 when a falling edge is
detected on the “start" signal.
• One cycle after that, signals "a" and "b" are expected to be low, and they are as
expected in clock cycle 4. From this point, signal "c" is expected to repeat itself
three times. It does repeat three times, once each in clock cycles 5, 7 and 11. In
clock cycle 12, it is expected that both signals "a" and "b" are high, and they are as
expected.
• Hence, the property starts at clock 3 and succeeds at clock 12. Note that signal
"start" was detected low from the clock cycles 3 through 12. That is the key
for the success of this check.

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 System Verilog Assertions
Failure 1 –
• The antecedent of the property succeeds on clock cycle 16 when a falling edge is
detected on the "start" signal.

• One cycle after that, signals "a" and "b" are expected to be low, and they are in
clock cycle 17. From this point signal, "c" is expected to repeat itself three times.

• We get two repeats on clock cycles 18 and 20. But on clock 21, before the third
repeat on signal "c" arrives, the signal "start" is detected high and the check fails
at clock cycle 21.

• The "throughout" condition was violated here and hence the check fails.

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 System Verilog Assertions
Local variables in properties:

It is possible to use a local variable within a property. Such variables are often
made use of in writing assertions / properties.

property p1;
int x;
@(posedge clk)
##1(sig1, x=sig2) |-> ##6 out1 == (x+1);
endproperty

x=sig2: this expression stores the value of sig2 in x for use later in the property.
SVA provides several built-in functions to check for some of the most common
design conditions.

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 System Verilog Assertions

$onehot(expression) - checks that the expression is one-hot, in other words, only

one bit of the expression can be high on any given clock edge.

$onehot0(expression) - checks that the expression is zero one-hot, in other

words, only one bit of the expression can be high or none of the bits can be high
on any given clock edge.

$isunknown(expression) - checks if any bit of the expression is X or Z.

$countones(expression) - counts the number of bits that are high in a vector.

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