Hardware Modeling using Verilog - - Unit 3 - Week 2 https://onlinecourses.nptel.ac.in/noc18_cs48/uni...

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Unit 3 - Week
2

Course
outline
Week 2 Assignment 2
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the portal assignment.

Week 1 1) Which of the following statements is false for Verilog modules? 1 point

Week 2 a. A module cannot contain definitions of other modules.

Lecture 6: b. When a module X is called multiple numbers of times from some other module, only one
VERILOG copy of module X is included in the hardware after synthesis.
LANGUAGE
FEATURES c. More than one module cannot be instantiated within another module.
(PART 1)
d. If a module X is instantiated 4 times within another module, 4 copies of X are created.
Lecture 7:
VERILOG No, the answer is incorrect.
LANGUAGE Score: 0
FEATURES
Accepted Answers:
(PART 2)
b. When a module X is called multiple numbers of times from some other module, only one copy of module
Lecture 8: X is included in the hardware after synthesis.
VERILOG c. More than one module cannot be instantiated within another module.
LANGUAGE
FEATURES 2) What does the statement the verilog statement “assign f = !(a & b) | !(a ^ b)” signify? 1 point
(PART 3)

Lecture 9: a. The value at LHS gets changed whenever there is a change in the expression at RHS.
VERILOG
b. The LHS is a register type variable.
OPERATORS

Lecture 10:
c. The variables at RHS must be wire type.
VERILOG d. Specification of a combinational circuit design at behavioral level.
MODELING
EXAMPLES No, the answer is incorrect.
Lecture 11: Score: 0
VERILOG Accepted Answers:
MODELING
a. The value at LHS gets changed whenever there is a change in the expression at RHS.
EXAMPLES
(Contd)
d. Specification of a combinational circuit design at behavioral level.

Week 2 Lecture 3) Which of the following is not true for net type variables? 1 point
Material
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continuously driven- by the outputs of the connected device.
Icarus User
A project of In association with
Guide b. It can be used in an expression on the RHS of an “assign” statement.
Programming c. Once a value is assigned, it will hold the value.
Assignment
1:4-bit adder- d. None of the above. Funded by
subtractor

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Hardware Modeling using Verilog - - Unit 3 - Week 2 https://onlinecourses.nptel.ac.in/noc18_cs48/uni...

No, the answer is incorrect.

Powered by
Programming
Assignment Score: 0
2:4-bit S-R Accepted Answers:
latch c. Once a value is assigned, it will hold the value.
Programming
4) For the following Verilog code segment, what will be the number of bits in S as deduced 1 point
Assignment
3:8-to-1 during synthesis? wire [31:0] X, Y; integer S; S = X + Y + 1;
Multiplexer
a. 62
Quiz : Week 2
Assignment 2 b. 32

Feedback for c. 33
Week 2
d. None of the above
Week 3
No, the answer is incorrect.
Score: 0
Week 4
Accepted Answers:
Week 5 c. 33

5) For the following Verilog code segment, if the initial value of IR is 3456ABCD (in hexadecimal), the
Week 6
value of “data” in decimal will be ………….. (Note that “data” is a 4-bit variable) wire [31:0] IR; wire [3:0]
Week 7 data; wire [15:0] d1; wire [31:16] d2; assign d1 = IR[31:16]; assign d2 = IR[15:0]; assign data = d1[7:4]
+ d2[23:20] + d2[27:24];
Week 8

Download
Videos No, the answer is incorrect.
Score: 0
Assignment Accepted Answers:
solution (Type: Numeric) 12

Text Transcripts 1 point

6) Consider the following Verilog module. module guess (data, cond, result); input [7:0] data; 1 point
input [1:0] cond; output reg result; always @(data) begin if (cond == 2’b00) result = |data; else result =
~^data; end endmodule Which of the following are true when the module is synthesized?

a. A combinational circuit will be generated.

b. A sequential circuit with a storage element for result will be generated.

c. The synthesize system will generate a wire for result.

d. None of the above.

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. A combinational circuit will be generated.
c. The synthesize system will generate a wire for result.

7) For the following Verilog code segment: wire [7:0] A; wire B; assign B = ~|A; if the value of 1 point
A is 8’b00111001, what will be the value of {A[5:3], 3{B}}?

a. 6’b111111

b. 6’b011000

c. 6’b111000

d. None of the above

No, the answer is incorrect.

Score: 0
Accepted Answers:

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Hardware Modeling using Verilog - - Unit 3 - Week 2 https://onlinecourses.nptel.ac.in/noc18_cs48/uni...

c. 6’b111000

8) Which of the followings is true regarding $monitor statement used in Verilog test bench? 1 point

a. It used to print the values of specified variables.

b. The values are printed whenever changes detected in any of the specified variables.

c. The printing occurs at the place $monitor statement is encountered.

d. None of the above.

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. It used to print the values of specified variables.
b. The values are printed whenever changes detected in any of the specified variables.

9) Which of the following statements is true for Verilog primitive gates? 1 point

a. In a behavioral specification a variable number of logic gates can be instantiated inside a

module.

b. The input and output ports of logic gates must be connected to wire type or register type
variables.

c. The optional delay in gate instantiation is only used during simulation and ignored during
logic synthesis.

d. All logic gates only respond to logic values 0 and 1.

No, the answer is incorrect.

Score: 0
Accepted Answers:
c. The optional delay in gate instantiation is only used during simulation and ignored during logic synthesis.

10)Identify the valid statements for Verilog operators. 1 point

a. The bitwise operators like & and | can acts as unary as well as binary operator.

b. The LHS of “assign” operator can be register type or net type variable.

c. The shift operators X>>2 and X>>>2 yields similar results when X is a signed number.

d. The equality operator == and === returns same logic value when either of the operands
contains all possible logic values.

No, the answer is incorrect.

Score: 0
Accepted Answers:
a. The bitwise operators like & and | can acts as unary as well as binary operator.

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