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# VIDEO SERIES ON

## TOUGHEST ANALOG GATE PREVIOUS YEAR PROBLEMS [EC | EE | IN] PART 1

GATE - EC - 1990
(1) The op-Amp of fig. has a very poor open loop voltage gain of 45 but is otherwise ideal. The gain of the
Amplifier equals -

## (A) 5 (B) 20 (C) 4 (D) 4.5

GATE - EE - 2007
(2) The circuit shown in the figure is :

rV r || R 2
(A) a voltage source with voltage (B) a voltage source with voltage V
R1 || R 2 R1
r || R 2 V R2 V
(C) a current source with current  (D) a current source with current 
R1 + R 2 r R1 + R 2 r

## Ans. (D) VIDEO SOLUTION LINK

GATE - IN - 2005
(3) In the circuit shown in the figure, assuming ideal diode characteristics with zero forward resistance and
0.7 V forward drop, the average value of V0 when the input waveform is as shown, is :

## (A) –0.7 V (B) –1.0 V (C) –2.0 V (D) –2.7 V

GATE - IN - 2007
(4) Consider the linear circuit with and ideal op-amp shown in the figure shown below

## The Z-parameters of the two port feedback network are :

Z11  Z22  11k , and
Z12  Z21  1k
The gain of the amplifier is
(A) +110 (B) +11 (C) –1 (D) –120
GATE - EE1 - 2015
(5) The op amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step
voltage V1= 1 mV is applied at the input at time t = 0 as shown.
Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output
voltage V0 is :

## (A) 1001 (B) 101 (C) 11 (D) 1

GATE - EC1 - 2015
(6) In the circuit shown, assume that the opamp is ideal. The bridge output voltage V 0 (in mV) for  = 0.05
is __.

## Ans. 250 VIDEO SOLUTION LINK

GATE - EC - 2006
(7) For the circuit shown in the following figure, the capacitor C is initially unchanged. At t = 0, the switch S
is closed. The voltage VC across the capacitor at t = 1 millisecond is

## In the figure shown above, the OP-AMP is supplied with  15V.

(A) 0 Volt (B) 6.3 Volts (C) 9.45 Volts (D) 10 Volts
Ans. 8.934 Volts (None of the Above) VIDEO SOLUTION LINK
GATE - S1 - EC - 2016
(8) A p-i-n photodiode of responsivity 0.8A/W is connected to the inverting input of an ideal opamp as
shown in the figure, VCC  15V, VCC  15V, , Load resistor RL  10k . If 10 W of power is
incident on the photodiode, then the value of photocurrent (in A ) through the load is _______.

## Ans. 790 to 810 & –810 to –790 VIDEO SOLUTION LINK

GATE - IN - 2009
(9) In the circuit shown in the figure, the switch S has been in Position 1 for a long time. It is then moved to
Position 2. Assume the Zener diodes to be ideal. The time delay between the switch moving to Position 2
and the transition in the output voltage V0 is

## (A) 5.00 ms (B) 8.75 ms (C) 10.00 ms (D) 13.75 ms

GATE - EE - 2008
(10) The block diagrams of two of half wave rectifiers are shown in the figure with the transfer characteristics
of the rectifiers.
It is desired to make full wave rectifier using above two half-wave rectifiers.
The resultant circuit will be

It is desired to make full wave rectifier using above two half-wave rectifiers. The resultants circuit will be

(A) (B)

(C) (D)

## Ans. (B) VIDEO SOLUTION LINK

GATE - IN - 2011
M1, M2 and M3 in the circuit shown below are matched N-channel enhancement mode MOSFETs operating in
saturation mode, forward voltage drop of each diode is 0.7 V, reverse leakage current of each diode is
negligible and the opamp is ideal.

## (11) (a) The current IS in the circuit is :

(A) –1 mA (B) 0.5 mA (C) 1 mA (D) 2 mA
Ans. (B)
(b) For the computed value of current Is , the output voltage V0 is :
(A) 1.2 V (B) 0.7 V (C) 0.2 V (D) –0.7 V
GATE - S3 - EC - 2016
(12) An opamp has a finite open loop voltage gain of 100. Its input offset voltage V ios (= +5mV) is modeled
as shown in the circuit below. The amplifier is ideal in all other respects. Vinput is 25 mV.

## The output voltage (in millivolts) is ________.

GATE - EE2 - 2015
(13) The filters F1 and F2 having characteristics as sown in figure (a) and (b) are connected as shown in
figure (c).

(a)

(b)

(c)

The cut-off frequencies of F1 and F2 are f1 and f2 respectively. If f1<f2, the resultant circuit exhibits the
characteristic of a
(A) Band-pass filter (B) Band-stop filter
(C) All pass filter (D) High-Q filter
GATE - IN - 1996
(14) In the circuit shown in figure, if ei  sin t , the voltage V0 is :

    1   1  
(A) 2 sin  t   (B) 2 sin  t   (C) sin  t   (D) sin  t  
 4  4 2  4 2  4

## Ans. (A) VIDEO SOLUTION LINK

GATE - S4 - IN - 2016
(15) The comparators (output = ‘1’, when input ≥ 0 and output =‘0’, when input < 0), exclusive-OR gate and
the unity gain low-pass filter given in the circuit are ideal. The logic output voltages of the exclusive-OR
gate are 0 V and 5 V. The cutoff frequency of the low-pass filter is 0.1 Hz. For V1 = 1 sin (3000t + 36o)
V and V2 = 1 sin (3000t) V, the value of VO in volt is _____.

## Ans. 1 VIDEO SOLUTION LINK

GATE - EC - 2018
(16) In the circuit shown below, the op-amp is ideal and Zener voltage of the diode is 2.5 volts. At the input,
unit step voltage is applied, i.e. vIN (t )  u(t ) volts. Also, at 𝑡 = 0, the voltage across each of the
capacitors is zero.

The time t, in milliseconds, at which the output voltage vOUT crosses −10 V is

## (A) 2.5 (B) 5 (C) 7.5 (D) 10

GATE - IN - 1999
(17) Pick up the correct relationship for the circuit shown in figure

R2 e1 e1
(A) e0  e1 (B) e0  e1 (C) I  (D) I 
R1 R2 R1
GATE - IN - 2017
(18) The two-input voltage multiplier, shown in the figure has a scaling factor of 1 and produces voltage
output. If V1  15V and V2  3V , the value of the V0 in volt is _______.

## Ans. – 5 VIDEO SOLUTION LINK

GATE - S4 - EC - 2016
(19) In the circuit shown in the figure, the channel length modulation of all transistors is non-zero (   0 ).
Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage
gain (Vo/Vin) of the circuit is

## (B)  g m1 (r01 || 1 || r03 )

g m3

  1  
(C)  g m1  r01 ||  || r02  || r03 
 
  gm2  

  1  
(D)  g m1  r01 ||  || r03  || r02 
 
  g m3  

## Ans. (C) VIDEO SOLUTION LINK

GATE - S2 - EC - 2017
(20) In the circuit shown, transistors Q1 and Q2 are biased at a collector current of 2.6 mA. Assuming that
transistor current gains are sufficiently large to assume collector current equal to emitter current and
thermal voltage of 26 mV, the magnitude of voltage gain V0 / VS in the mid-band frequency range is
_____ (upto second decimal place).

## Ans. 49.0-51.0 VIDEO SOLUTION LINK

GATE - EC - 2013
(21) The ac schematic of an NMOS common-source stage is shown in the figure below, where part of the
biasing circuits has been omitted for simplicity. For the n-channel MOSFET M, the transconductance
g m  1mA/V , and body effect and channel length modulation effect are to be neglected. The lower cut-
off frequency in Hz of the circuit is approximately at
(A) 8
(B) 32
(C) 50
(D) 200
GATE - EC - 2011

(22) In the circuit shown below, capacitors C1 and C 2 are very large and shorts at the input frequency. v i is

(A) maximum

(B) minimum

(C) unity

(D) zero

## Ans. (A) VIDEO SOLUTION LINK

GATE - EC - 2014
(23) Consider the common-collector amplifier in the figure (bias circuitry ensures that the transistor operates
in forward active region, but has been omitted for simplicity). Let IC be the collector current VBE be the
base-emitter voltage and VT be the thermal voltage. Also, gm and r0 are the small-signal
transconductance and output resistance of the transistor, respectively. Which one of the following
conditions ensures a nearly constant small signal voltage gain for a wide range of values of RE?

## Ans. (B) VIDEO SOLUTION LINK

GATE - EC - 2011
In the circuit shown below, assume that the voltage drop across a forward biased diode is 0.7 V. The thermal
voltage Vt  kT/q  25mV . The small signal input vi  Vp cos(t ) where Vp  100mV .

## (24) (a) The bias current I DC through the diodes is :

(A) 1 mA (B) 1.28 mA (C) 1.5 mA (D) 2 mA
Ans. (A)
(b) The ac output voltage Vac is
(A) 0.25cos(t)mV (B) 1cos(t)mV (C) 2cos(t )mV (D) 22cos(t )mV
GATE - S4 - IN - 2016
(25) The diode D used in the circuit below is ideal. The voltage drop Vab across the 1k resistor in volt is _.

## Ans. 0 VIDEO SOLUTION LINK

GATE - S3 - EC - 2016
(26) Assume that the diode in the figure has Von  0.7 V , but is otherwise ideal.

## Ans. 0.25-0.25 VIDEO SOLUTION LINK

GATE - EC - 2009
(27) In the circuit below, the diode is ideal the voltage V is given by

## (A) min(Vi, 1) (B) max(Vi, 1) (C) min(-Vi, 1) (D) max(-Vi, 1)

GATE - EC - 2014
(28) The figure shows a half wave rectifier. The diode D is ideal. The average state current (in Amperes)
through the diode is approximately -------------.

## Ans. 0.1 Ampere VIDEO SOLUTION LINK

GATE - S1 - EC - 2016
(29) The figure shows a half-wave rectifier with a 475 F filter capacitor. The load draws a constant current
I 0  1A from the rectifier. The figure also shows the input voltage Vi , the output voltage VC and the
peak-to-peak voltage ripple 𝑢 on VC . The input voltage Vi is a triangle-wave with an amplitude of 10 V
and a period of 1 ms.
The value of the ripple u (in volts) is ______.
GATE - EE - 2014

(30) The sinusoidal ac source in the figure has an rms value of 20 V . Considering all possible value of R L ,
2
the minimum value of R S in  to avoid burnout of the Zener diode is ______ .

## Ans. 300 VIDEO SOLUTION LINK

GATE - EC - 1996
(31) Value of R in the oscillator shown in the given figure. So chosen that it just oscillates at an angular
frequencies of '  ' . The value of '  ' and the required value of R will respectively be

(A) 105 rad / sec, 2 104  (B) 2 104 rad / sec, 2 104 

(C) 2 104 rad / sec, 105  (D) 105 rad / sec, 105 

## Ans. (A) VIDEO SOLUTION LINK

GATE - EC - 2011
(32) For the BJT Q1 in the circuit shown below,    , VBEon  0.7 V , VCESat  0.7 V . The switch is initially
closed. At time t = 0, the switch is opened. The time t at which Q1 leaves the active region is :

## (A) 10 ms (B) 25 ms (C) 50 ms (D) 100 ms

GATE - EC - 1996
(33) The circuit shown in the figure is that of –

## (A) A non-inverting Amplifiers (B) An inverting Amplifier

(C) An Oscillator (D) A Schmitt trigger
GATE - IN - 2004
(34) Figure (a) shows a Schmitt trigger circuit figure (b) the corresponding hysteresis characteristics. The
values of VTL and VTH are

## Ans. (D) VIDEO SOLUTION LINK

GATE - EC - 2017
(35) For the operational amplifier circuit shown, the output saturation voltages are 15V . The upper and
lower threshold voltages for the circuit are, respectively,

(A) +5V and -5V (B) +7V and -3V (C) +3V and -7V (D) +3V and -3V
GATE - IN - 2008
(36) In the op-amp circuit shown below the input voltage Vin is gradually increases from 0 V to +10V.
Assuming that the output voltage V0 saturates at – 10 V and +10V0 will change from

## (A) – 10 V to +10 V when Vi = - 1 V (B) – 10 V to +10V when Vi = 1 V

(C) +10 V to - 10 V when Vi = 1 (D) +10 V to – 10 V when Vi = +1V
Ans. (A & C) VIDEO SOLUTION LINK
GATE - EE - 2002
(37) The output voltage (V0 ) of the Schmitt trigger shown in figure swings between +15 V and 15 V.
Assume that the operational amplifier is ideal. The output will change from +15 V to 15 V when the
instantaneous value of the input sine wave is:

(A) 5 V in the positive slope only. (B) 5 V in the negative slope only.
(C) 5 V in the positive and negative slopes. (D) 3 V in the positive and negative slopes.
VIDEO SERIES ON
TOUGHEST ANALOG GATE PREVIOUS YEAR PROBLEMS [EC | EE | IN] PART 2

GATE - EC - 2017
(1) In the figure shown, the npn transistor acts as a switch

For the input Vin  t  as shown in the figure, the transistor switches between the cut-off and saturation
regions of operation, when T is large. Assume collector-to-emitter voltage at saturation VCEsat   0.2V and
base-to-emitter voltage. The minimum value of the common-base current gain (  ) of the transistor for
the switching should be :

## Ans. 0.89 to 0.91 Video Solution Link

GATE - EC - 2017
(2) In the figure, D1 is a real silicon pn junction diode with a drop of 0.7 V under forward bias condition and
D2 is a Zener diode with breakdown voltage of –6.8 V. The input Vin (t ) is a periodic square wave of
period T, whose one period is shown in the figure.

Assuming 10  T , where  is the time constant of the circuit, the maximum and minimum values of
the output waveform are respectively.

## (C) 7.5 V and – 21.2 V (D) 6.1 V and – 22.6 V

GATE - EC - 2015
(3) Assuming that the opamp in the circuit shown below is ideal, the output voltage V 0 (in volts)

## Ans. 12 Video Solution Link

GATE - IN - 2004

V 
(4) The gain  0  of the amplifier circuit shown in figure is
 Vi 

(A) 8 (B) 4
3RL
(C) –4 (D)
R

GATE - EE - 2017
VCC
(5) For the circuit shown in the figure below, it is given that VCE  . The transistor has   29 and
2
VBE  0.7 V when the B-E junction is forward biased.

RB
For this circuit, the value of is :
R
(A) 43 (B) 92
(C) 121 (D) 129

GATE - EE - 2005
(6) Consider the inverting amplifier, using an ideal operational amplifier shown in the figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between –10 and –25. The upper limit on R F is 1M . The value of R 1 should
be

## Ans. (C) Video Solution Link

GATE - IN - 2004
(7) The output voltage V0 in the circuit in figure is

R2 R2
(A) V (B) V
R R1

R2 R2
(C) V (D) V
R1 R(1  )

## Ans. (B) Video Solution Link

GATE - IN - 2011
(8) Assuming base-emitter voltage of 0.7 V and   99 of transistor Q1 , the output voltage V0 in the ideal
opamp circuit shown below is :
(A) –1 V (B) –1/3.3V
(C) 0 V (D) 2 V

GATE - EE - 2015
(9) Consider the circuit shown in the figure. In this circuit R = 1k , and C = 1F . The input voltage is
sinusoidal with a frequency of 50 Hz, represented as a phasor with magnitude Vi and phase angle 0
radian as shown in the figure. The output voltage is represented as a phasor with magnitude V 0 and phase
angle  radian. What is the value of the output phase angle  (in radian) relative to the phase angle of
the input voltage?

(A) 0 (B) 
(C)  / 2 (D)  / 2

GATE - IN - 2015
(10) For the circuit shown in the figure, the rising edge triggered D-flip flop with asynchronous reset has a
clock frequency of 1 Hz. The NMOS transistor has an ON resistance of 1000 and an OFF resistance
of infinity. The nature of the output waveform is :
(A)

(B)

(C)

(D)