4430 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO.
11, NOVEMBER 2017
A Planar Junctionless FET Using SiC With
Reduced Impact of Interface
Traps: Proposal and Analysis
Jaspreet Singh and Mamidala Jagadesh Kumar, Senior Member, IEEE
Abstract — In this paper, we propose the use of silicon
carbide (SiC) material in a planar junctionless FET (JLFET)
architecture for high-voltage operations. Using calibrated
device simulations, we show that the planar SiC JLFET
exhibits: 1) a breakdown voltage of ∼60 V; 2) a subthreshold
slope of 61 mV/decade; and 3) suppressed lateral band-to-
band tunneling. In addition, the proposed device exhibits
reduced impact of interface traps than the conventional
SiC MOSFETs due to the bulk conduction and may not
require additional fabrication steps such as counter-doping
and annealing to neutralize the semiconductor-oxide traps.
The device also gives excellent off-state characteristics and
shows promising results as a future device for power MOS
devices, system-on-panel, and 3-D-stacked applications.
Index Terms — Junctionless, junctionless FET (JLFET),
MOSFET, polysilicon, power devices, silicon carbide (SiC).
I. I NTRODUCTION
T HE conventional MOSFET scaling has reached its limit
because of the increased short-channel effects (SCE),
difficulty in realization of ultrasteep doping profiles, and
the large leakage currents [1]–[3]. The multigate MOSFETs
improve the SCE and the leakage behavior [4]–[6], but the
problem of realizing ultrasteep doping profile persists. The
junctionless FET (JLFET) having no metallurgical junction at
the source–channel and channel–drain interfaces provides a
solution to this problem [7], [8], but they show poor high-
voltage characteristics [9].
The high-voltage breakdown characteristics of a fabricated
polysilicon gate all around (GAA) and planar JLFET have
been studied in [9] and [10]. The thin channel polysilicon
GAA JLFET gives a breakdown voltage (BV) of ∼60 V but
at the cost of increased fabrication complexity due to the
GAA structure, while the planar polysilicon JLFET shows
poor breakdown performance [9]. But wide bandgap materials
such as silicon carbide (SiC) can be considered to improve
the high-voltage breakdown characteristics of JLFET, since
conventional SiC MOSFETs have shown great potential for
Manuscript received June 8, 2017; revised August 21, 2017; accepted
September 9, 2017. Date of publication September 26, 2017; date of
current version October 20, 2017. The review of this paper was arranged
by Editor W. Tsai. (Corresponding author: Jaspreet Singh.)
The authors are with the Department of Electrical Engineering,
IIT Delhi, New Delhi 110016, India (e-mail: jassi.achiever@gmail.com;
mamidala@ee.iitd.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2017.2752227
0018-9383 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
high-temperature and high-frequency applications due to their
large band gap, high thermal conductivity, and a higher
BV than that of silicon [11]–[14]. Also the SiC nanowire
FETs have been extensively studied experimentally [15]–[18].
However, the application of SiC for JLFETs has not yet been
reported.
In this paper, we propose the use of SiC material in a planar
JLFET architecture to improve the high-voltage characteristics
by suppressing the lateral band-to-band tunneling (L-BTBT)
across the channel direction [19]–[24]. Using calibrated device
simulations, we show that the wide bandgap of SiC enhances
the tunneling width at the channel–drain interface which
significantly reduces the L-BTBT. In addition, the device uses
high-k gate oxide which allows the use of thicker gate oxide
without losing its control over the channel. Hence, the planar
4H-SiC JLFET exhibits high-voltage characteristics better than
the complex GAA polysilicon JLFET device. Thus, the SiC
planar JLFET structure mitigates the complexity of using mul-
tiple gates or GAA structures to achieve high BV in JLFETs.
Moreover, the junctionless architecture helps in improving the
channel mobility of the planar 4H-SiC JLFET in partial deple-
tion mode (VTH ≤ VGS < VFB ), since the current conduction
in JLFETs is through the bulk, unlike the surface conduction in
conventional MOSFETs. Therefore, the semiconductor-oxide
interface imperfections do not impact the current flow; hence
the 4H-SiC JLFETs give higher channel mobility. While in the
accumulation mode (VGS ≥ 0VFB ), the carrier concentration
at semiconductor-oxide interface is greater than the bulk
concentration and as a result sufficient carriers are available
even after trapping of free carriers by the interface traps
and hence gives better ON-state current as compared to the
conventional MOSFETs. Therefore, unlike the conventional
4H-SiC MOSFETs, the counter-doping and additional anneal-
ing steps may not be required in SiC JLFETs in order to
neutralize the interface traps [25], [26]. In addition, the pro-
posed SiC JLFET shows superior subthreshold slope (SS) and
OFF -state characteristics, thus making the device very lucrative
as a future device for power applications. We believe that our
results may provide the incentive for further exploration of
planar 4H-SiC JLFETs.
II. D EVICE S TRUCTURE AND S IMULATION PARAMETERS
The cross-sectional view of the planar 4H-SiC JLFET
is shown in Fig. 1. The device has a uniform doping
SINGH AND KUMAR: PLANAR JLFET USING SiC 4431

Fig. 1. Schematic view of planar SiC JLFET.

TABLE I
S IMULATION PARAMETERS : 4H-S I C

Fig. 2. Simulation models calibrated by reproducing the results of

SiC MOSFET [27]. (a) Transfer characteristics. (b) Output characteristics.

of 1 × 1019 cm−3 in the source, channel, and drain regions.

The device parameters used in the simulations are:
1) channel length (L) = 1 μm; Fig. 3. Transfer characteristics of planar 4H-SiC JLFET on both linear
2) gate-oxide thickness (Tox ) = 5 nm (HfO2 ); and log scales.
3) channel thickness (Tsi ) = 6 nm;
4) channel width (W ) = 1 μm;
The threshold voltage (VTH ) of the device is 0.5 V (defined
5) metal-gate work function = 4.7 eV.
as the gate voltage at IDS = 0.1 nA [9]). The 4H-SiC JLFET
The device simulations were carried out using the
behaves as a gated resistor, controlled by the applied gate-to-
Synopsys device simulator Sentaurus [28]. Fermi–Dirac sta-
source voltage. At lower gate voltages, the channel region in
tistics, Shockley–Read–Hall recombination, and bandgap nar-
a JLFET is fully depleted due to the work function difference
rowing models were used. Nonlocal band-to-band tunnel-
between the gate and channel, and the device remains in
ing (BTBT) model was used to account for tunneling in the
OFF -state. When the gate voltage is greater than the threshold
lateral direction for JLFET. The remote coulomb scattering,
voltage, the thickness of the depletion region in the channel
remote phonon scattering, inversion- and accumulation-layer
decreases allowing the current to flow from the drain to
mobility (IalMob), interface charge mobility degradation, and
source. Since, the current flow occurs through the center of
trap-to-trap tunneling models were used to accurately model
the channel unlike the conventional MOSFETs where current
the mobility and leakage current for the 4H-SiC MOSFET.
flows near the semiconductor-oxide interface, the junctionless
The semiconductor-oxide interface imperfections were mod-
structure gives much better ON-state current than the con-
eled by using fixed charge traps (1.5 × 1013 cm−3 ) and
ventional SiC MOSFETs. The transfer characteristics show a
acceptor traps (2 × 1013 cm−3 ) at the 4H-SiC–SiO2 interface.
steep SS of 61 mV/decade with a sharper turn- ON behavior.
These traps densities are close to those reported in [28]. The
The excellent SS is achieved because of bulk conduction
velocity saturation model for nonsilicon materials (4H-SiC)
in the JLFET, since the device is less influenced by the
was enabled by setting the parameter Vsat_formula = 2.
semiconductor-oxide imperfections. However, the SS between
The IalMob model was enabled to account for the mobility
conventional MOSFETs and JLFETs is still controversially
degradation due to scattering at the 4H-SiC–SiO2 interface.
discussed in [7], [8], and [29].
The calibrated surface roughness parameters (delta and eta)
Fig. 4 shows the output characteristics of planar 4H-SiC
and 2-D coulomb scattering parameters (D1_inv, D1_acc,
JLFET. The device exhibits excellent I–V performance with
and D2_acc) are given in Table I [28]. The simulation models
good pinchoff and normally OFF-characteristics, despite the
were calibrated by reproducing the weak inversion and strong
heavily doped channel. The maximum ON-state current is
inversion characteristics of SiC MOSFET [27], as shown
∼50 μA at VGS − VTH = 4.5 V.
in Fig. 2. Table I provides the summary of 4H-SiC parameters
Fig. 5 shows the lateral band diagram along the channel
used in the simulations.
direction of 4H-SiC JLFET at different gate voltages. It can be
observed from Fig. 5 that for VGS = 3 V, the device operates
III. R ESULTS AND D ISCUSSION in ON-state with flat energy bands indicating that the electron
Fig. 3 shows the transfer characteristics of the 4H-SiC concentration in the source, channel, and drain regions are
planar JLFET on both linear and log scales for VDS = 0.5 V. the same, while for VGS = 0 V the device is in OFF-state
4432
Fig. 4. Output characteristics of planar 4H-SiC JLFET.
Fig. 5. Energy band diagram of 4H-SiC JLFET in depletion mode
(VGS = 0 V) and accumulation mode (VGS = 3 V) with VDS = 0 V
at 1 nm below the 4H-SiC–SiO2 interface.
Fig. 6. Energy band diagram of 4H-SiC JLFET in depletion mode
(VGS = 0 V) for VDS = 3, 10, and 40 V at 1 nm below the 4H-SiC–SiO2
interface.
and the channel is fully depleted due to the work function
difference between the gate and channel. It can also be noted
from Fig. 5 that for VDS = 0 V, there is no band overlap at the
drain–channel interface, and hence, L-BTBT is not present.
Fig. 6 shows the lateral band diagram of 4H-SiC JLFET at
different drain voltages in OFF-state (VGS = 0 V). It can
be observed from Fig. 6 that as the drain bias is increased
the conduction band of the drain region starts overlapping the
valence band of channel region. This band overlapping triggers
the L-BTBT which results in enhanced OFF-state current [30].
It is important to note that for VGS = 0 V and VDS = 1 V, the
4H-SiC JLFET does not have band overlap between the chan-
nel and drain junctions unlike the Si JLFETs [30]–[34] due to
the wide bandgap of SiC material. Further, it may be noted that
the minimum tunneling width between the channel and drain
regions in OFF-state is approximately 6 nm in 4H-SiC JLFET
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 11, NOVEMBER 2017
Fig. 7. Breakdown characteristics of planar 4H-SiC JLFET.
Fig. 8. Electric field distribution along the y-axis of planar 4H-SiC JLFET
for VDS = 40 V and VDS = 70 V at 0.5 nm below the 4H-SiC–SiO2
interface.
even at VDS = 10 V, while the Si JLFET has minimum
tunneling width of approximately 7 nm at VDS = 1 V and
VGS = 0 V as given in [30]. Therefore, the OFF-state leakage
current is significantly reduced in 4H-SiC JLFET due to the
suppressed L-BTBT as compared to Si JLFETs and hence, the
4H-SiC JLFET exhibits improved high-voltage characteristics
than the Si or polysilicon JLFETs [9].
Fig. 7 shows the high-voltage characteristics of the planar
4H-SiC JLFET. The BV (VBD ) of planar 4H-SiC JLFET
is ∼60 V (extracted from the IDS –VDS curve at IDS = 10 μA
and VGS = 0 V [9]), which is better than the polysilicon planar
JLFET and equivalent to the polysilicon GAA JLFET [9].
Fig. 8 shows the electric field distribution of 4H-SiC planar
JLFET at VDS = 40 V and VDS = 70 V during OFF-state.
It can be observed from Fig. 8 that the electric field distribution
changes at large VDS values due to the depletion of thin
drain regions, and the electric field peak lies near the drain
contact instead of the drain–channel interface causing the drain
breakdown, which is similar to the drain breakdown behavior
of ultrathin silicon on insulator MOSFET’s [35]. However,
the drain breakdown occurs after the L-BTBT breakdown in
planar 4H-SiC JLFET, and hence can be neglected.
Figs. 9 and 10 show the transfer characteristics of pla-
nar 4H-SiC JLFET and conventional 4H-SiC MOSFET [27]
with and without traps, respectively. The traps concentration
is the same for both devices, as mentioned in Table I.
It can be observed from Figs. 9 and 10, respectively, that
the conventional 4H-SiC MOSFET is very sensitive to the
presence of traps at the semiconductor-oxide interface due
to the surface conduction. In conventional SiC MOSFETs,
SINGH AND KUMAR: PLANAR JLFET USING SiC
Fig. 9. Transfer characteristics of planar 4H-SiC JLFET with and without
traps on both linear and log scales.
Fig. 10. Transfer characteristics of conventional 4H-SiC MOSFET with
and without traps on both linear and log scales.
the electron concentration in the channel is reduced due to
trapping of free electrons by traps near the semiconductor-
oxide interface, and the channel mobility is also degraded
due to different scattering mechanisms [36]–[42] resulting in a
large shift of threshold voltage and a reduction in the ON-state
current. On the other hand, JLFET is a bulk conduction device,
since the device is fully depleted when VGS < VTH and
as VGS is increased above VTH [but less than the flat band
voltage (VFB )] the depletion region starts to disappear from
the bulk of channel (as a result the energy bands tend to
become flat). Therefore, the carriers flowthrough the bulk of
channel and thus are not impacted by the semiconductor-oxide
interface imperfections. However, when VGS ≥ VFB , the device
is in accumulation mode, i.e., there is no depletion region
present in the channel and the electron concentration at the
surface is more than the background electron concentration,
i.e., 1×1019 cm−3 as shown in Fig. 11. Thus, in accumulation
mode (ON-state), the planar 4H-SiC JLFET has sufficient free
electrons to have high ON-state current, even after trapping
of free electrons by interface traps, unlike the conventional
SiC MOSFETs. Hence, the 4H-SiC planar JLFET exhibits
better electrical characteristics and the device is less suscep-
tible to the semiconductor-oxide interface imperfections as
compared to the conventional SiC MOSFETs. Further, it may
be noted that the purpose of comparing the impact of traps on
electrical characteristics of conventional and JLFET is to show
the relative variation of threshold voltage of devices with their
respective ideal device (i.e., without traps).
The 4H-SiC planar JLFET not only helps in improving the
high-voltage characteristics by suppressing the L-BTBT across
the channel direction due to the wide bandgap of SiC material
4433
Fig. 11. Electron concentration contour of planar 4H-SiC JLFET in
OFF-state (VGS = 0 V and VDS = 0 V) and ON-state (VGS = 4 V and
VDS = 0 V).
but also helps in improving the ON-state current and mobility
of the 4H-SiC planar JLFET device because of the thinner
gate oxides (in order to have effective control of gate over
channel) and due to the bulk conduction.
IV. C ONCLUSION
In this paper, we proposed a planar JLFET with 4H-SiC
material which significantly improves the high-voltage char-
acteristics by suppressing the L-BTBT across the channel
direction. Using calibrated 2-D simulations, we have demon-
strated that the proposed device exhibits better high-voltage
characteristics and ON-state current than the planar and
GAA polysilicon JLFETs and also the excellent OFF-state
characteristics and SS. Moreover, the 4H-SiC JLFET due to
bulk conduction exhibits reduced impact of interface traps than
the conventional 4H-SiC MOSFETs. The excellent OFF-state
behavior and high-voltage characteristics make the device very
attractive as a future device for power applications. We believe
that our results may provide the incentive for the experimental
realization of 4H-SiC JLFET.
R EFERENCES
[1] S. Saurabh, and M. J. Kumar, Fundamentals of Tunnel Field-Effect
Transistors, Boca Raton, FL, USA: CRC Press, Oct. 2016.
[2] M. J. Kumar, R. Vishnoi, and P. Pandey, Tunnel Field–Effect Tran-
sistors (TFET): Modelling and Simulation, West Sussex, U.K.: Wiley,
Nov. 2016.
[3] C.-W. Lee et al., “High-temperature performance of silicon junctionless
MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620–625,
Mar. 2010.
[4] Y.-K. Choi et al., “Ultrathin-body SOI MOSFET for deep-sub-tenth
micron era,” IEEE Electron Device Lett., vol. 21, no. 5, pp. 254–255,
May 2000.
[5] D. Hisamoto et al., “FinFET—A self-aligned double-gate MOSFET
scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12,
pp. 2320–2325, Dec. 2000.
[6] N. Singh et al., “High-performance fully depleted silicon nanowire
(diameter ≤ 5 nm) gate-all-around CMOS devices,” IEEE Electron
Device Lett., vol. 27, no. 5, pp. 383–385, May 2006.
4434 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 11, NOVEMBER 2017
[7] C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and
J.-P. Colinge, “Junctionless multigate field-effect transistor,” Appl. Phys.
Lett., vol. 94, no. 5, p. 053511, Feb. 2009.
[8] J.-P. Colinge et al., “Nanowire transistors without junctions,” Nature
Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010.
[9] Y.-C. Cheng et al., “High voltage characteristics of junctionless poly-
silicon thin film transistors,” Appl. Phys. Lett., vol. 103, no. 12,
p. 123510, 2013.
[10] H.-B. Chen, Y.-C. Wu, C.-Y. Chang, M.-H. Han, N.-H. Lu, and
Y.-C. Cheng, “Performance of GAA poly-Si nano sheet (2 nm) channel
of junctionless transistors with ideal subthreshold slope,” in Proc. Symp.
VLSI Technol. Circuits, Jun. 2013, pp. T232–T233.
[11] M. Shen, S. Krishnamurthy, and M. Mudholkar, “Design and perfor-
mance of a high frequency silicon carbide inverter,” in Proc. IEEE
Energy Convers. Congr. Expo., Sep. 2011, pp. 2044–2049.
[12] B. McPherson et al., “Packaging of high temperature 50 kW SiC motor
drive modules for hybrid-electric vehicles,” in Proc. 42nd Int. Symp.
Microelectron., Nov. 2009, pp. 663–670.
[13] J. Valle-Mayorga et al., “High-temperature silicon-on-insulator gate
driver for SiC-FET power modules,” IEEE Trans. Power Electron.,
vol. 27, no. 11, pp. 4417–4424, Nov. 2012.
[14] H. Linewih, “Design and application of SiC power MOSFET,”
Ph.D. dissertation, Dept. Eng. Inf. Technol., Griffith Univ., Brisbane,
QLD, Australia, 2002.
[15] H.-K. Seong, H.-J. Choi, S.-K. Lee, J.-I. Lee, and D. J. Choi, “Optical
and electrical transport properties in silicon carbide nanowires,” Appl.
Phys. Lett., vol. 85, no. 7, pp. 1256–1258, 2004.
[16] H. K. Seong et al., “Fabrication and electrical transport properties
of CVD grown silicon carbide nanowires (SiC NWs) for field effect
transistor,” Mater. Sci. Forum, vols. 527–529, pp. 771–774, Oct. 2006.
[17] K. Rogdakis, M. Bescond, E. Bano, and K. Zekentes, “Theoretical
comparison of 3C-SiC and Si nanowire FETs in ballistic and diffusive
regimes,” Nanotechnology, vol. 18, no. 47, p. 475715-1–475715-5,
Nov. 2007.
[18] W. M. Zhou, F. Fang, Z. Y. Hou, L. J. Yan, and Y. F. Zhang, “Field-
effect transistor based on β-SiC nanowire,” IEEE Electron Device Lett.,
vol. 27, no. 6, pp. 463–465, Jun. 2006.
[19] S. Sahay and M. J. Kumar, “A novel gate-stack-engineered nanowire
FET for scaling to the sub-10-nm regime,” IEEE Trans. Electron
Devices, vol. 63, no. 12, pp. 5055–5059, Dec. 2016.
[20] S. Sahay and M. J. Kumar, “Insight into lateral band-to-band-tunneling
in nanowire junctionless FETs,” IEEE Trans. Electron Devices, vol. 63,
no. 10, pp. 4138–4142, Oct. 2016.
[21] S. Sahay and M. J. Kumar, “Diameter dependence of leakage current
in nanowire junctionless field effect transistors,” IEEE Trans. Electron
Devices, vol. 64, no. 3, pp. 1330–1335, Mar. 2017.
[22] S. Sahay and M. J. Kumar, “Controlling L-BTBT and volume depletion
in nanowire JLFETs using core–shell architecture,” IEEE Trans. Electron
Devices, vol. 63, no. 9, pp. 3790–3794, Sep. 2016.
[23] S. Sahay and M. J. Kumar, “Nanotube junctionless FET: Proposal,
design, and investigation,” IEEE Trans. Electron Devices, vol. 64, no. 4,
pp. 1851–1856, Apr. 2017.
[24] S. Sahay and M. J. Kumar, “Symmetric operation in an extended
back gate JLFET for scaling to the 5-nm regime considering quantum
confinement effects,” IEEE Trans. Electron Devices, vol. 64, no. 1,
pp. 21–27, Jan. 2017.
[25] A. Poggi, F. Moscatelli, S. Solmi, and R. Nipoti, “Investigation
on the use of nitrogen implantation to improve the performance of
n-channel enhancement 4H-SiC MOSFETs,” IEEE Trans. Electron
Devices, vol. 55, no. 8, pp. 2021–2028, Aug. 2008.
[26] J. Rozen, S. Dhar, M. E. Zvanut, J. R. Williams, and L. C. Feldman,
“Density of interface states, electron traps, and hole traps as a function
of the nitrogen density in SiO2 on SiC,” J. Appl. Phys., vol. 105, no. 12,
p. 124506, Jun. 2009.
[27] M. Mudholkar and H. A. Mantooth, “Characterization and modeling of
4H-SiC lateral MOSFETs for integrated circuit design,” IEEE Trans.
Electron Devices, vol. 60, no. 6, pp. 1923–1930, Jun. 2013.
[28] Sentaurus Device User Guide, Synopsys, Inc., Mountain View, CA,
USA, 2014.
[29] R. Rios et al., “Comparison of junctionless and conventional trigate
transistors with Lg down to 26 nm,” IEEE Electron Device Lett., vol. 32,
no. 9, pp. 1170–1172, Sep. 2011.
[30] S. Gundapaneni, M. Bajaj, R. K. Pandey, K. V. R. Murali, S. Ganguly,
and A. Kottantharayil, “Effect of band-to-band tunneling on junc-
tionless transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4,
pp. 1023–1029, Apr. 2012.
[31] M. J. Kumar and S. Sahay, “Controlling BTBT-induced parasitic BJT
action in junctionless FETs using a hybrid channel,” IEEE Trans.
Electron Devices, vol. 63, no. 8, pp. 3350–3353, Aug. 2016.
[32] S. Sahay and M. J. Kumar, “Realizing efficient volume depletion in
SOI junctionless FETs,” IEEE J. Electron Devices Soc., vol. 4, no. 3,
pp. 110–115, May 2016.
[33] S. Sahay and M. J. Kumar, “Spacer design guidelines for nanowire FETs
from gate-induced drain leakage perspective,” IEEE Trans. Electron
Devices, vol. 64, no. 7, pp. 3007–3015, Jul. 2017, doi: 10.1109/TED.
2017.2702067.
[34] S. Sahay and M. J. Kumar, “Physical insights into the nature of gate-
induced drain leakage in ultrashort channel nanowire FETs,” IEEE
Trans. Electron Devices, vol. 64, no. 6, pp. 2604–2610, Jun. 2017.
[35] M. Yoshimi et al., “Analysis of the drain breakdown mechanism in ultra-
thin-film SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 37, no. 9,
pp. 2015–2021, Sep. 1990.
[36] C. Strenger et al., “Systematic analysis of the high- and low-field
channel mobility in lateral 4H-SiC MOSFETs,” Mater. Sci. Forum,
vols. 778–780, pp. 583–586, Feb. 2014.
[37] C. Strenger et al., “Correlation of interface characteristics to electron
mobility in channel-implanted 4H-SiC MOSFETs,” Mater. Sci. Forum,
vols. 740–742, pp. 537–540, Jan. 2013.
[38] C. Strenger et al., “Influence of ion implantation in SiC on the channel
mobility in lateral n-channel MOSFETs,” ECS Trans., vol. 58, no. 4,
pp. 71–80, 2013.
[39] A. F. Basile, S. Dhar, and P. M. Mooney, “Electron trapping in
4H-SiC MOS capacitors fabricated by pre-oxidation nitrogen implan-
tation,” J. Appl. Phys., vol. 109, no. 11, p. 114505, 2011.
[40] B. R. Tuttle et al., “High electron mobility due to sodium ions in the gate
oxide of SiC-metal-oxide-semiconductor field-effect transistors,” J. Appl.
Phys., vol. 109, no. 2, p. 023702, 2011.
[41] S. Dhar et al., “Inversion layer carrier concentration and mobility
in 4H–SiC metal-oxide-semiconductor field-effect transistors,” J. Appl.
Phys., vol. 108, no. 5, p. 054509, 2010.
[42] D. J. Lichtenwalner, V. Misra, S. Dhar, S.-H. Ryu, and A. Agarwal,
“High-mobility enhancement-mode 4H -SiC lateral field-effect transis-
tors utilizing atomic layer deposited Al2 O3 gate dielectric,” Appl. Phys.
Lett., vol. 95, no. 15, p. 152113, 2009.
Jaspreet Singh is currently pursuing the Ph.D.
degree in electrical engineering with IIT Delhi,
New Delhi, India.
He has been with the Solutions Group,
Synopsys India Pvt Ltd., Noida, India,
since 2010. His current research interests incl-
ude semiconductor device modeling, design,
and fabrication.
Mamidala Jagadesh Kumar (SM’98) is
currently a Professor (on-lien) with IIT Delhi,
New Delhi, India and the Vice-Chancellor
with Jawaharlal Nehru University, New
Delhi. He has authored many publications in
micro/nanoelectronics.
Mr. Kumar was an Editor of the IEEE
Transactions on Electron Devices. He is
currently the Editor-in-Chief of the IETE
Technical Review and an Editor of the IEEE
Journal of the Electron Devices Society.