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B2)

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY RAM64X8 IS
PORT(DIR : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
CS, RW : IN STD_LOGIC;
DATO : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END RAM64X8;
ARCHITECTURE FUNCION OF RAM64X8 IS
TYPE MEMORIA IS ARRAY(0 TO 3) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ram: MEMORIA;
BEGIN
PROCESS()
BEGIN
IF CS=’1’ THEN
IF RW=’0’ THEN
DATO<=ram(conv_integer(DIR));
END IF;
IF RW=’0’ THEN
ram(conv_integer(DIR))<=DATO;
END IF;
END IF;
END PROCESS;
END FUNCION;