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September 2010
The original datasheet pages have not been modified and do not reflect those changes.
Please refer to the table below for reference PCN and current product status.
5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Phone (503) 268-8000 FAX (503) 268-8347
Internet: http://www.latticesemi.com
ree
Lead-Fage
P a c k ns
GAL16V8
Optio le! High Performance E2CMOS PLD
b
Availa Generic Array Logic™
N ES
— 45mA Typ Icc on Quarter Power Device I
PROGRAMMABLE
8 OLMC I/O/Q
• E2 CELL TECHNOLOGY
ED
I
— Reconfigurable Logic
AND-ARRAY
— Reprogrammable Cells
(64 X 32)
8 OLMC I/O/Q
— 100% Tested/100% Yields
N VIC
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
I
8 OLMC I/O/Q
U
— Maximum Flexibility for Complex Logic Designs I
— Programmable Output Polarity
— Also Emulates 20-pin PAL® Devices with Full 8 OLMC I/O/Q
Function/Fuse Map/Parametric Compatibility
I
C DE
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
— 100% Functional Testability 8 OLMC I/O/Q
• APPLICATIONS INCLUDE:
TI
I
— DMA Control
— State Machine Control 8 OLMC I/O/Q
— High Speed Graphics Processing
I
— Standard Logic Speed Upgrade OE
I/OE
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
D LL
ficiently.
I 8 14 I/O/Q GAL
The generic architecture provides maximum design flexibility by 9 11 13 I I/O/Q
16V8
allowing the Output Logic Macrocell (OLMC) to be configured by I GND I/OE I/O/Q I/O/Q
5 I/O/Q
I
the user. An important subset of the many architecture configura-
tions possible with the GAL16V8 are the PAL architectures listed SOIC I 15 I/O/Q
in the table of the macrocell description section. GAL16V8 devices I/CLK 1 20 Vcc
I I/O/Q I I/O/Q
are capable of emulating any of these PAL architectures with full
I I/O/Q
function/fuse map/parametric compatibility. GAL I I/O/Q
I I/O/Q
Unique test circuitry and reprogrammable cells allow complete AC, I 5 16V8 I/O/Q
I I/O/Q
I Top 15 I/O/Q
DC, and functional testing during manufacture. As a result, Lattice
Semiconductor delivers 100% field programmability and function- I View I/O/Q GND 10 11 I/OE
I I/O/Q
ality of all GAL products. In addition, 100 erase/write cycles and I I/O/Q
data retention in excess of 20 years are specified. GND 10 11 I/OE
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. August 2006
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
16v8_11 1
Specifications GAL16V8
GAL16V8 Ordering Information
Conventional Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
3.5 2.5 3. 0 115 GAL16V8D-3LJ1 20-Lead PLCC
N ES
115 GAL16V8C-7LP 1 20-Pin Plastic DIP
115 GAL16V8D-7LJ 20-Lead PLCC
115 GAL16V8D-7LS1 20-Pin SOIC
ED
10 10 7 55 GAL16V8D-10QP 20-Pin Plastic DIP
55 GAL16V8D-10QJ 20-Lead PLCC
N VIC 115
115
115
GAL16V8D-10LP
GAL16V8D-10LJ
GAL16V8D-10LS1
20-Pin Plastic DIP
20-Lead PLCC
20-Pin SOIC
U
15 12 10 55 GAL16V8D-15QP 20-Pin Plastic DIP
55 GAL16V8D-15QJ 20-Lead PLCC
90 GAL16V8D-15LP 20-Pin Plastic DIP
C DE
90 GAL16V8D-15LJ 20-Lead PLCC
90 GAL16V8D-15LS 1 20-Pin SOIC
TI
25 15 12 55 GAL16V8D-25QP 20-Pin Plastic DIP
55 GAL16V8D-25QJ 20-Lead PLCC
90 GAL16V8D-25LP 20-Pin Plastic DIP
90 GAL16V8D-25LJ 20-Lead PLCC
D LL
90 GAL16V8D-25LS 1
20-Pin SOIC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
O
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
7.5 7 5 130 GAL16V8D-7LPI 20-Pin Plastic DIP
130 GAL16V8D-7LJI 20-Lead PLCC
IS
2
Specifications GAL16V8
Lead-Free Packaging
Commercial Grade Specifications
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
1
3.5 2.5 3. 0 115 GAL16V8D-3LJN Lead-Free 20-Lead PLCC
N ES
115 GAL16V8D-10LJN Lead-Free 20-Lead PLCC
15 12 10 55 GAL16V8D-15QPN Lead-Free 20-Pin Plastic DIP
55 GAL16V8D-15QJN Lead-Free 20-Lead PLCC
ED
90 GAL16V8D-15LPN Lead-Free 20-Pin Plastic DIP
90 GAL16V8D-15LJN Lead-Free 20-Lead PLCC
25
N VIC 15 12 55
55
90
GAL16V8D-25QPN
GAL16V8D-25QJN
GAL16V8D-25LPN
Lead-Free 20-Pin Plastic DIP
Lead-Free 20-Lead PLCC
Lead-Free 20-Pin Plastic DIP
U
90 GAL16V8D-25LJN Lead-Free 20-Lead PLCC
1. Discontinued per PCN #06-07. Contact Rochester Electronics for available inventory.
Industrial Grade Specifications
C DE
Tpd (ns) Tsu (ns) Tco (ns) Icc (mA) Ordering # Package
7.5 7 5 130 GAL16V8D-7LJNI Lead-Free 20-Lead PLCC
TI
130 GAL16V8D-7LPNI Lead-Free 20-Pin Plastic DIP
10 10 7 130 GAL16V8D-10LJNI Lead-Free 20-Lead PLCC
130 GAL16V8D-10LPNI Lead-Free 20-Pin Plastic DIP
15 12 10 13 0 GAL16V8D-15LJNI Lead-Free 20-Lead PLCC
D LL
3
Specifications GAL16V8
Output Logic Macrocell (OLMC)
N ES
three modes, while the AC1 bit of each of the macrocells controls 16L8 Complex
the input/output configuration. These two global and 16 individ- 16H8 Complex
ual architecture bits define all possible configurations in a GAL16V8 16P8 Complex
ED
. The information given on these architecture bits is only to give 10L8 Simple
a better understanding of the device. Compiler software will trans- 12L6 Simple
parently set these architecture bits from the pin definitions, so the 14L4 Simple
N VIC
user should not need to directly manipulate these architecture bits.
U
16H2 Simple
GAL16V8 emulates the PAL architecture. 10P8 Simple
12P6 Simple
14P4 Simple
16P2 Simple
C DE
ware to choose the registered mode. All combinatorial outputs with of this feedback path usage, pin 19 and pin 12 do not have the
OE controlled by the product term will force the software to choose feedback option in this mode.
O
the complex mode. The software will choose the simple mode only
when all outputs are dedicated combinatorial without OE control. In simple mode all feedback paths of the output pins are routed
The different device types listed in the table can be used to override via the adjacent pins. In doing so, the two inner most pins ( pins
A
the automatic device selection by the software. For further details, 15 and 16) will not have the feedback option as these pins are
refer to the compiler software manuals. always configured as dedicated combinatorial output.
4
Specifications GAL16V8
Registered Mode
In the Registered mode, macrocells are configured as dedicated Dedicated input or output functions can be implemented as sub-
registered outputs or as I/O functions. sets of the I/O function.
Architecture configurations available in this mode are similar to the Registered outputs have eight product terms per output. I/O's have
common 16R8 and 16RP4 devices with various permutations of seven product terms per output.
polarity, I/O and register placement.
The JEDEC fuse numbers, including the User Electronic Signature
All registered macrocells share common clock and output enable (UES) fuses and the Product Term Disable (PTD) fuses, are shown
control pins. Any macrocell can be configured as registered or I/ on the logic diagram on the following page.
O. Up to eight registers or up to eight I/O's are possible in this mode.
N ES
ED
CLK
- SYN=0.
U
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
D Q
- AC1=0 defines this output configuration.
C DE
Q - Pin 1 controls common CLK for the registered outputs.
XOR
- Pin 11 controls common OE for the registered outputs.
- Pin 1 & Pin 11 are permanently configured as CLK &
TI
OE for registered output configuration.
OE
D LL
- SYN=0.
- AC0=1.
A
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
5
Specifications GAL16V8
Registered Mode Logic Diagram
DIP & PLCC Package Pinouts
1 2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC 19
0224
XOR-2048
2 AC1-2120
N ES
0256
OLMC 18
0480
ED
XOR-2049
3 AC1-2121
0512
N VIC
4
0736
OLMC
XOR-2050
17
U
AC1-2122
0768
OLMC 16
C DE
0992
XOR-2051
5 AC1-2123
TI
1024
OLMC 15
1248
XOR-2052
6 AC1-2124
D LL
1280
O
OLMC 14
1504
XOR-2053
7 AC1-2125
A
1536
OLMC 13
IS
1760
XOR-2054
8 AC1-2126
1792
OLMC 12
2016
XOR-2055
9 AC1-2127
OE
2191 11
SYN-2192
AC0-2193
6
Specifications GAL16V8
Complex Mode
In the Complex mode, macrocells are configured as output only or bility. Designs requiring eight I/O's can be implemented in the
I/O functions. Registered mode.
Architecture configurations available in this mode are similar to the All macrocells have seven product terms per output. One product
common 16L8 and 16P8 devices with programmable polarity in term is used for programmable output enable control. Pins 1 and
each macrocell. 11 are always available as data inputs into the AND array.
Up to six I/O's are possible in this mode. Dedicated inputs or The JEDEC fuse numbers including the UES fuses and PTD fuses
outputs can be implemented as subsets of the I/O function. The are shown on the logic diagram on the following page.
two outer most macrocells (pins 12 & 19) do not have input capa-
N ES
ED
Combinatorial I/O Configuration for Complex Mode
N VIC - SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
U
XOR - AC1=1.
- Pin 13 through Pin 18 are configured to this function.
C DE
TI
Combinatorial Output Configuration for Complex Mode
D LL
- SYN=1.
O
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
XOR - AC1=1.
A
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
7
Specifications GAL16V8
Complex Mode Logic Diagram
DIP & PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC 19
0224 XOR-2048
2 AC1-2120
N ES
0256
OLMC 18
XOR-2049
ED
0480
3 AC1-2121
N VIC
4
0512
0736
OLMC
XOR-2050
AC1-2122
17
U
0768
OLMC
16
C DE
0992 XOR-2051
5 AC1-2123
TI
1024
OLMC 15
1248 XOR-2052
6 AC1-2124
D LL
1280
OLMC
O
14
1504 XOR-2053
7 AC1-2125
A
1536
OLMC 13
1760 XOR-2054
IS
8 AC1-2126
1792
OLMC 12
2016 XOR-2055
9 AC1-2127
11
2191
SYN-2192
AC0-2193
8
Specifications GAL16V8
Simple Mode
In the Simple mode, macrocells are configured as dedicated inputs Pins 1 and 11 are always available as data inputs into the AND
or as dedicated, always active, combinatorial outputs. array. The center two macrocells (pins 15 & 16) cannot be used
as input or I/O pins, and are only available as dedicated outputs.
Architecture configurations available in this mode are similar to the
common 10L8 and 12P6 devices with many permutations of ge- The JEDEC fuse numbers including the UES fuses and PTD fuses
neric output polarity or input choices. are shown on the logic diagram.
N ES
Combinatorial Output with Feedback Configuration
ED
Vcc for Simple Mode
- SYN=1.
N VIC - AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
U
XOR - AC1=0 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
C DE
TI
Combinatorial Output Configuration for Simple Mode
Vcc
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
D LL
function.
A
- SYN=1.
- AC0=0.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1 defines this configuration.
- All OLMC except pins 15 & 16 can be configured to
this function.
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
9
Specifications GAL16V8
Simple Mode Logic Diagram
DIP & PLCC Package Pinouts
1
2128
0 4 8 12 16 20 24 28 PTD
0000
OLMC
XOR-2048 19
0224 AC1-2120
2
N ES
0256
OLMC
XOR-2049 18
0480 AC1-2121
ED
3
0512
OLMC
N VIC4
0736
XOR-2050
AC1-2122
17
U
0768
OLMC
XOR-2051 16
0992 AC1-2123
C DE
5
TI
1024
OLMC
XOR-2052 15
1248 AC1-2124
6
D LL
1280
OLMC
XOR-2053 14
O
1504 AC1-2125
7
1536
OLMC
A
XOR-2054 13
1760 AC1-2126
8
IS
1792
OLMC
XOR-2055 12
2016 AC1-2127
9 11
2191
SYN-2192
AC0-2193
10
Specifications GAL16V8D
Absolute Maximum Ratings(1) Recommended Operating Conditions
Supply voltage VCC ...................................... –0.5 to +7V Commercial Devices:
Input voltage applied .......................... –2.5 to VCC +1.0V Ambient Temperature (TA) ............................... 0 to 75°C
Off-state output voltage applied ......... –2.5 to VCC +1.0V Supply voltage (VCC)
Storage Temperature ................................ –65 to 150°C with Respect to Ground ..................... +4.75 to +5.25V
Ambient Temperature with
Power Applied ........................................ –55 to 125°C Industrial Devices:
1.Stresses above those listed under the “Absolute Maximum Ambient Temperature (TA) ........................... –40 to 85°C
Ratings” may cause permanent damage to the device. These Supply voltage (VCC)
are stress only ratings and functional operation of the device at
with Respect to Ground ..................... +4.50 to +5.50V
N ES
these or at any other conditions above those indicated in the
operational sections of this specification is not implied (while
programming, follow the programming specifications).
ED
DC Electrical Characteristics
N VIC
SYMBOL PARAMETER
Over Recommended Operating Conditions (Unless Otherwise Specified)
U
VIL Input Low Voltage Vss – 0.5 — 0.8 V
IIH
TI
Input or I/O High Leakage Current 3.5V ≤ VIN ≤ VCC — — 10 μA
VOL Output Low Voltage IOL = MAX. Vin = VIL or VIH — — 0.5 V
VOH Output High Voltage IOH = MAX. Vin = VIL or VIH 2.4 — — V
Q-10/-15/-20/-25
IOS2 Output Short Circuit Current VCC = 5V VOUT = 0.5V TA= 25°C –30 — –150 mA
COMMERCIAL
IS
Q-10/-15/-25 — 45 55 mA
INDUSTRIAL
ICC Operating Power VIL = 0.5V VIH = 3.0V L -7/-10/-15/-25 — 75 130 mA
Supply Current ftoggle = 15MHz Outputs Open Q -20/-25 — 45 65 mA
1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information.
2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester
ground degradation. Characterized but not 100% tested.
3) Typical values are at Vcc = 5V and TA = 25 °C
11
Specifications GAL16V8D
AC Switching Characteristics
Over Recommended Operating Conditions
TEST -3 -5 -7
PARAMETER DESCRIPTION UNITS
COND1. MIN. MAX. MIN. MAX. MIN. MAX.
tpd A Input or I/O to Comb. Output 1 3.5 1 5 1 7.5 ns
N ES
tsu — Setup Time, Input or Feedback before Clock↑ 2.5 — 3 — 5 — ns
th
ED
— Hold Time, Input or Feedback after Clock↑ 0 — 0 — 0 — ns
A Maximum Clock Frequency with 182 — 142.8 — 100 — MHz
External Feedback, 1/(tsu + tco)
N VIC
fmax3
A Maximum Clock Frequency with
Internal Feedback, 1/(tsu + tcf)
200 — 166 — 125 — MHz
U
A Maximum Clock Frequency with 250 — 166 — 125 — MHz
No Feedback
ten
TI
B Input or I/O to Output Enabled — 4.5 1 6 1 9 ns
B OE to Output Enabled — 4.5 1 6 1 6 ns
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized but not 100% tested.
4) Characterized but not 100% tested.
A
12
Specifications
SpecificationsGAL16V8D
GAL16V8
AC Switching Characteristics
Over Recommended Operating Conditions
N ES
tcf2 — Clock to Feedback Delay — 6 — 8 — 9 — 10 ns
ED
th — Hold Time, Input or Fdbk after Clk↑ 0 — 0 — 0 — 0 — ns
A Maximum Clock Frequency with 66.7 — 45.5 — 41.6 — 37 — MHz
fmax3
N VIC A
External Feedback, 1/(tsu + tco)
U
A Maximum Clock Frequency with 83.3 — 62.5 — 50 — 41.6 — MHz
No Feedback
t B OE to Output Enabled 1 10 — 15 — 18 — 20 ns
t
D LL
C OE to Output Disabled 1 10 — 15 — 18 — 20 ns
2) Calculated from fmax with internal feedback. Refer to fmax Descriptions section.
3) Refer to fmax Descriptions section. Characterized but not 100% tested.
A
13
Specifications GAL16V8
Switching Waveforms
INPUT or
I/O FEEDBACK VALID INPUT
tsu th
CLK
INPUT or
I/O FEEDBACK VALID INPUT tco
REGISTERED
tpd OUTPUT
N ES
COMBINATIONAL 1/fmax
OUTPUT (external fdbk)
ED
Combinatorial Output Registered Output
N VIC
U
INPUT or
I/O FEEDBACK OE
(w/o fb)
FEEDBACK
Clock Width
14
Specifications GAL16V8
fmax Descriptions
CLK
LOGIC CLK
REGISTER
ARRAY
LOGIC
ARRAY
N ES
fmax with External Feedback 1/(tsu+tco)
ED
tsu and tco. t cf
CLK t pd
N VIC LOGIC
ARRAY
REGISTER
fmax with Internal Feedback 1/(tsu+tcf)
U
Note: tcf is a calculated value, derived by subtracting tsu from
the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The
tsu + th value of tcf is used primarily when calculating the delay from
clocking a register to a combinatorial output (through registered
fmax with No Feedback
C DE
feedback), as shown above. For example, the timing from clock
to a combinatorial output is equal to tcf + tpd.
Note: fmax with no feedback may be less than 1/(twh + twl). This
TI
is to allow for a clock duty cycle of other than 50%.
GAL16V8D-10
2 – 3ns 10% – 90%
O
R1
Test Condition R1 R2 CL
*C L INCLUDES TEST FIXTURE AND PROBE CAPACITANCE
A 200Ω 390Ω 50pF
B Active High ∞ 390Ω 50pF
Active Low 200Ω 390Ω 50pF
C Active High ∞ 390Ω 5pF
Active Low 200Ω 390Ω 5pF
15
Specifications GAL16V8
Switching Test Conditions (Continued)
GAL16V8D-3 Output Load Conditions (see figure at right) +1.45V
Test Condition R1 CL
A 50Ω 35pF TEST POINT
R1
B High Z to Active High at 1.9V 50Ω 35pF
High Z to Active Low at 1.0V 50Ω 35pF FROM OUTPUT (O/Q)
C Active High to High Z at 1.9V 50Ω 35pF UNDER TEST Z0 = 50Ω, CL = 35pF*
Active Low to High Z at 1.0V 50Ω 35pF
*CL includes test fixture and probe capacitance.
N ES
Electronic Signature Output Register Preload
ED
An electronic signature is provided in every GAL16V8 device. It When testing state machine designs, all possible states and state
contains 64 bits of reprogrammable memory that can contain user transitions must be verified in the design, not just those required
defined data. Some uses include user ID codes, revision numbers, in the normal machine operations. This is because, in system
N VIC
or inventory control. The signature data is always available to the
user independent of the state of the security cell.
U
tions. Changing the electronic signature will alter the checksum. illegal) state into the registers. Then the machine can be sequenced
and the outputs tested for correct next state conditions.
Security Cell
GAL16V8 devices include circuitry that allows each registered
C DE
A security cell is provided in the GAL16V8 devices to prevent un- output to be synchronously set either high or low. Thus, any present
authorized copying of the array patterns. Once programmed, this state condition can be forced for test sequencing. If necessary,
cell prevents further read access to the functional bits in the device. approved GAL programmers capable of executing text vectors
TI
This cell can only be erased by re-programming the device, so the perform output register preload automatically.
original configuration can never be examined once this cell is pro-
grammed. The Electronic Signature is always available to the user, Input Buffers
regardless of the state of this control cell.
GAL16V8 devices are designed with TTL level compatible input
D LL
-20
-40
-60
0 1.0 2.0 3.0 4.0 5.0
In p u t V o lt ag e ( V o lt s)
16
Specifications GAL16V8
Power-Up Reset
Vcc (min.)
Vcc
t su
CLK t wl
t pr
INTERNAL REGISTER Internal Register
N ES
Q - OUTPUT Reset to Logic "0"
FEEDBACK/EXTERNAL
ED
Device Pin
OUTPUT REGISTER Reset to Logic "1"
N VIC
Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1μs MAX). As a result,
the state on the registered output pins (if they are enabled) will
conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
U
always be high on power-up, regardless of the programmed As in normal system operation, avoid clocking the device until all
polarity of the output pins. This feature can greatly simplify state input and feedback path setup times have been met. The clock
machine design by providing a known state on power-up. Be- must also meet the minimum pulse width requirements.
cause of the asynchronous nature of system power-up, some
C DE
Input/Output
INPUT/OUTPUT Equivalent Schematics
EQUIVALENT SCHEMATICS
TI
PIN PIN
D LL
Feedback
O
Vcc
Active Pull-up Active Pull-up
Circuit Circuit
A
Vcc
Vcc Vcc Tri-State Vref
Vref
ESD Control
Protection
IS
Circuit
PIN Data
PIN
Output
ESD
Protection
Circuit
Feedback
Typ. Vref = 3.2V Typ. Vref = 3.2V (To Input Buffer)
Typical Input Typical Output
17
Specifications GAL16V8
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams
Normalized Tsu
Normalized Tco
1.1 PT L->H 1.1 FALL 1.1 PT L->H
1 1 1
N ES
0.8 0.8 0.8
4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50
ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
N VIC 1.3
1.2
PT H->L
1.3
1.2
RISE
1.3
1.2 PTH->L
Normalized Tpd
Normalized Tco
Normalized Tsu
PT L->H FALL PT L->H
U
1.1 1.1 1.1
1 1 1
0.8 0.8
C DE
0.8
0 0
Delta Tpd (ns)
-0.1 -0.1
Delta Tco (ns)
O
-0.2 -0.2
RISE
FALL
A
RISE
-0.3 -0.3
FALL
-0.4 -0.4
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
IS
12 12
RISE RISE
10
Delta Tco (ns)
10
Delta Tpd (ns)
FALL FALL
8 8
6 6
4 4
2 2
0 0
-2 -2
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00
18
Specifications GAL16V8
GAL16V8D-3/-5/-7 (IND PLCC): Typical AC and DC Characteristic Diagrams
4
0.75
3
Voh (V)
Voh (V)
3
Vol (V)
0.5
2
2.75
0.25
N ES
1
0 0 2.5
0 10 20 30 40 0 10 20 30 40 50 0 1 2 3 4
ED
Iol (mA) Ioh (mA) Ioh (mA)
N VIC 1.2
1.1
1.3
1.2
1.2
1.15
Normalized Icc
Normalized Icc
Normalized Icc
U
1.1
1.1
1 1.05
1
1
0.9
C DE
0.9
0.95
10
8 20
O
Delta Icc (mA)
30
Iik (mA)
6
40
50
4
A
60
2 70
80
0 90
IS
19
Specifications GAL16V8
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams
RISE
Normalized Tco
Normalized Tsu
FALL 1.1
FALL
FALL
1.05 1.05
1
1 1
0.9
0.95 0.95
N ES
0.9 0.9 0.8
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
N VIC 1.3
1.2 RISE
1.3
1.2 RISE
1.3
1.2 RISE
Normalized Tpd
Normalized Tco
Normalized Tsu
FALL FALL FALL
U
1.1 1.1 1.1
1 1 1
-0.2 -0.2
Delta Tpd (ns)
-0.3 -0.3
O
-0.4 -0.4
-0.5 -0.5
-0.6 -0.6
RISE RISE
-0.7 -0.7
FALL FALL
A
-0.8 -0.8
-0.9 -0.9
-1 -1
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
IS
RISE RISE
8 FALL 8
Delta Tpd (ns)
FALL
4 4
0 0
-4 -4
0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00
20
Specifications GAL16V8
GAL16V8D-7 (Except IND PLCC)/-10L: Typical AC and DC Characteristic Diagrams
0.4
3
3.5
Voh (V)
Voh (V)
0.3
Vol (V)
2
0.2
3
1
0.1
N ES
0 0 2.5
1 6 11 16 21 26 0 5 10 15 20 25 0.00 1.00 2.00 3.00 4.00 5.00
ED
Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq
1.1
1.15
1.1
Normalized Icc
Normalized Icc
Normalized Icc
1
U
1 1.05
0.9
0.9 1
C DE
8 10
7 20
Delta Icc (mA)
6 30
Iik (mA)
5 40
4 50
3 60
A
2 70
1 80
0 90
IS
21
Specifications GAL16V8
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams
RISE
FALL
Normalized Tpd
Normalized Tsu
PT H->L
Normalized Tco
1.1 1.1 1.1 PT H->L
PT L->H PT L->H
1 1 1
N ES
0.8 0.8 0.8
4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50 4.50 4.75 5.00 5.25 5.50
ED
Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp
N VIC 1.3
1.2 PT H->L
1.3
1.2 RISE
1.3
1.2
PT H->L
Normalized Tco
Normalized Tpd
Normalized Tsu
PT L->H FALL PT L->H
1.1 1.1 1.1
U
1 1 1
-0.2 -0.2
Delta Tpd (ns)
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
A
RISE RISE
-1 FALL -1 FALL
-1.2 -1.2
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
IS
8
Delta Tpd (ns)
FALL FALL
6
6
4
4
2
2
0
0
-2
-4 -2
-6 -4
0 50 100 150 200 250 300 0 50 100 150 200 250 300
22
Specifications GAL16V8
GAL16V8D-10Q (and Slower): Typical AC and DC Characteristic Diagrams
4 3.8
0.4
Voh (V)
Voh (V)
3 3.6
Vol (V)
2 3.4
0.2
1 3.2
N ES
0 0 3
0 10 20 30 40 0 10 20 30 40 50 0 1 2 3 4
ED
Normalized Icc vs Vcc Normalized Icc vs Temp Normalized Icc vs Freq.
1.2 1.3 1.4
N VIC 1.1
1.2 1.3
Normalized Icc
Normalized Icc
Normalized Icc
1.1 1.2
U
1 1 1.1
0.9 1
0.9
0.8 0.9
C DE
0.8 0.7 0.8
4.50 4.75 5.00 5.25 5.50 -55 -25 0 25 50 75 100 125 0 25 50 75 100
TI
Supply Voltage (V) Temperature (deg. C) Frequency (MHz)
10
6
Delta Icc (mA)
20
Iik (mA)
4 30
40
2
A
50
0 60
0 0.5 1 1.5 2 2.5 3 3.5 4 -2 -1.5 -1 -0.5 0
Vin (V) Vik (V)
IS
23
Specifications GAL16V8
Revision History
N ES
ED
N VIC
U
C DE
TI
D LL
O
A
IS
24
Mouser Electronics
Authorized Distributor
Lattice:
GAL16V8D-10LJN GAL16V8D-10LPN GAL16V8D-15LJN GAL16V8D-15LPI GAL16V8D-15LPN GAL16V8D-15QJN
GAL16V8D-15QPN GAL16V8D-25LJN GAL16V8D-25LPN GAL16V8D-25QJN GAL16V8D-25QPI GAL16V8D-
25QPN GAL16V8D-5LJ GAL16V8D-7LJN