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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_dataflow is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y : out STD_LOGIC);
end mux_dataflow;
begin
y<=((not s1) and (not s0) and i0) or ((not s1) and s0 and i1) or (s1 and (not s0) and i2) or (s1 and s0 and i3);
end Dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux_behavioral is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y : out STD_LOGIC);
end mux_behavioral;
begin
process(i0,i1,i2,i3,s1,s0)
begin
y<=i0 ;
y<=i1;
y<=i2;
else
y<=i3;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux2x1 is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
e : in STD_LOGIC;
y : out STD_LOGIC);
end mux2x1;
begin
process(i0,i1,s,e)
begin
if( e='1')then
else
y<=e;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or22 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or22;
begin
c<=a or b;
end Dataflow;
Package File Template
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package mux_testpack is
component mux2x1 is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
s : in STD_LOGIC;
e : in STD_LOGIC;
y : out STD_LOGIC);
component or22 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end mux_testpack;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mux_testpack.all;
entity mux_structural is
Port ( i0 : in STD_LOGIC;
i1 : in STD_LOGIC;
i2 : in STD_LOGIC;
i3 : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y : out STD_LOGIC);
end mux_structural;
signal t1,t2:STD_LOGIC;
begin
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_dataflow is
Port ( i : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC);
end demux_dataflow;
begin
end Dataflow;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux_behavioral is
Port ( i : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC);
end demux_behavioral;
begin
process(i,s1,s0)
begin
y0<='0';
y1<='0';
y2<='0';
y3<='0';
y0<=i;
y1<=i;
y2<=i;
else
y3<=i;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity demux1x2 is
Port ( i : in STD_LOGIC;
e : in STD_LOGIC;
s : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
end demux1x2;
begin
process(i,e,s)
begin
if( e='1')then
y0<=(not s) and i;
y1<=s and i;
else
y0<=e;
y1<=e;
end if;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package demux_testpack is
component demux1x2 is
Port ( i : in STD_LOGIC;
e : in STD_LOGIC;
s : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC);
end demux_testpack;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.demux_testpack.all;
entity demux_structural is
Port ( i : in STD_LOGIC;
s1 : in STD_LOGIC;
s0 : in STD_LOGIC;
y0 : out STD_LOGIC;
y1 : out STD_LOGIC;
y2 : out STD_LOGIC;
y3 : out STD_LOGIC);
end demux_structural;
begin
end Structural;