Byggsättsdagar 01.11.

2000

System in Package versus System on Chip

Paul Collander, IMN, Nokia Networks, Espoo, Finland
paul.collander@nokia.com and
Pekka Laukkala, Nokia Research Center, Helsinki, Finland

1. ABSTRACT

In spite of the huge R&D in chip technology world wide, single chip solutions or System on
Chip (SoC) is never applicable to real products. This paper describes old and new solutions
in packaging and interconnect (P&I) that enable designers to develop better products in
shorter time. Although even System in Package (SiP) is a delusion, this presentation
focuses on what can be integrated in a package, forgetting all user interfaces and
connections to the grid or network.

Finally CSPs are brought up as a solution to make very dense assemblies using ultra small
packages without the problem of bare-die handling.

SoC: complex chip & package

SOC - SRAM, µP, FLASH...

SiP: simpler chips & package

L, R, C SRAM
µP FLASH

Fig. 1. SoC and SiP [Amkor Technology]

2. INTRODUCTION

Under the last years, the vanguard of commercial electronic integration and packaging has
been the computer and wireless communication applications. The emphasis on packaging
in high-end products is changing from mechanical and structural support of the circuitry to
enabling the circuit’s function and optimizing its performance.

With the increasing emphasis on portable personal entertainment, communication and data
processing devices, the future electronic products will be characterized by increasing
design heterogeneity:

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• technology: digital, analog, RF, optoelectronics, MEMS, passives …

• frequency: from MHz range in digital and RF to GHz in microwave components
• architecture: low and high power analog functions together with event-driven, data-
driven and time-driven digital structures
• energy: extremely low power consumption for handheld
• other factors: form factor and weight constraints, thermal issues …

The on-chip clock frequency of a digital processor chip is today at the range of multiple
hundreds of MHz, while the assembly substrate or PWB can support only an order of
magnitude lower frequencies. The heavy penalties for transferring signals off-chip have
forced the industry to rely on single-chip integration.

The new challenge is not how many transistors can be built on a single chip, but how to
integrate diverse circuits together predictably, reliably and cost effectively. Today's
emphasis on SoC is concerned with packing different transistor technologies for different
functions on a single chip. Designers hope to merge memory with logic, mixed-signal
applications with digital, and integrated passive components with active circuits. Merging
any of the above will compromise each of the individual technologies, and increase the
complexity of the design and the manufacturing process, and thus increase the cost and
have an adverse effect on performance, reliability and time-to-market.

One solution to the problem is the System-in-Package approach, using optimized

technology for each function, opening natural path to modular design with concurrent
engineering and ability to utilize local high technology/high density interconnect.

3. TECHNOLOGY DRIVERS IN THE INDUSTRY

3.1 Optimizing system performance

Most new product introductions are radically improved versions of previous products. Very
often a number of different functionalities are merged, offering a gadget no one has dreamt
about before. All these improvements come as a result of combined integration on silicon
and advanced P&I.

When data-gadgets are getting wireless, the digital functions need to be combined with RF
transceivers making a complex system composed of processor, DSP, random digital,
memory, D/A, A/D and RF parts.

3.2 Speed and complexity

Product complexity has reached the level where R&D management is the most difficult
task. Chips come from different specialized suppliers and packaging and interconnect
need to be co-designed with chips.

Most product upgrades offer increased clock speed. These are based on combined effort
on chip and off chip. When will we see the limit to speeding up processors?

This year there is a vast interest in utilizing free or not-yet-utilized bandwidth in multi tens of
GHz frequency spectrum. GaAs chips are heavily dependent on the passives and the
features in their packages.

3.3 Design to market

The main competitive strength is based on fast time to market of complex systems. In
addition to general maximized productivity at design stations design re-use and parallel
engineering improves design to market considerably.

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If once designed and manufactured chips can be re-used in new applications saving up to 6
months in wafer fab time. For every re-used chip design the risk for non-functional system
is reduced.

3.4 Product size constraints

Not only mobile products need to be small but also everything else needs to be hide-able in
constructions. Also environmental push for less material usage pushes miniaturization.
Energy consumption is generally decreasing with miniaturization.

Generally size is minimized when as few chips are involved as possible. However due to
chip technology optimization total chip area is minimized when number of chips is
optimized in stead of minimized.

For single chip SiP applications board area is dominated by package area not by chip area
itself. Putting chips in MCMs wastes much less real estate. Chip area to board area can be
1 % for single chip packages whereas going up to 50 % in MCMs.

3.5 Power density

Chip temperature is a growing problem. Compressing more functions into a chip adds to
this problem. Also a small distance between chips in a MCM or similar decreases surface
area for heat dissipation. New cooling features need to be added.

4. MCM TECHNOLOGIES AND MANUFACTURING

System in Package is normally realized in the format of a Multichip Module (MCM), but also
a single chip package having passives integrated in the carrier external to the chip is called
SiP.

Multichip modules have been classified as tomorrow's technology, the break-trough of

which is always postponed. Looking at statistics, however, a steady growth is documented
but no big discontinuity in percentage of chips housed in multichip packages in stead of
single chip packages. As chip complexity is growing closer to its limits the pressure for
integration is spread outside the chip into packaging.

There are also some key enabling factors enabling a major increase in MCM utilization
where applicable: FlipChip availability and need and solutions for passive integration.

4.1 High density substrates

MCM is a local high technology island solving the local packaging density constraints. By
subcontracting these demanding modules system houses need not invest too much in
manufacturing technology. To assembly modern MCMs in BGA format onto PWBs demand
no new assembly technology.

The first enabling technology is high density substrates, which now are becoming available
in big enough volumes pushing cost per function low enough for the limited area needs in
MCMs. Micro-vias (µ-via) are offering dramatic size reduction but thin film on silicon, glass
or ceramic is still fighting back, especially with the help of added value integrated passives.

Also LTCC is a major player especially for RF and microwave where recessed chips
improve over-all performance.

4.2 Flip Chip: Electrical performance & weight/volume

FlipChip assembly short interconnection distance (20-80 µm) with low parasitic inductance
(around 0.1 nH) result in better signal propagation than other methods.

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Signal Path
Signal PathTop Layer Trace
Via

Bottom
Layer Trace
Ball
FlipChip BGA

Fig 2. Amkor's drawing of signal path in FlipChip and BGA.

For weight and substrate area the FlipChip solution is similar to chip and wire because the
underfill process needs same keep-out zone as wirebonding. Compared to normal
encapsulated chips (SMD, TSOP, BGA) FlipChip is a great improvement. Only Chip Scale
Packages, CSP, may enable similar packaging densities on PWB as with MCM but CSPs
on PWB are restricted to maximum 300 I/Os due to need for very expensive PWBs.

For high power chips there are solutions with both chip and wire (diebond to heat slug) and
for FlipChip (attach heat slug to back of chip after reflow and underfill). Also here
encapsulated packages are much harder to cool in spite of the larger area they occupy.

4.3 Passive integration

One of the fastest growing knowledge areas in packaging and interconnect is the methods
for passive integration on all different levels: On chip, in package and on boards. Additional
chips with passives only, Passive Integrated Devices PID, can also be used for cost and
size optimization although high-speed performance may be degraded. PIDs can be used
on either MCM substrate or directly on PWB.

Die real estate is more expensive than area of passives and substrate. Still integrating
passives may cost more than buying discrete passive chips. The benefit and advantage of
passive integration come from less component stock and fewer solder joints. Reliability, at
least in theory, can be doubled embedding passives in stead of soldering large number of
discretes.

4.4 Miniaturization

The biggest advantage of single-chip integration, as the name already implies, is the
unsurpassed density available. The performance of single-technology chips also exceeds
that of the multi-chip solution. The informed designer utilizes single chip integration as far
as is feasible but adds to the technology palette multichipping, passive integration and Chip
Scale Packaging.

A special solution suddenly conquering the electronics industry is the usage of stacked
chips. So far mainly two stacked chips in separate packages are used, but in aerospace
chip cubes are used and even multiple up on MCM substrates.

5. DESIGN AND TOOLING ISSUES

With both SoC and SIP approaches, the increasing functionality and shortening design and
product life cycles have increased the pressure for first-time-right design solutions. This
means an increasing emphasis on co-design, simulation and on-the-run verification EDA
tools.

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Regardless of the development of cross-technology design environments, like HW/SW co-

simulators and analog/digital capture tools, the design tools of today are mostly optimized
for one singular task, be it analog simulation or generation of digital logic from high-level
function description language. The tools available are mostly developed for single-
technology, either digital or analog, SoC approach. To successfully start designing SIP
solutions, the individual tools are mostly in place, but they need tighter integration.

The successful implementation of SIP design starts from the following elements:

• Design capture: the task starts, not from schematic capture, but from capturing the
specifications for the system in standardized, machine-process-able form. For SoC,
generally accepted specification and design solutions, like VHDL, already exist, but for
SIP an integrated environment is needed. Some tools like AHDL (Analog Hardware
Description Language) exist, but a structural approach applicable to all different needs
of analog circuitry in analog, digital and mixed-signal is needed.

• Reusable component models: In SoC world the idea of design reusability and IP blocks
has been generally accepted and developed. In analog world the concept is used on
chip level, but the combination of IP blocks from numerous IP-owners may not be
realistic due to difficulty to specify functions and variance in wafer fab induced
properties.

• With efficient design management, separate modular blocks can be developed in

parallel by individual designers. In best case functional blocks can be purchased as
fully tested and characterized MCMs.

For both product variation and early corrections, the opportunity to make changes on SIP
substrate or in PID is much faster than executing ASIC redesign rounds. Tooling for MCM
changes can be made in a week in stead of months for SoC.

If time to market or limited designer capacity is dominating a project design re-use in the
format of off-the-shelf available fully characterized chips may bring you a prototype in
weeks. With MCM and / or CSP technology the assembly may still be of acceptable size.
When first product is on the market a second version with more integration on chip and
more own IPR may be cost efficient for volume production.

6. PERFORMANCE OPTIMIZATION

All semiconductor technologies and their varieties have been developed for very specific
functions. Digital speed, analog speed, read/write in memory, low power operation and EMI
insensitiveness cannot be optimized all in one.

6.1 DIGITAL

Single-chip processors with embedded memories demand compromising in terms of chip

design, mask level, wafer processing, chip size, yield and testing. It is not economically
wise to integrate different function blocks with large price difference on a single chip. A
memory cell in an ASIC may cost 20 times same cell manufactured on a mass-produced
memory-only wafer.

6.2 On chip signal speed

In today's biggest chips signal speed across the chip is limited by metallization and signal
transfer capacity. Using microstrips on MCM substrate beneath the chip signal speed from
edge to edge can be improved.

Signal speed is generally lower when transmitted from package to package but
transmission lines on substrate are considerably faster than conductor lines on chip
bringing victory to SiP again.
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6.3 Wafer yield

In demanding or not yet matured technology the chip size need to be balanced against
optimal yield. This is particularly true for sensitive analog circuitry or where product life
span is too short to allow for design optimization.

6.4 RF

In RF circuits performance optimization may require that individual components use

different technologies, like semiconductor (BiCMOS, GaAs), ceramic (coupler, filter),
electromechanical (SAW, MEMS) or other, that are not suitable for integration on the same
chip. Integration in a single module is not necessarily easy but possible. Partitioning of a
system to easy enough modules, limiting assembly technologies needed for each module,
is non-trivial but well paid-off engineering. The early partitioning and technology choices
largely determine overall product cost.

6.5 Passives

Passives have been neglected for many years. It is not the sum of the purchasing costs
that matter, but firstly the elegance of utilizing existing distributed capacitance, inductance
and resistance for your benefit. Secondly, the necessarily needed passives can be
embedded in substrate, chip package or PWB, saving at least real estate and also
improving performance if done right. Even chip yield can be improved if passives are used
to buffer variance in chip performance or used for active trimming.

Fig.3 Intarsia RF module based on glass substrate, integrated passives and

wirebonded chips

6.6 MCM diversity

L, R, C SRAM
Optics µP FLASH MEMS
Embedded Antenna

Fig. 4. Amkor's view of MCM diversity

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If Flip chip assembly is needed for some chips, these should preferably be combined with
other SMD components, hopefully leaving pure chip and wire solutions on other module
substrates, having preferably integrated passives.

For RF the possibility to integrate EMI shielding in the package, e.g. GND layer in package
substrate and conductive coating on encapsulation or dropping chips into cavities solve
many SoC impossibilities when RF receiver and transmitter need to be isolated better than
90 dB.

Chip shrinks and technology changes, like changing from 0.25 to 0.18 µm process, can
more easily be accommodated in SIP without having to change the main motherboard.

6.7 Power

Power consumption may at first sight increase by going from SoC to SiP due to higher
capacitance and inductance in interconnects, but compared to chip to chip interconnects
using single chip packages, this addition is negligible.

With SIP FC and reduced parasitics the power consumption of inter-chip parasitics can be
significantly reduced.

7. TEST AND YIELD CONSIDERATIONS

Test and yield are extremely powerful factors in the cost estimation. While time spent on
test and screening should be minimized, even more important is to eliminate or scratch any
fault as early as possible before it has been integrated to other components, adding cost
but no value to the non-functional unit. The test and screen program need to be
streamlined to avoid any duplicated inspection of same details but instead check potentially
induced new failures as soon as possible after formation.

This strategy induces additional cost burden to any technology choice, where a lot of work
needs to be done un-interrupted postponing fault detection to complex and expensive sub-
units.

The yield of large silicon chip decreases with shrinking feature size and growing chip area.
SIP approach is more efficient and less risky: the yield is higher for smaller chips, and it can
be separately optimized for all the different technologies used. In the other hand the yield
still goes down with the increasing number of chips in the package, so the optimum has to
be found by suitable system level partitioning.

Large, complex mixed-signal dies are difficult to manufacture, but also to test.

Before SIP processing all chips should be functionally tested: KGD, Known Good Die. This
is the biggest single roadblock for MCM implementation. Either use small enough system
blocks (modules) that non-functional can be scrapped or integrate more but accept repair of
non-functional units.

Fig.4. BlueTooth by Amkor. A real free-standing system

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8. THE BIG PICTURE

Single chip integration will increase for at least next few years according to Moore's law.
The cost increase per product project and the investment rise in semiconductor fabs are
however exponential. For lower cost and faster time-to-market much bigger investments in
P&I are needed.

The problem is not only to assess today's technologies but to also estimate where the
technology will lead to and which new multichip packaging inventions will mature and grow
to large-scale utilization. Some technologies like the chip cube has remained limited to very
demanding, high cost, very high density applications, whereas few stacked chip packages
evolved very fast into multi-million a month volumes when mobile phones needed
increased memory density.

Today's engineering skills where every engineer has his own area of expertise and know
only vaguely the alternatives and what is designed next to his part of the system are very
far from the multi-skill, cross-scientific talents needed for fine-adjusting today's and
tomorrows demanding products.

Networking the thousands of engineers all over the World at different levels of the supply
chain is an enormous task. IWPC is trying to build an Internet based network where OEMs'
RF designers get online the properties of the latest material introductions in a format his
EDA system understands. Cross-linking the know-how of material scientists with those of
component designers and system designers is a task for numerous conferences like this.

No more is it enough to get a rat-nest prototype to function, somebody need to know the
manufacturing chain will be able to a rapid ramp-up not wasting a penny at any step and
simultaneously making the product in such a way no concerns will ever be raised about the
products environmental impact during manufacture, use or end-of-life. Who said mass-
production is easy? But it needs to be dumb cheap.

9. CONCLUSIONS

System-in-Package approach can overcome formidable integration barriers without

compromising individual chip technologies.

SIP is sometimes the only practical way to reuse IP from multiple sources, or to incorporate
a mix of semiconductor technologies.

SIP may be a gateway to early product introduction into a market whereas a SoC solution
may be more cost efficient when market is matured, volumes increased and giant chip
designs optimized.

SiP solutions have improved a lot due to advancement in chip interconnect, passive
integration, advanced substrates. But design and simulation tools are still developing and
engineering wisdom is built up painfully slow.

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