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A Best Known Method for Forming a Multi-Fab Cost Reduction Infrastructure and

Applying Innovative Cost Reduction Techniques in Diffusion.

Harel Hershkovitz Manoj Batra Third Author Name

Intel Electronics Ltd. Intel Corporation Dept. Affiliation, School/Corp.
Lachish, Israel Santa Clara, CA, USA City, State, Country
harel.hershkovitz@intel.com manoj.batra@intel.com email address@net.com

In advanced semiconductor manufacturing, capital equip-
Capital Equipment drives a significant portion of wafer
ment depreciation drives a significant fixed cost in pro-
cost. To remain competitive in the memory business, it is
ducing products. In order to remain competitive in the
critical to procure the right quantity of capital equipment.
Flash memory segment cost reduction aspects need to be
Procuring too much capital can inflate wafer cost and
in focus and it is imperative to put plans and actions in
thereby impact the ability of a business to meet its profit-
place in order to reduce the wafer cost in the early stages
ability. Procuring inadequate equipment can constrain Fab
of the technology development. This paper presents a Best
output and turn customers to competitors to meet demand,
Known Method (BKM) that describes a multi-factory cost
causing a loss of market share. Thus, it is extremely im-
infrastructure. The development and implementation of
portant to plan factories that are optimized, to meet de-
this BKM resulted in cost reduction, and specifically fo-
mand at the lowest possible cost.
cused on the various cost reduction techniques applied in
the Diffusion Clean Room Functional area. To date, 22% To plan an optimal factory, three different parameters need
Capital cost reduction has been attained for Intel Corpo- to be taken into consideration.
ration in the Diffusion area between Q1’04 to Q2’05,
1. Fluctuation of demand.
across the 200mm network
2. Lead time to order, install, and qualify equipment.
3. Technology changes during the process development
To attain the above goal it is important to have the right
structure in place with clear accountability, and well de-
fined business processes. Furthermore, the organization
needs to have the ability to balance resources between
technology development and cost reduction activities.
Since resources are a scare commodity, it is important to
adopt an 80:20 approach, and focus on a few critical items
that provide the best Return on investment (ROI).

Problem Statement
The actual wafer cost projected in 2003 was 20-22% above
the required affordability goal for 90nm Flash. If no action
was taken this would directly impact the profitability of the
Flash products group.

MRC - Infrastructure
The Factory managers sponsored a team to focus on capital
optimization and commodities reduction. The challenge
set forth to the Flash factories was to meet the affordability
goals, established by the Flash Products Division for the
90nm technology.
At the Technology Development site, a Management Re-
view Committee (MRC) was chartered to focus on cost
reduction within the 200mm network. (See Fig. 1) The

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2006 IEEE/SEMI Advanced Semiconductor Manufacturing Conference
MRC compiled a Pareto of 200mm equipment forecasts in
Capital Cost Management Structure
the systems across the flash factories. These forecasts were
segmented into N-Generation Equipment (defined as capi-
Flash (MOR)
tal needed to enable the 90nm technology node) and N-X Capacity
Long Range Plan

Generation equipment (defined as capital used for a prior Metrics

technology node). MRC Provide a Quarterly Cost Update
Process Flow to the Steering Committee
The mission set forth by the MRC was to eliminate all N-X
Generation forecasts by chartering sub-teams, also known To
w st s Manage CPI Team
as the Capital Productivity Improvement Teams (CPI Neoreca resources, address
help needed Compile projects to
Teams). Each CPI team was assigned 2-3 toolsets to focus Compile Pareto of 1. Eliminate new tool Quarterly
on. The CPI team membership consisted of Industrial En- 1. New tool
CPI Teams forecasts
2. Optimize conversion
Report Out to
the MRC
gineers, from the relevant multi-factory (200mm) network. 2. Tool Conversions
Fab xx Membership
In addition, financial analysts, commodity managers, Fab yy
Fab zz Finance, CED EDE, PE
process engineers and equipment development engineers Intel Corporation 3
(EDE’s) supported the CPI teams on an as needed basis.
On a quarterly basis, each team presented its progress to
the MRC. The MRC was responsible to manage team re- Figure 1. Capital Cost Management Structure
sources and clear roadblocks that impede team progress.

Methodology Elements: MRC Cost Structure:

Notation & definitions 1. Based on the long range demand and capacity metrics
Utilization – Machine utilization, represents the percent- published quarterly, each factory loads equipment
age of time that machine is actually running production. forecasts that are provided to suppliers on a quarterly
CPI – Capital productivity improvement team - chartered basis. Technology driven changes and demand fluc-
to focus on minimizing new machine purchases tuations are captured during the capacity metrics ap-
proval and the long range plan approval process on a
CED – Capital equipment development and procurement quarterly basis.
PE – Process Engineer 2. Every quarter, an allocation is conducted to allocate
EDE – Equipment development engineer equipment optimally within the 200mm VF Network.
MOR – Model of record OR capacity metrics datastore 3. Upon completion of the allocation the MRC seg-
mented the unique and non-unique equipment pur-
LRP – Long range plan
ROI – Return on investment
4. Each Capital Productivity Improvement (CPI) team
N Generation Equipment – Unique Capital Equipment was assigned 2 to 3 families of toolsets. The goal for
required for enabling the technology. (e.g. Advanced Li- each team was to eliminate N-X generation equipment
thography scanners, Advanced Defect Metrology) capital (non-unique) tools through optimizing reuse
N-X Generation Equipment – This is the non-unique and driving engineering improvement projects.
equipment which has been used by older technologies. N-1 5. Each CPI Team brainstormed capital avoidance pro-
denotes equipment used one generation ago. N-2 denotes jects and put plans in place to implement the projects
equipment used two generations ago. in a timely manner to avoid the purchase of equipment
(Fig. 3).
6. On a quarterly basis each CPI Team provided a stan-
dardized update to the MRC reporting the team ac-
complishments and specific help needed.
7. The MRC provided an update to the flash factory
managers on a quarterly basis.


The diffusion CPI sub-team set key indicators early on
which promoted the team to build an affordability road-
map. The indicators included the following items:

1. Keep all new machines purchases for Diffusion at
zero. - Figure 2 – Diffusion Internal Conv optimization -

2. Reduce total Intel Diffusion external capital needs by [3rd Vector] - Incorporate prior learning’s - The
15% (this was considered reasonable target) or up to CPI sub-team compiled cost saving opportunities, im-
30% (stretch goal). plemented previously by the logic and flash factories,
and partnered with Flash engineers to drive these pro-
3. Plan and execute a CPI roadmap to reduce Diffusion jects towards a successful completion.
capital needs by:
• Eliminating new machine purchases [4th Vector] - Output improvement - The team
• Minimizing the number of machine conver- partnered with the Equipment Development Engineer
sions and the commodity manager to implement a process
• Optimizing conversions with an objective to with the suppliers directly to resource productivity im-
minimize cost provements, resulting in $2.4M of capital avoidance.

There are 7 vectors that the group worked on:

[1st Vector] - Eliminate new machine forecasts - The
CPI sub-team did an extensive review of the equipment
release dates for each factory that was ramping down, and
matched them to the sites that had new forecasts. A sig-
nificant amount of negotiations were conducted to match - Figure 3 – CPI projects through all technologies -
the release dates with the need dates. Based on this method
a 50% reduction of new capital has been achieved. (Prior [5th Vector] - Machine transfer audit – The
to establishing the CPI Team: $4.5M was forecast. Pres- Team audited the internal machine conversion costs
ently only $2.2M remains as new purchases) by verifying needs vs. the quotation details received by
the suppliers: Work with the “combaya” process to
[2nd Vector] - Optimize internal machine allocations - drive down cost by optimizing the effective number of
Previously, the equipment allocation was done in a super- conversion Kits. Main targets were cost reduction
ficial manner, without delving into the details to see if a (>25% from original OEM cost).
more optimal internal allocation is feasible. The CPI sub-
team established a system that enables an optimal machine [6th Vector] - Alternate machine sourcing - The
allocation while minimizing cost (Fig. 2). team worked with the Commodity managers to identify
alternate second source suppliers to manage machines that
are considered end of life and are no longer manufactured
in the US by the primary supplier. A unique 2 Generation
approach was adopted to ensure the machine selected are
usable for at least 2 Generations.

[7th Vector] - Conversion Permutation Matrix

(CPM) - The CPI sub-team initiated a web-based matrix
that provides cost and lead-time information for all cur-
rently approved conversion permutations for CED pur-
chased machine types. In addition, this matrix documents
conversion permutations that have been deemed invalid as
well as conversions that are currently being reviewed for

90nm Wafer Cost Glide Path to
% change in Wafer Cost


















Figure 6: Wafer Cost reduction over time
From 2003 to date the wafer cost has decreased by 17%
(Fig. 6) and the gap to affordability has been reduced by
66%. Approximately $200M of capital (Fig. 5) has been
avoided across the 200mm network.
From Q1’04 to Q2’05 the Diffusion CPI sub-team
achieved a 22% cost reduction by deploying the actions
mentioned in the paper. All proactive vectors are in place
to date.
- Figure 4 Diffusion Capital Status - This equipment reuse effort has been recognized as an
outstanding accomplishment by the Technology Manufac-
turing Group at Intel.
Forming the MRC structure and chartering the sub teams
to actively focus on cost reduction, has borne significant
dividends for the 90nm Flash Memory program (Fig. 4).
Implementing a cost structure to manage capital across
multiple sites requires tremendous coordination. Over the
last two years there have been a number technology
2003-2005 CPI Team Accomplishments changes, demand fluctuations and people transitions. The
Capital Cost management infrastructure has been the key,
to have a laser focus on cost reduction in the ever changing
Total ~ $200M
Saving environment.
Setting the infrastructure early on during development,
establishing measurable goals, maintaining strong ac-
countability and strong partnership with stakeholders are
the key factors for implementing a successful cost reduc-
tion program.
Q1 2003

Q2 2003

Q3 2003

Q3 2003

Q1 2004

Q2 2004

Q3 2004

Q4 2004

Q1 2005

Q2 2005

Q3 2005

Q4 2005

We believe there is significant opportunity to make a dif-
ference to Intel’s bottom line by implementing a similar
cost structure in the 300mm factory network and to con-
tinue utilizing the structure implemented for 200mm for
Figure 5: CPI Team accomplishments across 200mm VF the 65nm and 45nm nodes.
The methodology described above has being proliferated to
other functional areas at Intel, resulting in significant im-
provements to machines quantities, capital saving and re-

REFERENCE Harel Hershkovitz – Harel Hershkovitz received his B.sc in
Industrial Engineering & Management from Shenkar Col-
[1] – Ho, C.M., & Chen, T. C., & Hseih, P., & Chu, E., &
lege, Israel & in his studies for M.Sc in Industrial Engi-
Houn, K. J., & Su, P.M., & Wang, W.C., & Sun, S. W.
neering & Management from Ben-Gurion University, Is-
Simultaneous cycle time reduction and output enhance-
rael. He is a Functional Area Manufacturing Engineer at
ment ina fully loaded foundry wafer fabrication
(2000 IEEE)
Intel Corporation in Lachish, Israel.

[2] Thielemier, C. T., & Devlin, P. J., & Wehrlin D. E. Manoj Batra – Manoj Batra received his BE in Mechanical
lost utilization – Constraint performance management Engineering from The University of Bombay, India, his
(2003 IEEE) M.Sc. in Industrial Engineering from The University of
Toledo, Ohio and his MBA in Finance from the Santa
[3] Allen, D.E., A. Kalir and K.G. Kempf,1999, Refine- Clara University. He is currently an Industrial Engineering
ment of Semiconductor Fab Capacity Planning through Group Leader with Intel in Santa Clara, CA
Dynamic Simulation, Proceedings of Winter Simulation
Conf., Phoenix, AZ, USA