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timescale is used for specifying reference time unit for

timescale <reference_time>/ <precision>


1. It is voltage controlled whereas BJT is current controlled
2. Scalability - Fortunately, MOSFET can be scaled down to a smaller
size maintaining the same current passing through it while it is ON
3. Ease of Fabrication
4. CMOS technology provides high input impedance which it
provides high drive current
5. CMOS technology provides high noise margin, packing density
6. CMOS gates dissipate power only while switching and NOT while
they are "open"(transistor off) or "close"(transistor on). Hence,
reduced power consumption.
7. Paralleling of MOSFET is easy than the transistors to handle high
current as MOSFET has positive temperature coefficient of
resistance unlike BJTs. BJTs suffer from thermal runaway. Power
is dissipated in the collector. As collector current increases, power
dissipated increases which in turn increases the collector base
junction temperature. So the process is cumulative leading
eventually to the destruction of the transistor.
 Active device – flow of e- can be controlled
 Depletion – Channel already exists at 0 Vgs (Normally ON)
 Enhancement – Channel does not exist (Inversion MOSFET–
when Vgs>0 , channel is formed) (Normally OFF)
 n channel – P type substrate
 p channel – N type substrate
 Depletion-mode devices are normally ON when the gate-source
voltage VGS = 0, whereas the enhancement-mode devices are
normally OFF when VGS = 0.
 It operates with large positive gate voltage only. It does not
conduct when the gate-source voltage VGS = 0. This is the reason
that it is called normally-off MOSFET.
 When the gate is made positive with respect to the source and the
substrate, negative (i.e. minority) charge carriers within the
substrate are attracted to the positive gate and accumulate close
to the-surface of the substrate. Called as Inversion Layer.
 Depletion MOSFET - the channel exists even for zero gate to
source voltage. In order to control the conductivity of channel the
gate terminal is reverse biased.
 The drain and transfer characteristics of depletion MOSFET are
similar except for the inverse effect of gate voltage on drain
 In N-type depletion mode MOSFET the control voltage Vgs is
negative whereas in Enhancement type MOSFET control voltage
Vgs is positive.
Devic Cutof Linear Saturated

NMO 1. Vgsn < 1. Vgsn > Vtn 1. Vgsn > Vtn

S Vtn Vin > Vtn Vin > Vtn
Vin < Vtn
2. Vdsn < Vgsn - Vtn 2. Vdsn > Vgsn - Vtn
Vout - Vss < Vin - Vout - Vss > Vin -
Vss - Vtn Vss - Vtn
Vout < Vin - Vtn Vout > Vin - Vtn

PMOS 1. Vgsp > 1. Vgsp < Vtp 1. Vgsp < Vtp

Vtp Vin < Vdd + Vtp Vin < Vdd + Vtp
Vin- Vdd >
Vtp 2. Vdsp > Vgsp - Vtp 2. Vdsp < Vgsp - Vtp
Vin > Vdd Vout - Vdd > Vin - Vout - Vdd < Vin -
+ Vtp Vdd - Vtp Vdd - Vtp
Vout > Vin - Vtp Vout < Vin - Vtp

MOSFET Amplifier
 MOSFET has extremely high input impedance which makes them
easy to bias.
 A small change in gate voltage produces a large change in drain
current as in JFET. This fact makes MOSFET capable of raising
the strength of a weak signal; thus acting as an amplifier.
 During the positive half-cycle of the signal, the positive voltage on
the gate increases and produces the enhancement-mode .This
increases the channel conductivity and hence the drain current.
 During the negative half-cycle of the signal, the positive voltage
decreases and produces depletion-mode. This decreases the
conductivity and hence the drain current.
Mealy and Moore State Machines
 A moore machine is defined as a machine in theory of
computation whose output values are determined only by its
current state.
 A mealy machine is defined as a machine in theory of computation
whose output values are determined by both its current state and
current inputs.

2nd order effects/Non-ideal effects in MOSFET:

1. Body Effect
 Body effect refers to the change in the transistor
threshold voltage (VT) resulting from a voltage difference
between the transistor source and body.
 Body effect occurs when body or substrate of transistor is not
biased at same level as that of source. The bulk voltage of
NMOS is drops below the source voltage
 As VB becomes more negative (i.e. VB < VS where VS = 0)
more holes are attracted to the substrate connection leaving a
larger negatively charged ions behind i.e. the depletion region
becomes, hence Vt increases.
 Because the voltage difference between the source and body
affects the VT, the body can be thought of as a second gate
2. Channel Length Modulation
 As the drain-to-source voltage increases, the
triode region transitions to the saturation region,
in which drain current is (ideally) independent of
drain-to-source voltage and thus influenced only
by the physical characteristics of the FET and
the gate-to-source voltage.
 The transition to saturation mode occurs because the
channel gets “pinched off” at the drain end.
 There are some subtleties to the operation of the transistor in
the saturation region.
 The length of the channel changes with changing values of
 *As the value of VDS is increased, it causes the depletion
region of the Drain junction to grow. This reduces the
channel length which impacts current.* The model current
equation must be modified to

 As Vds increases, Depletion region increases a.k.a Channel

length decreases.
 Thus, channel-length modulation means that the saturation-
region drain current will increase slightly as the drain-to-
source voltage increases.

3. Hot Electron Effect :

 When the NMOS transistor is operated in the saturation region
particularly "pinch off" condition hot carries i.e. electrons are
travelling with saturation velocity and cause parasitic effects at
the drain side of the channel. This effects are called as hot
electron effects.
 These hot electron have sufficient energy to generate the
electron-hole pairs by impact ionisation. Figure shows the
impact ionisation effect in the MOSFET.
 Therefore the hot electron effect limit the lifetime of the

4. Velocity Saturation.

From the physics of semiconductors it is proved that the velocity of

charge carriers is linearly proportional to the electric field and the
proportionality constant is called as mobility of carrier. But when we
increase the electric field beyond certain velocity called as the thermal
velocity or saturated velocity the velocity of the charge carrier does not
change with electric field as shown in Figure below.

The electric field at which the velocity of carrier saturates is called as the
critical electric field. The loss of energy is because of the collisions of
carriers called as scattering effect.
5. Mobility Variation
In the derivation of ideal I-V relationship we assumed that the mobility
was constant. This assumption must be modified for two reasons. The
first reason is the variation of mobility with gate voltage and the second
reason is that the effective carrier mobility decreases as the carrier
approaches the velocity saturation limit as discussed previously. The
inversion layer is created by a vertical electric field because of gate
voltage. A positive gate voltage produces a force on the electrons in the
inversion layer towards the surface. As the electrons travel through the
channel towards the drain they are attracted to the surface but then are
repelled by localized coulombic forces. This effect is shown in
Figure and called as surface scattering.
6. Subthreshold Conduction :
In order to address the subthreshold conduction phenomenon let us plot
IDS-VGS characteristics shown in Figure below.

A closer inspection of the IDS-VGS curve shows that the current does
not drop abruptly to '0' at VGS = VTH. It indicates that the MOS
transistor is partially conducting for voltages below the threshold voltage.
This effect is called as subthreshold or weak inversion conduction. To
study subthreshold conduction effect in more detail let us redraw the
curve of on logarithmic scale as shown in Figure below.

 From the IDS-VGS curve in log scale it is clear that current does
not drop to zero immediately for VGS < VTH but actually decays in
an exponential fashion.
 Thus even VGS < VTH IDS is finite but it exhibits exponential
dependence on VGS for smaller values of VDS roughly in the
range of 200 mV.
 In digital circuit designs the presence of subthreshold current is not
desirable because it deviates the transistor from its ideal switch
like behaviour which require that current should drop as fast as
possible once the gate to source voltage falls below VTH.
The subthreshold conduction effect can be formulated as :
IDS = I0 exp VGSn KTq

BJT eq. ckt MOSFET eq. ckt

Ic = BIb Id = Idss
[Vgs –Vth] ^2
For CMOS logic, give the various techniques you know to minimize
power consumption?

Power dissipation=CV2f, from this minimize the load capacitance, dc

voltage and the operating frequency.

For CMOS logic, give the various techniques you know to minimize
power consumption?

Power dissipation=CV2f ,from this minimize the load capacitance, dc

voltage and the operating frequency.

1. Pentavalent (valency 5); like Arsenic (As), Antimony (Sb),

Phosphorous (P), etc.

2. Trivalent (valency 3); like Indium (In), Boron (B), Aluminium (Al),

If the input of a combinational circuit changes, unwanted switching

variations may appear in the output. These variations occur when
different paths from the input to output have different delays. If, from
response to a single input change and for some combination of
propagation delay, an output momentarily goes to 0 when it should
remain a constant value of 1, the circuit is said to have a static 1-hazard.
Likewise, if the output momentarily goes to 1 when it should remain at a
constant value of 0, the circuit is said to have a 0-hazard.

Pass Transistor Logic (PTL):

 The Pass transistor logic is required to reduce the
transistors for implementing logic by using NMOS circuits.
 NMOS devices are effective in passing strong '0' but it is poor at
pulling a node to VDD. Hence when the pass transistor pulls a
node to high logic the output only changes upto VDD–VTh. This is
the major disadvantage of pass transistors.
 Figure below shows implementation of AND function using only
NMOS pass transistors. In this gate if the B input is high the left
NMOS is turned ON and copies the input A to the output F. When
B is low the right NMOS pass transistor is turned ON and passes a
'0' to the output F. This satisfies the truth table of AND gate

Types of power dissipation in CMOS inverter

Total power is the sum of the dynamic and leakage power

Total Power = Pswitching + Pshort-circuit + Pleakage

Dynamic power is the sum of two factors: switching power plus short-
circuit power.

Switching power is dissipated when charging or discharging internal and

net capacitances. Short-circuit power is the power dissipated by an
instantaneous short-circuit connection between the supply voltage and
the ground at the time the gate switches state.

Pswitching = a.f.Ceff.Vdd2

Where a = switching activity, f = switching frequency, C eff = the effective

capacitance and Vdd = the supply voltage.

Pshort-circuit = Isc.Vdd.f

Where Isc = the short-circuit current during switching, Vdd = the supply
voltage and f = switching frequency.
• Short circuit current occurs during signal transitions when
both the NMOS and PMOS are ON and there is a direct
path between Vdd and GND

• Also called crowbar current

• Accounts for more than 20% of total power dissipation

• As clock frequency increases transitions increase

consequently short circuit power dissipation increases

• Can be reduced :

– faster input and slower output

– Vdd <= Vtn + |Vtp|

Leakage power is a function of the supply voltage V dd, the switching

threshold voltage Vth, and the transistor size.

PLeakage = f (Vdd, Vth, W/L)

Where Vdd = the supply voltage, Vth = the threshold voltage, W = the
transistor width and L = the transistor length.

Hello, looking for open position in Physical Design Domain. Completed

Masters in Micro & Nanosystems, Germany. Worked as Tech. intern in
Synopsys, Hyderabad (R&D Design Group). Complete PD flow hands-
on training on 28nm tech. node (single & multi voltage designs). Like to
send my CV. Thank you.

static void decToBinary(int n)
// array to store binary number
int[] binaryNum = new int[1000];

// counter for binary array

int i = 0;
while (n > 0)
// storing remainder in binary array
binaryNum[i] = n % 2;
n = n / 2;

// printing binary array in reverse order

for (int j = i - 1; j >= 0; j--)


int num[] = new int[count];
System.out.println("Enter array elements:");
for (int i = 0; i < count; i++)
num[i] = scan.nextInt();
for (int i = 0; i < count; i++)
for (int j = i + 1; j < count; j++) {
if (num[i] > num[j])
temp = num[i];
num[i] = num[j];
num[j] = temp;


int [] arr = new int [] {1, 2, 3, 4, 2, 7, 8, 8, 3};

System.out.println("Duplicate elements in given array: ");

for (int i = 0; i < arr.length; i++) {
for (int j = i + 1; j < arr.length; j++) {
if (arr[i] == arr[j])
System.out.println(arr[j]); }

 Thermal noise is generated by thermally induced motion of electrons in
conductive regions, e.g., carbon resistors, polysilicon resistors, MOS
transistor channel in strong inversion
 Shot noise - Generated by fluctuations in static (dc) current flow through
depleted (junction) regions, e.g., in a pn junction diode, a bipolar
transistor, or MOS transistor in subthreshold regime
 Flicker noise (1/f noise) is associated with static (dc) current flow in both
conductive and depletion regions. (Shot noise is caused by the fact that
current flowing across a junction isn’t smooth). Flicker noise is also
commonly called 1/f noise, because the noise spectrum varies as 1/f^α,
where the exponent α is very close to unity (α = 1 ± 0.2). It is caused by
surface and bulk traps due to defects and contaminants that randomly
capture and release carriers
 In addition to the flicker noise caused by traps in the oxide, trapping
centers in the bulk of the device can cause generation/recombination
(G/R) noise. The trapping of carriers by these traps causes fluctuations in
the number of carriers, and thus fluctuation in the resistance.