Tunnel FETs - the Next Switch

in the Post FinFET Era?

Suman Datta
R. Pandey (Intel), M.Barth (Intel), Bijesh R. (Sandisk), H. Liu (Intel)

University of Notre Dame, Notre Dame, IN

The Pennsylvania State University, University Park, PA

2016 SEMICON WEST, CA

Moore’s Law: Dead or Alive ?
Can we increase transistor
density ?

Can we improve energy-

delay product ?

Can we continue lowering

supply voltage ?

Can we manage parasitic

resistance/capacitance ?

Can we control variation ?

IEEE Spectrum April 2015 Issue

 Different Eras of Scaling
I oni  C gate veff (Vdd  Vth )
I oni
I on 
(1  Go Rs )
I off  I o10 Vth / SS

Classical
scaling

Materials properties
scaling
New Physics ??

2020 2025
 Era of New Physics

𝑑 log10 𝐼𝐷𝑆 −1 𝑑𝜓𝑠 𝑑 log10 𝐼𝐷𝑆 −1

SS= = ≡𝑚×𝑛
𝑑𝑉𝐺 𝑑𝑉𝐺 𝑑𝜓𝑠

m
IDS Tunnel-FET Boltzmann-FET
Phase-FET (m>1, n=60)
(m>1, n<60) FinFET, NWFET
MOSFET: SS ≥ kT/q 1
IOFF TFET, Phase FET, Ferro-FET
Ferro FET, : SS < kT/q
Super-FET
IOFF
(m<1, n=60)
(m<1, n<60)
VGS (Negative Capacitance)

60 n
M. A. Alam (Purdue), A Tutorial on Landau Transistors, 2015
 Today’s Agenda
 Promise of Tunnel FETs
o sub 60 mV/decade switching with competitive on-
current

 Experiments
o materials choice
o device scaling
o performance

 Circuit and System level Benefit

o heterogeneous mixed core

 What remains ahead ?

 Tunnel FETs
MOSFET Tunnel FET
MOSFE
T

Thermionic emission Interband-tunneling

Over the barrier Through the barrier
High energy carriers in Fermi tail filtered in TFET
On Current Limitation in Tunnel FETs

S. Mookerjea, S. Datta , Device Research Conference (DRC) 2008

N-channel TFET
P-channel TFET

simulation
 Materials
P-HTFET N-HTFET
Source Drain
Tunnel Junc.
Channel
Channel NTFET
Tunnel Junc.
Drain Source

High quality abrupt hetero-junctions to maximize ION

and ION/IOFF
10
Hetero-structures growth done by IQE
 Device Challenges

Tunnel FET requirements more stringent than MOSFETs

Vertical Tunnel FET
 Vertical TFET: Fabrication
Multi-layer epi wafer Mesa definition High-K/metal gate

ILD planarization Gate, source Metallization

via definition

R. Pandey et al., VLSI 2015

 Vertical TFET: Cross-section
P-HTFET N-HTFET

GaAs0.35Sb0.65 In0.65Ga0.35As
Channel Channel
14
R. Pandey et al., VLSI 2015 False-colored TEM micro-graphs
 Enhancing ION with Gap Engineering

Bandgap engineering enhances on-current in III-V

Heterojunction Tunnel FET
15 D. Mohata, S. Datta et. al. VLSI Technology Symposium June 2012
 Tunnel Junction Abruptness
C-doped In0.65Ga0.35As
GaAs0.4Sb0.6Source Channel
3D Atom Probe Tomography in
In Sb C collaboration with Intel Corp, Hillsboro, OR
TW = 2.4 nm
Experiment Impact on ION,IOFF
60 2

IOFF [nA/m] @VGS=0V

Simulation

ION [A/m] @VGS = 0.5V

60
Concentration (at %)

40 50
40 1
20 In 30
As
Ga 20
*post-sample prep. Sb
0 0
400 410 420 430 440 0 1 2 3 4 5
Distance along tunnel junction [nm]* Tunnel interface width, TW

2.5 nm TW → 1 nm TW : 38% ION gain

 Gate Stack Engineering
Capacitance Density [F/cm2] P-HTFET N-HTFET
4

Capacitance Density [F/cm2]

150oC surface clean 4
300oC surface-clean
1.5 min H2 Plasma 9 cycles N2/TMA
3 FGA @350oC 3
FGA @400oC

2 2

1 10 KHz to 1
1MHz
10 KHz to 1MHz
0 0
-1 0 1
-1 0 1 2
Gate Voltage [V] Gate Voltage [V]
HfO2/GaAs0.35Sb0.65 ZrO2 /In0.65Ga0.35As
Interface Interface
17
R. Pandey et al., VLSI 2015 ZrO2 details: V. Chobpattana et al., APL, May 2014
 P-channel HTFET
101 250

Switching Slope [mV/dec.]

18 -3
Drain Current [A/m]

NS=810 cm
DC
0 VDS= -0.5V 200
10 10s
150 1s
-1
10 115mV/dec. T=300K
T=300K 100
-2 60 mV/dec.
10 50
DC, 10s, 1s VDS= -0.5V NS=81018cm-3
(Gate Pulse) 0
10-3
-1.5 -1.0 -0.5 0.0 10-2 10-1
Drain Current [A/m]
Gate Voltage [V]

Minimum switching slope =115mV/decade at room temp.

Fast IV measurements performed at NIST, MD

 N-channel HTFET
250

Switching Slope [mV/dec.]

102 VDS= 0.5V VDS= 0.5V T=300K
Drain Current [A/m]

101 T=300K 200

100 150
DC
10-1 100 1s
300ns 60 mV/dec.
10-2 DC, 1s, 300ns 50 55 mV/dec.
(Gate Pulse)
10-3 0
0.0 0.5 1.0 1.5 10-2 10-1 100 101
Gate Voltage [V] Drain Current [A/m]

Minimum switching slope = 55mV/decade at room temp.

Fast IV measurements performed at NIST, MD

 Benchmarking: p-TFET
240
Switching Slope, SS [mV/dec]
Han et al GaAs0.4Sb0.6/
GeSn QW In0.65Ga0.35As 1µs
VDS=-1V
VDS=-0.5 V DC
180 [6] VDS=-0.5V
[5]

s-SiGe [1] GaAs0.35Sb0.65/

120 VDS=-0.1V In Ga As [4]

0.7 0.3

Si [2] 60 mV/dec
VDS=-1V
60
Si [3]
VDS=-0.6V Desired
0 -8
10 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Drain Current, IDS [A/m]

[1] A. Villalon et al., VLSI 2012 [2] K. Jeon et al., VLSI 2010 [3] R. Gandhi et al., EDL, Nov. 2011

[4] R. Pandey et al., VLSI 2015 [6] Han et al, EDL June 2016
[5] PSU/ND June 2016
 Benchmarking: n-TFET
Switching Slope, SS [mV/dec] 200 In0.7Ga0.3As s-SiGe
[1] [6]
In0.53Ga0.47As
150
[2]

100
VDS=0.5V
InP/GaAs[3]
60 mV/dec
50 In0.65Ga0.35As/
Ge/MoS2 [4] Si-NW [5] GaAs0.4Sb0.6 [7]
Desired
0 -8
10 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101
Drain Current, IDS [A/m]

[1] H. Zhao et al, IEEE EDL, Dec. 2010 [2] M. Noguchi et al., IEDM 2013 [3] B. Ganjipour et al.,
ACS Nano, Apr. 2012
[4] D. Sarkar. et al., Nature Vol. 526, Oct. 2015 [5] L. Knoll et al., IEEE EDL, June 2013
[6] A. Villalon et al., VLSI 2012 [7] R. Pandey et al., VLSI 2015
 Trap Assisted Tunneling

3 Dominant transport mechanisms in HTFET

 Components of Transport

Switching Slope [mV/dec.]

102
Drain Current, IDS [A/m]

120 VDS=0.5V
VDS=0.5V
101 T=300K
T=300K 90
100
-1
Experiment 60 mV/dec.
10 60
Total BTBT
10-2 TCAD SRH 30 BTBT+TAT
10-3 TAT BTBT+TAT+SRH
BTBT Experiment
0 -6
0.0 0.5 1.0 1.5 10 10-5 10-4 10-3 10-2 10-1
Gate Voltage, VGS [V] Drain Current, IDS [A/m]

Reduced Dit (TAT), reduced body thickness (SRH) are

necessary for demonstrating steep slope TFETs

Slide 23
 Devices to Circuits
Look-up Table Based Verilog-A Modeling

simulation

V. Saripalli, V. Narayanan, S. Datta IEEE/ACM Nanoarch 2011.

 Lookup Table based Verilog-A model of Heterojunction Tunnel FET

 Charge Control

Normalized Capacitance, C/Cox

Normalized Capacitance, C/Cox

1.0 1.0
Si MOSFET Si TFET
0.8 VVDSDS=0.05
= 0 VV 0.8
VDSV=0.05
=0V V
0.6 0.6 DS

0.4 0.4 Cgg

Cgg
Cgd
Cgd
0.2 0.2 Cgs
Cgs
VDS = 1 V
0.0 0.0
-1.0 -0.5 0.0 0.5 1.0 -1.0 -0.5 0.0 0.5 1.0
Gate Voltage, VGS [V] Gate Voltage, VGS [V]

MOSFETs: Cgs and Cgd contribute equally towards Cgg

TFETs: Cgd is the dominant contributor towards Cgg due to
the presence of the source side tunnel barrier
S. Mookerjea, S. Datta, IEEE Electron Device Letters, 2009
 Enhanced Miller Capacitance
2.0 Vin
CL= 0 fF
1.5 Vout, TFET
VP=0.9 V
Vout, MOSFET
1.0

Voltage [V]
0.5 Si TFET
0.0
-0.5
Si MOSFET
-1.0
0 100 200 300 400 500
Time [ps]

TFETs exhibit higher transient overshoot than FinFETs due to

Miller feed through and lower ION
 Logic Performance
FO1 Inverter Energy-Delay 32-bit Adder En
2 3
10 Si FinFET 10
Total Energy [aJ]

Total Energy [fJ]

1V HTFET 1V
(a) Leakage
simulation
1 2
10 Dominate 10 0.6V
0.5V
0.6V 0.5V
0.4V 0.4V
0.5V
0.3V 0.4V
0.3V
0 0.2V 0.2V 0.15V 1 0.3V
10 10
Switching 0.2V
Activity Lg=20nm A
0.15V
Factor: 1% F
-1
1010-1 100 101 102 103 104 0
1010-2 10-1 100
Delay (ps)
[ps] Delay

TFETs show advantage over MOSFETs for supply

voltages below 0.4V
 Heterognous Core Processor

Evaluated multi-core configurations

Dark silicon Dim silicon

Run serial applications on CMOS cores in dark silicon setting
Run parallel applications on TFET cores in dim silicon setting
 Variation
Si FinFET Variance (σ2) Contribution HTFET Variance (σ2) Contribution
100% 100%

80% 80% simulation Workfunction

60% 60% GS Ovlp
S Doping Fluc
40% 40% GD Ovlp
tox
20% 20% tch

0% 0%
0.7V 0.5V 0.3V 0.2V 0.7V 0.5V 0.3V 0.2V
(a) (b)
0
10
r(RNM<26mV)

 Variation in TFETs arises from the variation in the tunnel

-3
10
barrier shape (body thickness, gate to source overlap)
-6
10 HTFET 10T ST-2
HTFET 10T ST-1
-9
10 HTFET 8T TG
 Scalability

• At Lg>4λ1/π, double gate

tunnel FETs exhibit
superior short channel
simulation
effects over MOSFETs.
• At Lg<4λ1/π, double gate
tunnel FETs exhibit
inferior short channel
effects over MOSFETs

L. Liu, D. K. Mohata, and S. Datta, "Scaling Length

The eigenvalues λn are solved from Theory of Double-Gate Interband Tunnel Field-Effect
Transistors" IEEE TED pp. 902-908, April 2012
T n Ts
 s tan( ox )   ox tan(  )
n 2 2n
s  T
1 /   (1  ox s )TsTox
2 ox 4 sTox
 Tunnel FETs for beyond 5nm ?

simulation

 Body thickness requirement more stringent for Tunnel

FETs at highly scaled technology nodes
 2D TMD Tunnel FETs
Atomically thin channels for scaled TFET operation
tox
tch
 Tunnel FETs after FINFETs ?
• Promise of Tunnel FETs
– Circuit level benefit for Vcc < 0.3V
• Experiments
– Gap engineering leading to demonstrating high Ion
– Dit improvement, body scaling leading to improved SS
• Benchmarking
– Tunnel FETs with steep slope and competitive Ion still
elusive
• Tunnel FETs are not a replacement for FinFETs
– Applications leveraging many parallel cores can benefit
from Tunnel FETs (coexisting with FinFETs)
 Acknowledgement

SRC / NIST sponsored MIND Center at

University of Notre Dame (Mid-West Institute
of Nanoelectronic Discovery)

NSF sponsored Nanosystem Engineering

Research Center (NERC) ASSIST at North
Carolina State University

THANK YOU !
 Projection
103
-0.5V -0.1V 0.1V 0.5V
0.5V N-channel TFETs
Drain Current IDS (A/m) -0.5V 0.3V Ids [3, Hej
InGaAs InGaAs,
DG [11]HJ, DG]
1
10 0.3V Ids [3, DG
InGaAs InGaAs,
[11] DG]
-0.3V GaSb/InAs
Ids R-TFET
[9, Intel, IEDM[12]2013]
-0.3V
Ge NW
Ids [12,[13]
Ge NW, GAA]
simulation
Si NW
[12,[13]
10-1 (a) -0.3V 0.7V Ids Si NW, GAA]
0.3V P-channel TFETs
Ids [14,DG
InGaAs InGaAs
[14] DG]
s-Ge DG [14] DG]
Ids[14,s-Ge,
10-3 1V GeSn [14]GeSn DG]
Ids[14,
Complementary
22nm SiSiFinFET
p-type [15] Vdp5
FinFET
10-5
60 mV/dec Ids
GNR[21,
[16]GNR]
60 mV/dec
pHTFET
GaSb-InAs Vdp5
DG [15]
10-7
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6
Gate Voltage VGS (V)

• Mixed As-Sb Complementary HTFETs primary focus of research

• Ge-Sn p-channel HTFETs remain of interest
• Graphene Nanoribbon TFETs show high ION but
gap opening remains a critical issue