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Harvard Architecture
In a computer using the Harvard architecture, the CPU can both read an instruction and
perform a data memory access at the same time, even without a cache. A Harvard
architecture computer can thus be faster for a given circuit complexity because
instruction fetches and data access do not contend for a single memory pathway .
The von Neumann architecture is a design model for a stored-program digital computer
that uses a central processing unit (CPU) and a single separate storage structure
("memory") to hold both instructions and data. It is named after the mathematician and
early computer scientist John von Neumann. Such computers implement a universal
Turing machine and have a sequential architecture.
INTRODUCTION :- The microprocessor is a clock-driven semiconductor device
consisting of electronic logic circuits manufactured by using either a large-scale
integration (LSI) or very-large-scale integration (VLSI) technique.
The microprocessor is capable of performing various computing functions and
making decisions to change the sequence of program execution.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
The basic Block Diagram of Micro Computer
Above figure consist of two main component ALU(Arithmetic and Logic Unit) and
CU ( Control Unit) .these two unit are the main functional unit of any MP but beside
these functional unit MP contains a Number of component Like Instruction Register
(IR), Program Counter (pc), Stack Pointer (SP), General Purpose Register
(GPR),Temporary Register and different set of buses .
Architecture of 8085
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
The architecture of 8085 can be divided in 5 main group namely
1> The ALU Group
2> Register Array Group
3> Instruction Register, Decoder and Control Group
4> Interrupt Control Group
5> Serial I/O Control Group
The ALU Group :-The ALU performs arithmetic operation such as addition subtraction
and logical operation such as ANDing ORing etc.
In 8085 input provided to ALU , by 8 bit Accumulator(A) and Temp. Reg.ALU of 8085
is of 8 bit so it can perform any operation on 8 bit data at a tiome.The ALU perform the
operation and put the result on 8 bit internal data bus from where it goes to “A”.
Accumulator :- It is a 8 bit GPR connected to internal data bus and ALU as shown in
above fig.It is the one of the input of the ALU. It is a general purpose nature so it can also
used to store 8 bit data Temporarily.
Temporary Register :- It is the second input of ALU. It is of 8 bit and not available for
programmer. To perform arithmetic and logical operation MP assume that one data is
available in A and takes another from other Reg/Mem(depending upon instruction) into
temp. reg. and then performs operation on the data.
Flag Register :- It is a group of flip-flops. It is connected to ALU. When an operation
performed by ALU, the result is transferred on internal data bus and status of result will
be stored in F/F.It will only give status if an operation is performed in ALU.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
Pin Configuration Of 8085
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.
AD0 - 7 (Input/Output 3state)
Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address)
appear on the bus during the first clock cycle of a machine state. It then becomes the
data bus during the second and third clock cycles. 3 stated during Hold and Halt
modes.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and
enables the address to get latched into the on chip latch of peripherals. The falling
edge of ALE is set to guarantee setup and hold times for the address information.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
ALE can also be used to strobe the status information. ALE is never 3stated.
SO, S1 (Output)
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
READ; indicates the selected memory or 1/0 device is to be read and that the Data
Bus is available for the data transfer.
WRITE; indicates the data on the Data Bus is to be written into the selected memory
or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt
modes.
READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If Ready is low, the CPU will wait for
Ready to go high before completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data
Buses. The CPU, upon receiving the Hold request. will relinquish the use of buses as
soon as the completion of the current machine cycle. Internal processing can continue.
The processor can regain the buses only after the Hold is removed. When the Hold is
acknowledged, the Address, Data, RD, WR, and IO/M(IO/M BAR) lines are 3stated.
HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and
that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold
request is removed. The CPU takes the buses one half clock cycle after HLDA goes
low.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
INTR (Input)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD(RD
BAR) during the Instruction cycle after an INTR is accepted. It can be used to activate
the 8259 Interrupt chip or some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except
they cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a
higher priority than the INTR.
TRAP (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA
flipflops. None of the other flags or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as Reset is applied.
RESET OUT (Output)
Indicates CPlJ is being reset. Can be used as a system RESET. The signal is
synchronized to the processor clock.
X1, X2 (Input)
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
Crystal or R/C network connections to set the internal clock generator X1 can also be
an external clock input instead of a crystal. The input frequency is divided by 2 to
give the internal operating frequency.
CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.
IO/M indicates whether the Read/Write is to memory or I/O Tristated during Hold and
Halt modes. If IO/M = 0 then mem. R/W operation other wise I/O R/W Op.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a
RIM instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM
instruction.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
The content of HL pair represent “M” (memory location) in the Instruction for ex MOV
C,M (this instruction move the content of M(Mem. Loc.) to reg. C. This M is defined by
HL pair where H holds Upper 8 Bit of Addr. And L holds Lower 8 bit of Addr..
Special Purpose Register (SPR) :- The 8085 contains 3 SPR named as
Program Counter (PC)
Stack Pointer (SP)
Increment Decrement Latch
Program Counter :- It is a memory pointer that’s why it is 16 bit. The MP uses this reg
to sequence the execution of the instruction. The function of the PC is to point the mem.
Location from which the next byte to be fetched (In case of one byte instruction it point
only OPCODE and In case of multiple byte it point first OPCODE then Lower order of
data and then Higher Order of data .)
Stack Pointer (SP):- It is also memory pointer it points to a memory location in R/W
memory called stack. it always point top of the stack.
Increment Decrement Latch :- This 16 bit register is used to increment or decrement
the contains of PC & SP.
FLAG REGISTER:-It is 8 bit register ,which is a set of F/F in which five flip-flops are
used, which are set or reset after an operation performed by the ALU. They are called
Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags
S Z A CY P CY
D7 D6 D5 D4 D3 D2 D1 D0
CY Flag:- If ALU Generate carry at MSB(D7 bit) the CY flag will be set other wise
reset. It work as 9th bit of result.
A CY Flag:- If an Operation performed by the ALU, generate carry at MSB of Lower
Nibble and pass it to Higher Nibble the A CY will be set . it is used by 8085 for BCD
Conversion. It not available for programming.
Z Flag:- If operation performed by ALU produce zero(all bit in result is zero) the zero
flag will set other wise reset
S Flag :- It is called Sign flag and it is the exact copy of D7 bit of result if D7 of result is
1 then S Flag will be set otherwise reset.
P Flag:- It is used to maintain ODD PARITY. In other words we can say that including
PARITY FLAG the number of ones(1’s) should be odd.
Or if the number of 1’s is even in result then P Flag will be set otherwise reset.
1(CY from MSB of Lower Nibble)
1000 1000(88 H)
+ 1000 1000(88H)
----------------------------
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
10001 0000(110H)
The ans produce 9th bit, D7 of result is 0,Number of one’s in result odd( do not include 9th
bit) , there is carry at MSB of Lower nibble which pass to LSB of Higher Nibble. so the
different condition of flag are
CY =1(set)
A CY=1(set)
Z=0(reset)
S=0(reset)
P=0(reset)
Generation of Control Signals:-
The 8085 generates a single RD signal. However, the signal needs to be used with
both memory and I/O. So, it must be combined with the IO/M signal to generate
different control signals for the memory and I/O.
IO/M + WR = MEMW(0+0=0)
(IO/M)’+RD=IOR
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
Given that ALE operates as a pulse during T1, we will be able to latch the address. Then
when ALE goes low, the address is saved and the AD7– AD0 lines can be used for their
purpose as the bi-directional data lines.
Dia. Of 74LS373
T- State: One subdivision of an operation. A T-state lasts for one clock period.
An instruction’s execution length is usually measured in a number of T-states. (clock
cycles).
Machine Cycle: The time required to complete one operation of accessing memory, I/O,
or acknowledging an external request.
This cycle may consist of 3 to 6 T-states.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
Instruction Cycle: The time required to complete the execution of an instruction.
In the 8085, an instruction cycle may consist of 1 to 6 machine cycles.
Instruction Timings and Operation Status
Steps For Fetching an Instruction(Instruction Timing)
Lets assume that we are trying to fetch the instruction at memory location 2008H. That
means that the program counter is now set to that value.
The following is the sequence of operations:
The program counter places the address value on the address bus and the controller issues
a RD signal.
The memory’s address decoder gets the value and determines which memory location is
being accessed.
The value in the memory location is placed on the data bus.
The value on the data bus is read into the instruction decoder inside the microprocessor.
After decoding the instruction, the control unit issues the proper control signals to
perform the operation.
Timing Signals For Fetching an Instruction
At T1 , the high order 8 address bits (20H) are placed on the address lines A8 – A15 and
the low order bits are placed on AD7–AD0. The ALE signal goes high to indicate that
AD0 – AD8 are carrying an address. At exactly the same time, the IO/M signal goes low
to indicate a memory operation.
At the beginning of the T2 cycle, the low order 8 address bits are removed from AD7–
AD0 and the controller sends the Read (RD) signal to the memory. The signal remains
low (active) for two clock periods to allow for slow devices. During T2 , memory places
the data from the memory location on the lines AD7– AD0
.
During T3 the RD signal is Disabled (goes high). This turns off the output Tri-state
buffers in the memory. That makes the AD7– AD0 lines go to high impedence mode.
Opcode Fetch Machine Cycle
The first step of executing any instruction is the Opcode fetch cycle.
In this cycle, the microprocessor brings in the instruction’s Opcode from memory.
To differentiate this machine cycle from the very similar “memory read” cycle, the
control & status signals are set as follows:
IO/M=0, s0 and s1 are both 1.
This machine cycle has four T-states(some time 6 T state).
The 8085 uses the first 3 T-states to fetch the opcode.
T4 is used to decode and execute it.
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
SOME POINT TO REMEMBERS
Work Station:- A powerful single user computer. it is like personal computer, but has
more powerful microprocessor and system configuration , used in engineering
application(CAD/CAM), S/W development work related to high quality graphics. High
end PC is equivalent to Low end Work station. (In Networking workstation refers to any
computer connected to local area network)
Workstation lies between PC and Minicomputer.
In the world of microcomputer(PC) the term microprocessor and CPU are used
interchangeably.
One or more microprocessor can act as Central processing Unit(CPU).
RISC ( Reduce Instruction Set Computer)
CISC(Complex Instruction Set Computer)
General purpose registers are also called “Scratch – Pad” registers.
M is also called a “Virtual register”
Some Question
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .
Saurabh Singh, Sr.Assistant Professor, Dept. Of Comp.Sc. & Engg BHILAI INSTITUTE OF
TECHNOLOGY- Durg,India
Email:- Saurabh_singh1983@rediffmail.com .