CAHAPTER 1

INTRODUCTION

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 CHAPTER1
INTRODUCTION

In the past few decades ago, the electronics industry has been experiencing an
unprecedented spurt in growth, thanks to the use of integrated circuits in computing,
telecommunications and consumer electronics. We have come a long way from the
single transistor era in 1958 to the present day ULSI (Ultra Large Scale
Integration) systems with more than 50 million transistors in a single chip [1].

The ever-growing number of transistors integrated on a chip and the increasing

transistor switching speed in recent decades has enabled great performance
improvement in computer systems by several orders of magnitude. Unfortunately,
such phenomenal performance improvements have been accompanied by an increase
in power and energy dissipation of the systems. Higher power and energy dissipation
in high performance systems require more expensive packaging and cooling
technologies, increase cost, and decrease system reliability. Nonetheless, the level of
on-chip integration and clock frequency will continue to grow with increasing
performance demands, and the power and energy dissipation of high-performance
systems will be a critical design constraint.

For example, high-end microprocessors in 2010 are predicted to employ billions of

transistors at clock rates over 30GHz to achieve TIPS (Tera Instructions per seconds)
performance [1]. With this rate, high-end microprocessor’s power dissipation is
projected to reach thousands of Watts. This thesis investigates one of the major
sources of the power/energy dissipation and proposes and evaluates the techniques to
reduce the dissipation.

Digital CMOS integrated circuits have been the driving force behind VLSI for high
performance computing and other applications, related to science and technology. The
demand for digital CMOS integrated circuits will continue to increase in the near
future, due to its important salient features like low power, reliable performance and
improvements in the processing technology.

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1.1 NEED FOR LOW POWER DESIGN

There are various interpretations of the Moore’s Law that predicts the growth rate of
integrated circuits. One estimate places the rate at 2X for every eighteen months.
Others claim that the device density increases ten-fold every seven years. Regardless
of the exact numbers, everyone agrees that the growth rate is rapid with no signs of
slowing down. New generations of processing technology are being developed while
present generation devices are at very safe distance from the fundamental physical
limits. A need for low power VLSI.

Chips arises from such evolution forces of integrated circuits. The Intel 4004
microprocessor, developed in 1971, had 2300 transistors, dissipated about 1 watts of
power and clocked at 1 MHz. Then comes the Pentium in 2001, with 42 million
transistors, dissipating around 65 watts of power and clocked at 2.40 GHz [1].

While the power dissipation increases linearly as the years go by, the power density
increases exponentially, because of the ever-shrinking size of the integrated
circuits. If this exponential rise in the power density were to increase continuously, a
microprocessor designed a few years later, would have the same power as that of
the nuclear reactor. Such high power density introduces reliability concerns such as,
electro migration, thermal stresses and hot carrier induced device degradation,
resulting in the loss of performance.

Another factor that fuels the need for low power chips is the increased market demand
for portable consumer electronics powered by batteries. The craving for smaller,
lighter and more durable electronic products indirectly translates to low power
requirements. Battery life is becoming a product differentiator in many portable
systems. Being the heaviest and biggest component in many portable systems,
batteries have not experienced the similar rapid density growth compared to the
electronic circuits. The main source of power dissipation in these high performance
battery-portable digital systems running on batteries such as note-book computers,
cellular phones and personal digital assistants are gaining prominence. For these
systems, low power consumption is a prime concern, because it directly affects the
performance by having effects on battery longevity. In this situation, low power VLSI
design has assumed great importance as an active and rapidly developing field.

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Another major demand for low power chips and systems comes from the
environmental concerns. Modern offices are now furnished with office automation
equipments that consume large amount of power. A study by American Council for
an Energy-Efficient Economy estimated that office equipment account for 5% for the
total US commercial energy usage in 1997 and could rise to 10% by the year 2004 if
no actions are taken to prevent the trend [3].

Loss from sub threshold leakage can be reduced by raising the threshold voltage and
lowering the supply voltage. Both these changes slow the circuit down significantly,
and some modern low-power circuits use dual supply voltages to provide speed on
critical parts of the circuit and lower power on non-critical paths. Some circuits even
use different transistors (with different threshold voltages) in different parts of the
circuit, in an attempt to further reduce power consumption without significant
performance loss.

Another method used to reduce static power consumption is power gating: the use of
sleep transistors to disable entire blocks when not in use. Systems which are dormant
for long periods of time and "wake up" to perform a periodic activity are often in an
isolated location monitoring an activity. These systems are generally battery-or solar-
powered; power consumption is a key design factor. By shutting down a functional
but leaky block until it is used, leakage current can be reduced significantly. For some
embedded systems that only function for short periods at a time, this can dramatically
reduce power consumption.

Two other approaches exist to lowering the power cost of state changes. One is to
reduce the operating voltage of the circuit, as in a dual-voltage CPU, or to reduce the
voltage change involved in a state change (making a state change only, changing node
voltage by a fraction of the supply voltage low voltage differential signaling, for
example). This approach is limited by thermal noise within the circuit. There is a
characteristic voltage (proportional to the device temperature and to the Boltzmann
constant), which the state switching voltage must exceed in order for the circuit to be
resistant to noise. This is typically on the order of 50–100 mV, for devices rated to
100 degrees Celsius external temperature (about 4 kT, where T is the device's internal
temperature in kelvinsand k is the Boltzmann constant).

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The second approach is to attempt to provide charge to the capacitive loads through
paths that are not primarily resistive. This is the principle behind adiabatic circuits.
The charge is supplied either from a variable-voltage inductive power supply, or by
other elements in a reversible-logic circuit. In both cases, the charge transfer must be
primarily regulated by the non-resistive load. As a practical rule of thumb, this means
the change rate of a signal must be slower than that dictated by the RC time
constant of the circuit being driven. In other words, the price of reduced power
consumption per unit computation is a reduced absolute speed of computation. In
practice although adiabatic circuits have been built, they have been difficult to use to
reduce computation power substantially in practical circuits.

Finally, there are several techniques used to reduce the number of state changes
associated with a given computation. For clocked- logic circuits the technique
of clock gating is used, to avoid changing the state of functional blocks that are not
required for a given operation. As a more-extreme alternative, the asynchronous
logic approach implements circuits in such a way that a specific externally supplied
clock is not required. While both of these techniques are used to varying extents in
integrated circuit design, the limit of practical applicability for each appears to have
been reached.

1.2 THESIS ORGANIZATION

The primary goal of this thesis is to demonstrate a circuit level design approach, for
use in designs which demand extreme low power dissipation.

This thesis is organized as follows:

CHAPTER 1: INTRODUCTION. This chapter introduces power consumption

issues in the area of VLSI.

CHAPTER 2: SOURCES OF POWER DISSIPATION AND REDUCTION

OF ENERGY IN CMOS DIGITAL CIRCUITS. This chapter briefly introduces the
different sources of power dissipation that occur in CMOS digital circuits and also
the different techniques of reducing power dissipation in CMOS digital circuits and
also the tools that have been used in this work.

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CHAPTER 3: LITERATURE SURVEY AND PROBLEM FORMULATION. This
chapter explains the principle of adiabatic switching that emerges as a new approach
to low power VLSI design.

CHAPTER 4: OPERATIONAL AND STRUCTURAL DETAILS OF PRACTICAL

ADIABATIC CIRCUITS. This chapter focuses on the operational and structural
details of the various practical adiabatic circuits. It presents a detailed account of the
steps involved in the implementation of various designs based on adiabatic logic
principle.

CHAPTER 5: DESIGN AND ANALYSIS LOW POWER CMOS CELL

STRUCTURES. This chapter gives a detailed description of the various design and
methodology used in the development of low-power cell structures at the VLSI
Design.

CHAPTER 6: PHYSICAL LAYOUT DESIGN AND POST-LAYOUT

SIMULATIONS. This chapter discusses the designs of different layouts for all the
proposed structures, which are designed in Mentor Graphics IC Station TSMC 0.35
micron Technology.

CHAPTER 7: CONCLUSIONS AND FUTURE RESEARCH. This chapter

summarizes the major accomplishments of this thesis and presents the scope for future
and further research.

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 CHAPTER 2

SOURCES OF POWER
DISSIPATION &
REDUCTION OF ENERGY
IN CMOS DIGITAL
CIRCUITS

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 CHAPTER 2
SOURCES OF POWER DISSIPATION &
REDUCTION OF ENERGY IN CMOS DIGITAL
CIRCUITS

Power consumption is one of the basic parameters of any kind of integrated circuit
(IC). Power and performance are always traded off to meet the system
requirements. Power has a direct impact on the system cost. If an IC is consuming
more power, then a better cooling mechanism would be required to keep the
circuit in normal conditions. Otherwise its performance is degraded and on
continuous use it may be permanently damaged.

The power consumption of digital CMOS circuits is generally considered in terms of

three components: The dynamic power component, related to the charging and
discharging of the load capacitance at the gate output. The short-circuit
power component. During the transition of the output line (of a CMOS gate) from one
voltage level to the other, there is a period of time when both the PMOS and the
NMOS transistors are on, thus creating a path from VDD to ground. The static
power component, due to leakage, that is present even when the circuit is not
switching. This, in turn, is composed of two components - gate to source leakage,
which is leakage directly though the gate insulator, mostly by tunnelling, and source-
drain leakage attributed to both tunnelling and sub-threshold conduction. The
contribution of the static power component to the total power number is growing very
rapidly in the current era of Deep Sub-Micrometre (DSM) Design.

Power can be estimated at a number of levels of detail. The higher levels of

abstraction are faster and handle larger circuits, but are less accurate. The main levels
include: Circuit Level Power Estimation, using a circuit simulator such as SPICE
Static Power Estimation does not use the input vectors, but may use the input
statistics. Analogous to static timing analysis. Logic-Level Power Estimation, often
linked to logic simulation. Analysis at the Register-Transfer Level. Fast and high
capacity, but not as accurate.

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Many different techniques are used to reduce power consumption at the circuit level.
Some of the main ones are:

Transistor sizing: adjusting the size of each gate or transistor for minimum power.
Voltage scaling: lower supply voltages use less power, but go slower.

Voltage islands: Different blocks can be run at different voltages, saving power. This
design practice may require the use of level-shifters when two blocks with different
supply voltages communicate with each other. Variable VDD: The voltage for a single
block can be varied during operation - high voltage (and high power) when the block
needs to go fast, low voltage when slow operation is acceptable.

Multiple threshold voltages: Modern processes can build transistors with different
thresholds. Power can be saved by using a mixture of CMOS transistors with two or
more different threshold voltages. In the simplest form there are two different
thresholds available, common called High-Vt and Low-Vt, where Vt stands for
threshold voltage. High threshold transistors are slower but leak less, and can be used
in non-critical circuits.

Power gating: This technique uses high Vt sleep transistors which cut-off a circuit
block when the block is not switching. The sleep transistor sizing is an important
design parameter. This technique, also known as MTCMOS, or Multi-Threshold
CMOS reduces stand-by or leakage power, and also enables Iddq testing. Long-
Channel transistors: Transistors of more than minimum length leak less, but are
bigger and slower.

Stacking and parking states: Logic gates may leak differently during logically
equivalent input states (say 10 on a NAND gate, as opposed to 01). State machines
may have less leakage in certain states. Logic styles: dynamic and static logic, for
example, have different speed/power tradeoffs.

2.1 POWER AND ENERGY DEFINITIONS

It is important at this point, to distinguish between energy and power. The power
consumed by a device is, by definition, the energy consumed per unit time. In other
words, the energy (E) required for a given operation is the integral of the power (P)

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consumed over the operation time (Top), hence,

E= ∫ P(t )dt (2.1)

Here, the power of digital CMOS circuit is given by

P = C VDD VS f (2.2)

where,

C is the capacitance being recharged during a transition. VDD is the supply

voltage, Vs is the voltage swing of the signal, and f is the clock frequency. If it
is assumed that an operation requires n clock cycles, Top can be expressed as n
/ f. Hence, Equation (2.1) can be rewritten as

E = n C VDD VS (2.3)

It is important to note that the energy per operation is independent of the clock
frequency. Reducing the frequency will lower the power consumption but will not
change the energy required to perform a given operation [1]. Since the energy
consumption is what determines the battery life, it is imperative to reduce the energy
rather than just the power. It is, however important to note that the power is critical
for heat dissipation considerations.

2.2 OVERVIEW OF POWER DISSIPATION

It is more convenient to talk about power dissipation of digital circuits at this point.
Although power depends greatly on the circuit style, it can be divided, in general, into
static and dynamic power. The static power is generated due to the DC bias current, as
is the case in transistor- transistor-logic (TTL), emitter-coupled logic (ECL), and N-
type MOS (NMOS) logic families, or due to leakage currents. In all of the logic
families except for the push-pull types such as CMOS, the static power tends to
dominate. That is the reason why CMOS is the most suitable circuit style for very
large scale integration (VLSI).

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CMOS is the logic family preferred in many designs due to following reasons:-

(a) Impeccable noise margins.

(b) Perfect logic levels.

(c) Negligible static power dissipation

(d) Gives good performance in most cases.

(e) Easy to get a functional circuits.

(f) Lot of tools available to automate the design process

The power consumed when the CMOS circuit is in use can be decomposed
into two basic classes: static and dynamic.

2.2.1 Static Power

The static or steady state power dissipation of a circuit is expressed by the

following relation [1]

Pstat = IstatVDD (2.4)

where,

Istat is the current that flows through the circuit when there is no
switching activity. Ideally, CMOS circuits dissipate no static (DC) power
since in the steady state there is no direct path from VDD to ground as
PMOS and NMOS transistors are never on simultaneously. Of course,
this scenario can never be realized in practice since in reality the MOS
transistor is not a perfect switch. Thus, there will always be leakage
currents and substrate injection currents, which will give to a static
component of CMOS power dissipation. For a sub-micron NMOS device W/
L = 10/ 0.5, the substrate injection current is of the order of 1- 100 µA for a
VDD of 5 V [2].

Another form of static power dissipation occurs for the so-called Ratioed
logic. Pseudo-NMOS is an example of a Ratioed CMOS logic family. In this,

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 the PMOS pull-up is always on and acts as a load device for the NMOS pull-
down network. Therefore, when the gate output is in low-state, there is a
direct path from VDD to ground and the static currents flow. In this state, the
exact value of the output voltage depends on the ratio of the strength of
PMOS and NMOS networks – hence the name. The static power consumed
by these logic families can be considerable. For this reason, logic
families such as this, which experience static power consumption,
should be avoided for low-power design. With that in mind, the static
component of power consumption in low-power CMOS circuits should be
negligible and the focus shifts primarily to dynamic power consumption.

Fig. 2.1 CMOS Inverter for Power Analysis

2.2.2 Dynamic Power

The dynamic component of power dissipation arises from the transient switching
behavior of the CMOS device. At some point during the switching transient, both the
NMOS and PMOS devices will be turned on. This occurs for gate voltages between
Vtn and VDD - Vtp . During this time, a short-circuit exists between VDD and ground
and the currents are allowed to flow. A detailed analysis of this phenomenon by
Veendrick reveals that with careful design of the transition edges, this component
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can be kept below 10-15% of the total power [2]; this can be achieved by keeping the
rise and fall times of all the signals throughout the design within a fixed range
(preferably equal). Thus, although short circuit dissipation cannot always be
completely ignored, it is certainly not the dominant component of power dissipation
in well-designed CMOS circuits. Instead, dynamic dissipation due to capacitance
charging consumes most of the power. This component of dynamic power
dissipation is the result of charging and discharging of the parasitic
capacitances in the circuit.

The situation is modeled in Figure 2.1, where the parasitic capacitances are lumped at
the output in the capacitor C. Consider the behavior of the circuit over one full cycle
of operation with the input voltage going from VDD to ground and back to VDD
again. As the input switches from high to low, the NMOS pull-down network is
cut-off and PMOS pull-up network is activated charging load capacitance C up to
VDD. This charging process draws energy equal to CVDD2 from the power supply.
Half of this is dissipated immediately in the PMOS transistors, while the other half is
stored on the load capacitance. Then, when the input returns to VDD, the
process is reversed and the capacitance is discharged, its energy being in the NMOS
network. In summary, every time a capacitive node switches from ground to VDD
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(and back to ground), energy of CV is consumed.

This leads to the conclusion that CMOS power consumption depends on the
switching activity of the signals involved. We can define activity, α as the expected
number of zero to one transition per data cycle. If this is coupled with the average
data rate, f, which may be the clock frequency in a synchronous system, then the
effective frequency of nodal charging is given the product of the activity and the data
rate: αf. This leads to the following formulation for the average CMOS power
consumption.

Pdyn = αCVDD2f (2.5)

This classical result illustrates that the dynamic power is proportional to the
switching activity, capacitive loading and the square of the supply voltage. In CMOS
circuits, this component of power dissipation is by far the most important accounting
for at least 90% of the total power dissipation [2].

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So, to reduce the power dissipation, the circuit designer can minimize the switching
event, decrease the node capacitance, reduce the voltage swing or apply a
combination of these methods. Yet, in all these cases, the energy drawn from
the power supply is used only once before being dissipated. To increase the
energy efficiency of the logic circuits, other measures can be introduced for
recycling the energy drawn from the power supply.

A novel class of logic circuits called ADIABATIC LOGIC offers the possibility of
further reducing the energy dissipated during the switching events and the possibility
of recycling or reusing some of the energy drawn from the power supply [3]. To
accomplish this goal, the circuit topology and the operating principle have to be
modified, sometimes drastically. The amount of energy recycling achievable using
adiabatic techniques is also determined by the fabrication technology, switching
speed and the voltage swing.

2.3 ENERGY-DELAY PRODUCT: A METRIC FOR LOW

ENERGY DESIGN

The scaling of VDD is beneficial from the energy point of view but may have serious
side effects on the delay. This implies that using the energy as the metric is not
sufficient. Horowitz et al. [4] have proposed an alternative which accounts for both
energy and delay by using the product of the ENERGY PER OPERATION and the
DELAY PER OPERATION. This metric can be used as the basis for design
optimization and comparison between different systems.

To minimize the energy-delay product (EDP), we need to consider the trends of

CMOS scaling and its implications on the delay. The delay of CMOS circuit will
most probably increase as the supply voltage increases. This is illustrated below in
Figure 2.2. It also shows the energy as a function of VDD.

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Fig. 2.2 Normalized delay, energy and energy-delay product vs. supply voltage. Delay is
normalized to delay value at largest supply voltage (3.0 V), and Energy is normalized to
energy value at smallest supply voltage (0.6 V)

The product of the energy and the delay, which is also shown in the same figure,
demonstrates the trade-off between the delay and the energy. For low supply
voltages, the energy is minimum but the delay is not. Increasing the supply voltage
may improve the speed but at the expense of the energy. The EDP is a metric that
accounts for both and can be used to compare different processes. The closer the
minimum of the energy-delay curve to the 1-V supply, the better the process is. The
optimum supply voltage can also be determined from the EDP.

Now, so far we have discussed the energy consumption in digital CMOS circuits. In
this section, we would look at the means of reducing the energy/ power in digital
CMOS circuits and systems.

2.4 REDUCTION OF POWER SUPPLY

The energy and power consumed by the CMOS digital circuits are sensitive to the
power supply voltage as given by:

E = CVDD2 (2.6)

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 P = CVDD2f (2.7)

Reducing the power supply voltage is an efficient approach to lower the energy and
power. The power supply voltage is actually the most crucial factor in reducing
energy/ power. This will, however, be at the expense of the delay of the circuits.
Using the EDP as a metric, one can derive the optimum supply voltage that would
yield minimum EDP.

To simplify the analysis, it will be assumed that the saturation current of deep sub
micro-meter MOSFETs is proportional to (VGS-VT)α [5]. Assuming VGS = VDD (for
maximum current) and using the delay expression, it can be shown that the delay
becomes KVDD/ (VDD-VT)α , where K is a constant independent of VDD. The EDP can
hence be expressed as

Ext=consVDD/(V-VT) (2.8)

The optimum supply voltage (for minimum EDP) can be found from Equation (2.7)
and is given by

VDD ( opt )=3Vt/(3-a) (2.9)

The above expression is valid for long-channel and deep sub micrometer devices. For
long- channel transistors (α = 2), the optimum supply voltage is equal to 3VT, which
agrees with the result of the analysis presented in [6]. For deep sub micrometer
devices with α closer to unity the optimum voltage is expected to be less than 3VT.
For example, if α = 1.5, then VDD(opt) = 2VT. At any rate, the optimum value for VDD is
proportional to the threshold voltage

So, the conclusion is that the supply voltage must be reduced to minimize the EDP.
Scaling the supply voltage below the point of minimum EDP will cause severe
degradation in the delay. The second point is that the optimum supply voltage is
related to the threshold voltage.

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2.5 REDUCTION OF SWITCHING ACTIVITY

In the previous section, the method for minimizing dynamic power consumption
in CMOS digital integrated circuits by supply voltage scaling has been discussed.
Another approach to low-power design is to reduce the switching activity and the
amount of the switched capacitance to the minimum level required to perform a given
task. The measures to accomplish this goal can range from optimization of algorithm
to logic design, and finally to physical mask design.

2.5.1 Switching Activity Reduction

Switching activity in CMOS digital integrated circuits can be reduced by algorithmic

optimization, architecture optimization, logic topology and circuit optimization. Each
of these aspects will be discussed briefly as below [7].

(a) ALGORITHMIC OPTIMIZATION. Algorithmic Optimization depends

heavily on the application and on the characteristics of the data, such as the
dynamic range, the correlation, statistics of the data transmission and so on.
Some of the techniques apply only to applications such as digital Signal
Processing (DSP) and cannot be used for general-purpose processing.
(b) ARCHITECTURE OPTIMIZATION. Several architectural techniques have
been proposed to reduce the switching activity, such as, ordering of the input
signals [7] and delay path balancing to remove glitching. In multi-level logic
circuits, the propagation delay from one logic block to the next can cause
spurious signal transitions or glitches, as a result of critical races or dynamic
hazards. In general, if all input signals of a gate change simultaneously, no
glitching occurs. But a dynamic hazard or glitch can occur if input signals
change at different times. Thus, a node can exhibit multiple transitions in a
single clock cycle before settling to the correct logic level.

2.6 REDUCTION OF SWITCHED CAPACITANCE

The amount of switched capacitance plays a significant role in the dynamic power
dissipation of the circuit as is given by Equation (2.5). Hence, the reduction of this
parasitic capacitance is a major goal for low-power design of digital integrated
circuits. The switching capacitance can be broken down into two categories, the

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capacitance in dense logic (which includes the transistor parasitic and wire
capacitances at the output of the gates) and the capacitances of the busses and a
clock network (which is mainly the wire capacitance). In some systems, the
capacitance of the busses and a clock network may comprise close to 50% of the
overall chip capacitance [7]. An example of such system is the Alpha chip.

At the system level, one of the approaches to reduce the switched capacitance is to
limit the use of shared resources. A simple example is the use of a global bus
structure for the data transmission between a large numbers of operational modules
[6].

The type of logic style used to implement a digital circuit also affects the physical
capacitance of the circuit. The physical capacitance is a function of the number of
transistors that are required to implement a given function. For example, one
approach to reduce the physical capacitance is to use transfer gates over conventional
CMOS logic gates to implement logic functions. Pass-gate logic design is attractive
since fewer transistors are required for certain functions such as XOR and XNOR. In
many arithmetic operations where binary adders and multipliers are used, pass
transistor logic offers significant advantages. Similarly, multiplexers and other key
building blocks can also be simplified using deign style.

The amount of parasitic capacitance that is switched (i.e., charged up or charged

down) during operation can also be reduced at the physical design level, or mask
level. Designing a logic gate with minimum-size transistors certainly affects the
dynamic performance of the circuit, and this trade-off between dynamic performance
and power dissipation should be carefully considered in critical circuits.
Consequently, a standard-cell based design may have considerable overhead in terms
of switched capacitance in each cell.

Several structures had been explored at the beginning of the 1980s, when the first
Power MOSFETs were introduced. However, most of them have been abandoned (at
least until recently) in favour of the Vertical Diffused MOS (VDMOS) structure (also
called Double-Diffused MOS or simply DMOS).

The cross section of a VDMOS (see figure 1) shows the "verticality" of the device: It
can be seen that the source electrode is placed over the drain, resulting in a current

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mainly vertical when the transistor is in the on-state. The "diffusion" in VDMOS
refers to the manufacturing process: the P wells (see figure 1) are obtained by a
diffusion process (actually a double diffusion process to get the P and N+ regions,
hence the name double diffused).

Power MOSFETs have a different structure than the lateral MOSFET: as with most
power devices, their structure is vertical and not planar. In a planar structure, the
current and breakdown voltage ratings are both functions of the channel dimensions
(respectively width and length of the channel), resulting in inefficient use of the
"silicon estate". With a vertical structure, the voltage rating of the transistor is a
function of the doping and thickness of the N epitaxial layer (see cross section), while
the current rating is a function of the channel width. This makes possible for the
transistor to sustain both high blocking voltage and high current within a compact
piece of silicon.

It is worth noting that power MOSFETs with lateral structure exist. They are mainly
used in high-end audio amplifiers. Their advantage is a better behaviour in the
saturated region (corresponding to the linear region of abipolar transistor) than the
vertical MOSFETs. Vertical MOSFETs are designed for switching applications, so
they are only used in On or Off states.

When in the OFF-state, the power MOSFET is equivalent to a PIN diode (constituted
by the P+ diffusion, the N− epitaxial layer and the N+ substrate). When this highly
non-symmetrical structure is reverse-biased, the space-charge region extends
principally on the light-doped side, i.e. over the N− layer. This means that this layer
has to withstand most of the MOSFET's OFF-state drain-to-source voltage.

However, when the MOSFET is in the ON-state, this N− layer has no function.
Furthermore, as it is a lightly doped region, its intrinsic resistivity is non-negligible
and adds to the MOSFET's ON-state Drain-to-Source Resistance (RDSon) (this is the
Rn resistance in figure 2).

Two main parameters govern both the breakdown voltage and the R DSon of the
transistor: the doping level and the thickness of the N− epitaxial layer. The thicker the
layer and the lower its doping level, the higher the breakdown voltage. On the
contrary, the thinner the layer and the higher the doping level, the lower the

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RDSon (and therefore the lower the conduction losses of the MOSFET). Therefore, it
can be seen that there is a trade-off in the design of a MOSFET, between its voltage
rating and its ON-state resistance. This is demonstrated by the plot.

It can be seen in figure 1 that the source metallization connects both the N+ and P
implantations, although the operating principle of the MOSFET only requires the
source to be connected to the N+ zone. However, if it were, this would result in a
floating P zone between the N-doped source and drain, which is equivalent to
a NPN transistor with a non-connected base. Under certain conditions (under high
drain current, when the on-state drain to source voltage is in the order of some volts),
this parasitic NPN transistor would be triggered, making the MOSFET uncontrollable.
The connection of the P implantation to the source metallization shorts the base of the
parasitic transistor to its emitter (the source of the MOSFET) and thus prevents
spurious latching. This solution, however, creates a diode between the drain (cathode)
and the source (anode) of the MOSFET, making it able to block current in only one
direction. Body diodes may be utilized as freewheeling diodes for inductive loads in
configurations such as bridge or half bridge. While these diodes usually have rather
high forward voltage drop, they can handle large currents and are sufficient in many
applications, reducing part count, and thus, device cost and board space. Because of
their. unipolar nature, the power MOSFET can switch at very high speed. Indeed,
there is no need to remove minority carriers as with bipolar devices.

The only intrinsic limitation in commutation speed is due to the internal capacitances
of the MOSFET (see figure 4). These capacitances must be charged or discharged
when the transistor switches. This can be a relatively slow process because the current
that flows through the gate capacitances is limited by the external driver circuit. This
circuit will actually dictate the commutation speed of the transistor (assuming the
power circuit has sufficiently low inductance).

To operate, the MOSFET must be connected to the external circuit, most of the time
using wire bonding (although alternative techniques are investigated). These
connections exhibit a parasitic inductance, which is in no way specific to the
MOSFET technology, but has important effects because of the high commutation
speeds. Parasitic inductances tend to maintain their current constant and generate
overvoltage during the transistor turn off, resulting in increasing commutation losses.

20
A parasitic inductance can be associated with each terminal of the MOSFET. They
have different effects: the gate inductance has little influence (assuming it is lower
than some hundreds of nanohenries), because the current gradients on the gate are
relatively slow. In some cases, however, the gate inductance and the input capacitance
of the transistor can constitute an oscillator. This must be avoided as it results in very
high commutation losses (up to the destruction of the device). On a typical design,
parasitic inductances are kept low enough to prevent this phenomenon; the drain
inductance tends to reduce the drain voltage when the MOSFET turns on, so it
reduces turn on losses. However, as it creates an overvoltage during turn-off, it
increases turn-off losses; the source parasitic inductance has the same behaviour as
the drain inductance, plus a feedback effect that makes commutation last longer, thus
increasing commutation losses. at the beginning of a fast turn-on, due to the source
inductance, the voltage at the source (on the die) will be able to jump up as well as the
gate voltage; the internal VGS voltage will remain low for a longer time, therefore
delaying turn-on. at the beginning of a fast turn-off, as current through the source
inductance decreases sharply, the resulting voltage across it goes negative (with
respect to the lead outside the package) raising the internal V GS voltage, keeping the
MOSFET on, and therefore delaying turn-off.

As described above, the current handling capability of a power MOSFET is

determined by its gate channel width. The gate channel width is the third (Z-axis)
dimension of the cross-sections pictured To minimize cost and size, it is valuable to
keep the transistor's die area size as small as possible. Therefore, optimizations have
been developed to increase the width of the channel surface area (i.e. increase the
"channel density"). They mainly consist of creating cellular structures repeated over
the whole area of the MOSFET die. Several shapes have been proposed for these
cells, the most famous being the International Rectifier's "Hexfet" (hexagonal shape).

Another way to increase the channel density is to reduce the size of the elementary
structure. This allows for more cells in a given surface area, and therefore more
channel width. However, as the cell size shrinks, it becomes more difficult to ensure
proper contact of every cell. To overcome this, a "strip" structure is often used (see
figure). It is less efficient than a cellular structure of equivalent resolution in terms of
channel density, but can cope with smaller pitch.

21
 CHAPTER 3

LITERATURE SURVEY
AND PROBLEM
FORMULATION

22
 CHAPTER 3
LITERATURE SURVEY AND PROBLEM
FORMULATION

LITERATURE SURVEY
The popularity of complementary MOS technology can be mainly attributed to
inherently lower power dissipation and high levels of integration. However, the
current trend towards ultra low-power has made researchers search for techniques to
recover/ recycle energy from the circuits. In the early days, researchers largely
focused on the possibility of having physical machines that consume almost zero
energy while computing and tried to find the lower bound of energy consumption In
conventional level-restoring CMOS logic circuits with rail-to-rail output voltage
swing, each switching event causes an energy transfer from the power supply to
the output node or from the output node to the ground. During a 0-to-VDD
transition of the output, the total output charge Q = Cload VDD is drawn from the

power supply at a constant voltage. Thus, an energy of Esupply = Cload VDD2 is

drawn from the power supply during this transition. Charging the output node
capacitance to the voltage level VDD means that at the end of the transition, the

amount of stored energy in the output node is Estored = Cload VDD 2 / 2. Thus,
half of the injected energy from the power supply is dissipated in the PMOS network
while only one half is delivered to the output node. During a subsequent VDD -to- 0
transition of the output node, no charge is drawn from the power supply and the
energy stored in the load capacitance is dissipated in the NMOS network.

To reduce the dissipation, the circuit designer can minimize the switching
events, decrease the node capacitance, reduce the voltage swing, or apply a
combination of these methods. Yet in all these cases, the energy drawn from the
power supply is used only once before being dissipated. To increase the energy
efficiency of the logic circuits, other measures can be introduced for recycling the
energy drawn from the power supply. A novel class of logic circuits called
adiabatic logic offers the possibility of further reducing the energy dissipated
during the switching events, and the possibility of recycling, or reusing, some of the

23
energy drawn from the power supply. To accomplish this goal, the circuit topology
and the operation principles have to be modified, sometimes drastically. The
amount of energy recycling achievable using adiabatic techniques is also determined
by the fabrication technology, switching speed, and the voltage swing.

3.1 PROBLEM FORMULATION

The word ADIABATIC comes from a Greek word that is used to describe
thermodynamic processes that exchange no energy with the environment and
therefore, no energy loss in the form of dissipated heat. In real-life computing, such
ideal process cannot be achieved because of the presence of dissipative elements like
resistances in a circuit. However, one can achieve very low energy dissipation by
slowing down the speed of operation and only switching transistors under certain
conditions. The signal energies stored in the circuit capacitances are recycled instead,
of being dissipated as heat. The adiabatic logic is also known as ENERGY
RECOVERY CMOS [3].

It should be noted that the fully adiabatic operation of the circuit is an ideal condition
which may only be approached asymptotically as the switching process is slowed
down. In most practical cases, the energy dissipation associated with a charge
transfer event is usually composed of an adiabatic component and a non-adiabatic
component. Therefore, reducing all the energy loss to zero may not possible,
regardless of the switching speed. With the adiabatic switching approach, the circuit
energies are conserved rather than dissipated as heat. Depending on the application
and the system requirements, this approach can sometimes be used to reduce the
power dissipation of the digital systems.

24
Fig. 3.1. (a) Circuit explaining Adiabatic Switching

Fig. 3.1. (b) Circuit explaining Adiabatic Switching

25
 Fig. 3.1 (c) Circuit explaining Adiabatic Switching

Here, the load capacitance is charged by a constant-current source (instead

of the constant-voltage source as in the conventional CMOS circuits).

Here, R is the resistance of the PMOS network. A constant charging current

corresponds to a linear voltage ramp. Assume, the capacitor voltage VC is zero
initially [12].

 The voltage across the switch = IR

P(t) in the switch = I2R

 Energy during charge = (I2R) T (3.1)

26
 where,

the various terms of Equation (3.3) are described as follows:

E ― energy dissipated during charging,

Q ― charge being transferred to the load,

C ― value of the load capacitance,

R ― resistance of the MOS switch turned on,

V ― final value of the voltage at the load,

T ― time spent for charging

Now, a number of observations can be made based on Equation (3.3) as follows:

(i) The dissipated energy is smaller than for the conventional case, if the
charging time T is larger than 2RC. That is, the dissipated energy can
be made arbitrarily small by increasing the charging time,
(ii) Also, the dissipated energy is proportional to R, as opposed to
the conventional case, where the dissipation depends on the capacitance and
the voltage swing. Thus, reducing the on-resistance of the PMOS network
will reduce the energy dissipation.

3.1.1 Energy Dissipation in Transistor Channel Using an Rc Model

Let us consider a simple RC model to compute the energy dissipation in a transistor

channel while working in the linear region. Consider a PMOS pass transistor, as
shown in Fig. 3.3. When the voltage at the power/ clock terminal swings from 0 to
VDD to charge node capacitance through a transistor channel, there is a voltage drop
(and hence energy dissipation) in the channel due to the channel resistance. The RC
model representing such a phenomenon is shown in Figure 3.2. Let us consider the
amount of energy dissipated when charging capacitance C from 0 to VDD in time T
with a linear power supply voltage of Figure 3.2 (b).

27
We have

(3.4)

Fig. 3.2 An RC Model

28
 Fig. 3.3 Basic Recovery Process

The energy dissipation in the above charging process can be calculated as follows
[23]:

El i near = ∫i VRdt= ∫i V dt + ∫i V dt
R R

(3.7)

29
It is clear from Equation (3.3) that the energy dissipation through the dissipative
medium can be made arbitrarily small by making the transition time T arbitrarily
large. This observation also points to the fact that for low-power dissipation, a MOS
device (or switch) should not be turned on unless the potential across it is zero or a
switch should not be disabled if current is flowing through it. The response voltage
VC over time is shown in Figure 3.4 (a) and the dissipated energy versus RC / T is
shown in Figure 3.4 (c).

30
3.1.2 Energy Dissipation from Non-Linear Mechanism

The above analysis ignores the threshold voltage drop of a transistor. Let us
consider Figure 3.2 (c). When the voltage drop Φ at the power terminal swings from
0 to VDD (as shown in the figure) to charge the node capacitance, the PMOS transistor
does not turn on until Φ exceeds the threshold voltage Vth. There is voltage drop
VDS ≈ Vth between the drain and source ends when the transistor jumps from the cut-
off region to the linear region, which results in the energy dissipation. Since an
amount of CVth charge is required the voltage to the Vth level, the energy loss due to
the threshold voltage can be approximated by
1
(3.14)

Due to the channel resistance, there is still a small voltage drop (and hence energy
dissipation) in the channel when the transistor works in the linear region. We use
Elinear to represent this amount of energy loss.

Let us use the model shown in Figure 3.2 (c) to calculate the energy dissipation. Let
us consider charging C from 0 to VDD in time T with the linear power supply
voltage of Figure 3.2 (c) (note that the power supply voltage shown in the figure
considers the effect of transistor threshold voltage drop).

(a) Voltage at RC / T = 0.1 (b) Voltages at RC / T = 0.1

31
 (c) Power Dissipation in RC model (d) Power Dissipation with a Threshold Voltage

Fig. 3.4 Linear and Non-linear Power Dissipation with the RC model [24]

Discharging consumes the same amount of energy, and hence, 11.50 % of energy is
consumed due to the non-linear mechanism (i.e., the threshold voltage). Since this
non- linear dissipation is independent of the transition time, it dominates the power
consumption when the operating frequency is low, while linear dissipation is more
significant in the higher frequency region.

3.2 A SIMPLE ADIABATIC LOGIC GATE

In the following, we will examine simple circuit configurations which can be used for
adiabatic switching. Figure 3.2 shows a general circuit topology for the conventional
CMOS gates and adiabatic counterparts. To convert a conventional CMOS logic gate
into an adiabatic gate, the pull-up and the pull-down networks must be replaced with
complementary transmission-gate (T-gate) networks. The T-gate network
implementing the pull-up function is used to drive the true output of the adiabatic
gate, while the T-gate network implementing the pull-down function drives the
complementary output node. Note that all the inputs should also be available in
complementary form. Both the networks in the adiabatic logic circuit are used to
charge-up as well as charge-down the output capacitance, which ensures that the
energy stored at the output node can be retrieved by the power supply, at the end of
each cycle. To allow adiabatic operation, the DC voltage source of the original circuit
must be replaced by a pulsed-power supply with the ramped voltage output.

32
 Fig. 3.5 (a) The general circuit topology of a conventional CMOS Logic Gate
(b) The topology of an Adiabatic Logic Gate implementing the same function
Note the difference in charge-up and charge-down paths for the output capacitance.

Note the circuit modifications which are necessary to convert a conventional CMOS
logic circuit into an adiabatic logic circuit increase the device count by a factor of two
or even more [6].

33
3.3 ADIABATIC COMPUTING

The energy CVDD2, which is consumed in the conventional CMOS circuits, is

unavoidable since the charge is transferred from the supply and returned to the
ground [9]. The current drawn from the supply during a 0 → 1 transition is
relatively large because of the large drain-source voltage. If, however, the supply
voltage can be varied in a manner that would reduce the drain current, the energy will
be significantly reduced. This can be achieved by using adiabatic circuits. Consider
the circuit shown in the Figure 3.3. This circuit is sometimes refereed to as a pulse
power supply CMOS (or PPS CMOS) [9].

Fig. 3.6 Schematic of (Adiabatic) PPS CMOS Inverter [9]

Its topology is very similar to that of the conventional CMOS inverter, except that
its supply is driven with a pulsed supply waveform ω.

Let us assume, the input is low and that the output (out) was initially low.

With the VDD being low, the drain current = 0.

Now, as the voltage supply VDD ramps up, the output follows the supply voltage VDD.

34
The drain-to-source voltage is always small and so is the current drawn from the
supply.

The adiabatic logic circuit is also known as PULSED POWER SUPPLY (PPS)
CMOS.

Fig. 3.7 The RC model of PPS CMOS Inverter

Assume that the supply is increasing in steps from 0 to VDD. Let us first derive the
energy per step as follows [11] ⇒

Between the ith-step and the next one, the supply voltage changes from Vi to Vi+1.

dV0 Vi 1  V0 
I D  IC  (3.19)
dt R

Solving this differential equation from t = ti (when the supply switches to Vi+1) to
any time t < ti+1, we get the following expression for the output voltage as a function
of time.

The PPS-CMOS can be used for the complex Boolean function implementation.
Hence, the adiabatic circuits are operable only much lesser speeds comparable
to SCMOS circuits. Another disadvantage is the requirement of a special type of
power supply.

35
3.4 POWER SUPPLIES FOR ADIABATIC CIRCUITS

The design of a power clock generator is an important part of the whole adiabatic
system design. Many studies on adiabatic logic design have been made and various
approaches have been proposed. All of them require extra circuitry for one or more
time- varying power sources to provide extended charging time. There are methods
such as those using either inductive power supplies, step-wise charging through
banks of capacitance tanks, or resonant drivers, etc.

3.4.1 Phases in an Adiabatic Power Supply

The constant-current source needed for the adiabatic operation is usually a

trapezoidal or, sinusoidal voltage source. In an adiabatic circuit, the power supply
also acts as a clock. Hence, it is given the term “power clock”. A single-phase
sinusoidal power-clock can easily be generated using resonant circuits.

Fig. 3.8 Phases in an Adiabatic Power Supply [11].

Figure 3.8 above shows a trapezoidal voltage waveform, which acts as an

adiabatic power supply. The four phases of the clock are also shown [11].

Initially, the adiabatic supply is in the IDLE / WAIT phase and the supply
voltage is LOW maintaining at the same time the outputs in the LOW state. Then the
inputs are set (one goes LOW the other HIGH) and the supply voltage ramps-up. As
the inputs are evaluated, the outputs change complementary to each other and the one
that goes HIGH follows the power supply until it reaches VDD. At that moment the
inputs are returned to the LOW state and after a certain period of time in the

36
HOLD “1” phase, the supply ramps down with the outputs following until the
LOW state is reached again. That is, to say, during the IDLE/ WAIT phase, the
circuit idles. In the EVALUATE phase, the load capacitance either charges up or
does not, depending upon the inputs to the functional blocks. In the HOLD phase, the
output is kept at steady, so that the subsequent stage can evaluate. Finally, in the
RECOVERY/ RESET phase, the charge held on the capacitance is recovered.

Any digital system with multiple stages/ cascades based upon the described adiabatic
power clocking scheme must have at least four clocks, each leading its previous
phase by 90° [11]. Practical adiabatic circuits use sinusoidal power clock. This is an
approximation of the trapezoidal waveform with the duration of the hold phase
tending to zero.

3.4.2 Design of an Adiabatic Power Supply

The adiabatic power supply needs an efficient energy recovery design which implies
quality factor Q of the power supply to be very high. Not only the Q should be high, it
should be proportional to the cycle time so that the energy dissipation in the
power supply should also decrease with the frequency. Otherwise, dissipation in the
power supply itself will dominate the logic circuit dissipation at lower frequencies.
Most preferable technique is to use sinusoidal voltage supply because of its ease to
design as compared to the pure trapezoidal wave.

The constant current charging needed can be approximated using a sinusoidal power
supply. To account for the non-constant charging current, the dissipation of
Equation (3.3) must be multiplied by a constant shape factor ξ (which takes the value
π2 / 8 for a sine-shaped current). The sinusoidal power supply can be realized using
an external inductor. Thus an LC resonant circuit with a resonance frequency

of approximately 1 is created and the energy is oscillated between the

LC
external inductor and the capacitances to be switched.

In inductor based approach [21] energy can be circulated between electrostatic

field in the load capacitor and magnetic field in the off-chip inductor. Analysis of
this approach [21] shows that by applying sinusoidal ramp, energy saved in the
circuit is reduced by the factor of π2 / 8 compared to pure trapezoidal wave and

37
the total energy consumption.

Thus, it is often simpler to reduce the voltage, V, or reduce the switched

capacitance, C, in order to save power. However when the limits of C and V have
been reached (or they are fixed), adiabatic charging proves to be the powerful tool for
reducing the dissipation below ½CV 2.

38
 CHAPTER 4

OPERATIONAL &
STRUCTURAL DETAILS
OF PRACTICAL
ADIABATIC CIRCUITS

39
 CHAPTER 4
OPERATIONAL & STRUCTURAL DETAILS
OF PRACTICAL ADIABATIC CIRCUITS

A limiting factor for the exponentially increasing integration of microelectronics is

represented by the power dissipation. Though CMOS technology provides circuits
with very low static power dissipation, during the switching operation currents are
generated, due to the discharge of load capacitances that cause a power dissipation
increasing with the clock frequency. The adiabatic technique prevents such losses: the
charge does not flow from the supply voltage to the load capacitance and then to
ground, but it flows back to a trapezoidal or sinusoidal supply voltage and can be
reused. Just losses due to the resistance of the switches needed for the logic operation
still occur. In order to keep these losses small, the clock frequency has to be much
lower than the technological limit.

In the literature, a multitude of adiabatic logic families are proposed [13] - [18]. Each
different implementation shows some particular advantages, but there are also some
basic drawbacks for these circuits. The following paragraphs below will deal with
these different adiabatic logic families. Let’s see the details about each of these.

There are some classical approaches to reduce the dynamic power such as reducing
supply voltage, decreasing physical capacitance and reducing switching activity.
These techniques are not fit enough to meet today’s power requirement. However,
most research has focused on building adiabatic logic, which is a promising design for
low power applications. Adiabatic logic works with the concept of switching activities
which reduces the power by giving stored energy back to the supply. Thus, the term
adiabatic logic is used in low-power VLSI circuits which implements reversible logic.
In this, the main design changes are focused in power clock which plays the vital role
in the principle of operation. Each phase of the power clock gives user to achieve the
two major design rules for the adiabatic circuit design.

 Never turn on a transistor if there is a voltage across it (VDS>0)

 Never turn off a transistor if there is a current through it (IDS≠ 0)

40
  Never pass current through a diode

If these conditions with regard to the inputs, in all the four phases of power clock,
recovery phase will restore the energy to the power clock, resulting considerable
energy saving. Yet some complexities in adiabatic logic design perpetuate. Two such
complexities, for instance, are circuit implementation for time-varying power sources
needs to be done and computational implementation by low overhead circuit
structures needs to be followed. There are two big challenges of energy recovering
circuits; first, slowness in terms of today’s standards, second it requires ~50% of more
area than conventional CMOS, and simple circuit designs get complicated. The basic
concepts of adiabatic logic will be introduced. “Adiabatic” is a term of Greek origin
that has spent most of its history associated with classical thermodynamics. It refers to
a system in which a transition occurs without energy (usually in the form of heat)
being either lost to or gained from the system. In the context of electronic systems,
rather than heat, electronic charge is preserved. Thus, an ideal adiabatic circuit would
operate without the loss or gain of electronic charge. The first usage of the term
“Adiabatic” in this context appears to be traceable back to a paper presented in 1992
at the Second Workshop on Physics and Computation. Although an earlier suggestion
of the possibility of energy recovery was made by Bennett where in relation to the
energy used to perform computation, he stated “This energy could in principle be
saved and reused”.

Etymology of the term “adiabatic logic”. Because of the Second Law of

Thermodynamics, it is not possible to completely convert energy into useful work.
However, the term “Adiabatic Logic” is used to describe logic families that could
theoretically operate without losses, and the term “Quasi-Adiabatic Logic” is used to
describe logic that operates with a lower power than static CMOS logic, but which
still has some theoretical non-adiabatic losses. In both cases, the nomenclature is used
to indicate that these systems are capable of operating with substantially less power
dissipation than traditional static CMOS circuits.

There are several important principles that are shared by all of these low-power
adiabatic systems. These include only turning switches on when there is no potential
difference across them, only turning switches off when no current is flowing through
them, and using a power supply that is capable of recovering or recycling energy in

41
the form of electric charge. To achieve this, in general, the power supplies of
adiabatic logic circuits have used constant current charging (or an approximation
thereto), in contrast to more traditional non-adiabatic systems that have generally used
constant voltage charging from a fixed-voltage power supply.

The power supplies of adiabatic logic circuits have also used circuit elements capable
of storing energy. This is often done using inductors, which store the energy by
converting it to magnetic flux, or, as in case of Asynchrobatic Logic, by using
capacitors, which can directly store electric charge. There are a number of synonyms
that have been used by other authors to refer to adiabatic logic type systems, these
include: “Charge recovery logic”, “Charge recycling logic”, “Clock-powered logic”,
“Energy recovery logic” and “Energy recycling logic” . Because of the reversibility
requirements for a system to be fully adiabatic, most of these synonyms actually refer
to, and can be used inter-changeably, to describe quasi-adiabatic systems. These terms
are succinct and self-explanatory, so the only term that warrants further explanation is
“Clock-Powered Logic”. This has been used because many adiabatic circuits use a
combined power supply and clock, or a “power- clock”. This variable, usually multi-
phase, power-supply which controls the operation of the logic by supplying energy to
it, and subsequently recovering energy from it.

4.1 DIFFERENT ADIABATIC LOGIC FAMILIES

Practical adiabatic families can be classified as either PARTIALLY ADIABATIC or
FULLY ADIABATIC [12]. In a PARTIALLY ADIABATIC CIRCUIT, some charge
is allowed to be transferred to the ground, while in a FULLY ADIABATIC
CIRCUIT, all the charge on the load capacitance is recovered by the power supply.
Fully adiabatic circuits face a lot of problems with respect to the operating speed and
the inputs power clock synchronization.

Popular Partially Adiabatic families include the following:

i. Efficient Charge Recovery Logic (ECRL).

ii. 2N-2N2P Adiabatic Logic.

iii. Positive Feedback Adiabatic Logic (PFAL).

iv. NMOS Energy Recovery Logic (NERL).

42
v. Clocked Adiabatic Logic (CAL).

vi. True Single-Phase Adiabatic Logic (TSEL).

vii. Source-coupled Adiabatic Logic (SCAL).

Some Fully adiabatic logic families include:

i. Pass Transistor Adiabatic Logic (PAL).

ii. Split- Rail Charge Recovery Logic (SCRL).

4.2 EFFICIENT CHARGE – RECOVERY LOGIC (ECRL)

Efficient Charge – Recovery Logic (ECRL) proposed by Moon and Jeong [13],
shown in Figure 4.1, uses cross-coupled PMOS transistors. It has the structure similar
to Cascode Voltage Switch Logic (CVSL) with differential signaling.

It consists of two cross-coupled transistors M1 and M2 and two NMOS transistors

in the N-functional blocks for the ECRL adiabatic logic block [13].

An AC power supply pwr is used for ECRL gates, so as to recover and reuse the
supplied energy. Both out and /out are generated so that the power clock
generator can always drive a constant load capacitance independent of the input
signal. A more detailed description of ECRL can be found in [13]. Full output swing
is obtained because of the cross-coupled PMOS transistors in both precharge and
recover phases. But due to the threshold voltage of the PMOS transistors, the circuits
suffer from the non-adiabatic loss both in the precharge and recover phases. That is,
to say, ECRL always pumps charge on the output with a full swing. However, as the
voltage on the supply clock approaches to

|Vtp|, the PMOS transistor gets turned off.

43
 Fig. 4.1 The Basic Structure of the Adiabatic ECRL Logic

So the recovery path to the supply clock to the supply clock is disconnected, thus,
resulting in incomplete recovery. Vtp is the threshold voltage of PMOS transistor. The
amount of loss is given as

EECRL = C|Vtp|2 / 2 (4.2)

Thus, from Equation (4.2), it can be inferred that the non-adiabatic energy loss is
dependent on the load capacitance and independent of the frequency of operation.

The ECRL circuits are operated in a pipelining style with the four-phase supply
clocks. When the output is directly connected to the input of the next stage (which is a
combinational logic), only one phase is enough for a logic value to propagate.
However, when the output of a gate is fed back to the input, the supply clocks should
be in phase. A latch is one of the simplest cases which have a feedback path. The
input signals propagate to the next stage in a single phase, and the input values are
stored in four phases (1-clock) safely.

Let us assume in is at high and inb is at low. At the beginning of a cycle, when the
supply clock ‘pwr’ rises from zero to VDD , out remains at a ground level, because in
turns on F- tree (NMOS logic tree). /out follows pwr through M1. When pwr reaches
VDD, the outputs hold valid logic levels. These values are maintained during the hold

44
phase and used as inputs for the evaluation of the next stage. After the hold phase,
pwr falls down to a ground level, /out node returns its energy to pwr so that the
delivered charge is recovered. Thus, the clock pwr acts as both a clock and power
supply.

A major disadvantage of this circuit is the existence of the coupling effects, because
the two outputs are connected by the PMOS latch and the two complementary outputs
can interfere each other.

4.3 2N-2N2P ADIABATIC LOGIC

This was proposed as a modification to ECRL logic, in order to reduce the coupling
effects. Figure 4.2 shows the general schematic of the 2N-2N2P logic. The 2N-
2N2P logic [14] uses a cross-coupled latch of two PMOSFETs and two NMOSFETs
(M1-M4), as shown in the Figure 4.2, instead of only two NMOSFETs as in ECRL
logic family.

The N-functional block is in parallel with NMOSFETs of the latch and thus occupies
additional area, but the primary advantage of 2N-2N2P over ECRL is that the cross-
coupled NMOSFETS switches result in non-floating outputs for large part of the
recovery phase.

Fig. 4.2 The Basic Structure of the Adiabatic 2N-2N2P Logic

45
The 2N-2N2P uses two cross-coupled PMOS transistors for both pre-charge
and recovery.

4.4 POSITIVE FEEDBACK ADIABATIC LOGIC (PFAL)

The partial energy recovery circuit structure named Positive Feedback Adiabatic
Logic (PFAL) [15] has been used, since it shows the lowest energy consumption if
compared to other similar families, and a good robustness against technological
parameter variations. It is a dual-rail circuit with partial energy recovery. The general
schematic of the PFAL gate is shown in Figure 4.3. The core of all the PFAL gates is
an adiabatic amplifier, a latch made by the two PMOS M1-M2 and two NMOS M3-
M4, that avoids a logic level degradation on the output nodes out and /out. The two
n-trees realize the logic functions. This logic family also generates both positive and
negative outputs. The functional blocks are in parallel with the PMOSFETs of the
adiabatic amplifier and form a transmission gate. The two n-trees realize the logic
functions. This logic family also generates both positive and negative outputs.

The two major differences with respect to ECRL are that the latch is made by two
PMOSFETs and two NMOSFETS, rather than by only two PMOSFETs as in
ECRL logic, and that the functional blocks are in parallel with the transmission
PMOSFETs. Thus the equivalent resistance is smaller when the capacitance needs
to be charged. The energy dissipation by the CMOS Logic family and Adiabatic
PFAL Logic family can be seen as in Figure 4.4.

Fig. 4.3 The Basic Structure of the Adiabatic PFAL Logic

46
Fig.4.4 Comparison of the Energy Dissipation by CMOS Logic and an Adiabatic PFAL
Logic (Simulated with ELDO Simulator of Mentor Graphics Corporation, in Standard
TSMC 0.35 µm Technology)

PFAL uses a four-phase power-clock pwr ø (t) as shown in Figure 3.7: ø (t) rises
from 0 to VDD in the EVALUATE PHASE (E) and supplies energy to the circuit,
then ø (t) returns to 0 in the RECOVERY PHASE (R) and the energy flows back
from the circuit to the power-clock generator; the HOLD PHASE (H) and the IDLE
PHASE (I) are needed for cascading gates.

4.5 CLOCKED ADIABATIC LOGIC (CAL)

CAL is a dual-rail logic that operates from a single-phase AC power-clock supply

[17]. In the adiabatic mode, the power-clock supply waveform is generated using an
on-chip switching transistor and a small external inductor between the chip and a
low-voltage dc supply.

47
 Fig. 4.5 The Basic Structure of the Adiabatic CAL Logic

The basic CAL gate, the inverter, is shown in Fig. 4.4. Cross-coupled CMOS
inverters, transistors M1 – M4, provide memory function. In order to realize an
adiabatic inverter and other logic functions with a single power clock, we
introduced auxiliary timing control clock signal CX, as shown in above Figure 4.4.
This signal controls the transistors that are in series with the logic trees represented
by the functional blocks F and /F. The CX-enabled devices allow operation with a
single power clock pwr.

48
 CHAPTER 5

DESIGN AND ANALYSIS

OF LOW POWER CMOS
CELL STRUCTURES

49
 CHAPTER 5
DESIGN AND ANALYSIS OF LOW POWER
CMOS CELL STRUCTURES

All the design structures based on CMOS Logic and Adiabatic Switching Logic are
designed and simulated using standard TSMC 0.35 µm CMOS technology and 3.3 V
voltage supply at an operating temperature of 27º C. Mentor Graphics Corporation
based tool known as IC Design Architect have been used for all the design and
analysis. The basic cells, for example, Inverter, Two-Input NAND Gate, Two-Input
NOR Gate, Two- Input Exclusive-OR Gate, Two-to-One Multiplexer, One-Bit Full
Adder are designed and analyzed with appropriate sizing.

Fig. 5.1(a) Improved Efficient Charge Recovery Logic (IECRL)

The operating principle and energy consumption of several typical CMOS adiabatic
logic circuits are analyzed. Compared with other circuits, the ECRL circuit rejects the
diode in the process of charging, and does not exist vacant flat problem for output of
high and low voltage, so it is selected as key research circuit. Based on the analysis of
the sources of the energy consumption, the defects of the ECRL circuits in energy
recovery are discussed. When the voltage across the load capacitance is blow to
threshold voltage of MOS transistor some left energy can not be recycled to the power
clock, the circuit produces some of the non-adiabatic power. A new IECRL circuit
50
structure is proposed, which achieves the recovery of non-adiabatic energy
completely by using limited adiabatic losing energy. At the same time, a new
structure of flip-flop based on IECRL is proposed, by adding a feedback path it
samples and maintain the logic state of the output at the previous cycle, then the logic
state of the output is feedback to the side of the input at the next cycle, so it achieves
the logic function of the trigger. The simulation results prove that the trigger has made
a certain degree of improvement in reducing the power dissipation compared with the
ECRL trigger. Then we analyze the circuit structure of a four-phase sinusoidal power
clock used for the adiabatic Logic, and make some of the optimization of its
parameters. The Hospice simulation with 0.5 m BSIM3v3 model technology show
that non-adiabatic consumption of ECRL circuit accounts for the major part of
dynamic power consumption in low frequency (1Hz-40MHz) range. By adding the
energy recovery path to achieve the effective recovery of non-adiabatic energy,
compared with the ECRL, improved ECRL circuit (IECRL) reduces power
consumption about 30.6%. Comparing with the existing flip-flops based on ECRL
circuit, the new trigger based on IECRL has a slight consumption increase of RS flip-
flop. Due to the application of the new feedback path, JK flip-flop omits the four
inverter chain which is used to maintain the output state of the previous cycle, so the
power consumption is reduced by about 50.9%. A designed four-phase sinusoidal
power clock is realized, the phase of each level lag of 90 degrees compared with its
previous level, and its own power is decreased by increasing frequency. - See more at:
http://www.research-degree-thesis.com/showinfo-26-172263-0.html#sthash.0.ed
Am434.of improvement in reducing the power dissipation compared with the ECRL
trigger. Then we analyze the circuit structure of a four-phase sinusoidal power clock
used for the adiabatic Logic, and make some of the optimization of its parameters.
The Hospice simulation with 0.5 m BSIM3v3 model technology show that non-
adiabatic consumption of ECRL circuit accounts for the major part of dynamic power
consumption in low frequency (1Hz-40MHz) range. By adding the energy recovery
path to achieve the effective recovery of non-adiabatic energy, compared with the
ECRL, improved ECRL circuit (IECRL) reduces power consumption about 30.6%.
Comparing with the existing flip-flops based on ECRL circuit, the new trigger based
on IECRL has a slight consumption increase of RS flip-flop. Due to the application of
the new feedback path, JK flip-flop omits the four inverter chain which is used to
maintain the output state of the previous cycle, so the power consumption is reduced
51
by about 50.9%. A designed four-phase sinusoidal power clock is realized, the phase
of each level lag of 90 degrees compared with its previous level, and its own power is
decreased by increasing frequency.

Fig. 5.1(b) Improved Efficient Charge Recovery Logic (IECRL)

Improves ECRL with the addition of a pair of cross-coupled NMOS devices. This
produces a logic family that is based around a pair of cross-coupled inverters, a structure
that is identical to the storage elements in a Static RAM (SRAM). The cross-coupled NMOS
devices are an improvement over ECRL because they provide a pull down path to ground that
remains even after the charge is recovered from the gates of the evaluation FETs. However,
because of the two extra NMOS devices, it will require a larger area in which to be
implemented. Figure 5.1 shows an inverter/buffer (also in buffer configuration) implemented
using the IECRL style. This figure uses the same naming and assertion level conventions as
the ECRL circuit shown on the previous page.

52
Fig. 5.1(c) Improved Efficient Charge Recovery Logic (IECRL)

Fig. 5.1(d) Improved Efficient Charge Recovery Logic (IECRL)

53
Fig. 5.1(e) Improved Efficient Charge Recovery Logic (IECRL)

Fig. 5.1(f) Improved Efficient Charge Recovery Logic (IECRL)

54
Graph: 5.1(a) Improved Efficient Charge Recovery Logic (IECRL)rise/fall time

Graph: 5.1(b) Improved Efficient Charge Recovery Logic (IECRL)rise/fall time

55
 Fig 5.2(a) Positive Feedback Adiabatic Logic (PFAL)

Fig 5.2(b) Positive Feedback Adiabatic Logic (PFAL)

Like IECRL, is also based around a pair of cross coupled inverters. However, whilst in
IECRL the NMOS devices used to evaluate the function are connected between the outputs
and ground, in PFAL, these evaluation NMOS devices are connected between the outputs and
the power-clock. The similarities between PFAL and IECRL gates are such that IECRL gates
can be easily converted into PFAL gates. This is done by re-labelling the outputs so that their
assertion levels are swapped, and connecting the NMOS evaluation devices between the
power-clock and the outputs rather than between ground and the outputs. This can be made as
easy to achieve in layout as it is in abstract representations of the circuit. When the power-
clock is in its recovery phase, the NMOS devices between the outputs and the power-clock

56
can allow complete recovery of those outputs. This means that the low-power performance of
PFAL can be enhanced by making it fully reversible Figure 5.2 shows an inverter/buffer
(again in buffer configuration, with identical signal naming conventions) implemented in the
PFAL style.

Fig 5.2(c) Positive Feedback Adiabatic Logic (PFAL)

Fig 5.2(d) Positive Feedback Adiabatic Logic (PFAL)

57
Fig. 5.2(e) Adiabatic power supply

Fig 5.2(f) Adiabatic power supply

58
Fig 5.2(g) Positive Feedback Adiabatic Logic (PFAL) with power supply

Fig 5.2(h) Positive Feedback Adiabatic Logic (PFAL) with power supply

59
Graph 5.2 Positive Feedback Adiabatic Logic (PFAL) with power supply

60
 CHAPTER 6

PHYSICAL LAYOUT
DESIGN & POST LAYOUT
SIMULATIONS

61
 CHAPTER 6
PHYSICAL LAYOUT DESIGN & POST LAYOUT
SIMULATIONS

6.1 DESIGN AND SIMULATION FOR A CMOS INVERTER

The first basic cell which the VLSI designers implements and analyze is the basic
CMOS Inverter. Here also this thesis work starts with the designing of the basic
CMOS Inverter of minimum transistor size. The standard TSMC 0.35 µm CMOS
technologies have been used and a load capacitance of 4 fF is used. The transient
analysis is done by use of the ELDO Simulator of Mentor Graphics Corporation.
The basic structure of a CMOS Inverter is shown in Figure 5.1.

CMOS inverters (Complementary MOSFET Inverters) are some of the most widely
used and adaptable MOSFET inverters used in chip design. They operate with very
little power loss and at a relatively high speed. Furthermore, the CMOS inverter has
good logic buffer characteristics, in that, its noise margins in both low and high
states are large. This short description of CMOS inverters gives a basic
understanding of the how a CMOS inverter works. It will cover input or output
characteristics, MOSFET states at different input voltages, and power losses due to
electrical current. A CMOS inverter is the combination of a PMOS and a NMOS
transistor connected at the drain and gate terminals, a supply voltage VDD at the
PMOS source terminal, and a ground connected at the NMOS source terminal.

The input source, Vis connected to the gate terminals, while the output, V is
connected to the drain terminals. It is important to notice that the CMOS does not
contain any resistors, which makes it more power efficient that a regular resistor-
MOSFET inverter. As the voltage at the input of the CMOS device varies between 0
and2.5 Volts, the state of the NMOS and PMOS varies accordingly. In this
assignment, we were asked to design and simulate a CMOS inverter using
Tanner EDA for a given width and length of the PMOS and the NMOS transistor.
The S-Edit was used to draw the schematic circuit and the circuit was simulated to
get the graphical responses for the VTC and Transient analysis. In addition, L-Edit
was used to draw the two dimensional geometry of the layout layer of the CMOS
inverter. Basically, what we have done in this assignment are designing and do some
62
responses analysis of the CMOS inverter. Schematic design is a CMOS inverter
circuit which consists of two different type of transistor which are NMOS and PMOS
transistor with their gates connected together at the input. The applied voltage is
denoted by VGS_param and the output voltage, Vout is taken out from the
commondrain terminals. The transistors are connected in a manner that ensures that
only one of the MOSFET sconducts when the input is stable at a low or high voltage.
This happened due to the use of the complementary arrangement. The DC
characteristics of the inverter are shown in the voltage transfer characteristic (VTC)
graph, which is a plot of Vout as a function of VGS_. The response is obtained by
varying the VGS_param value in the range of 0 V to VDD. From the graph above,
the threshold voltage value, Vm.

For the transient analysis, the previous schematic design of CMOS inverter were
modified and the schematic is shown in figure above. The master interface of the
input voltage, is set to PULSE the purpose of this transient analysis is to study the
characteristics of the CMOS inverter for with respect to time such as the delay. From
this, we can conclude the performance of the inverter. As the transient response of
the inverter is printed out, there are delays between the each inverter have its own
delay, depends on the design. To study the delay, we do connect a capacitor in
parallel with the NMOS transistor. Keeping the load capacitance small is the most
effective means of implementing high-performance circuits.

63
Fig. 6.1 The Basic Structure of CMOS Inverter

64
The transient simulation results are as shown in the Figure 5.2 below

Fig. 6.2 Simulation Results of CMOS Inverter:

(a) Input Signal, (b) Voltage Waveform of Output Signal

Fig. 6.3 CMOS Inverter voltage and current

65
 Graph 6.1 CMOS Inverter power dissipation from supply to output (2.58 uW)

Graph 6.2 CMOS Inverter maximum current from supply to output (0.190mA)

6.2 DESIGN AND SIMULATION FOR AN ADIABATIC PFAL

BUFFER / INVERTER
The design of a basic inverter based on an adiabatic switching principle is to be
design and analyze first. In this section, a family of a partially adiabatic logic known

66
as Positive Feedback Adiabatic Logic (PFAL) is used for the design of a basic
buffer/ inverter. PFAL family is used because of the reason mentioned in the
Chapter 4. The minimum size PFAL buffer/ inverter are designed and simulated
in the standard TSMC 0.35 µm Technology.

Fig. 6.4 The Basic Structure of an Adiabatic PFAL Buffer / Inverter

Simulation results of an Adiabatic PFAL Buffer / Inverter:

Fig. 6.5 Voltage v/s Time

67
 Fig. 6.6 Adiabatic Inverter voltage and current

Graph 6.3 Adiabatic Inverter maximum current from supply to output (0.130mA)

68
POWER DISSIPATION ANALYSIS
VARIATION OF POWER DISSIPATION WITH FREQUENCY

This section deals with the comparison of the full complementary CMOS logic style
with the ultra low-power adiabatic logic style in terms of the average dynamic power
dissipation, expressed in micro-Watts.

TABLE 6.1
AVERAGE DYNAMIC POWER DISSIPATED BY STATIC CMOS FAMILY
AND ADIABATIC PFAL FAMILY FOR
AN INVERTER FOR DIFFERENT POWER CLOCK FREQUENCIES

Frequency Static CMOS Adiabatic (PFAL) Logic

(MHz) (µW) (µW)
25 M 1.4752 µ 0.1249 µ
50 M 2.9497 µ 0.2820 µ
100 M 5.8979 µ 1.3681 µ
125 M 7.2918 µ 1.7383 µ
150 M 8.8989 µ 3.2294 µ
200 M 11.7937 µ 8.3552 µ
250 M 14.5424 µ 12.5624 µ

6. 3 VARIATION OF POWER DISSIPATION WITH THE LOAD

CAPACITANCE

TABLE 5.2
ADIABATIC PARAMETRIC ANALYSIS

69
This section discusses the power dissipation analysis of the various design units
implemented in standard TSMC 0.35 micron technology. The variation of the power
dissipation with the varying load capacitance is shown as in the following figures
below. It is inferred from the following figures that with the increase in the load
capacitance, there is an increase in the power dissipation of the circuit structure or, the
digital system under consideration.

Graph 6.4 Variation of Power Dissipation with the Load Capacitance for an INVERTER
operating @ f = 100 MHz and VDD = 3.3 V.

70
 CHAPTER 7

CONCLUSIONS AND
FUTURE SCOPE OF WORK

71
 CHAPTER 7
CONCLUSIONS AND FUTURE SCOPE OF WORK

7.1 CONCLUSIONS
The thesis primarily was focused on the design of low power CMOS cell
structures, which is the main contribution of this work. The design of low power
CMOS cell structures uses fully complementary CMOS logic style and an
adiabatic PFAL logic style. The basic principle behind implementing various
design units in the two logic styles is to compare them with reference to the average
power dissipated by all of them.

A family of full-custom conventional CMOS Logic and an Adiabatic Logic units

were designed in Mentor Graphics IC Design Architect using standard TSMC 0.35
µm technology, layout them in Mentor Graphics IC Station and the analysis of the
average dynamic power dissipation with respect to the frequency and the load
capacitance was done. It was found that the adiabatic PFAL logic style is
advantageous in applications where power reduction is of prime importance as in high
performance battery-portable digital systems running on batteries such as note-book
computers, cellular phones and personal digital assistants.

With the adiabatic switching approach, the circuit energies are conserved rather than
dissipated as heat. Depending on the application and the system requirements, this
approach can be used to reduce the power dissipation of the digital systems. With
the help of adiabatic logic, the energy savings of upto 76 % to 90 % [15] can be
reached.

Circuit simulations show that the adiabatic design units can save energy by a factor of
10 at 50 MHz and about 2 at 250 MHz, as compared to logically equivalent
conventional CMOS implementation.

72
7.2 FUTURE SCOPE OF WORK

This section summarizes a few potential future directions for this work.

(a) ADIAMEMS: To perform digital logic in CMOS in a truly adiabatic

(asymptotically thermodynamically reversible) fashion requires that the logic
transitions be driven by a quasi-trapezoidal (flat-topped) power-clock voltage
waveform, which must be generated by a resonant element with very high
Q (quality factor). Recently, MEMS resonators have attained very high
frequencies and Q factors and are becoming widely used in communications
system-on-chip (SOC) for RF signal filtering, amplification, etc.

(b) APPLICATION OF NANO-TECHNOLOGY: Carbon nano-tubes grown

using Chemical Vapor Deposition (CVD) can be selected to conform to a
spiraling shape. Thus, a good quality factor Q can be achieved. The work left
to be done for this design would include a method for causing it to keep its
form, since nano-tubes are typically not rigid. Also, putting the tube to use in a
circuit would lower the effective Q due to the junction discontinuities.

(c) SPACECRAFT: The high cost-per-weight of launching computing-related

power supplies, solar panels and cooling systems into orbit imposes a demand
for adiabatic power reduction in spacecraft in which these components weigh
a significant fraction of total spacecraft weight.

73
REFERENCES

74
 REFERENCES
[1] A. P. CHANDRAKASAN, S. SHENG, AND R. W. BRODERSEN, “Low
Power CMOS Digital Design,” IEEE Journal of Solid-state Circuits, Vol.
27, No. 04, pp. 473-484, April 2011.

[2] H. J. M. VEENDRICK, “Short-circuit Dissipation of Static CMOS Circuitry

and its Impact on the Design of Buffer Circuits,” IEEE JSSC, pp. 468-473,
August 2010.

[3] J. M. RABAEY, AND M. PEDRAM, “Low Power Design Methodologies,”

Kluwer Academic Publishers, 2008.

[4] M. HOROWITZ, T. INDENNAUR, AND R. GONZALEZ, “Low Power

Digital Design, “Technical Digest IEEE Symposium Low Power Electronics,
San Diego, pp. 08-11, October 2010.

[5] T. SAKURAI AND A. R. NEWTON, “Alpha-Power Law MOSET Model

and its Applications to CMOS Inverter Delay and other Formulas,” IEEE
JSSC, vol. 25, no. 02, pp. 584- 594, October 2010.

[6] A. P. CHANDRAKASAN AND R. W. BRODERSEN, Low-power CMOS

digital design, Kluwer Academic, Norwell, Ma, 2008.

[7] SUNG-MO KANG AND YUSUF LEBLEBICI, CMOS Digital Integrated

Circuits - Analysis and Design, McGraw-Hill, 2009.

[8] J. S. DENKER, “A Review of Adiabatic Computing,” Technical Digest

IEEE Symposium Low Power Electronics, San Diego, pp. 94-97, October
2010.

[9] T. GABARA, “Pulsed Power Supply CMOS,” Technical Digest IEEE

Symposium Low Power Electronics, San Diego, pp. 98- 99, October 2009.

[10] B. VOSS AND M. GLESNER, “A Low Power Sinusoidal Clock,” In Proc.

of the International Symposium on Circuits and Systems, ISCAS 2001.

[11] W. C. ATHAS, J. G. KOLLER, L. SVENSSON, “An Energy- Efficient

75
 CMOS Line Driver using Adiabatic Switching,” Fourth Great Lakes
symposium on VLSI, California, March 2005.

[12] T. INDERMAUER AND M. HOROWITZ, “Evaluation of Charge Recovery

Circuits and Adiabatic Switching for Low Power Design,” Technical Digest
IEEE Symposium Low Power Electronics, San Diego, pp. 102-103, October
2002.

[13] Y. MOON AND D. K. JEONG, “An Efficient Charge Recovery Logic

Circuit,” IEEE JSSC, Vol. 31, No. 04, pp. 514-522, April 1996.

[14] A. KAMER, J. S. DENKER, B. FLOWER, et al., “2N2D-order

Adiabatic Computation with 2N-2P and 2N-2N2P Logic Circuits,” In Proc. of
the International Symposium on Low Power design, Dana Point, pp. 191-196,
1995.

[15] A. BLOTTI AND R. SALETTI, “Ultralow- Power Adiabatic Circuit Semi-

Custom Design,” IEEE Transactions on VLSI Systems, vol. 12, no. 11, pp.
1248-1253, November 2004.

[16] S. YOUNIS, T. KNIGHT, “Asymptotically Zero Energy Split-Level

Charge Recovery Logic. Proceedings Workshop Low Power Design, Napa
Valley, California 2004, pp. 177- 182.

[17] DRAGAN MAKSIMOVIC´, G. VOJIN, OKLOBDŽIJA, BORIVOJE

NIKOLIC´ AND K. WAYNE CURRENT, “Clocked CMOS Adiabatic Logic
with Integrated Single-Phase Power-Clock Supply,” IEEE Transactions on
VLSI Systems, Vol. 08, No. 04, pp. 460-463, August 2000.

[18] A. BLOTTI, S. PASCOLI, AND R. SALETTI, “Sample Model for

Positive Feedback Adiabatic Logic Power Consumption Estimation,”
Electronics Letters, Vol. 36, No. 2, pp. 116-118, Jan. 2000.

[19] C. HU, “Future CMOS Scaling and Reliability,” Proceedings IEEE, Vol. 81,
No. 05, pp. 682-689, February 2004. [20] W. C. ATHAS, L. SVENSSON, J.
KOLLER, N. TZARTZANIS, AND Y. CHOU, “Low Power Digital Systems

76
 based on Adiabatic Switching Principles,” IEEE Trans. on VLSI Systems, Vol.
2, No. 4, pp. 398-406, Dec.2004.

[21] SAED G. YOUNIS, “Asymptotically Zero Energy Computing Using Split-

Level Charge Recovery Logic,” PhD thesis, 2003.

[22] MICHAEL P. FRANK AND MARCO OTTAVI, “Energy Transfer and

Recovery Efficiencies for Adiabatic Charging with various driving
waveforms,” Research Memo, 2006.

[23] KAUSHIK ROY, SHARAT C. PRASAD, Low-Power CMOS VLSI Circuit

Design, John Wiley & Sons, Inc, 2000.

[24] KAUSHIK ROY, YIBIN YE, Ultra Low Energy Computing using
Adiabatic Switching Principle, ECE Technical Reports, Purdue University,
Indiana, March, 1995.

[25] MOSIS: MOS Integration Service. Available online: www.mosis.org

77