BCD TO 7 Segment Driver for common cathode display

Exp.No: Date:
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Aim: To write a verilog program for BCD TO 7 Segment Driver for common cathode display to synthesize
and simulate using Xilinx software tool..

Tools Required: 1.PC

2. Xilinx ISE Design Suite 14.7

Seven-Segment Display
The seven-segment display has seven LED segments which are arranged in the shape of the digit ‘8’ as shown
in the Figure (a) below. It takes in a set of four bits as inputs, and based on the inputs a unique combination of
LEDs start glowing. In such a display, a specific set of input patterns result in a specific digit being shown on
the display by means of glowing LEDs. The way BCD digits from ‘0’ to ‘9’ get displayed is shown in Fig(b).
Fig(a)

Fig(b)
BCD to Seven-Segment Driver Chip

A BCD to seven-segment driver takes a BCD digit as input (usually 4 bits long) and decodes it into seven
outputs which serve as the inputs for each of the seven segment of a seven-segment display. In the case shown
in Figure 2.3, input A is the least significant bit and D is the most significant bit. The outputs bits of this
decoder (a, b, c, d, e, f, g) correspond to the different segments on the Seven-segment display as shown in
Figure (a)

Fig(c) Seven Segment Display Driver Input /Output

VERILOG CODE

module BCD_to_7Seg ( bcd , seg7 );

output [6:0] seg7 ;
reg [6:0] seg7 ;
input [3:0] bcd ;
wire [3:0] bcd ;

always @ (bcd) begin

case (bcd)
0 : seg7 = 7'b1111110;
1 : seg7 = 7'b0110000;
2 : seg7 = 7'b1101101;
3 : seg7 = 7'b1111001;
4 : seg7 = 7'b0110011;
5 : seg7 = 7'b1011011;
6 : seg7 = 7'b0011111;
7 : seg7 = 7'b1110000;
8 : seg7 = 7'b1111111;
9 : seg7 = 7'b1110011;
default : seg7 = 7'b0000000;
endcase
end

endmodule
RTL SCHEMATIC

SIMULATION RESULT:

Conclusion: