Design of Approximate Dividers for Error Tolerant Applications

Scholar Name: Karri Manikantta Reddy Supervisors: Dr. Vasantha M.H. and Dr. Devesh Dwivedi
(National Institute of Technology Goa, India)

I NTRODUCTION A PPROXIMATE D IVIDERS S IMULATION R ESULTS E RROR A NALYSIS

Approximate computing has become an effective A subtractor cell is the basic building block of both non- All the simulations are carried at 45-nm CMOS tech- The error metrics of proposed non-restoring and resto-
paradigm to improve the speed and energy efficiency restoring and restoring dividers. Hence, the design of nology node with a supply voltage of 1.0 Volt. The ring dividers along with the approximate dividers pre-
of portable devices. In case of visual data, small errors approximate dividers starts with the design of appro- conventional (exact) subractor and divider along with sented in [2] are compared in below figure.
in the output are undetectable due to the persistence ximate subtractors. The 1-bit accurate full subtractor the proposed approximate designs and the appro-
of human eyes. This allows approximate computation operation is given by the logic equations (2) and (3). ximate designs of [2] are simulated and the design
in place of exact computation. parameters are compared in the below figure.
D = X ⊕ Y ⊕ Bin (2)
Division is one of the most complex basic arithmetic Bout = Bin (X ⊕ Y ) + XY (3) Approximate Subtractors
operations. It is a sequential operation and hardest to
speed up. The basic division operation is given by the The approximate subtractor deisgns (AXS) are ob- 6
5 .4 2
8 0
7 1 .3
7 0
equation (1). tained by logic complexity reduction. The following 5 4 .7 4 6 1 .7
6 0 5 7 .4
5 3 .6
figures summarizes the design and operation of three 4

P o w e r ( µw )
5 0 4 7 .7 4 6 .2
X = Y Q + R, R<Y (1)

D e la y (p s )
proposed approximate subtractors. 3
3 .0 3
4 0
2 .4 2
2 .0 7 8 1 .8 8 6 3 0 2 5 .3
2
An unsigned 2k-by-k bit integer divider takes 2k-bit Implementation of Proposed Subtractors 1 .0 2
2 0
1
and k-bit inputs X (Dividend) and Y (Divisor) res- 1 0

pectively and produces k-bit outputs Q (Quotient) VDD X Y

0
E x a c t A X S 1 A X S 2 A X S 3 A X S 4 A X S 5 A X S 6
0
E x a c t A X S 1 A X S 2 A X S 3 A X S 4 A X S 5 A X S 6
[2 ] [2 ] [2 ] [2 ] [2 ] [2 ]
and R (Remainder). Dividers can be designed using
two algorithms called restoring and non-restoring
S u b tra c to r d e s ig n S u b tra c to r d e s ig n
C ONCLUSION
A B A
algorithms [1]. Approximate Dividers This work has presented the design of approximate
A B
B Bout DGC C Bin non-restoring and restoring dividers for unsigned inte-
O 4 0 0 3 .5
8-by-4 Unsigned Non-restoring Divider [1] C O 3 5 0
N o n -re s to rin g d iv id e r N o n -re s to rin g d iv id e r ger division. Three designs of approximate subtractor
R e s to rin g d iv id e r 3 .0 R e s to rin g d iv id e r
A 3 0 0 cells are proposed and are used in the design of divi-
2 .5
Non-Restoring X Y Q ders, which reduced the power consumption and de-

P o w e r ( µw )
2 5 0
Divider Cell 2 .0

D e la y (p s )
X7 X6 X5 X4 X3
0 Y3 Y2 Y1 Y0 (NRDC)
XOR A B B D
2 0 0
1 .5
lay by 33% and 31% respectively as compared to that of
1 5 0
Q3 NRDC NRDC NRDC NRDC
X2
Bout
1-bit
Bin
D = Bin(X+Y)+XY 1 .0
exact dividers. The efficacy of proposed dividers is ex-
Subtractor Bout = Bin 1 0 0
Number of Transistors =14 tensively analyzed with several error metrics. Finally,
X1
R
(a) Difference Generator Circuit (DGC) 5 0 0 .5
Q2 NRDC NRDC NRDC NRDC (c) AXS2 0 0 .0 this paper concludes that proposed approximate resto-
X Y E x a c t A X S 1 A X S 2 A X S 3 A X S 4 A X S 5 A X S 6 E x a c t A X S 1 A X S 2 A X S 3 A X S 4 A X S 5 A X S 6
X0 S u b tra c to r d e s ig n
[2 ] [2 ] [2 ] [2 ]
S u b tra c to r d e s ig n
[2 ] [2 ]
ring dividers are performing better than approximate
Q1 NRDC NRDC NRDC NRDC X Y
non-restoring dividers both in-terms of design parame-
A B Error Metrics
Q0 NRDC NRDC NRDC NRDC
Bout DGC C
ters and accuracy metrics.
Bin A B
O Bout DGC C Bin
O
The accuracy of the Quotient and Remainder are eva-
Remainder 1
Correction NRDC NRDC NRDC NRDC
luated using the following error metrics. A CKNOWLEDGMENT
Circuit

D
D 22N
This work is an outcome of the R&D work underta-
R3 R2 R1 R0
D = Bin(X+Y)+XY 1 X
D = Bin(X+Y)+XY
Bout = X Mean Error Distance (MED) = |EDi | (4) ken in the project under Visvesvaraya PhD Scheme of
Bout = Y
Number of Transistors =12
22N Ministry of Electronics & Information Technology, Go-
8-by-4 Unsigned Restoring Divider [1] Number of Transistors =14 i=1
(b) AXS1 (d) AXS3 where EDi is the Error Distance at output correspon- vernment of India, being implemented by Digital India
th Corporation (formerly Media Lab Asia).
Restoring
Divider Cell
X Y ding to i input combination.
(RDC)
X7 X6
Y3
X5
Y2
X4
Y1
X3
Y0
Bout 1-bit
Subtractor
Bin
Implementation of Approximate Dividers 2 2N
1 X EDi
Q3 RDC RDC RDC RDC
X2
1
MUX
0
X
Q
The approximate non-restoring and restoring dividers
Mean Relative ED (MRED) =
22N Si
(5) R EFERENCES
0 i=1
R
X1 are obtained by replacing NRDC and RDC cells in ac- th [1] A. B. Gardiner and J. Hont, “Comparison of restoring and
Q2 RDC RDC RDC RDC 0 where Si is the exact output corresponding to i input
curate divider with approximate NRDC and RDC cells nonrestoring cellular-array dividers”, in Elect. Letters, vol.
X0 combination. 7, pp. 172-173, Apr. 1971.
Q1 RDC RDC RDC RDC respectively. These six approximate dividers are desig-
0 2N
2
ned for 16-by-8 bit length because these dividers can be MED 1 X EDi [2] L. Chen, J. Han, W. Liu, and F. Lombardi, “Design of Ap-
Q0 RDC RDC RDC RDC used for image processing applications such as pixel Normalized ED (NED) = = 2N (6) proximate Unsigned Integer Non-restoring Divider for
0 D 2 i=1
D
R3 R2 R1 R0 division where input images have pixel values range Inexact Computing”, in Proc. of the 25th edition on Great
from 0 to 255. where D is the maximum possible ED for a design. Lakes Symp. on VLSI, New York, 2015, pp. 51-56.