DESIGN FOR TEST

Contents

1.What is Design for Testability (DFT)? ................................................................................................... 2

2. What are the goals of DFT? ................................................................................................................. 2
3. Why is DFT required? .......................................................................................................................... 2
4. What is the difference between structural and functional testing?................................................... 3
5.Explain: DUT, DPPM, ATE. .................................................................................................................... 3
6.What are burn in and wafer level tests?.............................................................................................. 3
7.What are the challenges in DFT? ......................................................................................................... 4
8. What is yield analysis? ........................................................................................................................ 4
1.What is Design for Testability (DFT)?

Design for testing or design for testability (DFT) consists of IC design techniques that add testability
features to a hardware product design. The added features make it easier to develop and apply
manufacturing tests to the designed hardware.

DFT often is associated with design modifications that provide improved access to internal circuit
elements such that the local internal state can be controlled (controllability) and/or observed
(observability) more easily.

1.1 Approaches to DFT: ATE or BIST

ATE: Test vectors applied to a manufactured chip using ATE (Automatic Test Equipment), if the response
matches the expected ‘golden response’ the chip is OK. Otherwise it is defective.

Built in Self-Test (BIST): test circuitry is present within the chip itself.

Primary focus of DFT is digital circuits, analog circuits have a completely different approach to testing
and diagnosis. Most DFT features these days are implemented using commercial EDA tools during the
IC design flow.

1.2 The DFT concept: Controllability and Observability

For today's highly complex designs, most gates are deeply embedded whereas the test equipment is
only connected to the primary Input/outputs (I/Os) and/or some physical test points. The embedded
gates, hence, must be manipulated through intervening layers of logic. If the intervening logic contains
state elements, then the issue of an exponentially exploding state space and state transition sequencing
creates an unsolvable problem for test generation. To simplify test generation, DFT addresses the
accessibility problem by removing the need for complicated state transition sequences when trying to
control and/or observe what's happening at some internal circuit element

2. What are the goals of DFT?

1. Identify and separate defective chips from being used in actual products.
2. Prevent catastrophic failures of critical electronic systems by providing an early warning of
failure.
3. Objectives of DFT are to facilitate/simplify fail data collection and diagnostics to an extent that
can enable intelligent failure analysis (FA) sample selection, to identify the source of failure.
4. Improve the cost, accuracy, speed, and throughput of testing, diagnostics, and FA.
5. In addition to being useful for manufacturing "go/no go" testing, scan chains can also be used
to "debug" chip designs which have already been mounted on a PCB.

3. Why is DFT required?

• Given the complexity of multi-million transistor based VLSI designs, ensuring the reliability,
dependability and testability of design is impossible without systematic DFT techniques.
• In volume production, if bad parts are accidentally delivered to a customer often and exceed
certain levels, this can result in huge financial loses, catastrophic failures and loss of
reputation. By separating the non-functional chips from the functional chips at the
manufacturing stage, resulting damages are prevented.
• Automatic Test Pattern Generation (ATPG) is much easier if proper DFT techniques have been
employed.
4. What is the difference between structural and functional testing?

DFT affects and depends on the methods used for test development, test application, and diagnostics.
DFT focusses on the structural testing paradigm rather than functional testing.

Structural testing Functional Testing

Structural test makes no direct attempt to Attempts to validate that the design under test
determine if the overall functionality of the functions according to its functional
circuit is correct. Instead, it tries to make sure specification.
that the circuit has been assembled correctly
from some low-level building blocks as specified
in a structural netlist.

The idea is that if the netlist is correct, and Functional testing focusses on testing all
structural testing has confirmed the correct possible functional states, given the complexity
assembly of the circuit elements, then the of VLSI designs this is almost impossible because
circuit should be functioning correctly. of the infinite possible combinations.

One benefit of the Structural paradigm is that Test vectors for functional testing focus on the
test generation can focus on testing a limited entire system as a black box, without giving any
number of relatively simple circuit elements consideration to the internal structure.
rather than having to deal with an exponentially
exploding multiplicity of functional states and
state transitions.

5. Explain: DUT, DPPM, ATE.

DUT: Design under test

ATE: Automatic Test Equipment is used to test individual IC’s. An ATE provides electrical bias and
excitation voltage by mechanically contacting its leads.

DPPM: Defective parts per million.

6.What are burn in and wafer level tests?

Burn in testing: Burn-in is a temperature/bias reliability stress test used in detecting and screening
potential early life failures.

Wafer-level testing: Wafer-level testing employs a wafer probe to supply the necessary electrical
excitation to the die on the wafer through hundreds or thousands of ultra- thin probing needles that
land on the bond pads, balls, or bumps on the die.
 • During the wafer-level testing and burn-in, the electrical bias and excitation required by the
devices are delivered directly to the interconnection points of each die on the wafer. The
required die temperature elevation is achieved by the wafer probe through a built-in hot
plate that heats up the wafer to the correct junction temperature.
• In burn-in, the units are placed on burn-in boards, which in turn are placed inside burn-in
ovens. The burn-in ovens provide the electrical bias and excitation needed by the devices
through these burn-in boards.
• Wafer-level testing and burn-in is a pre-screen test. Only parts that pass this test undergo
back-end processing (assembly and final test). They also provide additional information on
identifying design and process problems. Such information is helpful during the design and
process development phases for debugging purposes.

7.What are the challenges in DFT?

1. Keeping up with the rapid advances in chip technology (I/O count/size/placement/spacing,
I/O speed, internal circuit count/speed/power, thermal control, etc.)
2. Modern DFT techniques must ensure that next generation chips and assemblies can be tested
on existing test equipment and/or reduce the requirements/cost for new test equipment.
3. Integrating DFT features in multi-million transistor circuits, without affecting the performance
and functionality of the original design.
4. Improvements in EDA tools for DFT.
5. Making trade-offs between the amount and type of DFT and the cost/benefit (time, effort,
quality) of the test generation task.

8. What is yield analysis? How to identify the reason for manufacturing failures?
What is root-cause analysis and how to identify the reason for failing chip and
reduced yields?
Chips must go through a debug process that tries to identify the reason for reduced-yield situation. vital
information about the nature of the underlying problem may be hidden in the way the chips fail during
test.

To facilitate better analysis, additional fail information beyond a simple pass/fail is collected into a fail
log. The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester
channel), and how (e.g., logic value) the test failed.

Diagnostics attempt to derive from the fail log at which logical/physical location inside the chip the
problem most likely started. By running a large number of failures through the diagnostics process,
called volume diagnostics, systematic failures can be identified.

In some cases (e.g., Printed circuit boards, Multi-Chip Modules (MCMs), embedded or stand-alone
memories) it may be possible to repair a failing circuit under test. For that purpose, diagnostics must
quickly find the failing unit and create a work-order for repairing/replacing the failing unit.