COMPUTER ARCHITECTURE AND ORGANIZATION

UNIT-3
SYLLABOUS :
Type of Instructions: Arithmetic and Logic Instructions, Branch Instructions, Addressing
Modes, Input/output Operations.

Type of Instructions :
1. Arithmetic Instructions
2. Logic Instructions
3. Branch Instructions
1.ARITHMETIC INSTRUCTIONS : Arithmetic instructions are used to perform arithmetic
operations like addition, subtraction, multiplication, division, etc.
The basic assembly language expression for arithmetic instruction is
OPcode Rd, Rn, Rm
Where the operation specified by the OP code is performed using the operands in general
purpose registers Rn and Rm. The result is placed in register Rd.

i) The ADD Instruction :The ADD instruction adds the contents of source registers and place
the result in destination register.
Examples:
1. The instruction ADD R0,R2,R4 performs the operation
R0  [ R2]+[R4].
This instruction means, add the contents of registers R2 and R4 and place the result in
register R0.
2. The instruction ADD R0,R3,#17 performs the operation
R0  [R3]+17
This instruction means, the immediate operand value 17 is added to the contents of register
R3 and place the result in register R0.
3. The instruction ADD R0,R1,R5, LSL #4
This instruction means, the second operand which is contained in register R5, is shifted left 4 bit
positions and it is then added to the contents of register R1 and sum is placed in register R0.

ii)The SUB Instruction: The SUB instruction subtracts the contents of source registers and
place the result in destination register.
Example : The instruction SUB R0,R6,R5 performs the operation
R0  [ R6] - [R5]
This instruction means, subtracts the contents of registers R6 and R5 and place the result in
register R0.

iii) The MULTIPLY Instruction : The Multiply instruction multiplies the contents of two
registers and place the product in a destination register.
There are two versions of multiply instruction are provided. The first version multiplies the
contents of two registers and place the lower order 32-bits of the product in a third register.
 For Example , The instruction MUL R0,R1,R2 performs the operation
R0  [R1] × [R2]
The second version specifies a fourth register whose contents are added to the product before
storing the result in the destination register.
For Example : The instruction MLA R0,R1,R2,R3
R0  [R1] ×[R2]+[R3]
This is called a Multiply Accumulator operation. It is often used in numerical algorithm for
digital signal processing.

2. LOGIC INSTRUCTIONS : The logic instructions are used to performs the logic operations
such as AND, OR,XOR, Bit-Clear and Move Negative etc. These operations are implemented by
instructions with the OP codes AND, ORR, EOR, BIC, and MVN.
i) The AND Instruction : The AND instruction is used for supporting logical expressions by
performing bitwise logical AND operation. The bitwise logical AND operation returns 1, if the
matching bits from both the operands are 1, otherwise it returns 0.
The AND instruction Format is : AND Rd, Rn, Rm performs the operation

Rd  [Rn] ^ [Rm]
Which is a bitwise logical AND between the operands in registers Rn and Rm and result is
placed in register Rd.

Example: The instruction AND R0,R1,R2 performs the operation

R0 [R1] ^ [R2]
The bitwise logical AND performs the operation between the operands in registers R1 and R2
and place the result in register R0.
R1 = 0 1 1 0
R2 = 0 0 1 1
----------------
After AND -> R0 : 0010
-----------------
ii) The OR Instruction : The OR instruction is used for supporting logical expression by
performing bitwise logical OR operation. The bitwise logical OR operator returns 1, if the
matching bits from either or both operands are one. It returns 0, if both the operands bits are
zero.
The OR instruction Format is : ORR Rd, Rn, Rm
The bitwise logical OR performs the operation between the operands in registers Rn and Rm and
place the result in register Rd.
Example : The instruction ORR R0, R1, R2
The bitwise logical OR performs the operation between the operands in registers R1 and R2 and
place the result in register R0.
R1 = 0 1 1 0
R2 = 0 0 1 1
----------------
After ORR -> R0 : 0111
-----------------

iii) The XOR Instruction : The XOR instruction implements the bitwise logical XOR operation.
The bitwise logical XOR operation sets the resultant bit to 1, if and only if the bits from the
operands are different. If the bits from the operands are same (both 0 or both 1), the resultant bit
is cleared to 0.
The XOR instruction Format is : EOR Rd, Rn, Rm
The bitwise logical XOR performs the operation between the operands in registers Rn and Rm
and place the result in register Rd.
Example : The instruction EOR R0, R1, R2
The bitwise logical XOR performs the operation between the operands in registers R1 and R2
and place the result in register R0.
R1 = 0 1 1 0
R2 = 0 0 1 1
----------------
After EOR -> R0 : 0101
-----------------

iii) BIC(Bit Clear) Instruction : The BIC instruction performs an AND operation on the bits in
register Rn with the complements of the corresponding bits in the value of register Rm.

The BIC instruction Format is : BIC Rd, Rn, Rm

Example : The instruction BIC R0, R1, R2
The BIC instruction performs the AND operation on the bits in register R1 with the complements
the corresponding bits in the value of R2 and place the result in register R0.
R1 = 1 1 1 1
R2 = 0 1 0 1
Complements the each bit in operand R2
R1 = 1 1 1 1
R2 = 1 0 1 0
Apply AND Operation: ----------------
After BIC -> R0 : 1 0 1 0 (Result )
---------------
iv) MVN (Move Negative ) Instruction: The Move Negative instruction complements the bits
of the source operand and places the result in destination operand Rd.
The MVN instruction format is MVN Rd, Rn
Example 1: The instruction MVN R0, R1
This instruction means , it complements each bit in operand of register R1 and the result is
moved to register R0.
R1 = 0 0 1 0
After MVN -> R0 : 1 1 0 1 (Result )

Example 2: The instruction MVN R0, R3

This instruction means, the contents of R3 are complemented and then moved to R0.
R3 = 0 F 0 F 0 F 0 F
After MVN -> R0 : F 0 F 0 F 0 F 0

v) NAND Instruction : The bitwise logical NAND operation returns the 0 if and only if both
operands are 1, otherwise the result is 1. We will use (x⋅x)′ to designate the NAND operation. It
is also common to use the ‘↑’ symbol or simply “NAND.”
The NAND instruction Format is : NAND Rd, Rn, Rm performs the operation

Rd  [Rn] ↑ [Rm]
Which is a bitwise logical NAND between the operands in registers Rn and Rm and result is
placed in register Rd.

Example: The instruction NAND R0,R1,R2 performs the operation

R0 [R1] ↑ [R2]
The bitwise logical NAND performs the operation between the operands in registers R1 and R2
and place the result in register R0.
R1 = 0 0 1 1
R2 = 0 1 0 1
----------------
After NAND -> R0 : 1110
-----------------
vi) NOR Instruction : The bitwise logical NOR operation returns the 0 if at least one of the two
operands are 1, otherwise the result is 1. We will use (x+y)′ to designate the NOR operation. It is
also common to use the ‘↓’ symbol or simply “NOR.”
The NOR instruction Format is : NOR Rd, Rn, Rm performs the operation

Rd  [Rn] ↓ [Rm]
Which is a bitwise logical NOR between the operands in registers Rn and Rm and result is
placed in register Rd.
 Example: The instruction NOR R0,R1,R2 performs the operation
R0 [R1] ↓ [R2]
The bitwise logical NOR performs the operation between the operands in registers R1 and R2
and place the result in register R0.
R1 = 0 0 1 1
R2 = 0 1 0 1
----------------
After NOR -> R0 : 1000
-----------------

3. BRANCH INSTRUCTIONS :
 Branch instructions are used to implement control flow in program loops and
conditionals(executing a particular sequence of instructions only if certain conditions are
satisfied).
 A branch instruction can be either an unconditional branch, which always results in
branching or a conditional branch, which may or may not causes branching depending
on some condition.
 These instructions can change the flow of control in a program.
 Conditional branch instruction contains a signed 2’s complement, 24 bit offset that is
added to update the contents of the program counter to generate the branch target
address.
 The BEQ(Branch if equal to zero) causes a branch if Z(Zero) flag is set to 1. The
condition to be tested to determine whether or not branching should takes place is
specified in the higher order 4 bits(b31-28)of the instruction word.

Condition Codes Meaning

EQ --- Equal
NE --- Not Equal
GT --- Greater than
LE --- Less than
GE --- Greater than or Equal
LE --- Less than or Equal

Condition Code Flags :

 The condition code flags are grouped together in a special processor register called the
condition code register or status register.
 Individual condition code flags are set to 1 or cleared to 0, depending on the outcome of
the operation performed.
The common used condition code flags are
N(negative) : Set to 1if the result is negative, otherwise cleared to 0
Z(zero) : Set to 1 if the result is 0,otherwise cleared to 0
C(carry) : Set to 1 if carry-out results from the operation, otherwise cleared to 0
V(overflow) : Set to 1 if arithmetic overflow occurs, otherwise cleared to 0

The format for the branch instruction is as follows:

Figure 1: ARM Branch Instructions

 At the same time that the branch target address is computed ,the content of PC have
been updated to contain the address of the instruction that is two words beyond the
branch instruction it self.
 If the branch instruction is at address location 1000, and the branch target address is
1100, then the offset has to be 92. Because the contents of updated PC will be
1000+8=1008 when the address 1100 is computed.
3.1 SETTING CONDITION CODES :
CMP Instruction:
 The CMP instruction subtracts the value of operand in register Rm from the value in
register Rn.
 The compare instruction is the same as a SUBS instruction except that the result is
discarded and is used in conditional execution.
 CMP instruction format is as follows
CMP Rn, Rm which performs the operation [Rn] - [Rm]
have the sole purpose of setting the condition code flags based on the result of the
subtraction operation.
 On the other hand, the arithmetic and logic instructions effect the condition code flags
only if explicitly specified to do by a bit in the op code field. This is indicated by
suspending the suffix S to the assembly language op code mnemonic.
For Example that, the instruction
ADDS R0,R1,R2
Sets the condition code flags but

ADD R0,R1,R2 does not.

3.2 A LOOP PROGRAM FOR ADDING NUMBERS:

Figure 2: An ARM program for adding numbers

4 . ARM REGISTER STRUCTURE :
 There are sixteen 32 –bit registers labeled R0 through R15, which consists of 15 general
purpose registers(R0 through R14) called Banked Registers and the program counter
register R15.

Figure 3: ARM Register Structure

  The general purpose registers can hold either memory address or data operands. They are
used when the processor switches into supervisor or interrupt modes of operation.
 The current program status register(CPSR) holds the condition code flags(N,Z,C,V),
interrupt disable flags, and processor mode bits.
 The use of processor mode bits and interrupt disable bits will be described in conjunction
with input/output operations and interrupts.
ARM INSTRUCTION FORMAT:
 An instruction specifies a conditional execution code(Condition), the OP code, three
registers (Rn, Rd, and Rm ), and some other information. If Rm is not needed, the ”Other
info” field extends to bit b0.
 In ARM processor, all instructions are conditionally executed depending on a condition
specified in the instruction.
 The instruction is executed only if the current state of the processor condition code flags
satisfies in bits b 31-28 of the instruction.
 The magnitude of the offset is either an immediate value, contained in the low-order 12
bits of the instruction, or it is the contents of a third register Rm.
 The sign(direction) of the offset is contained in the OP-code field.

Figure 4: ARM Instruction format

4. MEMORY ACCESS INSTRUCTIONS :
Load Instructions :
 Access to memory is provided only by Load and Store instructions. In a Load
instruction, the operand is transferred from the memory into the general-purpose-register
named in the 4-bit Rd field.
 Load instructions have the mnemonics LDR and LDRB.
 The OP-code mnemonic LDR specifies that a 32-bit word is loads from the memory into
a register.
 A byte operand can be loaded into the low-order byte position of a register by using the
mnemonic LDRB. The higher order bits are filled with zeros.
Examples for Load instructions :
i) The Load instruction LDR Rd, [Rn, #offset ] specifies the offset in the immediate
and performs the operation Rd [ [ Rn ] + offset ]
ii) The Load instruction LDR Rd, [ Rn, Rm ] performs the operation
Rd [ [ Rn ] + [ Rm ] ]
iii) The Load instruction LDR Rd, [Rn ] performs the operation
Rd [ [ Rn ] ]
Store Instructions :
 Store instructions have the mnemonics STR and STRB.
 In a Store instruction, the operand is transferred from Rd into the memory. If the operand
is a byte, it is always located in the low-order byte position of the register Rd by sing the
mnemonic STRB.
 For example, the Store instruction STR Rd, [ Rn ] performs the operation
[ Rn ] [ Rd ] transferring a word operand into the memory.
 The STRB instruction transfers the byte contained in the low-order end of Rd.
5.ARM MEMORY ADDRESSING MODES :
 The form of all these three indexed addressing modes are as follows: Pre-indexed mode,
Pre-indexed with write back mode and Post-indexed mode.
1. Pre-indexed mode : The effective address of the operand is the sum of the contents of the
base register Rn and an offset value.
2. Pre-indexed with writeback mode : The effective address of the operand is generated in the
same way as in the Pre-indexed mode and then the effective address is written back into Rn.
3. Post-indexed mode : The effective address of the operand is the contents of Rn. The offset is
then added to this address and the result is written back into Rn.
Table 1 specifies the assembly language syntax for these addressing modes, and gives
expressions for the calculation of the effective address EA, and the writeback operations. The
exclamation mark signifies writeback in the Pre-indexed addressing mode. The Post-indexed
mode always involves writeback, so the exclamation mark is not needed.
In all three addressing modes, the offset may be given as an immediate value in the range
+4095. The magnitude of the offset may be specified as the contents of the third register Rm,
with the sign of the offset specified by a + prefix on the register name.
For example, the instruction LDR, [R1, - R2 ] ! performs the operation
R0 [[R1] - [R2]]
The effective address of the operand [R1] - [R2] is then loaded into R1 because writeback is
specified by the exclamation mark.
When the offset is given in a register, it may be scaled by a power of 2 by shifting to the
right or left. The amount of shift is specified by an immediate value.

For example, the instruction LDR R0,[R1 – 16 [R2]] performs the operation

R0 [[R1] – 16 × [R2]]
The contents of R2 is multiplied by 16 before being used as an offset and then load the effective
address into R1.
Table 1: ARM Indexed Addressing Modes
Figure 5(a) is an example of the Relative addressing mode. The address of the operand
given symbolically as ITEM in the instruction is 1060. The Relative addressing mode is
implemented by the pre-indexed mode with an immediate offset using PC as the base register.
The offset calculated by the assembler is 52 because the updated PC will contain 1008 when the
offset is added to it during program execution, and the effective address to be generated is
1060=1008 + 52.
Figure5(b) shows an example of the Pre-indexed mode with the offset contained in
register R6 and the base value contained in R5. The Store instruction(STR) stores the contents of
R3 into memory word location 1200.
Figure 5: Examples of ARM memory addressing modes
Figure 6 illustrates the writeback future in the Post-indexed and Pre-indexed addressing
modes. Figure6(a) shows the Post-indexed addressing with writeback. Suppose that R2 is used
as the base register and that it contains the initial address value 1000. Register R10 is used to
hold the offset, and it is loaded with the value 25.
The Load instruction LDR R1,[R2],R10,LSL #2
 The load instruction is executed and the effective address is [R2]=1000.The number 6 at
this address , is loaded into R1. Then, the writeback operation changes the contents of R2 from
1000 to 1100, so that it points to the second number -17. It does this by shifting the contents,25
of the offset register R10 left by two bit positions and then adding them to the contents of R2.
The left shift is equivalent to multiplying 25 by 4, generating the required offset 100. After this
offset is added to the contents of R2, the new address 1100 is written back into R2. When the
Load instruction is executed on the second pass through the loop, the second number -17 is
loaded into R1. The third number 321 is loaded into R1 on the third pass, and so on.

Figure 6: ARM memory addressing modes involving writeback.

Figure 6(b) shows the Pre-indexed addressing with writeback. The register R0 value 27 is
pushed onto a stack. Register R5 is used as the stack pointer. Initially, it contains the address
2012 of the current TOS(top of stack) element. The Pre-indexed addressing mode with
writeback, using an immediate offset, can be used to perform the Push operation with the
instruction STR R0,[R5,#-4]!
The immediate offset -4 is added to the contents, 2012 of R5 and written back into R5. This
new TOS location 2008 is used as the effective address for the Store operation. The contents 27
of register R0 are stored at location 2008.
LOAD/STORE MULTIPLE OPERANDS:
There are two instructions for loading and storing multiple operands. They are called
Block transfer instructions. Only word operands are allowed and the OP codes used are
LDM(Load Multiple) and STM(Store Multiple). They operate on a base register Rn specified in
the instruction. The list of registers must appear in increasing order in the assembly language
expression for the instruction.
For example, the instruction LDMIA R10!,[R0,R1,R6,R7]
The register R10 is the Base register and that it contains the value 1000 initially. The above
instruction transfers the words from locations 1000,1004,1008 and 1012 into registers R0,R1,R6
and R7, leaving the address value 1016 in R10 after the last transfer. The suffix IA in the OP
code indicates “Increment After” corresponding to post-indexing.

6. REGISTER MOVE INSTRUCTIONS:

 The Register move instructions are used to copy the contents of one register into another
register, or to load an immediate value into register.
 The Move instruction format is : MOV Rd , Rm
This instruction means, copy the contents of register Rm into register Rd.
 An immediate operand in the low-order 8 bits of the instruction can also be loaded into
register Rd by the Move instruction.
 For example, MOV R0, #76 places the immediate value 76 into register R0. In both
forms of the Move instruction, the source operand can be shifted before being placed in
the destination register.

7. INPUT/OUTPUT OPERATIONS :
 The ARM architecture uses memory-mapped I/O. Reading a character from a keyboard
or sending a character to a display can be done using program-controlled I/O.
 Suppose that bit 3 in each of the device status registers INSTATUS(keyboard) and
OUTSTATUS(display) contains the respective control flags SIN and SOUT.
 The keyboard DATAIN and display DATAOUT registers are located at address
INSTATUS + 4 and OUTSTATUS + 4, immediately following the status register
locations.
 The read and write wait loops can be implemented as follows. Assume that address
INSTATUS has been loaded into register R1. The instruction sequence
 READWAIT LDR R3, [R1]
TST R3, #8
BEQ READWAIT
LDRB R3, [R1, #4]
 Reads a character into register R3 when a key has been pressed on the keyboard. The
test(TST) instruction performs the bitwise logical AND operation on its two operands and
sets the condition code flags based on the result.
 The immediate operand 8 has a single one in the bit 3 position. Therefore , the result of
the TST operation will be zero if bit 3 of INSTATUS is zero and will be nonzero if bit 3
is one, signifying that a character is available in DATAIN.
 The BEQ instruction branches back to READWAIT if the result is zero, looping until a
key is pressed, which sets bit 3 of INSTATUS to one.
 Assuming that address OUTSTATUS has been loaded into register R2, the instruction
sequence
WRITEWAIT LDR R4, [R2]
TST R4, #8
BEQ WRITEWAIT
STRB R3, [R2, #4]
 Sends the character in register R3 to the DATAOUT register when the display is ready
to receive it.

These two routines can be used to read a line of characters from a keyboard, store them in
the memory, and echo them back to a display as shown in Figure 7. Registers R1 through R4
have the same usage as in the READWAIT and WRITEWAIT loops. The Store(STRB)
instruction stores the character read from the keyboard into the memory. The Test if
Equal(TEQ) instruction tests whether or not the two operands are equal and sets the Z condition
code flag accordingly.

Figure 7: An ARM program that reads a line of characters and displays it.