Compal confidential schematics for G470/G570 motherboards

A B C D E
1 1
2
Compal Confidential 2
G470/G570 DIS+UMA+Muxless M/B Schematics Document

Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
ATI Robson/PX3.0,PX4.0
3
2010-10-22 3
LA-6751P / LA-6753P
REV:0.3
4 4
Security Classification Compal Secret Data Compal Electronics,

Cover Page Inc.
THII S SHEET
IssuedOFDate 2010/07/12
ENGII NEERII NG DRAWII NG I S THE PROPRII ETARY PROPERTY OF COMPAL ELECTRONII CS,, I NC.. AND CONTAII NS 2012/07/11
Deciphered Date CONFII DENTII AL Tiitlle
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D Siize Document Number Rev
0.2
DEPART MENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-6751P
Date: Friiday, November 26, 2010 Sheet 1 of 59
A B C D E
A B C D E
Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)

File Name : G470/G570 LS6753P PWR/B LS6753P PWR/B
LS6751P CardReader/B LS6751P CardReader/B
Page23-30 LS6754P LED/B
AMD LS6755P ODD/B
Intel
Robson XT Sandy Bridge
1 1
VRA D M *2
DDR3*4 Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
37.5mm*37.5mm
Dual Channel Up to 8GB
Page33 Page5-11 DDR3 1066MHz(1.5V)
HDMI
DDR3 1333MHz(1.5V)
Connector
100MHz
CRT Page32 2.7GT/s FDI *8 DMI *4
Connector A 2 channel
LVDS Page31 AZALIA C
Cougar Point Int. MIC
CX20671
2
Connector FCBGA 989 2
Page39 Audio Jacks

25mm*25mm
Page35 PCI-E x1 *6 USB2.0 *14
LAN
Athros Camera Conn.
AR8151-B(GLAN)
AR8152-B(10/100) SATA *6 BlueTooth Conn.
Page42
Page14-22
Page36 Mini Card Slot *1
RJ-45 SPIROM Page34
Connector BIOS
LPC BUS Card Reader
Page40 Reltek
PCI Express PCI-E( WLAN) EC RTS5139
Mini Card Slot *1 ENE KB930
USB(WiMAX) SDXC/MMC/MS/xD
ENE KB9012
3
WLAN 3
WiMAX Page34 USB2.0 *1(Right)
Int. KBD USB2.0 *2(Left)

Touch Pad
Thermal Sensor SPI ROM
Page41
eSATA+USB(Left) Page42
EMC1403 Page37
SATA3 HDD (Port 0/Port 1 support SATA3)
Page38
SATA ODD Page38

4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Tiitlle
Block Diagram
THII S SHEET OF ENGII NEERII NG DRAWII NG I S THE PROPRII ETARY PROPERTY OF COMPAL ELECTRONII CS,, I NC.. AND CONTAII NS CONFII DENTII AL
Siize Document Number Rev
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
Custom 0.2
LA-6751P
A B C D E
A B C D
SIGNA
Voltage Rails L STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

+3VS
powe S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
r +1.5VS
1
plan +VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
e +5VALW +1.5V +CPU_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +GFX_CORE
+1.8VS
BOARD ID Table Board ID / SKU ID Table for AD channel
+0.75VS Vcc 3.3V +/- 5%
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
State +1.05VS 0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1
0 0 0 V 0 V 0 V EVT
2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
3
2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
4
3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
5
S0
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
6
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
7
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
S3 O O O 7 NC 2.500 V 3.300 V 3.300 V
X
2
S5 S4/AC O O X X
USB Port Table BOM Structure Tab le
S5 S4/ Battery only O X X X 3 External BTO Item BOM Structure
USB 2.0 USB 1.1 Port USB Port UMA and PX bus PX@
S5 S4/AC &
Battery don't X X X X UHCI0
0 USB/B (Right Side) Discrete Only DIS@
exist Address 1 USB Port (Left Side) PX3.0 only, not for BACO PX3@
EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side) BACO BACO@
UHCI1
3 USB Port (Left Side) COMMON HDMI HDMI@
Device Device Address EHCI1 4 UMA HDMI UMA_HDMI@
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb UHCI2
5 Camera Discrete HDMI VGA_HDMI@
Thermal Sensor EMC1402-1 100_1100 b
6 eSATA ESATA@
UHCI3
7 Blue Tooth BT@
PCH SM Bus address 8 Mini Card(WLAN) Connector ME@
UHCI4
9 45 LEVEL 45@
Device Address
10 10/100 LAN 8152@
DDR DIMM0 1001 000Xb EHCI2 UHCI5
3 11 Card Reader GIGA LAN GIGA@
DDR DIMM2 1001 010Xb
12 Cameara CMOS@
UHCI6
13 Blue Tooth
SMBUS Control Table Unpop @

Thermal
WLAN
SOURC VGA BATT KE930 SODIMM WWA Sensor PCH
E
SMB_EC_CK1 N
KB930
SMB_EC_DA1 +3VALW
X V
+3VALW
X X X X X
SMB_EC_CK2
KB930
SMB_EC_DA2 +3VALW
X X X X X X V
+3VS
SMBCLK
SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
+3VALW
SML0CLK
SML0DATA
PCH
+3VALW
X X X X X X X
4
SML1CLK
SML1DATA
PCH
+3VALW +3VS
V X V
+3VS
X X V
+3VS
X
Security Classification Compal Secret Data Compal Ele

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Tiitle
Notes List
Siize D
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D DEPART MENT
B
EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS
Dat e:
A B C D
5 4 3 2 1
Without BACO option :

Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. D
dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
ramp-up (or vice versa).) DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
Note: Do not drive any IOs before VDDR3 is ramped up. PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = 55mA@1.0V, in Same as OFF ON Same 70mA
PCIE_VDDC(1.0V) BACO mode)
VDDC as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VGS) VDDC/VDDCI 1.12V OFF OFF 12.9A C
VDDC/VDDCI(1.12V
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb
BIF_VDDC PE_GPIO1
B B
REFCLK PX_mode
+3.3VALW +3.3VGS
1
MOS
Straps Reset
+1.5V +1.5VGS
Straps Valid +1.0V Regulator
2
+1.0VGS SI4800
3
Global ASIC Reset

+B +VGA_CORE
4
+1.8V +1.8VGS Regulator
T4+16clock
SI4800
5
PWRGOOD
A A

Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
dGPU Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS Size Document Number Rev
CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE B 0.2
COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS LA-6751P
SHEET NOR THE INFORMATION IT CONTAINS Date: Friday, November 26, 2010 Sheet 4 of 59
5 4 MAY BE USED BY OR DISCLOSED TO ANY THIRD3 PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
2 INC. 1
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals
should be shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed
1
with - max length = 500 mils
R1
24.9_0402_1% - typical impedance = 14.5 mohms
2
JCPU1A
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
<16> DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
<16> DMI_CRX_PTX_N1 B25 DMI_RX#[1]
<16> DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_CRX_GTX_N[0..15] <23>
B24 K33 PCIE_CRX_GTX_N15
<16> DMI_CRX_PTX_N3 DMI_RX#[3] PEG_RX#[0]
M35 PCIE_CRX_GTX_N14
DMI
B28 PEG_RX#[1] L34 PCIE_CRX_GTX_N13
<16> DMI_CRX_PTX_P0 DMI_RX[0] PEG_RX#[2]
<16> DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 PCIE_CRX_GTX_N12 PEG Static Lane Reversal - CFG2 is for the 16x
A24 J32 PCIE_CRX_GTX_N11
<16> DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4] PCIE_CRX_GTX_N10
<16> DMI_CRX_PTX_P3 B23 H34
DMI_RX[3] PEG_RX#[5] H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
<16> DMI_CTX_PRX_N0 G21 DMI_TX#[0]
PEG_RX#[6]
PEG_RX#[7] G33 PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N7
CFG2 socket pin map definition
<16> DMI_CTX_PRX_N1 E22 DMI_TX#[1] PEG_RX#[8] G30
F21 F35 PCIE_CRX_GTX_N6
<16> DMI_CTX_PRX_N2
D21 DMI_TX#[2] PEG_RX#[9] E34 PCIE_CRX_GTX_N5 0:Lane Reversed
<16> DMI_CTX_PRX_N3
G22
DMI_TX#[3] PEG_RX#[10]
PEG_RX#[11] E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
*
<16> DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12] PCIE_CRX_GTX_N2
<16> DMI_CTX_PRX_P1 D22 DMI_TX[1] PEG_RX#[13] D31
C F20 B33 PCIE_CRX_GTX_N1 C
<16> DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PCIE_CRX_GTX_N0
<16> DMI_CTX_PRX_P3 C21 C32
DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] <23>
PCIE_CRX_GTX_P15
PEG_RX[0] J33
L35 PCIE_CRX_GTX_P14
PEG_RX[1]
K34 PCIE_CRX_GTX_P13
A21 PEG_RX[2] H35 PCIE_CRX_GTX_P12
<16> FDI_CTX_PRX_N0 FDI0_TX#[0] PEG_RX[3]
H19 H32 PCIE_CRX_GTX_P11
<16> FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] G34
<16> FDI_CTX_PRX_N2 E19 PCIE_CRX_GTX_P10
FDI0_TX#[2] PEG_RX[5] PCIE_CRX_GTX_P9
<16> FDI_CTX_PRX_N3 F18 FDI0_TX#[3] PEG_RX[6] G31
DISCRETE ONLY <16> FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33 PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P7
C20 PEG_RX[8] F30
PCI EXPRESS* -
1K_0402_5% 2 DIS@ <16> FDI_CTX_PRX_N5 FDI1_TX#[1]
1 R2 FDI_FSYNC0
<16> FDI_CTX_PRX_N6 D18 FDI1_TX#[2] PEG_RX[9] E35
PCIE_CRX_GTX_P6
E17 E33 PCIE_CRX_GTX_P5
Intel(R)
DIS@ <16> FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
1 R3 FDI_FSYNC1 F32
PEG_RX[11] D34
PCIE_CRX_GTX_P4
GRAPHICS
PCIE_CRX_GTX_P3
1K_0402_5% 2 DIS@ PEG_RX[12]
1 R4 FDI_INT
<16> FDI_CTX_PRX_P0 A22 FDI0_TX[0] PEG_RX[13] E31 PCIE_CRX_GTX_P2
G19 C33 PCIE_CRX_GTX_P1
FDI_LSYNC0 <16> FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] PCIE_CRX_GTX_P0
1K_0402_5% 2 DIS@ 1 R5 <16> FDI_CTX_PRX_P2 E20 FDI0_TX[2] PEG_RX[15] B32
G18
FDI_LSYNC1 <16> FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N[0..15] <23>
1K_0402_5% 2 DIS@ 1 R6 <16> FDI_CTX_PRX_P4 B20 FDI1_TX[0] PEG_TX#[0] M29 C1 1 2 0.1U_0402_10V6K
C19 M32 PCIE_CTX_GRX_C_N14 C2 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N14
<16> FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
FDI
D19 M31 PCIE_CTX_GRX_C_N13 C3 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N13
1K_0402_5% 2 <16> FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] PCIE_CTX_GRX_C_N12 C4 0.1U_0402_10V6K PCIE_CTX_GRX_N12
<16> FDI_CTX_PRX_P7 F17 L32 1 2
FDI1_TX[3] PEG_TX#[3] L29 PCIE_CTX_GRX_C_N11 C5 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N11
FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_N10
<16> FDI_FSYNC0 J18 K31 C6 1 2 0.1U_0402_10V6K
+1.05VS FDI_FSYNC1 FDI0_FSYNC PEG_TX#[5] PCIE_CTX_GRX_C_N9 C7 0.1U_0402_10V6K PCIE_CTX_GRX_N9
<16> FDI_FSYNC1 J17 K28 1 2
FDI1_FSYNC PEG_TX#[6] J30 PCIE_CTX_GRX_C_N8 C8 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N8
PEG_TX#[7]
<16> FDI_INT FDI_INT H20 J28 PCIE_CTX_GRX_C_N7 C9 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N7
FDI_INT PEG_TX#[8]
H29 PCIE_CTX_GRX_C_N6 C10 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N6
PEG_TX#[9]
1
FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5

<16> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
R7 <16> FDI_LSYNC1 FDI_LSYNC1 H17 E29 PCIE_CTX_GRX_C_N4 C12 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N4
24.9_0402_1% FDI1_LSYNC PEG_TX#[11] PCIE_CTX_GRX_C_N3 C13 0.1U_0402_10V6K PCIE_CTX_GRX_N3
F27 1 2
PEG_TX#[12]
D28 PCIE_CTX_GRX_C_N2 C14 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N2
B PEG_TX#[13] B
2
F26 PCIE_CTX_GRX_C_N1 C15 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N1

PEG_TX#[14]
E25 PCIE_CTX_GRX_C_N0 C16 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N0
EDP_COMP PEG_TX#[15]
A18 eDP_COMPIO PCIE_CTX_GRX_P[0..15] <23>
eDP_COMPIO and ICOMPO signals A17
eDP_ICOMPO PEG_TX[0]
M28 PCIE_CTX_GRX_C_P15 C17 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P15
eDP_HPD B16 M33 PCIE_CTX_GRX_C_P14 C18 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P14
should be shorted near balls eDP_HPD PEG_TX[1]
M30 PCIE_CTX_GRX_C_P13 C19 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P13
PEG_TX[2]
and routed with typical L31 PCIE_CTX_GRX_C_P12 C20 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P12
PEG_TX[3]
eDP
PCIE_CTX_GRX_C_P11 C21 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11

impedance <25 mohms C15
D15
eDP_AUX PEG_TX[4] L28 PCIE_CTX_GRX_C_P10 C22 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P10
eDP_AUX# PEG_TX[5] K30
K27 PCIE_CTX_GRX_C_P9 C23 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P9
PEG_TX[6]
J29 PCIE_CTX_GRX_C_P8 C24 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P8
PEG_TX[7]
C17 J27 PCIE_CTX_GRX_C_P7 C25 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P7
eDP_TX[0] PEG_TX[8]
F16 H28 PCIE_CTX_GRX_C_P6 C26 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P6
eDP_TX[1] PEG_TX[9]
C16 G28 PCIE_CTX_GRX_C_P5 C27 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P5
eDP_TX[2] PEG_TX[10]
G15 E28 PCIE_CTX_GRX_C_P4 C28 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P4
eDP_TX[3] PEG_TX[11]
F28 PCIE_CTX_GRX_C_P3 C29 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P3
PEG_TX[12]
C18 D27 PCIE_CTX_GRX_C_P2 C30 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P2
eDP_TX#[0] PEG_TX[13]
E16 E26 PCIE_CTX_GRX_C_P1 C31 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P1
D16 D25 PCIE_CTX_GRX_C_P0 C32 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P0
F15
eDP_TX#[3]
Sandy Briidge_rPGA_Rev1p0
ME@
A A

PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D Custom 0.2
DEPART MENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS LA-6751P
5 4 3 2 1
5 4 3 2 1
JCPU1B
D D
CLK_CPU_DMI_R
R10 0_0402_5% DG1.0
A28 1 2
CLOCKS
CLK_CPU_DMI <15>
MISC
C26 BCLK A27 CLK_CPU_DMII#_R R11 1 2
<18> H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# <15>
0_0402_5%
AN34
SKTOCC#
DPLL_REF_CLK A16 R12
R13
2 1 1K_0402_5% DG1.0
A15 2 1 1K_0402_5% +1.05VS
DPLL_REF_CLK#
+1.05VS
closs to EC 250~750mils H_CATERR# AL33
1
CATERR# R9
THERMAL
62_0402_5%
H_PECI AN33 R8 H_DRAMRST#
<19,40> H_PECI PECI SM_DRAMRST# H_DRAMRST# <7>
R15
DDR3
MISC
2
56_0402_5%
H_PROCHOT# 1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP0 R16 2 1 140_0402_1%
<40> H_PROCHOT# PROCHOT# SM_RCOMP[0]
SM_RCOMP[1]
A5 SM_RCOMP1
SM_RCOMP2
R17 2 1 25.5_0402_1% DDR3 Compensation Signals
A4 R18 2 1 200_0402_1%
SM_RCOMP[2]
H_THRMTRIP# AN32
<19> H_THRMTRIP# THERMTRIP#
AP29 XDP_PRDY# +1.05VS

PRDY# XDP_PREQ#
AP27
PREQ#
R22 AR26 XDP_TCK XDP_TMS R20 2 1 51_0402_5%
TCK
0_0402_5% AR27 XDP_TMS XDP_TDI R21 2 1 51_0402_5% PU/PD for JTAG
C
H_PM_SYNC_R TMS signals
XDP_TRST# XDP_TDO R23 @
C
<16> H_PM_SYNC 1 2 AM34 AP30 2 1 51_0402_5%
PM_SYNC TRST#
AR28 XDP_TDI XDP_TCK R24 2 1 51_0402_5%
TDI XDP_TDO XDP_TRST# R25
R26 AP26 2 1 51_0402_5%
H_CPUPW RGD_R TDO
MANAGEMENT
0_0402_5%1 2 AP33
<19> H_CPUPW RGD
JTAG &
UNCOREPW RGOOD
2
R27 1 2 PM_DRAM_PW RGD_R V8 SM_DRAMPW ROK
BPM
10K_0402_5% 130_0402_5%
AT28 XDP_BPM#0
BPM#[0] XDP_BPM#1
AR29
BPM#[1]
1
AR30 XDP_BPM#2
BUF_CPU_RST# AR33 BPM#[2] AT30 XDP_BPM#3
RESET# BPM#[3] XDP_BPM#4
AP32
PWR
BPM#[4] XDP_BPM#5
BPM#[5] AR31
XDP_BPM#6
AR32
+3VALW BPM#[7]
1
C33 Sandy Briidge_rPGA_Rev1p0
0.1U_0402_16V4Z ME@
2
10/12 reserve R880 / R882

+1.5V_CPU_VDDQ
0_0402_5% R882 +3VS
1 @ 2
<16,40> PCH_POK
B B
1
0_0402_5% R880 R30

1 @ 2 U1 200_0402_5% +1.05VS
<16> SYS_PW ROK 1
C34
R161 100K_0402_5% 0.1U_0402_16V4Z
5
+3VS 1 2 1 B 2
2
1
PM_SYS_PW RGD_BUF R32
P
4
2 O 75_0402_5%
<16> PM_DRAM_PW RGD A
G
74AHC1G09GW _TSSOP5 R34 U2

1
5
@ 43_0402_1% 1 3V
3
R33 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC
P
39_0402_5% Y PLT_RST#
A 2 PLT_RST# <18>
SN74LVC1G07DCKR_SC70-5
G
1
1 2
@ R35 @
D
3
<10,44,51> SUSP SUSP 2 Q1 0_0402_5%
G 2N7002H_SOT23-3
Change footprint
20100814
2
S
3
A A

PROCESSOR(2/7) PM,XDP,CLK
5 4 3 2 1
5 4 3 2 1
JCPU1C JCPU1D
SA_CLK[0] AB6 M_CLK_DDR0 <12> SB_CLK[0] AE2 M_CLK_DDR2 <13>

<12> DDR_A_D[0..63] AA6 <13> DDR_B_D[0..63] AD2
SA_CLK#[0] M_CLK_DDR#0 <12> SB_CLK#[0] M_CLK_DDR#2 <13>
DDR_A_D0 DDR_B_D0
C5 V9 C9 R9
SA_DQ[0] SA_CKE[0] DDR_CKE0_DIMMA <12> SB_DQ[0] SB_CKE[0] DDR_CKE2_DIMMB <13>
DDR_A_D1 D5 DDR_B_D1 A7
DDR_A_D2 D3 SA_DQ[1] DDR_B_D2 D10 SB_DQ[1]
DDR_A_D3 D2 SA_DQ[2] DDR_B_D3 C8 SB_DQ[2]
DDR_A_D4 D6 SA_DQ[3] AA5 DDR_B_D4 A9 SB_DQ[3] AE1
D DDR_A_D5 C6 SA_DQ[4] SA_CLK[1] M_CLK_DDR1 <12> DDR_B_D5 A8 SB_DQ[4] SB_CLK[1] M_CLK_DDR3 <13> D
SA_CLK#[1] AB5 SB_CLK#[1] AD1
DDR_A_D6 C2 SA_DQ[5] V10 M_CLK_DDR#1 <12> DDR_B_D6 D9 SB_DQ[5] R10 M_CLK_DDR#3 <13>
DDR_A_D7 C3 SA_CKE[1] DDR_CKE1_DIMMA <12> DDR_B_D7 D8 SB_CKE[1] DDR_CKE3_DIMMB <13>
SA_DQ[6] SB_DQ[6]
DDR_A_D8 F10 DDR_B_D8 G4
F8 SA_DQ[7] F4 SB_DQ[7]
DDR_A_D9 DDR_B_D9
DDR_A_D10 G10 SA_DQ[8] DDR_B_D10 F1 SB_DQ[8]
DDR_A_D11 G9 SA_DQ[9] RSVD_TP[1] AB4 DDR_B_D11 G1 SB_DQ[9] RSVD_TP[11] AB2
DDR_A_D12 F9 SA_DQ[10] RSVD_TP[2] AA4 DDR_B_D12 G5 SB_DQ[10] RSVD_TP[12] AA2
DDR_A_D13 F7 SA_DQ[11] W9 DDR_B_D13 F5 SB_DQ[11] T9
RSVD_TP[3] RSVD_TP[13]
DDR_A_D14 G8 SA_DQ[12] DDR_B_D14 F2 SB_DQ[12]
DDR_A_D15 G7 SA_DQ[13] DDR_B_D15 G2 SB_DQ[13]
DDR_A_D16 K4 SA_DQ[14] DDR_B_D16 J7 SB_DQ[14]
DDR_A_D17 K5 AB3 DDR_B_D17 J8 AA1
K1 SA_DQ[15] RSVD_TP[4] K10 SB_DQ[15] RSVD_TP[14]
DDR_A_D18 AA3 DDR_B_D18 AB1
DDR_A_D19 J1 SA_DQ[16] RSVD_TP[5] W 10 DDR_B_D19 K9 SB_DQ[16] RSVD_TP[15] T10
J5 SA_DQ[17] RSVD_TP[6] J9 SB_DQ[17] RSVD_TP[16]
DDR_A_D20 DDR_B_D20
DDR_A_D21 J4 SA_DQ[18] DDR_B_D21 J10 SB_DQ[18]
DDR_A_D22 J2 SA_DQ[19] DDR_B_D22 K8 SB_DQ[19]
DDR_A_D23 SA_DQ[20] AK3 DDR_B_D23 SB_DQ[20] AD3
SA_DQ[21] SA_CS#[0] SB_DQ[21] SB_CS#[0]
DDR_CS0_DIMMA# <12> DDR_CS2_DIMMB# <13>
SA_DQ[22] SB_DQ[22]
K2 AL3 K7 AE3
SA_DQ[23] SA_CS#[1] DDR_CS1_DIMMA# <12> SB_DQ[23] SB_CS#[1] DDR_CS3_DIMMB# <13>
DDR_A_D24 M8 AG1 DDR_B_D24 M5 AD6
DDR_A_D25 N10 SA_DQ[24] RSVD_TP[7] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
SA_DQ[25] AH1 N4 AE6
DDR_A_D26 N8 RSVD_TP[8] DDR_B_D26 SB_DQ[25] RSVD_TP[18]
DDR_A_D27 N7 SA_DQ[26] DDR_B_D27 N2
SB_DQ[26]
DDR_A_D28 M10 SA_DQ[27] DDR_B_D28 N1
M9 SB_DQ[27]
DDR_A_D29 SA_DQ[28] DDR_B_D29 M4
DDR_A_D30 AH3 M_ODT0 <12> DDR_B_D30 SB_DQ[28] AE4 M_ODT2 <13>
SA_DQ[29] SA_ODT[0] N5 SB_ODT[0]
SB_DQ[29]
N9 AG3 M2 AD4
SA_DQ[30] SA_ODT[1] M_ODT1 <12> SB_DQ[30] SB_ODT[1] M_ODT3 <13>
DDR_A_D31 M7 AG2 DDR_B_D31 M1 AD5
SA_DQ[31] RSVD_TP[9] SB_DQ[31] RSVD_TP[19]
DDR SYSTEM MEMORY

DDR_A_D32 AG6 AH2 DDR_B_D32 AM5 AE5
DDR SYSTEM MEMORY

SA_DQ[32] RSVD_TP[10] SB_DQ[32] RSVD_TP[20]
DDR_A_D33 AG5 DDR_B_D33 AM6
DDR_A_D34 AK6 SA_DQ[33] DDR_B_D34 AR3 SB_DQ[33]
DDR_A_D35 AK5 SA_DQ[34] DDR_B_D35 AP3 SB_DQ[34]
DDR_A_D36 AH5 SA_DQ[35] DDR_B_D36 AN3 SB_DQ[35]
C
DDR_A_D37 AH6 SA_DQ[36] C4 DDR_A_DQS#[0..7] <12> DDR_B_D37 AN2 SB_DQ[36] D7 DDR_B_DQS#[0..7] <13>
DDR_A_D38 AJ5 SA_DQS#[0] DDR_A_DQS#0 DDR_B_D38 AN1 SB_DQS#[0] DDR_B_DQS#0 C
AJ6 SA_DQ[37] G6 DDR_A_DQS#1 AP2 SB_DQ[37] F3 DDR_B_DQS#1
DDR_A_D39 SA_DQS#[1] DDR_B_D39 SB_DQS#[1]
AJ8 SA_DQ[38] SA_DQS#[2] J3 DDR_A_DQS#2 AP5 SB_DQ[38] SB_DQS#[2] K6 DDR_B_DQS#2
DDR_A_D40 DDR_B_D40
DDR_A_D41 AK8 SA_DQ[39] SA_DQS#[3] M6 DDR_A_DQS#3 DDR_B_D41 AN9 SB_DQ[39] SB_DQS#[3] N3 DDR_B_DQS#3
DDR_A_D42 AJ9 SA_DQ[40] SA_DQS#[4] AL6 DDR_A_DQS#4 DDR_B_D42 AT5 SB_DQ[40] SB_DQS#[4] AN5 DDR_B_DQS#4
AK9 SA_DQS#[5] AM8 DDR_A_DQS#5 AT6 SB_DQS#[5] AP9 DDR_B_DQS#5
DDR_A_D43 SA_DQ[41] DDR_B_D43 SB_DQ[41]
DDR_A_D44 AH8 SA_DQS#[6] AR12 DDR_A_DQS#6 DDR_B_D44 AP6 SB_DQS#[6] AK12 DDR_B_DQS#6
SA_DQ[42] AM15 SB_DQ[42] AP15
DDR_A_D45 AH9 SA_DQS#[7] DDR_A_DQS#7 DDR_B_D45 AN8 SB_DQS#[7] DDR_B_DQS#7
SA_DQ[43] SB_DQ[43]
DDR_A_D46 AL9 SA_DQ[44] DDR_B_D46 AR6 SB_DQ[44]
DDR_A_D47 AL8 DDR_B_D47 AR5
DDR_A_D48 AP11 SA_DQ[45] DDR_B_D48 AR9 SB_DQ[45]
DDR_A_D49 AN11 SA_DQ[46] DDR_B_D49 AJ11 SB_DQ[46]
DDR_A_D50 AL12 SA_DQ[47] D4 DDR_B_D50 AT8 SB_DQ[47] C7
SA_DQS[0] DDR_A_DQS0 DDR_A_DQS[0..7] <12> SB_DQS[0] DDR_B_DQS0
DDR_A_D51 AM12 SA_DQ[48] F6 DDR_B_D51 AT9 SB_DQ[48] G3 DDR_B_DQS[0..7] <13>
SA_DQS[1] DDR_A_DQS1 SB_DQS[1] DDR_B_DQS1
DDR_A_D52 AM11 SA_DQ[49] K3 DDR_A_DQS2 DDR_B_D52 AH11 SB_DQ[49] J6 DDR_B_DQS2
DDR_A_D53 AL11 SA_DQS[2] DDR_B_D53 AR8 SB_DQS[2]
SA_DQ[50] SA_DQS[3] N6 DDR_A_DQS3 SB_DQ[50] SB_DQS[3] M3 DDR_B_DQS3
DDR_A_D54 AP12 SA_DQ[51] AL5 DDR_A_DQS4 DDR_B_D54 AJ12 SB_DQ[51] AN6 DDR_B_DQS4
AN12 SA_DQS[4] AH12 SB_DQS[4]
DDR_A_D55 SA_DQ[52] AM9 DDR_A_DQS5 DDR_B_D55 SB_DQ[52] AP8 DDR_B_DQS5
DDR_A_D56 AJ14 SA_DQS[5] DDR_B_D56 AT11 SB_DQS[5]
SA_DQS[6] AR11 DDR_A_DQS6 SB_DQS[6] AK11 DDR_B_DQS6
DDR_A_D57 AH14 SA_DQ[53] AM14 DDR_B_D57 AN14 SB_DQ[53] AP14
SA_DQ[54] SA_DQS[7] DDR_A_DQS7 SB_DQ[54] SB_DQS[7] DDR_B_DQS7
DDR_A_D58 AL15 DDR_B_D58 AR14
B
DDR_A_D59 AK15 SA_DQ[55] DDR_B_D59 AT14 SB_DQ[55]
A
DDR_A_D60 AL14 SA_DQ[56] DDR_B_D60 AT12 SB_DQ[56]

DDR_A_D61 AK14 SA_DQ[57] DDR_B_D61 AN15 SB_DQ[57]
DDR_A_D62 AJ15 SA_DQ[58] DDR_B_D62 AR15 SB_DQ[58]
AH15 SA_MA[0] AD10 AT15 SB_MA[0] AA8
DDR_A_D63 SA_DQ[59] DDR_A_MA0 DDR_B_D63 SB_DQ[59] DDR_B_MA0
SA_MA[1] W1 DDR_A_MA1 SB_MA[1] T7 DDR_B_MA1
SA_DQ[60] W2 DDR_A_MA[0..15] <12> SB_DQ[60] R7 DDR_B_MA[0..15] <13>
SA_MA[2] DDR_A_MA2 SB_MA[2] DDR_B_MA2
SA_DQ[61] SA_MA[3] W7 DDR_A_MA3 SB_DQ[61] SB_MA[3] T6 DDR_B_MA3
SA_DQ[62] SA_MA[4] V3 DDR_A_MA4 SB_DQ[62] SB_MA[4] T2 DDR_B_MA4
SA_DQ[63] SA_MA[5] V2 DDR_A_MA5 SB_DQ[63] SB_MA[5] T4 DDR_B_MA5
AE10 SA_MA[6] W3 DDR_A_MA6 AA9 SB_MA[6] T3 DDR_B_MA6
AF10 SA_MA[7] W6 DDR_A_MA7 AA7 SB_MA[7] R2 DDR_B_MA7
V6 SA_MA[8] V1 DDR_A_MA8 R6 SB_MA[8] T5 DDR_B_MA8
SA_MA[9] W5 DDR_A_MA9 SB_MA[9] R3 DDR_B_MA9
SA_MA[10] AD8 DDR_A_MA10 SB_MA[10] AB7 DDR_B_MA10
B <12> DDR_A_BS0 SA_BS[0] V4 <13> DDR_B_BS0 SB_BS[0] R1 B
<12> DDR_A_BS1 SA_BS[1] SA_MA[11] DDR_A_MA11 SB_BS[1] SB_MA[11] DDR_B_MA11
SA_MA[12] W4 DDR_A_MA12 <13> DDR_B_BS1 SB_MA[12] T1 DDR_B_MA12
<12> DDR_A_BS2 AE8 SA_BS[2] AF8 <13> DDR_B_BS2 AA10 SB_BS[2] AB10
AD9 SA_MA[13] DDR_A_MA13 AB8 SB_MA[13] DDR_B_MA13
SA_MA[14] V5 DDR_A_MA14 SB_MA[14] R5 DDR_B_MA14
AF9 V7 AB9 R4
SA_MA[15] DDR_A_MA15 SB_MA[15] DDR_B_MA15
<12> DDR_A_CAS# SA_CAS# <13> DDR_B_CAS# SB_CAS#
<12> DDR_A_RAS# SA_RAS# <13> DDR_B_RAS# SB_RAS#
<12> DDR_A_W E# SA_W E# <13> DDR_B_W E# SB_W E#
Sandy Briidge_rPGA_Rev1p0 Sandy Briidge_rPGA_Rev1p0

ME@ ME@
+1.5V
1
@ R36
0_0402_5%
1 2 R37
1K_0402_5%
R38
2
1K_0402_5%
DDR3_DRAMRST#_R
S
<6> H_DRAMRST# H_DRAMRST# 3 1 1 2 DDR3_DRAMRST# <12,13>

Q2
G
2
2
R39 BSS138_NL_SOT23-3
4.99K_0402_1%
1
A A
R40
0_0402_5%
<15> DRAMRST_CNTRL_PCH 1 2 DRAMRST_CNTRL
Security Classification Compal Secret
1
Eiffel used 0.01u Data
Compal Electronics, Inc.
C35 2010/07/12 2012/07/11 Tiitlle
0.047U_0402_16V4Z Module design used Issued Date Deciphered
2
0.047u Date PROCESSOR(3/7) DDRIII
Custom 0.2
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
CFG2
1
R41
1K_0402_1%
2
D D
JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x
RSVD28
L7 1: Normal Operation; Lane # definition matches
AK28 RSVD29
AG7
AE7
CFG2 socket pin map definition
AK29 CFG[0] RSVD30 AK2
CFG[1] RSVD31
CFG2 0:Lane Reversed
CFG4
CFG5
AL26
AL27
AK26
AL29
CFG[2]
CFG[3]
CFG[4]
RSVD32 W8
AT26
* CFG4
CFG6 CFG[5] RSVD33
AL30 CFG[6] RSVD34 AM33
CFG7 AM31 AJ27
CFG[7] RSVD35
1
AM32 CFG[8]
AM30 @ R42
CFG[9]
AM28 1K_0402_1%
CFG[10]
AM26 CFG[11]
AN28 CFG[12]
2
AN31 CFG[13] RSVD37 T8
AN26 CFG[14] RSVD38 J16
AM27 CFG[15] RSVD39 H16
AK31 CFG[16] RSVD40 G16
AN29 CFG[17]
Display Port Presence Strap
AR35 1 : Disabled; No Physical Display Port

C
T9
T10
T11
PAD
PAD
PAD
AJ31
AH31
AJ33
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
RSVD41
RSVD42
RSVD43
AT34
AT33
AP35
CFG4 * attached to Embedded Display Port C
VCC_VAL_SENSE RSVD44
T12 PAD AH33 VSS_VAL_SENSE RSVD45 AR34 0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
AJ26
RSVD5
B34 CFG6
RESERVED
RSVD46
B4 A33
D1 RSVD6 RSVD47 A34
RSVD7 RSVD48 CFG5
RSVD49 B35
RSVD50 C35
@ R43 @ R44
R64 R353 F25 1K_0402_1% 1K_0402_1%
RSVD8
1
1K_0402_1% 1K_0402_1% F24 RSVD9
1
F23 RSVD10
D24 RSVD11 RSVD51 AJ32
G25 RSVD12 RSVD52 AK32
G24 RSVD13
8/5 Check E23
2
RSVD14
D23 RSVD15
2
C30 RSVD16 VCC_DIE_SENSE AH27 PAD T13

A31 RSVD17
B30 RSVD18
B29 RSVD19 PCIE Port Bifurcation Straps
D30 RSVD20 RSVD54 AN35
B31 AM35
RSVD21 RSVD55
*11:
A30 RSVD22 (Default) x16 - Device 1 functions 1 and 2 disabled
C29
RSVD23
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
J20 disabled
B18
RSVD24
RSVD25 RSVD56 AT2 01: Reserved - (Device 1 function 1 disabled ; function
A19
VCCIO_SEL RSVD57
AT1
AR1
2 enabled)
B RSVD58 B
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
J15
RSVD27
KEY B1
CFG7
@ R45
1K_0402_1%
Sandy Briidge_rPGA_Rev1p0
ME@
1
2
PEG DEFER
TRAINING
1: (Default) PEG Train immediately following

xxRESETB CFG7 de assertion
0: PEG Wait for BIOS for training
A A

PROCESSOR(4/7) RSVD,CFG
5 4 3 2 1
5 4 3 2 1
JCPU1F POWER
+CPU_CORE Cap quantity follow
(6/16 change 10uF_0603_6.3V)*5 HR_PDDG_Rev07
QC=94A 18A +1.05VS
22uF*7 NO-STUFF
DC=53A AG35
OSCAN(22uF_0805_6.3V)*13
VCC1
1 1 1 1 1 AG34 VCC2 AH13 +1.05VS
VCCIO1
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C36
C37
C38
C39
C40
AG33 VCC3 AH10 1 1 1 1 1 1 1 1 1 1
VCCIO2
22U_0805_6.3V6M
C41
22U_0805_6.3V6M
C42
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
C44
22U_0805_6.3V6M
C54
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
C46
22U_0805_6.3V6M
C55
22U_0805_6.3V6M
C56
22U_0805_6.3V6M
C47
AG31 VCCIO4 AC10
D 2 2 2 2 2 VCC5 Y10 D
AG30 VCCIO5
AG29 VCC6 U10 2 2 2 2 2 2 2 2 2 2
VCC7 VCCIO6
AG28 VCCIO7 P10
VCC8 L10
AG27 VCCIO8
AG26 VCC9 J14
VCC10 VCCIO9
AF35 VCCIO10 J13
VCC11 J12
AF34 VCCIO11
AF33 VCC12 J11
1 1 1 1 1 1 VCC13 VCCIO12
10U_0603_6.3V6M
C48
10U_0603_6.3V6M
C49
10U_0603_6.3V6M
C50
10U_0603_6.3V6M
C51
10U_0603_6.3V6M
C52
10U_0603_6.3V6M
C53
AF32 VCCIO13 H14 1 1 1 1 1 1 1 1 1
VCC14
22U_0805_6.3V6M
C59
22U_0805_6.3V6M
C60
22U_0805_6.3V6M
C61
22U_0805_6.3V6M
C62
22U_0805_6.3V6M
C63
22U_0805_6.3V6M
C64
22U_0805_6.3V6M
C65
22U_0805_6.3V6M
C57
22U_0805_6.3V6M
C58
AF31 VCCIO14 H12
AF30 VCC15 H11 @ @ @ @ @ @ @
VCC16 VCCIO15
2 2 2 2 2 2 AF29 VCCIO16 G14
VCC17 G13 2 2 2 2 2 2
AF28 VCCIO17 2 2 2
AF27 VCC18 G12
@ VCC19 VCCIO18
AF26 VCCIO19 F14
VCC20 F13
AD35 VCC21 VCCIO20
PEG AND
+CPU_CORE (22uF_0805_6.3V)*16 AD34
AD33 VCC22 VCCIO21
VCCIO22
F12
F11
AD32 VCC23 E14
VCC24 VCCIO23 E12
AD31
330U_D2_2.5VY_R9M
VCC25 VCCIO24 1 1 1
AD30
C73
AD29 E11
22U_0805_6.3V6M
C70
22U_0805_6.3V6M
C71
VCCIO25
22U_0805_6.3V6M
C68
VCC27
DDR
220U_6.3V_M 220U_6.3V_M @
AD27 D13
AD26 VCC29 VCCIO27
D12 2 2 2
22U_0805_6.3V6M
C66
22U_0805_6.3V6M
C67
2 2 2 2 2 VCC30 VCCIO28
@ AC35
AC34
VCC31
VCC32
VCCIO29
VCCIO30
D11
C14 OSCAN
AC33
AC32
VCC33
VCC34
VCCIO31
VCCIO32
C13
C12 (220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCCIO35 B12
1 1 1 VCC37 A14
1 1 AC28 VCCIO36
22U_0805_6.3V6M
C76
22U_0805_6.3V6M
C77
22U_0805_6.3V6M
C78
VCC38
22U_0805_6.3V6M
C74
22U_0805_6.3V6M
C75
C C
AC26 VCCIO38 A12

VCC40 A11
2 2 2 AA35 VCC41 VCCIO39
2 2 AA34 VCC42
AA33 VCC43 J23
VCCIO40
AA32 VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47
AA28 VCC48
1 1 1 1 1 AA27 VCC49
22U_0805_6.3V6M
C81
22U_0805_6.3V6M
C82
22U_0805_6.3V6M
C83
22U_0805_6.3V6M
C79
22U_0805_6.3V6M
C80
AA26 VCC50
Y35 VCC51
@ @ Y34
2 2 2 VCC52
2 2 Y33 VCC53 +1.05VS
Y32 VCC54
Y31 VCC55
Y30 VCC56
Y29
1
VCC57
Y28
SUPPLY
R46
1 1 1 VCC59
1 Y26 75_0402_5%
22U_0805_6.3V6M
C85
22U_0805_6.3V6M
C86
22U_0805_6.3V6M
C87
VCC60
22U_0805_6.3V6M
C84
V35
CORE
SVID
2
2 2 2 2
VCC61 H_CPU_SVIDALRT# R47 2 43_0402_5%

V34 VCC62 VIDALERT# AJ29 1 VR_SVID_ALRT# <53>
V33 AJ30 H_CPU_SVIDCLK R48 1 2 0_0402_5%
VCC63 VIDSCLK H_CPU_SVIDDAT VR_SVID_CLK <53>
V32 AJ28 R49 1 2 0_0402_5% VR_SVID_DAT <53>
VCC64 VIDSOUT
V31 VCC65
+CPU_CORE V30 VCC66
V29 VCC67 R50 2
V28 1 130_0402_5% +1.05VS
VCC68
V27 VCC69
V26 VCC70 B
B
U35 VCC71
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1 1 1 1 1 1 U34 VCC72
330U_X_2VM_R6M
330U_X_2VM_R6M
330U_X_2VM_R6M
C394 C397 C400 U33 VCC73

+ + + + +
C91
+ +
C88
330U_X_2VM_R6M
330U_X_2VM_R6M
C89
C90
2 2 2
(330uF)*4 U32
VCC74
2 2 2 2
U31
U30 VCC75
VCC76
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
U29
VCC77
U28
U27 VCC78
@ @ @ VCC79
U26
VCC80
R35 +CPU_CORE
R34 VCC81
R33 VCC82
VCC83
R32
VCC84
1
R31
R30 VCC85
10/21 modify R29
VCC86 R51
VCC87 100_0402_1%
2
VCC88
R27 VCC89 AJ35 VCCSENSE_R R52 1 2 0_0402_5%
VCC_SENSE AJ34 VSSSENSE_R R53 0_0402_5% VCCSENSE <53>
R26 VCC90 VSS_SENSE 1 2 VSSSENSE <53>
P35 VCC91
1
P34 VCC92
P33 VCC93
P32 VCCIO_SENSE B10 R54
VCC94 A10 VCCIO_SENSE <51>
P31 VSSIO_SENSE 1 2 100_0402_1%
P30 VCC95 R74
2
SENSE
LINES
VCC96 0_0402_5% VSSIO_SENSE 1 2

P29 VCC97
P28 @ R75
VCC98 0_0402_5%
P27 VCC99
P26 @
VCC100
A VSS_SENCE 100ohm +-1% pull-down to GND near processor A
8/12 Modify, need follow diffential routing
R74 close CPU,R75 close PWR
Sandy Briidge_rPGA_R ev1p0
ME@
Security Classification Compal Secret Compal Electronics, Inc.
Data
Issued Date 2010/07/12 Deciphered 2012/07/11 Tiitlle
Date PROCESSOR(5/7) PWR,BYPASS

Custom 0.2

5 4 3 2 1
5 4 3 2 1
+1.5V @ J1 +1.5V_CPU_VDDQ
1 2
8/27 change to
stuff +1.5V
PAD-OPEN 4x4m
1
1
1 2 R55 @ C92
<6,44,51> SUSP 0_0402_5% R668 220_0402_5% 0.1U_0402_10V6K
2 @ @
12
D
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
U3
C95
C96
C129
C396
+3VALW +VSB DMN3030LSS-13_SOP8L-8 Q3 2 RUN_ON_CPU1.5VS3# 1 1 1 1
8 1 2N7002H_SOT23-3 G
D
8/27 change to @ S 7 2 Change footprint D
3
1
6 3 20100814
1
R56 5 +1.5V_CPU_VDDQ 2 2 2 2
R667
100K_0402_5% @ 15K_0402_1%
4
2
R885 11/18 add for
2
sequence
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3 1 2
1
@ 1
1
1
D D 0_0402_5%
1 @ 2 2 Q7 2 Q4 R57 C97
<40> CPU1.5V_S3_GATE 0_0402_5% R58 G 2N7002H_SOT23-3 G 2N7002H_SOT23-3 330K_0402_5% 0.1U_0603_25V7K
Change footprint @ 2
S S
20100814
2
<26,40,44,49,51,52> SUSP# 1 @ 2
0_0402_5% R59
Change footprint
POWER
20100814
8/27 change to @
+VGFX_CORE JCPU1G
AT24 AK35
SENSE
LINES
VAXG1 VAXG_SENSE VCC_AXG_SENSE <53>
AT23 AK34 VSS_AXG_SENSE <53>
VAXG2 VSSAXG_SENSE
1 1 1 1 1 1 1 1 1 1 AT21
1
VAXG3
AT20
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
C101
22U_0805_6.3V6M
C102
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
C104
22U_0805_6.3V6M
C105
22U_0805_6.3V6M
C106
22U_0805_6.3V6M
C107
0_0402_5% VAXG4
+1.5V_CPU_VDDQ
VAXG5 AT18
R60 AT17 R61
2 2 2 2 2 2 2 2 2 2 VAXG6
DIS@ AR24 0_0402_5%
VAXG7
2
1
AR23 VAXG8 2 1
C PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ PX@ AR21 VAXG9 C
AR20 R62
VAXG10
VREF
AR18 1K_0402_1%
VAXG11
AR17
2
VAXG12 +V_SM_VREF_CNT +V_SM_VREF
AP24 AL1 3 1
VAXG13 SM_VREF
1
AP23
VAXG14
AP21 1 100K_0402_5% Q5 @
VAXG15
22U_0805_6.3V6M
C108
22U_0805_6.3V6M
C109
22U_0805_6.3V6M
C110
22U_0805_6.3V6M
C111
22U_0805_6.3V6M
C112
22U_0805_6.3V6M
C113
1 1 1 1 1 1 AP20 VAXG16 C114 R666 AP2302GN-HF_SOT23-3
AP18 VAXG17 0.1U_0402_16V4Z @ R63
2
AP17 1K_0402_1%
2
VAXG18 2 RUN_ON_CPU1.5VS3
AN24 VAXG19
2 2 2 2 2 2 AN23 VAXG20
AN21 VAXG21
DDR3 -1.5V RAILS

PX@ PX@ @ @ PX@ PX@ AN20 VAXG22
AN18 VAXG23 10/5 change to 1K
GRAPHICS
AN17 VAXG24 +1.5V_CPU_VDDQ
AM24 VAXG25 VDDQ1 AF7
10/21 Change AM23
AM21
VAXG26 VDDQ2 AF4
AF1 1
AM20 VAXG27 VDDQ3
330U_D2_2.5VY_R9M
330U_D2_2.5VY_R9M
1 1 AC7 1 1 1 1 1 1
AM18 VAXG28 VDDQ4 AC4 + C123
C115
C116
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
C122
+ + VAXG29 VDDQ5 330U_2.5V_M
@ AM17 AC1
VAXG30 VDDQ6
PX@ AL24 VAXG31 VDDQ7 Y7
AL23 Y4 2 2 2 2 2 2 2
2 2 VAXG32 VDDQ8
AL21 VAXG33 VDDQ9 Y1
AL20 VAXG34 VDDQ10 U7
AK24 VAXG37 VDDQ13 P7
AK20 VAXG40
AK18 VAXG41
B AK17 VAXG42 B
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20 VAXG46
AJ18 VAXG47
AJ17 VAXG48
AH24 VAXG49 +VCCSA
AH23
VAXG50 +VCCSA
AH21 M27
SA RAIL
VAXG51 VCCSA1
AH20 VAXG52 VCCSA2 M26
AH18 VAXG53 VCCSA3 L26 @
AH17 VAXG54 J26 1 1 1 1 R65 1 2 0_0402_5% VCCSA_SENSE
VCCSA4 VCCSA_SENSE <50>
J25 1
VCCSA5
Sandy Briidge_rPGA_Rev1p0 J24
VCCSA6 +
10U_0805_6.3V6M
C124
10U_0805_6.3V6M
C125
10U_0805_6.3V6M
C126
10U_0805_6.3V6M
C127
330U_D2_2.5VY_R9M
ME@ H26
VCCSA7 2 2 2 2 @
H25
C128
VCCSA8
2 R66 1 2 0_0402_5% VSSSA_SENSE <50>
1.8V RAIL
+1.8VS R67
0_0805_5%
+1.8VS_VCCPLL VCCSA_SENSE
9/27 update C128 to D2 and @
1 2 B6 VCCPLL1 VCCSA_SENSE H23
A6 VCCPLL2
1 1 1 1 A2 @
VCCPLL3 R68 2 0_0402_5%
MISC
1 1
C22 H_FC_C22
FC_C22
10U_0805_6.3V6M
C130
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
C132
C24
2 2 VCCSA_VID1
22U_0805_6.3V6M
C154
22U_0805_6.3V6M
C345
@
2 R69 1 2 10K_0402_5%
2 @ 2
VCCSA_SEL <50>
A A
6/9 change 330U to 22U X2
Security Classification Compal Secret Data

PROCESSOR(6/7) PWR
5 4 3 2 1
5 4 3 2 1
JCPU1H JCPU1I
D AT35 AJ22 D
AT32 VSS1 VSS81 AJ19
VSS2 VSS82
AT29 VSS3 VSS83 AJ16 T35 VSS161 VSS234 F22
AT27 VSS4 VSS84 AJ13 T34 VSS162 VSS235 F19
AT25 VSS5 VSS85 AJ10 T33 VSS163 VSS236 E30
AT7 VSS11 VSS91 AH35 T27 VSS169 VSS242 E13
AT4 VSS12 VSS92 AH34 T26 VSS170 VSS243 E10
AT3 VSS13 VSS93 AH32 P9 VSS171 VSS244 E9
AR25 VSS14 VSS94 AH30 P8 VSS172 VSS245 E8
AR10 VSS19 VSS99 AH22 N35 VSS177 VSS250 E3
AR2 VSS22 VSS102 AH7 N32 VSS180 VSS253 D35
AP34 VSS23 VSS103 AH4 N31 VSS181 VSS254 D32
AP31 VSS24 VSS104 AG9 N30 VSS182 VSS255 D29
AP22 VSS27 VSS107 AF6 N27 VSS185 VSS258 D17
AP19 VSS28 VSS108 AF5 N26 VSS186 VSS259 C34
AP16 VSS29 VSS109 AF3 M34 VSS187 VSS260 C31
AP13 VSS30 VSS110 AF2 L33 VSS188 VSS261 C28
AP10 VSS31 VSS111 AE35 L30 VSS189 VSS262 C27
AN30 VSS35 VSS115 AE31 L6 VSS193 VSS266 C1
AN27 VSS36 VSS116 AE30 L5 VSS194 VSS267 B22
VSS
C L4 B19 C
VSS195 VSS268
AN13 VSS41 VSS121 AE9 K35 VSS199 VSS272 B11
AN10 VSS42 VSS122 AD7 K32 VSS200 VSS273 B9
AN7 VSS43 VSS123 AC9 K29 VSS201 VSS274 B8
AN4 VSS44 VSS124 AC8 K26 VSS202 VSS275 B7
AM29 VSS45 VSS125 AC6 J34 VSS203 VSS276 B5
AM25 VSS46 VSS126 AC5 J31 VSS204 VSS277 B3
AM22 VSS47 VSS127 AC3 H33 VSS205 VSS278 B2
AM19 VSS48 VSS128 AC2 H30 VSS206 VSS279 A35
AM16 VSS49 VSS129 AB35 H27 VSS207 VSS280 A32
AM2 VSS55 VSS135 AB29 H10 VSS213
AM1 VSS56 VSS136 AB28 H9 VSS214
AL34 VSS57 VSS137 AB27 H8 VSS215
AL31 VSS58 VSS138 AB26 H7 VSS216
AL28 VSS59 VSS139 Y9 H6 VSS217
AL10 VSS65 VSS145 W 35 G35 VSS223
AL7 VSS66 VSS146 W 34 G32 VSS224
AK33 VSS69 VSS149 W 31 G23 VSS227
AK30 VSS70 VSS150 W 30 G20 VSS228
AK27 VSS71 VSS151 W 29 G17 VSS229
AK25 VSS72 VSS152 W 28 G11 VSS230
B AK22 VSS73 VSS153 W 27 F34 VSS231 B
AK19 VSS74 VSS154 W 26 F31 VSS232
AK16 VSS75 VSS155 U9 F29 VSS233
AK13 VSS76 VSS156 U8
AK10 VSS77 VSS157 U6
AK7 VSS78 VSS158 U5
AK4 VSS79 VSS159 U3
AJ25 U2
VSS80 VSS160
Sandy Briidge_rPGA_Rev1p0 Sandy Briidge_rPGA_Rev1p0

ME@ ME@
A A

PROCESSOR(7/7) VSS
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMA +1.5V +1.5V +1.5V

3A@1.5V <7> DDR_A_D[0..63]
DDR3 SO-DIMM A
1
<7> DDR_A_DQS[0..7] R70
JDIIMM1 1K_0402_1%
+VREF_DQ_DIMMA <7> DDR_A_DQS#[0..7] +VREF_DQ_DIMMA
1 2
VREF_DQ VSS1 DDR_A_D4
3 VSS2 DQ4 4 <7> DDR_A_MA[0..15]
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5
2
DDR_A_D1
0..1U_0402_10V6K
2..2U_0603_6..3V4Z
1 1 7 DQ1 VSS3 8
9 10 DDR_A_DQS#0
C133
C134
VSS4 DQS#0
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 14
1
2 2 VSS5 VSS6
DDR_A_D2 15 16 DDR_A_D6 R71
DQ2 DQ6
DDR_A_D3 17 18 DDR_A_D7 1K_0402_1%
DQ3 DQ7
D 19 VSS7 VSS8 20 D
DQ8 DQ12
2
DQ9 DQ13
25 VSS9 VSS10 26
DDR_A_DQS#1 27 DQS#1 DM1 28 DDR_A_DM1
DDR_A_DQS1 29 30 DDR3_DRAMRST# DDR3_DRAMRST# <7,13>
DQS1 RESET#
31 VSS11 VSS12 32
DQ10 DQ14
DQ11 DQ15
37 VSS13 VSS14 38
DQ16 DQ20
DQ17 DQ21
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DQS#2 DM2
DDR_A_DQS2 47 48
DQS2 VSS17
49 50 DDR_A_D22
VSS18 DQ22
DQ18 DQ23
DDR_A_D19 53 54
DQ19 VSS19
55 56 DDR_A_D28
VSS20 DQ28
DQ24 DQ29
DDR_A_D25 59 60
DQ25 VSS21
61 62 DDR_A_DQS#3
VSS22 DQS#3
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3
65 VSS23 VSS24 66
DQ26 DQ30
DQ27 DQ31
71 VSS25 VSS26 72
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
75 76
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78
<7> DDR_A_BS2 DDR_A_BS2 79 BA2 A14 80 DDR_A_MA14
81 VDD3 VDD4 82
C C
DDR_A_MA12 83 84 DDR_A_MA11
A12/BC# A11
A9 A7
87 VDD5 VDD6 88
A8 A6
A5 A4
93 VDD7 VDD8 94
A3 A2
A1 A0
99 VDD9 VDD10 100
<7> M_CLK_DDR0
<7> M_CLK_DDR#0
M_CLK_DDR0
M_CLK_DDR#0
101
103
CK0
CK0#
CK1
CK1#
102
104
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
OSCAN (220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)
105 VDD11 VDD12 106
<7> DDR_A_BS0
DDR_A_MA10
DDR_A_BS0
107
109
A10/AP BA1 108
110
DDR_A_BS1
DDR_A_RAS#
DDR_A_BS1 <7>
DDR_A_RAS# <7>
+1.5V Layout Note: (10uF_0603_6.3V)*8
111
BA0
VDD13
RAS#
VDD14 112 Place near DIMM
<7> DDR_A_WE#
<7> DDR_A_CAS#
DDR_A_WE#
DDR_A_CAS#
113
115
W E#
CAS#
S0#
ODT0
114
116
DDR_CS0_DIMMA#
M_ODT0 DDR_CS0_DIMMA#
M_ODT0 <7>
<7> (0.1uF_402_10V)*4
117 118 R72
DDR_A_MA13 VDD15 VDD16 M_ODT1 1K_0402_1%
119 120
1
A13 ODT1 M_ODT1 <7>
<7> DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
123 S1# NC2 124
VDD17 VDD18 +VREF_CA +1.5V
125 126
NCTEST VREF_CA
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
2
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 DQ33 DQ37 132 1 1
133 VSS29 VSS30 134 1
0..1U_0402_10V6K
2..2U_0603_6..3V4Z
DDR_A_DQS#4 135 136 DDR_A_DM4 R73 1 1 1 1 1 1 1 1 1 1 1 1
DQS#4 DM4
1
+
C135
C136
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
DDR_A_DQS4 1K_0402_1% C149
139 VSS32 DQ38 140
C137
C138
C139
C140
DDR_A_D34 141 142 DDR_A_D39 @ @
DQ34 DQ39 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
DDR_A_D35 143
137 144
138
DQ35
DQS4 VSS33
VSS31 2 2
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
145 146 DDR_A_D44
DDR_A_D38 220U_6..3V_M
2
VSS34 DQ44
C141
C142
C143
C144
C145
C146
C147
C148
DDR_A_D40 147 148 DDR_A_D45 @
DQ40 DQ45
DDR_A_D41 149 150
B DQ41 VSS35 DDR_A_DQS#5 B
151 VSS36 DQS#5 152
DDR_A_DM5 153 DM5 DQS5 154 DDR_A_DQS5
DDR_A_D42
155 VSS37 VSS38 156
DDR_A_D46
VDDQ(1.5V) =
157 DQ42 DQ46 158
DDR_A_D43 159 DQ43 DQ47 160 DDR_A_D47 3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
161 VSS39 VSS40 162
DDR_A_D48
DDR_A_D49
163 DQ48 DQ52 164 DDR_A_D52
DDR_A_D53
6*0603 10uf (PER CONNECTOR)
165
167
DQ49 DQ53 166
168
Layout Note:
VSS41 VSS42 Place near DIMM
DDR_A_DQS#6
DDR_A_DQS6
169 DQS#6 DM6 170 DDR_A_DM6 VTT(0.75V) =
171 DQS6 VSS43 172
DDR_A_D50
173 VSS44 DQ54 174 DDR_A_D54
DDR_A_D55
3*0805 10uf 4*0402 1uf 7/28 Update connect GND directly
175 DQ50 DQ55 176
DDR_A_D51 177 DQ51 VSS45 178
DDR_A_D60
VREF = +0.75VS
179 180
VSS46 DQ60
DDR_A_D56
DDR_A_DM0
181 182 DDR_A_D61 1*0402 0.1uf 1*0402 2.2uf
DQ56 DQ61
DDR_A_D57 183 184 DDR_A_DM1
DQ57 VSS47
DDR_A_DM2
185 186 DDR_A_DQS#7 VDDSPD (3.3V)=
VSS48 DQS#7
DDR_A_DM7 187 188 DDR_A_DQS7 DDR_A_DM3
DM7 DQS7
DDR_A_DM4
189 190 1*0402 0.1uf 1*0402 2.2uf
DDR_A_D58 VSS49 VSS50 DDR_A_D62 DDR_A_DM5
191 192 1 1 1 1
DQ58 DQ62
C150
1U_0402_6..3V6K
C151
DDR_A_D59 193 DQ59 DQ63 194 DDR_A_D63 DDR_A_DM6
1 R81 2 195 VSS51 VSS52 196 DDR_A_DM7
10K_0402_5% 197 SA0 EVENT# 198 SMB_DATA_S3
1U_0402_6..3V6K
C152
1U_0402_6..3V6K
C153
1U_0402_6..3V6K
+3VS 199 VDDSPD SDA 200 SMB_DATA_S3 <13,15,34>
201 202 SMB_CLK_S3 Layout Note:
SA1 SCL SMB_CLK_S3 <13,15,34>
1 1 203 204 +0.75VS
VTT1 VTT2 Place near
0..1U_0402_10V6K
DIMM
C156
2 2 2 2
10K_0402_5%
R83
205 206 0.65A@0.75V

G1 G2
2..2U_0603_6..3V4Z
FOX_AS0A626-U4SN-7F
C155
A @ @ A
ME@
2
2 2
Security Classification
2010/07/12
Compal Secret Data
2012/07/11 Tiitle
Issued Date Deciiphered Date
THIIS SHEET OF ENGII NEERII NG DRAW I NG IS THE PROPRII ETARY PROPERTY OF COMPAL ELECTRONII CS,, I NC.. AND CONTAII NS CONFII DENTII AL
DDRIII-SODIMM SLOT1
Sii ze Documentt Number Rev
AND TRADE SECRET I NFORMATII ON.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DII VII SII ON OF R&D Custtom 0..2
DEPARTMENT EXCEPT AS AUTHORII ZED BY COMPAL ELECTRONII CS,, I NC.. NEII THER THIIS SHEET NOR THE I NFORMATII ON I T CONTAII NS LA-6751P
MAY BE USED BY OR DII SCLOSED TO ANY THII RD PARTY WII THOUT PRII OR WRII TTEN CONSENT OF COMPAL ELECTRONII CS,, INC..
Datte:: Friiday,, November 26,, 2010 Sheett 12 off 59
5 4 3 2 1
5 4 3 2 1
+VREF_DQ_DIMMB 3A@1.5V
<7> DDR_B_D[0..63]
+1.5V +1.5V
<7> DDR_B_DQS[0..7]
JDIIMM2 +1.5V
<7> DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
VREF_DQ VSS1
3 4 DDR_B_D4
VSS2 DQ4 <7> DDR_B_MA[0..15]
1
2..2U_0603_6..3V4Z
0..1U_0402_10V6K
DDR_B_D0 5 DQ0 DQ5 6 DDR_B_D5
1 1 DDR_B_D1 R84
C158
C157
7 8 DDR_B_DQS#0 1K_0402_1%
DDR_B_DM0 DQ1 VSS3 DDR_B_DQS0 +VREF_DQ_DIMMB
2
2 2 9 10
VSS4 DQS#0
11 DM0 DQS0 12 DDR_B_D6
DDR_B_D2
13 VSS5 VSS6 14 DDR_B_D7
DDR_B_D3
1
D
15 DQ2 DQ6 16
D
17 DQ3 DQ7 18
DDR_B_D8 DDR_B_D12
19 20
DDR_B_D9 VSS7 VSS8 DDR_B_D13
21 DQ8 DQ12 22
23 24 R85
DDR_B_DQS#1 DQ9 DQ13 DDR_B_DM1 1K_0402_1%
25 VSS9 VSS10 26
DDR_B_DQS1 27 28 DDR3_DRAMRST#
2
DQS#1 DM1 DDR3_DRAMRST# <7,12>
29 30
DDR_B_D10 DQS1 RESET# DDR_B_D14
31 VSS11 VSS12 32
DDR_B_D11 33 34 DDR_B_D15
DQ10 DQ14
35 DQ11 DQ15 36
DDR_B_D16 37 38 DDR_B_D20
VSS13 VSS14
39 40
41
43
DQ16 DQ20
DDR_B_D17 42 DDR_B_D21
DQ17 DQ21
44
For Arranale only +VREF_DQ_DIMMB
VSS15 VSS16
DDR_B_DQS#2 45
DQS#2 DM2 46
48
DDR_B_DM2 supply from a external 1.5V voltage
DDR_B_DQS2 47 VSS17
DQS2
49 VSS18 DQ22
50 DDR_B_D22 divide circuit.
DDR_B_D18 51 DQ23 52 DDR_B_D23
DDR_B_D19 53
DQ18
VSS19 54 07/17/2009
DQ19 56
55 DQ28 DDR_B_D28
VSS20 58
DDR_B_D24 57 DQ29 DDR_B_D29
DQ24 60
DDR_B_D25 59 VSS21
DQ25 62
61 DQS#3 DDR_B_DQS#3
VSS22 64
DDR_B_DM3 63 DQS3 DDR_B_DQS3
DM3 VSS24 66
65
VSS23 DQ30 68
DDR_B_D26 67 DDR_B_D30
DQ26 70
DDR_B_D27 69 DQ31 72 DDR_B_D31
DQ27 VSS26
71
VSS25
<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

CKE0 CKE1 DDR_CKE3_DIMMB <7>
75 VDD1 VDD2 76
C 77 78 DDR_B_MA15 C
NC1 A15
<7> DDR_B_BS2 DDR_B_BS2 79 BA2 A14 80 DDR_B_MA14
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
A12/BC# A11
DDR_B_MA9 85 A9 A7 86 DDR_B_MA7
87 VDD5 VDD6 88
93 VDD7 VDD8 94
99 VDD9 VDD10 100
M_CLK_DDR2 101 CK0 CK1 102 M_CLK_DDR3
<7> M_CLK_DDR2 103 104 M_CLK_DDR3 <7>
M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3
<7> M_CLK_DDR#2 105 106 M_CLK_DDR#3 <7>
VDD11 VDD12
107 A10/AP BA1 108
DDR_B_MA10 DDR_B_BS1
109 110 DDR_B_BS1 <7> +1.5V
<7> DDR_B_BS0
DDR_B_BS0 111
113
BA0
VDD13
RAS#
VDD14 112
114
DDR_B_RAS#
DDR_B_RAS# <7> Layout Note: (10uF_0603_6.3V)*8
DDR_B_WE# WE# S0# DDR_CS2_DIMMB# Place near
<7> DDR_B_WE# 115 116 DDR_CS2_DIMMB# <7>
1
CAS# ODT0
<7> DDR_B_CAS# DDR_B_CAS# M_ODT2
M_ODT2 <7>
R86 DIMM (0.1uF_402_10V)*4
117 118
DDR_B_MA13 VDD15 VDD16 M_ODT3 1K_0402_1%
119 A13 ODT1 120 M_ODT3 <7>
<7> DDR_CS3_DIMMB# DDR_CS3_DIMMB# 121 122
S1# NC2
123 VDD17 VDD18 124
2
125 NCTEST VREF_CA 126 +VREF_CB
+1.5V
0..1U_0402_10V6K
2..2U_0603_6..3V4Z
127 VSS27 VSS28 128

DDR_B_D32 129 DQ32 DQ36 130 DDR_B_D36
1
C159
C160
DDR_B_D33 131 DQ33 DQ37 132 DDR_B_D37 1

1
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
10U_0603_6..3V6M
133 134
VSS29 VSS30
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
DDR_B_DQS#4 135 DQS#4 DM4 136 DDR_B_DM4 R87
1K_0402_1%
C161
C162
C163
C164
C165
C166
C167
C168
137 138
C169
C170
C171
C172
DDR_B_DQS4 DQS4 VSS31 1 1 1 1 1 1 1 1 1 1 1 1
139 140 2 2
VSS32 DQ38 DDR_B_D38
2
B DDR_B_D34 141 DQ34 DQ39 142 DDR_B_D39 B

DDR_B_D35 143 144 @ @
DQ35 VSS33 2 2 2
145 VSS34 DQ44 146 DDR_B_D44 2 2 2 2 2 2 2 2 2
DDR_B_D40 147 DQ40 DQ45 148 DDR_B_D45
DDR_B_D41 149 DQ41 VSS35 150
151 152 DDR_B_DQS#5
VSS36 DQS#5
DDR_B_DM5 153
DM5 DQS5
154 DDR_B_DQS5 VDDQ(1.5V) =
155 VSS37 VSS38 156
DDR_B_D42 DDR_B_D46
DDR_B_D43
157
159
DQ42 DQ46 158
160 DDR_B_D47
3*330uf / 12m ohm (TOTAL FOR 2 SO-
DQ43 DQ47
161 VSS39 VSS40 162 DIMMs)
DDR_B_D48 163 DQ48 164 DDR_B_D52
DQ52
DDR_B_D49 165 DQ49 DQ53 166 DDR_B_D53 6*0603 10uf (PER CONNECTOR) Layout Note:
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6 Place near
172 VTT(0.75V) = DIMM
173
DQS#6 DM6
DDR_B_DQS6 171
DQS6 VSS43 3*0805 4*0402 1uf
DDR_B_D50 175
VSS44 DQ54
174
176
DDR_B_D54
DDR_B_D55 10uf 7/28 Update connect GND directly
DQ50 DQ55
DDR_B_D51 177 VSS45 178
DQ51 +0.75VS
DDR_B_D60
181 DQ61
182 1*0402
DQ56
DDR_B_D57 183
DQ57 VSS47
184
186
1*0402 2.2uf DDR_B_DM0
DDR_B_DQS#7
185
187 0.1uf DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
VDDSPD DDR_B_DM4
(3.3V)= DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
VSS48 DQS#7
DDR_B_DM7
DM7 DQS7 188 DDR_B_DQS7 1*0402 0.1uf 1*0402
C173
1U_0402_6..3V6K
C174
1U_0402_6..3V6K
C175
1U_0402_6..3V6K
C176
1U_0402_6..3V6K
191
DQ58 DQ62
192 2.2uf 1 1 1 1
DDR_B_D59 193 194 DDR_B_D63
195 DQ59 DQ63 196
SA0 EVENT#
10K_0402_5% 199 200 SMB_DATA_S3 2 2 2 2
VDDSPD SDA
SMB_CLK_S3
203 204
2..2U_0603_6..3V4Z
0..1U_0402_10V6K
R97 10K_0402_5% VTT1 VTT2 0.65A@0.75V SMB_DATA_S3 <12,15,34> @ @

C177
C178
A A
1 1 205 206 Layout Note:
G1 G2 +0.75VS
Place near DIMM
2 2
FOX_AS0A626-U8SN-7F
ME@
THIIS SHEET OF ENGII NEERII NG DRAW I NG IS THE PROPRII ETARY PROPERTY OF COMPAL ELECTRONII CS,, I NC.. AND CONTAII NS CONFII DENTII AL
DDRIII-SODIMM SLOT2
AND TRADE SECRET I NFORMATII ON.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DII VII SII ON OF R&D
0..2
DEPARTMENT EXCEPT AS AUTHORII ZED BY COMPAL ELECTRONII CS,, I NC.. NEII THER THIIS SHEET NOR THE I NFORMATII ON I T CONTAII NS LA-6751P
MAY BE USED BY OR DII SCLOSED TO ANY THIIRD PARTY WII THOUT PRII OR WRII TTEN CONSENT OF COMPAL ELECTRONII CS,, INC..
Datte:: Friiday,, November 26,, 2010 Sheett 13 off 59

5 4 3 2 1
5 4 3 2 1
PCH_RTCX1 1 @ 2 R663 0_0402_5% PCH_RTCX1_OUT <40>

W=20mils W=20mils 1 2 PCH_RTCX2 1 @ 2 R670 0_0402_5% PCH_RTCX2_OUT <40>
R98 10M_0402_5%
+RTCVCC +RTCBATT
6/24 Update R663,R670 must be close Y1
4
R99
1K_0402_5%
OSC
1 2
32.768KHZ_12.5PF_9H03200413
2
1 Y1
OSC
C179 CLRP1 1 1
1U_0603_10V4Z SHORT PADS

C180 C181
NC
2
NC
15P_0402_50V8J
D 2 2 15P_0402_50V8J D
3
CMOS
SHORT PADS
CLRP2
+RTCVCC
+RTCVCC PCH_RTCX1 LPC_AD0
A20 C38 LPC_AD0 <34,40>
1
SM_INTRUDER# RTCX1 FW H0 / LAD0 LPC_AD1
R101 1 2 1M_0402_5% 1 A38
C183 PCH_RTCX2 FW H1 / LAD1 LPC_AD2 LPC_AD1 <34,40>
C20 B37 EC and Mini card debug port
LPC
2 PCH_RTCRST#
PCH_INTVRMEN RTCX2 FW H2 / LAD2 LPC_AD3 LPC_AD2 <34,40>
R102 1 2 330K_0402_5% 1U_0603_10V4Z C37
FW H3 / LAD3 LPC_AD3 <34,40>
1 2 D20
R103 20K_0402_5% RTCRST# LPC_FRAME#
1 2 G22
R100 20K_0 402_5% SRTCRST# +3VS
H：Integrated VRM enable 1 E36
1
SM_INTRUDER# K22
RTC
LDRQ0# R104
L：Integrated VRM disable K36 2 1 10K_0402_5%
INTRUDER# LDRQ1# / GPIO23
SATA
C182
SHORT PADS
CLRP3
6G
(INTVRMEN should always be pull high.) 1U_0603_10V4Z PCH_INTVRMEN C17 V5 SERIRQ
SERIRQ <40>
2
2 INTVRMEN SERIRQ
SATA0RXN AM3 SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 <38>

+3VS HDA_BIT_CLK AM1 SATA_DTX_C_IRX_P0
N34 SATA0RXP SATA_DTX_C_IRX_P0 <38>
HDA_BCLK
SATA0TXN AP7 SATA_ITX_C_DRX_N0 0.01U_0402_16V7K 2 1 C184 SATA_ITX_DRX_N0

SATA_ITX_DRX_N0 <38> HDD
R105 1 @ 2 1K_0402_5% HDA_SPKR HDA_SYNC L34 AP5 SATA_ITX_C_DRX_P0 0.01U_0402_16V7K 2 1 C185 SATA_ITX_DRX_P0
HDA_SYNC SATA0TXP SATA_ITX_DRX_P0 <38>
HIGH= Enable ( No Reboot ) HDA_SPKR T10 AM10

<39> HDA_SPKR SPKR SATA1RXN
* LOW= Disable (Default)
HDA_RST# K34 HDA_RST#
SATA1RXP
SATA1TXN
AM8
AP11
AP10
SATA1TXP
C +3VALW SATA2RXN AD7 C
<39> HDA_SDIN0 HDA_SDIN0 E34 SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_N2 <56,57>
HDA_SDIN0 AD5
SATA2RXP SATA_DTX_C_IRX_P2 SATA_DTX_C_IRX_P2 <56,57> ODD
IHDA
R106 2 @ 1 1K_0402_5% HDA_SDOUT G34 AH5 SATA_ITX_C_DRX_N2 0.01U_0402_16V7K 2 1 C186 SATA_ITX_DRX_N2_CONN
HDA_SDIN1 SATA2TXN SATA_ITX_C_DRX_P2 0.01U_0402_16V7K SATA_ITX_DRX_P2_C SATA_ITX_DRX_N2_CONN <56,57>
AH4 2 1 C187 ONN
SATA2TXP SATA_ITX_DRX_P2_CONN <56,57>
* Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
C34
HDA_SDIN2
SATA3RXN AB8
A34 HDA_SDIN3 SATA3RXP AB10
SATA3TXN AF3
R109 AF1
ME_FLASH 1 2 HDA_SDOUT A36 SATA3TXP
<40> ME_FLASH
SATA
+3VALW 0_0402_5% HDA_SDO Y7 SATA_DTX_C_IRX_N4
SATA4RXN SATA_DTX_C_IRX_N4 <42>
Y5 ESATA@ SATA_DTX_C_IRX_P4 ESATA
SATA4RXP SATA_DTX_C_IRX_P4 <42>

R108 2 1 1K_0402_5% HDA_SYNC R107 1 @ 2 1K_0402_1% PCH_GPIO33 C36 AD3 SATA_ITX_C_DRX_N4 0.01U_0402_16V7K 2 1 C188 SATA_ITX_DRX_N4
HDA_DOCK_EN# / GPIO33 SATA4TXN SATA_ITX_C_DRX_P4 SATA_ITX_DRX_N4 <42>
SATA4TXP AD1 0.01U_0402_16V7K 2 1 C189 SATA_ITX_DRX_P4
SATA_ITX_DRX_P4 <42>
This signal has a weak internal pull-down <56,57> Kill_SW #

Kill_SW # N32
HDA_DOCK_RST# / GPIO13
ESATA@
SATA5RXN Y3
R110 Y1
On Die PLL VR Select is supplied by 51_0402_5% SATA5RXP AB3 7/28 change from port 5 to port 4
SATA5TXN
1.5V when smapled high
* 1.8V when sampled low
2 1 PCH_JTAG_TCK
PCH_JTAG_TMS
J3
JTAG_TCK SATA5TXP
AB1
H7 R111
JTAG
Needs to be pulled High for Huron River platfrom JTAG_TMS Y11

SATAICOMPO 37.4_0402_1% +1.05VS_VCC_SATA
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
JTAG_TDI SATAICOMPI
R112 PCH_JTAG_TDO H1
JTAG_TDO
33_0402_5% +3VS AB12 R113 +1.05VS_SATA3
2
G
1 HDA_BIT_CLK SATA3RCOMPO 49.9_0402_1%

<39> HDA_BITCLK_AUDIO 2
D
R114 Q10 SATA3_COMP
AB13 1 2
33_0402_5% BSS138_NL_SOT23-3 SATA3COMPI
<39> HDA_SYNC_AUDIO 1 2 HDA_SYNC_R 3 1 HDA_SYNC

R116 SPI_CLK_PCH_R RBIAS_SATA3 R115 750_0402_1%
T3 AH1 1 2
33_0402_5% SPI_CLK SATA3RBIAS
S
2
B HDA_RST# SPI_SB_CS0# B
<39> HDA_RST_AUDIO# 1 2 Y14
R118 R878 SPI_CS0# R117
1 2 2 1 10K_0402_5% +3VS
33_0402_5% 1M_0402_5% T1 SPI_CS1#

SPI
<39> HDA_SDOUT_AUDIO 1 2 HDA_SDOUT @ R325 9/27 S ISO S #

P3 HDD_LED#
0_0402_5% reserv A
1
eSPI_SI
R878 V4
P
COUGARPOINT_FCBGA989 TSATA0GP / GPIO21 V14 PCH_GPIO21
for SPI
I A
DG1.5 SPI_SO_R _MOSI L SATA1GP / GPIO19 P1 PCH_GPIO19
+3VALW +3VALW +3VALW _
E
U3
M D
HDD_LED#
<56,57>
2 R119 1 10K_0402_5% +3VS
2 R187 1 10K_0402_5% +3VS

4MB SPI SPI_CLK_PCH
@ ROM
1
FOR ME
& Non-
share
ROM.
8/16 reserved for
R121 R122 R123 R124
@ 200_0402_5% 200_0402_5% 200_0402_5%
MOW 33_0402_5%
+3VS @
2
21
2
PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI

1
R127 1 2 SPI_W P# C190
R125 R126 R128 3.3K_0402_5% 22P_0402_50V8J

@ 100_0402_1% 100_0402_1% 100_0402_1% @
2
2
3.3K_0402_5%
C191
DPDG1.1 1 2
R130
0_0402_5%
6/30 update R121, R122, SPI_SB_CS0# 1 2
U5 0.1U_0402_16V4Z
1 8
R123
SPI_SO_R SPI_SO_L CS# VCC SPI_HOLD# 0_0402_5% R132

1 2 2 7
SPI_W P# SO HOLD# SPI_CLK_PCH 1 SPI_CLK_PCH_R
3 6 2
33_0402_5% W P# SCLK SPI_SI_R SPI_SI
4 5 1 2
R131 GND SI
A
S IC FL 32M W 25Q32BVSSIG SOIC 33_0402_5% A
8P R133
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom 0.2

5 4 3 2 1
2010/07/12
Compal Secret Data
2012/07/11 Tiitlle
Issued Date Deciphered Date
5 4 3 2 1
10K_0402_5%
U4B Q60A
2 1 +3VALW 2N7002DW -T/R7_SOT363-6
<35> PCIE_PRX_DTX_N1 PCIE_PRX_DTX_N1 BG34 R134 6 1 SMB_CLK_S3 SMB_CLK_S3 <12,13,34>
LAN <35> PCIE_PRX_DTX_P1
PCIE_PRX_DTX_P1 BJ34
PERN1
PERP1 SMBALERT# / GPIO11
E12 EC_LID_OUT# EC_LID_OUT# <40>
C192 0.1U_0402_10V7K PCIE_PTX_DRX_N1 2.2K_0402_5% 2.2K_0402_5%
<35> PCIE_PTX_C_DRX_N1
<35> PCIE_PTX_C_DRX_P1 C193
1
1
2
2 0.1U_0402_10V7K PCIE_PTX_DRX_P1
AV32
AU32
PETN1
PETP1 H14 PCH_SMBCLK 1 R136 2 1 2 R137 DIMM1
2
SMBCLK
<34> PCIE_PRX_DTX_N2 PCIE_PRX_DTX_N2 BE34
PERN2 SMBDATA
C9 PCH_SMBDATA
+3VALW
1 2
+3VS
1 2 DIMM2
5
<34> PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 R135
WLAN C194 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_N2 BF34 PERP2 2.2K_0402_5% 2.2K_0402_5% R138

MINI CARD
C195 1 2 0.1U_0402_10V7K PCIE_PTX_DRX_P2 3 4 SMB_DATA_S3
<34> PCIE_PTX_C_DRX_N2 BB32 PETN2 SMB_DATA_S3 <12,13,34>
<34> PCIE_PTX_C_DRX_P2 AY32 PETP2 A12 DRAMRST_CNTRL_PCH
SMBUS
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH <7>
BG36
PERN3 PCH_SML0CLK
2N7002DW -T/R7_SOT363-6 8/14 change P/N to
BJ36 C8 Q60B
D
AV34 PERP3
PETN3
SML0CLK
2 R139 1 +3VALW
2N7002KDW(SB00000EO10)
AU34 G12 PCH_SML0DATA 1 K_0402_ 5% D
PETP3 SML0DATA Q61A
BF36 7/28 7/5 change to 2N7002DW -T/R7_SOT363-6

PERN4
reserved 1K
BE36 10K_0402_5% 6 1 EC_SMB_CK2

PERP4 PCH_GPIO74 EC_SMB_CK2 <24,37,40>
AY34 PETN4 C13 2 1 +3VALW
SML1ALERT# / PCHHOT# / GPIO74
BB34 PETP4
E14 PCH_SML1CLK R140
2.2K_0402_5%
1 R141 2 VGA
PCI-E*
2
SML1CLK / GPIO58
BG37
BH37
PERN5
PERP5 SML1DATA / GPIO75
M16 PCH_SML1DATA
+3VALW
1 2
+3VS
EC
5
AY36
BB36
PETN5
PETP5
R142
2.2K_0402_5% thermal sensor
3 4 EC_SMB_DA2
EC_SMB_DA2 <24,37,40>
BJ38 PERN6
BG38 2N7002DW -T/R7_SOT363-6
AU36 PERP6
PETN6 M7 Q61B
AV36 CL_CLK1 +3VALW
Controller
PETP6
+3VALW
2
2
Link
BG40 T11
2
PERN7 CL_DATA1
BJ40
AY40 PERP7 R143
BB40 PETN7
PETP7 P10 10K_0402_5%
CL_RST1# @ R544 R545
BE38 R144 2.2K_0402_5% 2.2K_0402_5%
PERN8
1
0_0402_5% PCH_SML0CLK
BC38
PERP8 @
AW 38 PETN8 1 2 PEG_CLKREQ# <24> PCH_SML0DATA
AY38 PETP8 10K_0402_5% R145

M10 PEG_CLKREQ#_R 1 2
PEG_A_CLKRQ# / GPIO47
Desktop Only Y40
Y39
CLKOUT_PCIE0N
CLKOUT_PCIE0P CLK_PCIE_VGA#_R R146 1 2 0_0402_5% CLK_PCIE_VGA#
7/28 reserved
CLOCKS
0_0402_5% CLK_PCIE_VGA
C
@
R147 10K_0402_5% PCH_GPIO73 AB37 CLK_PCIE_VGA_R R148 CLK_CPU_DMI# CLK_PCIE_VGA# 2<23>10K_0402_5%
R349 C
CLKOUT_PEG_A_N 1
CLK_CPU_DMI R347 1 2 10K_0402_5%
+3VALW 2 1 J2 AB38 1 2
PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P CLK_PCIE_VGA
@ <23>
<34> CLK_PCIE_W LAN1# R149 1 2 0_0402_5% CLK_PCIE_W LAN1#_R AB49 AV22 CLK_CPU_DMI# CLK_CPU_DMI# <6>
R150 1 2 0_0402_5% CLK_PCIE_W LAN1_R CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI
<34> CLK_PCIE_W LAN1 AB47 CLKOUT_PCIE1P CLKOUT_DMI_P AU22 CLK_CPU_DMI <6>
WLAN
<34> W LAN_CLKREQ1# R156 1 2 0_0402_5% W LAN_CLKREQ1#_R M1

PCIECLKRQ1# / GPIO18
R158 2 1 10K_0402_5% AM12
+3VS CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM13
6/30 Update to @
AA47 CLKOUT_PCIE2P BF18 CLK_BUF_CPU_DMI# R155 1 2 10K_0402_5%
CLKIN_DMI_N CLK_BUF_CPU_DMI
+3VS R301 10K_0402_5% R157
2 1 V10 PCIECLKRQ2# / GPIO20 BE18 1 2
CLKIN_DMI_P
R153 1 2 0_0402_5% CLK_PCIE_LAN#_R Y37 CLKIN_DMI2_N BJ30 CLKIN_DMI2# R159 1

<35> CLK_PCIE_LAN# CLK_PCIE_LAN_R CLKOUT_PCIE3N BG30 CLKIN_DMI2
LAN <35> CLK_PCIE_LAN R154 1 2 0_0402_5% Y36
CLKOUT_PCIE3P CLKIN_DMI2_P R160 1
10K_0402_5%
<35> CLKREQ_LAN# 1 2 A8
R152 10K_0402_5% PCIECLKRQ3# / GPIO25 CLK_BUF_DREF_96M# R162
2 10K_0402_5%
2 10K_0402_5%
+3VALW 2 1 CLKIN_DOT_96N G24 1 2
E24 CLK_BUF_DREF_96M R163 1 10K_0402_5%
CLKIN_DOT_96P
10K_0402_5%
2
Y45
CLKOUT_PCIE4P CLK_BUF_PCIE_SATA# R164 1 10K_0402_5%
AK7 2
10K_0402_5%
PCH_GPIO26 CLKIN_SATA_N / CKSSCD_N CLK_BUF_PCIE_SATA

+3VALW R165 10K_0402_5% R166
2 1 L12 PCIECLKRQ4# / GPIO26 AK5 1 2
CLKIN_SATA_P / CKSSCD_P 10K_0402_5%
B PCH_GPIO44
PCIE CLK_BUF_ICH_14M CLK_PCI_LPBACK
V45 CLKOUT_PCI CLKR K45
REFCLK14IN
V46 E5N Q5# /
CLKOUT_PCI GPIO
R168 2 1 L14 E5P H45
+3VALW 44 CLKIN_PCILOOPBACK
10K_0402_5%
R167 1 2
CLK_PCI_LPB
ACK <18> XTAL25_IN
B
CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT XTAL25_OUT

AB40 XTAL25_OUT V49 1 2
CLKOUT_PEG_B_P R169 1M_0402_5%
90.9_0402_1% Y2
Y47 XCLK_RCOMP 1 2 2 1
XCLK_RCOMP
V40 1 1
CLKOUT_PCIE6N
@ 1 R520 2 100K_0402_5% V42 CLKOUT_PCIE6P 25MHZ_20PF_7A25000012
C196 C197
2 R172 1 10K_0402_5% PCH_GPIO45 T13 27P_0402_50V8J 27P_0402_50V8J
+3VALW PCIECLKRQ6# / GPIO45 2 2
PE_GPIO0 1 @ 2 V38 CLKOUT_PCIE7N K43
<18> PE_GPIO0 CLKOUTFLEX0 / GPIO64
FLEX CLOCKS
R700 0_0402_5% V37 R173
CLKOUT_PCIE7P CLK_PCI_DB_R 22_0402_5%
F47 1 2 CLK_PCI_DB <34>

CLKOUTFLEX1 / GPIO65
+3VALW R174 2 1 10K_0402_5% PCH_GPIO46 PCIECLKRQ7# / GPIO46
@
K12 H47
PE_GPIO1 1 2 PCIE_CLK_8N CLKOUTFLEX2 / GPIO66

<18,25,26,52> PE_GPIO1 AK14 CLKOUT_BCLK0_N / CLKOUT_PCIE8N
R701 0_0402_5% PCIE_CLK_8P AK13 K49
@ CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLKOUTFLEX3 / GPIO67
@ R175 @ C198
33_0402_5% 22P_0402_50V8J
COUGARPOINT_FCBGA989 CLK_BUF_ICH_14M 2 1 1 2
6/23 for GPU
Reserve for EMI please close to PCH
@ R176 @ C199
33_0402_5% 22P_0402_50V8J
CLK_PCI_LPBACK 2 1 1 2
A A
Reserve for EMI please close to PCH

Tiitlle
2010/07/12 2012/07/11
Issued Date Deciphered Date PCH (2/8) PCIE, SMBUS, CLK
Custom 0.2

5 4 3 2 1
5 4 3 2 1
D D
U4C
DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0

<5> DMI_CTX_PRX_N0 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N0 <5>
MC74VHC1G08DFT2G SC70 5P DMI_CTX_PRX_N1 BE20 AY14 FDI_CTX_PRX_N1
<5> DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI1RXN FDI_RXN1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N1 <5>
<5> DMI_CTX_PRX_N2 BG18 FDI_RXN2 BE14
DMI_CTX_PRX_N3 DMI2RXN FDI_CTX_PRX_N3 FDI_CTX_PRX_N2 <5>
VGATE <5> DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13
3
G
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N3 <5>

4 SYS_PW ROK FDI_RXN4
1 Y SYS_PW ROK <6> DMI_CTX_PRX_P0 BE24 BJ12 FDI_CTX_PRX_N5 FDI_CTX_PRX_N4 <5>
PCH_POK A <5> DMI_CTX_PRX_P0 DMI0RXP FDI_RXN5 FDI_CTX_PRX_N6
DMI_CTX_PRX_P1 BG10 FDI_CTX_PRX_N5 <5>
P
<5> DMI_CTX_PRX_P1 BC20 DMI1RXP FDI_RXN6

DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N6 <5>
2 U6 <5> DMI_CTX_PRX_P2 DMI2RXP FDI_RXN7
B DMI_CTX_PRX_P3 BJ20 DMI3RXP FDI_CTX_PRX_N7 <5>
<5> DMI_CTX_PRX_P3
5
7/28 Defult use AND

*
Gate <5> DMI_CRX_PTX_N0
DMI_CRX_PTX_N0 AW 24 DMI0TXN
FDI_RXP0
FDI_RXP1
BG14
BB14
BF14
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
+3VS DMI_CRX_PTX_N1 AW 20 FDI_RXP2 FDI_CTX_PRX_P2 <5>
<5> DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI1TXN FDI_CTX_PRX_P3
DMI
FDI
BB18 BG13 FDI_CTX_PRX_P3 <5>
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI2TXN FDI_RXP3 FDI_CTX_PRX_P4
R180 100K_0402_1% SYS_PW ROK
2 1 <5> DMI_CRX_PTX_N3 AV18 FDI_RXP4 BE12 FDI_CTX_PRX_P4 <5>
DMI3TXN FDI_CTX_PRX_P5
FDI_RXP5 BG12 FDI_CTX_PRX_P5 <5>
DMI_CRX_PTX_P0 AY24 BJ10 FDI_CTX_PRX_P6 FDI_CTX_PRX_P6 <5>
<5> DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI0TXP FDI_RXP6 BH9 FDI_CTX_PRX_P7
AY20 DMI1TXP FDI_RXP7 FDI_CTX_PRX_P7 <5>
<5> DMI_CRX_PTX_P1 DMI_CRX_PTX_P2
<5> DMI_CRX_PTX_P2 AY18 DMI2TXP
DMI_CRX_PTX_P3 AU18
<5> DMI_CRX_PTX_P3 DMI3TXP
AW 16 FDI_INT FDI_INT <5>
FDI_INT
R743 +RTCVCC
1
PCH_POK_R 1 2 @ SYS_PW ROK +1.05VS_PCH BJ24 AV12 FDI_FSYNC0
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 <5>
0_0402_5%
1 2 DMI_IRCOMP BG25 BC10 FDI_FSYNC1
DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC1 <5>
2
R742 R177 49.9_0402_1% R179
1 2 @ 1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 330K_0402_5%

<40> SYS_PW ROK_EC DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 <5> C
1
C 0_0402_5% R178 750_0402_1%
4mil width and place FDI_LSYNC1

BB10 FDI_LSYNC1
FDI_LSYNC1 <5>
within 500mil of the
7/22 modify PCH DSW ODVREN
A18
DSW VRMEN 0_0402_5% 1 R181 2 @ PCH_RSMRST#_R
SUSACK# is only used on platform R183
that support the Deep Sx state.
T72 PAD SUSACK# C12 E22 PCH_DPW ROK_R 0_0402_5% 1 R182 2 330K_0402_5%
SUSACK# DPW ROK PCH_DPW ROK <40>
R185
@
0_0402_5% 7/28
2
Update
2 1 SYS_RST# K3 B9 W AKE# 1 2
+3VS SYS_RESET# W AKE# PCIE_W AKE# <34,35>
R184 10K_0402_5% 1 2 10K_0402_5% +3VALW
R186
SYS_PW ROK P12 N3 PM_CLKRUN# PAD T73

SYS_PW ROK CLKRUN# / GPIO32 DSWODVREN - On Die DSW VR Enable
<53> VGATE
R188 1 @ 2 0_0402_5% 1 R189 2
+3VS *
System Power Management

8.2K_0402_5% H：Enable
AEPWROK can be connect to <6,40> PCH_POK R190 1 2 0_0402_5% PCH_POK_R L22 G8 SUS_STAT# L：Disable
PWROK if iAMT disable PW ROK SUS_STAT# / GPIO61
R191 R302 0_0402_5% APW ROK SUSCLK
<40> PCH_APW ROK 1 2 L10 N14 SUSCLK <40>

PCH_POK_R APW ROK APW ROK SUSCLK / GPIO62
1 2
0_0402_5% @ 7/22 modify <6> PM_DRAM_PW RGD

PM_DRAM_PW RGD B13 DRAMPW ROK SLP_S5# / GPIO63
D10 SLP_S5#
SLP_S5# <40>
1 2 PCH_RSMRST#_R C21 H4 SLP_S4#

+3VALW <40> EC_RSMRST# RSMRST# SLP_S4# SLP_S4# <40>
R193 0_0402_5%
1 2 SUSW ARN#_R K16 F4 SLP_S3#

<40> SUSW ARN# SUSW ARN# / SUS_PW R_DN_ACK / GPIO30 SLP_S3# SLP_S3# <40>
@ R196 0_0402_5%
B
<40> PBTN_OUT# 1 2 PBTN_OUT#_R E20 PW RBTN# SLP_A#
G10 when IAMT is not B
R194 2 1 10K_0402_5% SUSW ARN# R198 0_0402_5% support on the

R195
2 1 ACIN_R PAD T71
platfrom
<24,40,47> ACIN 1 2 D29 ACIN_R H20 ACPRESENT / GPIO31 G16 PM_SLP_SUS#
SLP_SUS#
1
200K_0402_1% CH751H-40PT_SOD323-2
2
R197 2 1 10K_0402_5% PCH_RSMRST#_R R199 @ 0_04021_5% R200 2 PCH_GPIO72 E10 AP14 H_PM_SYNC
8.2K_0402_5% BATLOW # / GPIO72 PMSYNCH H_PM_SYNC <6>
R201 Can be left NC if no use
+3VALW 2 1 RI# A10 RI# SLP_LAN# / GPIO29

K14 @ T66 PAD integrated LAN.
10K_0402_5%
7/28 modify COUGARPOINT_FCBGA989
+3VS
R546 2 1 200_0402_5% PM_DRAM_PW RGD
7/28 Modify follow CRB & ORB
A A
PCH Compal Electronics, Inc.

Issued
THII S SHEET OFDate 2010/07/12
CONFII DENTII AL Tiitlle (3/8) DMI,FDI,PM,
Deciphered Date Siize Document Number Rev

5 4 3 2 1
5 4 3 2 1
D D
+3VS
1
R234 R523
2
2.2K_0402_5% 2.2K_0402_5%
PX@ PX@ U4D
PCH_ENBKL J47 AP43
<31> PCH_ENBKL L_BKLTEN SDVO_TVCLKINN
2
PCH_ENVDD M45 AP45 +3VS
<31> PCH_ENVDD L_VDD_EN SDVO_TVCLKINP
EDID_CLK
1
EDID_DATA <31> PCH_PW M P45 L_BKLTCTL SDVO_STALLN AM42
AM40
SDVO_STALLP
<31> EDID_CLK EDID_CLK T40 L_DDC_CLK
Pull up R for Chipset SIDE EDID_DATA K47 L_DDC_DATA R202 R203
<31> EDID_DATA SDVO_INTN AP39 2.2K_0402_5% 2.2K_0402_5%
SDVO_INTP AP40
2
R204 1 2 2.2K_0402_5% CTRL_CLK T45 UMA_HDMI@ UMA_HDMI@
+3VS L_CTRL_CLK
R205 1 2 2.2K_0402_5% CTRL_DATA P39 L_CTRL_DATA
2.37K_0402_1%
R206 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
LVD_IBG SDVO_CTRLCLK HDMICLK_NB <33>
PX@ AF36 M39 HDMIDAT_NB
LVD_VBG SDVO_CTRLDATA HDMIDAT_NB <33>
0_0402_5% LVD_VREF AE48
R207 2 1 AE47 LVD_VREFH AT49
PX@ LVD_VREFL DDPB_AUXN
AT47
LVDS
DDPB_AUXP
DDPB_HPD AT40 TMDS_B_HPD# <33>
<31> LVDS_ACLK# AK39
LVDSA_CLK# TMDS_B_DATA2#_PCH UMA_HDMI@ C200 0.1U_0402_10V6K
<31> LVDS_ACLK AK40 AV42 1 2 HDMI_TX2-_CK <33>
LVDSA_CLK DDPB_0N TMDS_B_DATA2_PCH
<31> LVDS_A1# UMA_HDMI@ C201 1 0.1U_0402_10V6K HDMI_TX1+_CK
HDMI_TX2+_CK <33>
Digital Display Interface

LVDSA_DATA#1 DDPB_1P AV40 TMDS_B_DATA0#_PCH 2
<31> LVDS_A0#
AK47
AN48
DDPB_0P AU48
AV45 TMDS_B_DATA1#_PCH
UMA_HDMI@
UMA_HDMI@ C204
C202 11 2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
<33>
HDMI_TX1-_CK <33>
HDMI
LVDSA_DATA#0 DDPB_1N
AM47 AV46 TMDS_B_DATA1_PCH UMA_HDMI@ C203 1 2 0.1U_0402_10V6K
C C
<31> LVDS_A2# LVDSA_DATA#2 DDPB_2N HDMI_TX0-_CK <33>
AJ48 AU47 TMDS_B_DATA0_PCH UMA_HDMI@ C205 1 2 0.1U_0402_10V6K
LVDSA_DATA#3 DDPB_2P HDMI_TX0+_CK <33>
TMDS_B_CLK#_PCH UMA_HDMI@ C206 0.1U_0402_10V6K
AV47 1 2 HDMI_CLK-_CK <33>
DDPB_3N
<31> LVDS_A0 AN47 LVDSA_DATA0 DDPB_3P AV49 TMDS_B_CLK_PCH UMA_HDMI@ C207 1 2 0.1U_0402_10V6K HDMI_CLK+_CK <33>
<31> LVDS_A1 AM49 LVDSA_DATA1
<31> LVDS_A2 AK49 LVDSA_DATA2 UMA_HDMI@
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46
P42
DDPC_CTRLDATA
AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 BB47
DAC_BLU LVDSB_DATA3 DDPC_3N BB49
<32> DAC_BLU DDPC_3P
R208 2 1 150_0402_1%
PX@ DAC_GRN
<32> DAC_GRN R209 2 1 150_0402_1% N48 CRT_BLUE DDPD_CTRLCLK M43
PX@ DAC_RED P49 M36
<32> DAC_RED CRT_GREEN DDPD_CTRLDATA
R210 2 1 150_0402_1% T49
CRT_RED
PX@
CRT
AT45
+3VS CRT_DDC_CLK DDPD_AUXN
T39 AT43
<32> CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
Pull up R for Chipset SIDE <32> CRT_DDC_DATA CRT_DDC_DATA
BH41
M40
CRT_DDC_DATA DDPD_HPD
1
DDPD_0N BB43
B
<32> CRT_HSYNC M47 BB45 B
CRT_HSYNC DDPD_0P
R524 R559 <32> CRT_VSYNC M49 BF44
2.2K_0402_5% 2.2K_0402_5% CRT_VSYNC DDPD_1N
BE44
PX@ PX@ DDPD_1P BF42
2
CRT_IREF T43 DDPD_2N BE42

DAC_IREF DDPD_2P
T42 CRT_IRTN DDPD_3N BJ42
1
BG42
2
DDPD_3P
CRT_DDC_CLK
COUGARPOINT_FCBGA989
CRT_DDC_DATA R211
1K_0402_1%
2
A A

PCH (4/9) LVDS,CRT,DP,HDMI
5 4 3 2 1
5 4 3 2 1
+3VS
R551 1 @ 2 8.2K_0402_5% PCH_GPIO53

U4E
8
RP2
1 PCI_PIRQA#
8/17 reserved NV_CE#0
AY7
AV7
PCI_PIRQD# NV_CE#1
7 2 BG26 TP1 NV_CE#2 AU3
6 3 PCI_PIRQC# BJ26 TP2 BG4
PCI_PIRQB# NV_CE#3
5 4 BH25 TP3
BJ16 TP4 NV_DQS0 AT10
8.2K_0804_8P4R_5% BG16 TP5 NV_DQS1 BC8
AH38 TP6
8 RP1 1 AK43
AH37 TP8 AT4
AU2
PCH_GPIO54
PCH_GPIO2 TP7 NV_DQ1
NV_DQ0 // NV_IO1
NV_IO0
7 2 AK45 TP9 NV_DQ2 / NV_IO2 AT3
6 3 PCH_GPIO4 C18 AT1
D
PCH_GPIO3 TP10 NV_DQ3 / NV_IO3 D
5 4 N30 TP11 NV_DQ4 / NV_IO4 AY3
H3 AT5
NVRAM
TP12 NV_DQ5 / NV_IO5
8.2K_0804_8P4R_5% AH12 TP13 NV_DQ6 / NV_IO6 AV3
AM4 TP14 NV_DQ7 / NV_IO7 AV1
R225 1 2 8.2K_0402_5% W L_OFF# AM5 BB1
Y13 TP16 NV_DQ9 / NV_IO9 BA3
K24 TP17 NV_DQ10 / NV_IO10 BB5
R212 1 2 8.2K_0402_5% PCH_GPIO52 L24 BB3
AB46 TP19 NV_DQ12 / NV_IO12 BB7
R213 1 2 8.2K_0402_5% PCH_GPIO5 AB45 BE8
RSVD
NV_DQ14 / NV_IO14 BD4
NV_DQ15 / NV_IO15 BF6
R214 1 2 8.2K_0402_5% PCH_GPIO50
B21 AV5
TP21 NV_ALE NV_CLE
@ M20 AY1
TP22 NV_CLE
AY16 TP23
BG46 AV10
TP24 NV_RCOMP
GPIO55 NV_RB#
AT8
PCH_GPIO51 R221 1 @ 2 1K_0402_5%
W L_OFF# R215 1 @ 2 1K_0402_5% BE28 AY5
TP25 NV_RE#_W RB0
BC30
TP26 NV_RE#_W RB1
BA2 DMI Termination Voltage
BE32
TP27
BJ32 TP28 AT12
NV_W E#_CK0 Set to Vcc when
Boot BIOS Strap bit1 BBS1 A16 swap overide Strap/Top-Block BC28TP29 NV_W E#_CK1 BF3 NV_CLE HIGH
Swap Override jumper BE30 USB DEBUG=PORT1 AND Set to Vss when LOW
PORT9 TP30
Boot BIOS +1.8VS
BF32
TP31
Destination Low=A16 swap BG32
TP32
C24
USBP0N
USB20_N0
USB20_N0 <56,57>
Bit11 Bit10 override/Top-Block AV26 A24 USB20_P0
RIGHT USB
PCI_GNT3# Swap Override enabled TP33
BB26
TP34
USBP0P USB20_N1
USBP1N
C25
USB20_P0 <56,57>
USB20_N1 <38> 6/24 change to 1K
0 1 Reserved
1
USB20_P1
High=Default
C
* AU28
TP35
R216
charger USBP1P
B25
USB20_N2
USB20_P1 <38> LEFT USB USB C
GNT1#/ AY30 TP36 USBP2N C26 USB20_N2 <42> 1K_0402_5%

GPIO51 1 0 Reserved AU26 TP37 USBP2P A26 USB20_P2 USB20_P2 <42> LEFT USB
AY26 TP38 USB20_N3
USBP3N K28
2
USB20_N3 <42>
1 1 SPI (Default)
* AV28
<6> AW 30
TP39 USBP3P
H28
E28
USB20_P3
USB20_P3 <42> LEFT USB (COMBO) NV_CLE
R217
2 1
4.7K_0402_5%
H_SNB_IVB#
TP40 USBP4N
0 0 LPC D28
USBP4P C28
USBP5N A28
USB20_N5
USB20_N5 <31> CLOSE TO THE BRANCHING POINT
USBP5P
USB20_P5
USB20_P5 <31> USB Camera
PCI
USBP6N C29
PCI_PIRQA# USBP6P B29
K40 PIRQA# USBP7N N28
10/5 change to PX@ PCI_PIRQB#
PCI_PIRQC#
K38 PIRQB# USBP7P M28 USB20_N8
H38 PIRQC# USBP8N L30
USB
PX@
PCI_PIRQD# G38 PIRQD# USBP8P K30
USB20_P8
USB20_N9 8/6 WLAN change
USBP9N G30
<15> PE_GPIO0
PE_GPIO0 1 2 PCH_GPIO50 C46
REQ1# / GPIO50 USBP9P
E30 USB20_P9
USB20_N9 <34>
USB20_P9 <34> WLAN to port 9 +3VALW
R553 0_0402_5% PCH_GPIO52 C44 USB20_N10
REQ2# / GPIO52 USBP10N C30
PE_GPIO1 1 2 PCH_GPIO54 E40 A30 USB20_P10 RP3
<15,25,26,52> PE_GPIO1 REQ3# / GPIO54 USBP10P
R691
PX@
0_0402_5%
PCH_GPIO51 USBP11N
L32 USB20_N11
USB20_P11
USB20_N11 <43> CARD READER USB_OC0#
USB_OC2#
4 5
D47 GNT1# / GPIO51 USBP11P K32 USB20_P11 <43> 3 6
PCH_GPIO53 E42 GNT2# / GPIO53 USBP12N G32 USB_OC7# 2 7
W L_OFF# F46 E32 USB_OC5# 1 8
<34> W L_OFF# GNT3# / GPIO55 USBP12P C32 USB20_N13 USB20_N13 <42>
USBP13N USB20_P13
GPIO53=This Signal has a weak internal pull-up. PCH_GPIO2 G42 USBP13P A32 USB20_P13 <42> Bluetooth 10K_1206_8P4R_5%
NOTE: The internal pull-up is disabled after<40,56,57> PIRQE# / GPIO2
ODD_DA# ODD_DA# 1 @ 2 PCH_GPIO3 G40 Within 500 mils
PLTRST# deasserts. 0_0402_5% R715 PCH_GPIO4 C42 PIRQF# / GPIO3
PIRQG# / GPIO4 USBRBIAS# C33 USBRBIAS 1 2
PCH_GPIO5 D44 R218 22.6_0402_1% RP4
PIRQH# / GPIO5 USB_OC1# 4 5
B33 USB_OC4# 3 6
<40> PCI_PME# PME# USBRBIAS USB_OC6#
USB_OC3#
K10 12 87
PLT_RST# C6 A14 USB_OC0#

B
<6> PLT_RST# PLTRST# OC0# / GPIO59 USB_OC1# USB_OC0# <38,56,57> B
10K_1206_8P4R_5%
K20
OC1# / GPIO40 USB_OC2# USB_OC1# <42>
R219 22_0402_5% OC2# / GPIO41 B17
1 2 CLK_PCI_LPBACK_R H49 C16 USB_OC3#
<15> CLK_PCI_LPBACK CLKOUT_PCI0 OC3# / GPIO42
1 2 CLK_PCI_LPC_R H43 L16 USB_OC4#
<40> CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
R220 22_0402_5% J48 A16 USB_OC5#
CLKOUT_PCI2 OC5# / GPIO9 USB_OC6#
K42 D14
H40 CLKOUT_PCI3 OC6# / GPIO10 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
7/12 For DIS only

1 2
R690 2 DIS@ 1 R222 0_0402_5%
0_0402_5%
1 R487 2 +3VGS
10K_0402_5% +3VGS
@
@ MC74VHC1G08DFT2G SC70
5
D27 5P R693 @ @
P
PE_GPIO0 1 2 2 1 VGA_RST# U12 1
3
PLT_RST# PLT_RST# A
B 2 PX@ R682 <34,35,40> BUF_PLT_RST# Y 4
G
CH751H-40PT_SOD323-2 0_0402_5% 4 VGA_RST#_R 2 1 2
G
PE_GPIO0 Y VGA_RST# <23> B

1 0_0402_5%
A
7/12 Reserve for BACO suggestion 1 U7
3
P
NC7SZ08P5X_NL_SC70-5 PX@ PX@ R684 1U_0402_6.3V4Z
1
100K_0402_5% C208 R223
5
@ 100K_0402_5%
2
2
+3VS
A A
2
PE_GPIO0
R741 @
2 1 VGA_RST#
10/5 change to PX@
0_0402_5%
7/12 Reserve for PX3.0 Issued Date 2010/07/12 Deciphered Date 2012/07/11 Tiitlle
PCH (5/9) PCI, USB
5 4 3 2 1
5 4 3 2 1
+3VS
R702 R703 R704
PCH_GPIO69 PCH_GPIO70 PCH_GPIO71 Function
2
10K_0402_5%
0 0 0 UMA
2
10K_0402_5%
10K_0402_5%
1
1 0 0 DIS
1
PCH_GPIO69
0 1 0 PX3.0 PCH_GPIO70
PX@ @
D D
+3VS R233 1 2 10K_0402_5% PCH_GPIO0 1 1 0 PX4.0 * PCH_GPIO71 R707 R705 R706
2
10K_0402_5%
10K_0402_5%
10K_0402_5%
@ U4F
ICC_EN# ESATA_DET# 1 2
Integrated Clock Chip Enable
1
0_0402_5% R303 C40 PCH_GPIO68
BMBUSY# / GPIO0 TACH4 / GPIO68
T7
H ; Disable 7/22 update to reserve only R227 1 2 10K_0402_5% A42 B41 PCH_GPIO69 @ DIS@
* L ; Enable
R228 1 2 10K_0402_5%
TACH1 / GPIO1
PCH_GPIO6 H36
TACH5 / GPIO69
C41 PCH_GPIO70 +3VS
+3VS TACH2 / GPIO6 TACH6 / GPIO70
@ 6/23 update for MB ID
R235 1 2 1K_0402_5% EC_SMI# EC_SCI# E38 A40 PCH_GPIO71
2
<40> EC_SCI# TACH3 / GPIO7 TACH7 / GPIO71
EC_SMI# C10 R236
<40> EC_SMI# GPIO8
Weak internal pull-high 10K_0402_5%
R229 1 @ 2 10K_0402_5% CPUSB# C4
+3VALW LAN_PHY_PW R_CTRL / GPIO12
1
R230
1 2 1K_0402_5% PCH_GPIO15 G2 P4
GPIO15 A20GATE GATEA20 <40> +3VS
GPIO28 PCH_PECI_R 1 @ 2
AU16
CPU/MISC
PECI H_PECI <6,40>
On-Die PLL Voltage Regulator +3VS R231 1 2 10K_0402_5% PCH_GPIO16 U2 0_0402_5% R237 PCH_GPIO68 R224 1 2 10K_0402_5%
This
up signal has a weak internal pull SATA4GP / GPIO16
P5 KB_RST#
R542 @ RCIN# KB_RST# <40> KB_RST# R226

<42> ESATA_DET# 1 2 0_0402_5% 1 2 10K_0402_5%
GPIO
H：On-Die voltage regulator enable
* L：On-Die PLL Voltage Regulator disable +3VS R232 1 2 10K_0402_1% GPIO17 D40
TACH0 / GPIO17 PROCPW RGD
AY11
PCH_THRMTRIP#_R
H_CPUPW RGD <6>
R238 1 2 10K_0402_5% PCH_GPIO22 T5 AY10 1 2 H_THRMTRIP#
+3VS SCLOCK / GPIO22 THRMTRIP# H_THRMTRIP# <6>
R240 1 @ 2 1K_0402_5% PCH_GPIO28 R239 390_0402_5%

7/22 update to <38> ODD_EN
ODD_EN E8 GPIO24 / MEM_LED T14
+3VALW INIT3_3V# INIT3_3V
used intel PCH_GPIO27 E16
function
1 2 10K_0402_5% PCH_GPIO28 P8 GPIO28 PU, can't pull low
AH8
@ BT_OFF# NC_1
1 2 10K_0402_5% K1 STP_PCI# / GPIO34
<42> BT_OFF# R242 AK11
+3VS NC_2
PCH_GPIO27 (Have internal Pull- R243 1 2 10K_0402_5% PCH_GPIO35 K4

GPIO35
High) PCH_GPIO36 NC_3
AH10
*High: VCCVRM VR
V8
SATA2GP / GPIO36
NC_4
AK10 Intel schematic reviwe recommand.
Enable
Low: VCCVRM VR Disable
P37
R245 PCH_GPIO27 PCH_GPIO38 NC_5
1 @ 2 10K_0402_5% R246 1 2 10K_0402_5% N2
SLOAD / GPIO38
R247 1 2 10K_0402_5% PCH_GPIO39 M3
SDATAOUT0 / GPIO39
R248 1
2 10K_0402_5% PCH_GPIO48 V13 BG2 @ T15 PAD

SDATAOUT1 / GPIO48 VSS_NCTF_15
R249 1 2 10K_0402_5% ESATA_DET#_R V3 BG48 @ T16 PAD
+3VS SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6 BH3 @ T17 PAD
PCH_GPIO36 GPIO57 VSS_NCTF_17
+3VS R250 1 @ 2 10K_0402_5%
BH47 @ T18 PAD
1 2 10K_0402_5% VSS_NCTF_18
+3VALW R251
R547 1 2 10K_0402_5% PAD T19 @ A4 BJ4 @ T20 PAD

VSS_NCTF_1 VSS_NCTF_19
PAD T21 @ A44 BJ44 @ T22 PAD
8/5 update to pull down PAD T23 @ A45

BJ45 @ T24 PAD
NCTF
PAD T25 @ A46 BJ46 @ T26 PAD

PAD T27 @ A5 BJ5 @ T28 PAD
B VSS_NCTF_5 VSS_NCTF_23 B
PAD T29 @ A6 BJ6 @ T30 PAD
PCH_GPIO37 VSS_NCTF_6 VSS_NCTF_24
R881 1 2 10K_0402_5%
PAD T31 @ B3 C2 @ T32 PAD
PAD T33 @ B47 C48 @ T34 PAD
PAD T35 @ BD1 D1 @ T36 PAD
10/8 update to pull down for checklist PAD T37 @ @ T38 PAD
BD49 D49
Rev1.2 VSS_NCTF_10 VSS_NCTF_28
PAD T39 @ BE1 E1 @ T40 PAD
PAD T41 @ BE49 E49 @ T42 PAD
PAD T43 @ BF1 F1 @ T44 PAD
PAD T45 @ BF49 F49 @ T46 PAD
A A
PCH Compal Electronics, Inc.

Issued
THII S SHEET OFDate 2010/07/12
CONFII DENTII AL Tiitlle (6/9) GPIO, CPU, MISC
Deciphered Date Siize Document Number Rev

5 4 3 2 1
5 4 3 2 1
PCH Power Rail Table

+1.05VS U4G POWER +3VS S0 Iccmax
L1 Voltage Rail Voltage Current (A)
@ PJP1 1300mA MBK1608221YZF_2P
0.01U_0402_16V7K
C213
0.1U_0402_10V7K
C214
1U_0402_6.3V6K
C212
CRT
2 1 +1.05VS_PCH AA23 U48 +VCCADAC 2 1
VCCCORE[1] 1mA VCCADAC
AC23
VCCCORE[2] 1 1 1 V_PROC_IO 1.05 0.001
VCC CORE
1U_0402_6.3V6K
C210
1U_0402_6.3V6K
C211
1 1 1 1 AD21 C215 1
PAD-OPEN 4x4m VCCCORE[3]
10U_0603_6.3V6M
C209
AD23 U47 10U_0805_6.3V6M C395
VCCCORE[4] VSSADAC 10U_0805_6.3V6M
AF21
VCCCORE[5] 2 2 2 V5REF 5 0.001
AF23
2 VCCCORE[6] +3VS 2
D 2 2 2 AG21 R252 @ D
VCCCORE[7]
0.022_0805_1% V5REF_Sus 5 0.001
1
AG23
VCCCORE[8] +VCCA_LVDS
AG24 VCCCORE[9] 1mA VCCALVDS AK36 1 2
AG26 PX@
AG27 VCCCORE[10] AK37 8/5 Reserved Vcc3_3 3.3 0.266
LVDS
VCCCORE[11] VSSALVDS
AG29 DIS@
VCCCORE[12]
2
AJ23 R253
VCCCORE[13] VccADAC 3.3 0.001
AJ26 AM37 0_0402_5%
VCCCORE[14] VCCTX_LVDS[1] +1.8VS
AJ27
VCCCORE[15] L2 PX@
AJ29 VCCCORE[16] VCCTX_LVDS[2] AM38 VccADPLLA 1.05 0.08
1
22U_0805_6.3V6M
C218
AJ31 0.1UH_MLF1608DR10KT_10%_1608
+1.05VS_PCH VCCCORE[17] AP36 +VCCTX_LVDS 2 1
60mA VCCTX_LVDS[3] 0.1uH inductor, 200mA
1 1 1
VCCTX_LVDS[4]
AP37 VccADPLLB 1.05 0.08
R254 2 1 0_0603_5% +1.05VS_VCCDPLLEXP AN19 C216 C217 DIS@
VCCIO[28]
2
0.01U_0402_16V7K 0.01U_0402_16V7K PX@ R255
2 PX@ 2 PX@ 2 0_0402_5% VccCore 1.05 1.3
PAD T47 @ +VCCAPLLEXP BJ22 R256 +3VS
HVCMOS
VCCAPLLEXP
0_0805_5%
This pin can be left as no connect in VCC3_3[6] V33 +3VS_VCC3_3_6 1 2 VccDMI 1.05 0.042
AN16
On-Die VR enabled mode (default). VCCIO[15]
1
AN17 VCCIO[16] VccIO 1.05 2.925
V34 C219
VCC3_3[7]
0.1U_0402_10V7K
2
AN21 VCCIO[17] VccASW 1.05 1.01
@ J12
2 1 AN26
VCCIO[18]
VccSPI 3.3 0.02
PAD-OPEN 4x4m
AN27
VCCIO[19]
2925mA VCCVRM[3]
AT16 +VCCAFDI_VRM
+1.05VS_PCH AP21 +VCCP_VCCDMI R258 +1.05VS VccDSW 3.3 0.003

C VCCIO[20]
@
DMI
C
1U_0402_6.3V6K
C222
1U_0402_6.3V6K
C223
1U_0402_6.3V6K
C224
1U_0402_6.3V6K
C225
1 2 +1.05VS_VCC_EXP AP23 AT20 +VCCP_VCCDMI 1 2
VCCIO
VCCIO[21] VCCDMI[1]
10U_0805_6.3V6M
C221
+1.05VS_PCH 1 VccpNAND 1.8 0.19

R257 0_0805_5% 1 1 1 1 1 AP24 0_0805_5%
VCCIO[22] @ C220
AP26
VCCIO[23] 20mA VCCIO[1]
AB36 +1.05VS_VCC_DMI_CCI 0_0805_5% 1 R259 2
2
1U_0402_6.3V6K VccRTC 3.3 6 uA
1 1
2 2 2 2 2 C917 L75
AT24 VCCIO[24]
C226 10UH_LBR2012T100M_20%
VccSus3_3 3.3 0.119
1U_0402_6.3V6K @ 1 2
2 2
AN33
VCCIO[25] 10U_0603_6.3V6M 8/11 update for PDGD 1.2 VccSusHDA 3.3 / 1.5 0.01
AN34 AG16 8/27
+1.8VS update L75 symbol
NAND / SPI
+3VS +3VS_VCCA3GBG VCCIO[26] VCCPNAND[1] AG17 +VCCPNAND
1 R260 2 BH29 VCC3_3[3] 190mA VCCPNAND[2]
0_0805_5% VccVRM 1.8 / 1.5 0.16
1 R261
C227 0_0805_5% VccCLKDMI 1.05 0.02
0.1U_0402_10V7K AJ16 1 2
VCCPNAND[3]
1
2 +VCCAFDI_VRM AP16 VCCVRM[2] C228 VccSSC 1.05 0.095
+1.05VS_PCH @ R262 0.1U_0402_10V7K
VCCPNAND[4] AJ17
0_0603_5% Place CH53 Near BG6 pin 2
2 1 +1.05VS_VCCAPLL_FDI BG6 VccDIFFCLKN 1.05 0.055
VCCFDIPLL
FDI
+1.05VS_PCH R263
1
1 2 +1.05VS_VCCDPLL_FDI AP17 VCCIO[27] VccALVDS 3.3 0.001
@ C229 0_0805_5% V1 +3V_VCCPSPI 1 R399 2
1U_0402_6.3V6K 20mA VCCSPI +3VS
2 AU20 0_0805_5% VccTX_LVDS 1.8 0.06
+VCCP_VCCDMI VCCDMI[2] 1
C230
B COUGARPOINT_FCBGA989 1U_0402_6.3V6K B
2
6/30 update
+VCCAFDI_VRM
+1.5VS
R265 2 1 0_0603_5% +VCCAFDI_VRM
+1.8VS
R266 2 @ 1 0_0603_5%
Intel recommand VCCVRM==>1.5V FOR MOBILE

stuff R265 and unstuff R266 VCCVRM==>1.8V FOR DESKTOP
VCCVRM = 160mA detal waiting for newest spec
A A

PCH (7/9) PWR
Custom 0.2
5 4 3 2 1
10U_0805_10V4Z
C231
1U_0402_6.3V6K
C232
1 VCCACLK VCCIO[29]
1
C234 P26
0.1U_0402_10V7K VCCIO[30] C233
VCCDSW 3_3 3mA 1U_0402_6.3V6K
VCCIO[31] P28 2
DCPSUSBYP VCCIO[32] T27
VCCIO[33] T29
VCC3_3[5]
0.1U_0402_10V7K
C236
119mA VCCSUS3_3[7]
VCCAPLLDMI2 T24 1
VCCSUS3_3[8]
VCCIO[14] V23 +3V_VCCAUB
USB
VCCSUS3_3[9]
C237
10U_0805_6.3V6M
2 1
2
V24 C238
DCPSUS[3] VCCSUS3_3[10]
VCCSUS3_3[6]
1
VCCASW [1]
VCCIO[34]
VCCASW [2]
1010mA
iscellaneous
VCCASW [3] 1mA V5REF_SUS
22U_0805_6.3V6M
C241
22U_0805_6.3V6M
C242
VCCASW [4]
DCPSUS[4]
VCCASW [5]
VCCSUS3_3[1]
VCCASW [6]
2
VCCASW [7]
1mA
PCI/GPIO/LPC
VCCASW [8] V5REF
1U_0402_6.3V6K
C244
1U_0402_6.3V6K
C245
1U_0402_6.3V6K
C246
Clock and
1
VCCASW [9]
M
VCCSUS3_3[2]
VCCASW [10]
VCCSUS3_3[3]
VCCASW [11]
VCCSUS3_3[4]
VCCASW [12]
VCCSUS3_3[5]
VCCASW [13]
VCCASW [14] VCC3_3[1]

220U_B2_2.5VM_R35
C250
1U_0402_6.3V6K
C251
220U_B2_2.5VM_R35
C252
1U_0402_6.3V6K
C253
VCCASW [17]
VCCASW [18]
VCCASW [20]
VCCIO[5]
DCPRTC
VCCIO[12]
@ @ R287 +1.05VS_PCH
VCCVRM[4] VCCIO[13]
SATA
VCCIO[6]
VCCADPLLA 80mA
VCCAPLLSATA
VCCADPLLB 80mA
VCCVRM[1]
VCCIO[7]
VCCIO[8]
VCCIO[9] 55mA
AC17 1
VCCIO[2] C261
VCCIO[11] AD17 1U_0
VCCIO[3]
VCCIO[10] 95mA VCCIO[4]
DCPSST
MISC
DCPSUS[1] VCCASW [22]

DCPSUS[2]
VCCASW [23]
CPU
V_PROC_IO 1mA
VCCASW [21]
HDA
4.7U_0603_6.3V6K
C265
0.1U_0402_10V7K
C266
0.1U_0402_10V7K
C267
RTC
VCCRTC 10mA VCCSUSHDA

1U_0402_6.3V6K
C268
0.1U_0402_10V7K
C269
0.1U_0402_10V7K
C270
5 4 3 2 1
U4I
AY4 VSS[159] VSS[259] H46

AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
U4H B15 VSS[164] VSS[264] K7
D D
H5 B19 VSS[165] VSS[265] L18
VSS[0] B23 VSS[166] VSS[266] L2
AK38 B27 VSS[167] VSS[267] L20
AA17 B31 VSS[168] VSS[268] L26
VSS[1] VSS[80] B35 L28
AA2 AK4 VSS[169] VSS[269]
VSS[2] VSS[81] B39 L36
AA3 AK42 VSS[170] VSS[270]
VSS[3] VSS[82] B7 VSS[171] VSS[271] L48
AA33 AK46
VSS[4] VSS[83] F45 VSS[172] VSS[272] M12
AA34 AK8 BB12 P16
VSS[5] VSS[84] VSS[173] VSS[273]
AB11 AL16 BB16 M18
VSS[6] VSS[85] VSS[174] VSS[274]
AB14 AL17 BB20 VSS[175] VSS[275] M22
VSS[7] VSS[86]
AB39 AL19 BB22 VSS[176] VSS[276] M24
VSS[8] VSS[87] BB24 M30
AB4 AL2 VSS[177] VSS[277]
VSS[9] VSS[88] BB28 M32
AB43 AL21 VSS[178] VSS[278]
VSS[10] VSS[89] BB30 VSS[179] VSS[279] M34
AB5 AL23
VSS[11] VSS[90] BB38 VSS[180] VSS[280] M38
AB7 AL26 BB4 M4
VSS[12] VSS[91] VSS[181] VSS[281]
AC19 AL27 BB46 M42
VSS[13] VSS[92] VSS[182] VSS[282]
AC2 AL31 BC14 M46
VSS[14] VSS[93] VSS[183] VSS[283]
AC21 AL33 BC18 VSS[184] VSS[284] M8
VSS[15] VSS[94] BC2 N18
AC24 AL34 VSS[185] VSS[285]
VSS[16] VSS[95] BC22 P30
AC33 AL48 VSS[186] VSS[286]
VSS[17] VSS[96] BC26 N47
AC34 AM11 VSS[187] VSS[287]
VSS[18] VSS[97] BC32 VSS[188] VSS[288] P11
AC48 AM14
VSS[19] VSS[98] BC34 VSS[189] VSS[289] P18
AD10 AM36 BC36 T33
VSS[20] VSS[99] VSS[190] VSS[290]
AD11 AM39 BC40 P40
VSS[21] VSS[100] VSS[191] VSS[291]
AD12 AM43 BC42 VSS[192] VSS[292] P43
VSS[22] VSS[101]
AD13 AM45 BC48 VSS[193] VSS[293] P47
VSS[23] VSS[102] BD46 P7
AD19 AM46 VSS[194] VSS[294]
VSS[24] VSS[103] BD5 R2
AD24 AM7 VSS[195] VSS[295]
VSS[25] VSS[104] BE22 R48
AD26 AN2 VSS[196] VSS[296]
VSS[26] VSS[105] BE26 VSS[197] VSS[297] T12
AD27 AN29 BE40 T31
VSS[27] VSS[106] VSS[198] VSS[298]
AD33 AN3 BF10 T37
VSS[28] VSS[107] VSS[199] VSS[299]
AD34 AN31 BF12 T4
C VSS[29] VSS[108] VSS[200] VSS[300] C
AD36 AP12 BF16 VSS[201] VSS[301] W 34
VSS[30] VSS[109]
AD37 AP19 BF20 VSS[202] VSS[302] T46
VSS[31] VSS[110] BF22 T47
AD38 AP28 VSS[203] VSS[303]
VSS[32] VSS[111] BF24 T8
AD39 AP30 VSS[204] VSS[304]
VSS[33] VSS[112] BF26 VSS[205] VSS[305] V11
AD4 AP32
VSS[34] VSS[113] BF28 VSS[206] VSS[306] V17
AD40 AP38 BD3 V26
VSS[35] VSS[114] VSS[207] VSS[307]
AD42 AP4 BF30 V27
VSS[36] VSS[115] VSS[208] VSS[308]
AD43 AP42 BF38 VSS[209] VSS[309] V29
VSS[37] VSS[116]
AD45 AP46 BF40 VSS[210] VSS[310] V31
VSS[38] VSS[117] BF8 V36
AD46 AP8 VSS[211] VSS[311]
VSS[39] VSS[118] BG17 V39
AD8 AR2 VSS[212] VSS[312]
VSS[40] VSS[119] BG21 V43
AE2 AR48 VSS[213] VSS[313]
VSS[41] VSS[120] BG33 VSS[214] VSS[314] V7
AE3 VSS[42] VSS[121] AT11 BG44 W 17
AF10 AT13 VSS[215] VSS[315]
VSS[43] VSS[122] BG8 VSS[216] VSS[316] W 19
AF12 AT18 BH11 W2
VSS[44] VSS[123] VSS[217] VSS[317]
AD14 AT22 BH15 VSS[218] VSS[318] W 27
VSS[45] VSS[124]
AD16 AT26 BH17 VSS[219] VSS[319] W 48
VSS[46] VSS[125] BH19 Y12
AF16 AT28 VSS[220] VSS[320]
VSS[47] VSS[126] H10 Y38
AF19 VSS[48] VSS[127] AT30 VSS[221] VSS[321]
AF24 AT32 BH27 VSS[222] VSS[322] Y4
VSS[49] VSS[128] BH31 VSS[223] VSS[323] Y42
AF26 AT34 BH33 Y46
VSS[50] VSS[129] VSS[224] VSS[324]
AF27 VSS[51] VSS[130] AT39 BH35 Y8
VSS[225] VSS[325]
AF29 VSS[52] VSS[131] AT42 BH39 VSS[226] VSS[328] BG29
AF31 AT46 BH43 VSS[227] VSS[329] N24
VSS[53] VSS[132] BH7 AJ3
AF38 AT7 VSS[228] VSS[330]
VSS[54] VSS[133] D3 AD47
AF4 VSS[55] VSS[134] AU24 VSS[229] VSS[331]
AF42 AU30 D12 VSS[230] VSS[333] B43
VSS[56] VSS[135] D16 VSS[231] VSS[334] BE10
AF46 VSS[57] VSS[136] AV16 D18 BG41
AF5 AV20 VSS[232] VSS[335]
VSS[58] VSS[137] D22 VSS[233] VSS[337] G14
AF7 AV24 D24 H16
VSS[59] VSS[138] VSS[234] VSS[338]
AF8 VSS[60] VSS[139] AV30 D26 VSS[235] VSS[340] T36
AG19 AV38 D30 VSS[236] VSS[342] BG22
B
VSS[61] VSS[140] D32 BG24 B
AG2 VSS[62] VSS[141] AV4 VSS[237] VSS[343]
AG31 AV43 D34 VSS[238] VSS[344] C22
VSS[63] VSS[142] D38 AP13
AG48 AV8 VSS[239] VSS[345]
VSS[64] VSS[143] D42 VSS[240] VSS[346] M14
AH11 VSS[65] VSS[144] AW 14 D8 AP3
AH3 AW 18 VSS[241] VSS[347]
VSS[66] VSS[145] E18 VSS[242] VSS[348] AP1
AH36 VSS[67] VSS[146] AW 2 E26 BE16
VSS[243] VSS[349]
AH39 VSS[68] VSS[147] AW 22 G18 VSS[244] VSS[350] BC16
AH40 AW 26 G20 VSS[245] VSS[351] BG28
VSS[69] VSS[148] G26 BJ28
AH42 VSS[70] VSS[149] AW 28 VSS[246] VSS[352]
AH46 AW 32 G28 VSS[247]
VSS[71] VSS[150] G36
AH7 AW 34 VSS[248]
VSS[72] VSS[151] G48 VSS[249]
AJ19 VSS[73] VSS[152] AW 36 H12
AJ21 AW 40 VSS[250]
VSS[74] VSS[153] H18 VSS[251]
AJ24 VSS[75] VSS[154] AW 48 H22 VSS[252]
AJ33 AV11 H24 VSS[253]
VSS[76] VSS[155] H26
AJ34 VSS[77] VSS[156] AY12 VSS[254]
AK12 AY22 H30 VSS[255]
VSS[78] VSS[157] H32
AK3 AY28 VSS[256]
VSS[79] VSS[158] H34 VSS[257]
F3
COUGARPOINT_FCBGA989 VSS[258]
A A

PCH (9/9) VSS
5 4 3 2 1
5 4 3 2 1
PCIE_CTX_GRX_P[15..0] U8A PCIE_CRX_GTX_P[15..0]
<5> PCIE_CTX_GRX_P[15..0] PCIE_CRX_GTX_P[15..0] <5>
PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] R296
<5> PCIE_CTX_GRX_N[15..0] PCIE_CRX_GTX_N[15..0] <5>
1 2
10K_0402_5%
LVDS CONTROL
DIGON AB12 VGA_ENVDD <31>

PCIE_CTX_GRX_P0 PCIE_CRX_C_GTX_P0 0.1U_0402_10V7K C273 PCIE_CRX_GTX_P0
AF30 AH30 2 1
PCIE_CTX_GRX_N0 PCIE_RX0P PCIE_TX0P AG31 PCIE_CRX_C_GTX_N0 2 1 PCIE_CRX_GTX_N0 1 2
AE31
PCIE_RX0N PCIE_TX0N R297

0.1U_0402_10V7K C272 D
D 10K_0402_5%
PCIE_CTX_GRX_P1 AE29 AG29 PCIE_CRX_C_GTX_P1 0.1U_0402_10V2
7K C2174 PCIE_CRX_GTX_P1 AH20
PCIE_RX1P PCIE_TX1P TXCLK_UP_DPF3P

PCIE_CTX_GRX_N1 AD28 AF28 PCIE_CRX_C_GTX_N1 2 1 PCIE_CRX_GTX_N1 AJ19
PCIE_RX1N PCIE_TX1N TXCLK_UN_DPF3N
0.1U_0402_10V7K C275
TXOUT_U0P_DPF2P
PCIE_CTX_GRX_P2 AD30 PCIE_RX2P PCIE_TX2P AF27 PCIE_CRX_C_GTX_P2 0.1U_0402_10V2
7K C2176 PCIE_CRX_GTX_P2 TXOUT_U0N_DPF2N AK20
PCIE_CTX_GRX_N2 PCIE_CRX_C_GTX_N2 PCIE_CRX_GTX_N2
AC31 AF26 2 1
PCIE_RX2N PCIE_TX2N
TXOUT_U1N_DPF1N AJ21
AC29 PCIE_TX3P AD27 2 1
PCIE_RX3P
PCIE_CTX_GRX_N3 AB28
PCIE_RX3N PCIE_TX3N AD26 PCIE_CRX_C_GTX_N3 2 1 PCIE_CRX_GTX_N3 AL23
TXOUT_U2P_DPF0P
0.1U_0402_10V7K C279 AK22
TXOUT_U2N_DPF0N
PCIE_CTX_GRX_P4 AB30 AC25 PCIE_CRX_C_GTX_P4 0.1U_0402_10V2
7K C2180 PCIE_CRX_GTX_P4 AK24
PCIE_RX4P PCIE_TX4P TXOUT_U3P

PCIE_CTX_GRX_N4 AA31 AB25 PCIE_CRX_C_GTX_N4 2 1 PCIE_CRX_GTX_N4 AJ23
PCIE_RX4N PCIE_TX4N TXOUT_U3N
0.1U_0402_10V7K C281
PCIE_CTX_GRX_P5 PCIE_CRX_C_GTX_P5 0.1U_0402_10V7K C282 PCIE_CRX_GTX_P5 LVTMDP
AA29 PCIE_RX5P PCIE_TX5P Y23 2 1

PCIE_CTX_GRX_N5 Y28 Y24 PCIE_CRX_C_GTX_N5 2 1 PCIE_CRX_GTX_N5
PCIE_RX5N PCIE_TX5N
TXCLK_LN_DPE3N AK14 VGA_LVDS_ACLK# <31>

Y30 PCIE_TX6P AB27 2 1
PCIE_CTX_GRX_N6 W31 PCIE_RX6P AB26 PCIE_CRX_C_GTX_N6 2 1 PCIE_CRX_GTX_N6
PCIE_RX6N PCIE_TX6N TXOUT_L0P_DPE2P AH16 VGA_LVDS_A0 <31>
0.1U_0402_10V7K C285 AJ15
C TXOUT_L0N_DPE2N VGA_LVDS_A0# <31> C
PCIE_CTX_GRX_P7 W29 Y27 PCIE_CRX_C_GTX_P7 0.1U_0402_10V2

7K C2186 PCIE_CRX_GTX_P7 AL17
PCIE_CTX_GRX_N7 PCIE_RX7P PCIE_TX7P TXOUT_L1P_DPE1P VGA_LVDS_A1 <31>

V28 Y26 PCIE_CRX_C_GTX_N7 2 1 PCIE_CRX_GTX_N7 AK16
PCIE_RX7N PCIE_TX7N TXOUT_L1N_DPE1N VGA_LVDS_A1# <31>
INTERFACE
PCI EXPRESS
0.1U_0402_10V7K C287
AH18 VGA_LVDS_A2 <31>
PCIE_CTX_GRX_P8 PCIE_CRX_C_GTX_P8 PCIE_CRX_GTX_P8 TXOUT_L2P_DPE0P
0.1U_0402_10V7K C288
W 23
V30 PCIE_TX8P W24 2 1 AJ17 VGA_LVDS_A2# <31>
PCIE_CTX_GRX_N8 U31 PCIE_RX8P PCIE_CRX_C_GTX_N8 2 1 PCIE_CRX_GTX_N8 TXOUT_L2N_DPE0N
PCIE_RX8N PCIE_TX8N
0.1U_0402_10V7K C289 AL19
TXOUT_L3N
PCIE_CTX_GRX_P9 U29 V27 PCIE_CRX_C_GTX_P9 0.1U_0402_10V2
7K C2190 PCIE_CRX_GTX_P9
PCIE_RX9P PCIE_TX9P
PCIE_CTX_GRX_N9 T28 U26 PCIE_CRX_C_GTX_N9 2 1 PCIE_CRX_GTX_N9
PCIE_RX9N PCIE_TX9N
0.1U_0402_10V7K C291
PCIE_CTX_GRX_P10 PCIE_CRX_C_GTX_P10 0.1U_0402_10V7K C292 PCIE_CRX_GTX_P10 216-0774207-A11ROB_FCBGA631

T30 U24 2 1
PCIE_CTX_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_CRX_C_GTX_N10 PCIE_CRX_GTX_N10
R31 U23
PCIE_RX10N PCIE_TX10N 0.1U_0402_10V7K C293
PCIE_CTX_GRX_P11 R29 T26 PCIE_CRX_C_GTX_P11 0.1U_0402_10V2

LVDS
PCIE_RX11P PCIE_TX11P
PCIE_CTX_GRX_N11 P28 T27 PCIE_CRX_C_GTX_N11 2 1 PCIE_CRX_GTX_N11
PCIE_RX11N PCIE_TX11N
0.1U_0402_10V7K C295
PCIE_CTX_GRX_P12 P30 T24 PCIE_CRX_C_GTX_P12 0.1U_0402_10V2

PCIE_CTX_GRX_N12 N31 T23 PCIE_CRX_C_GTX_N12 2 1 PCIE_CRX_GTX_N12
B 0.1U_0402_10V7K C297 B
PCIE_CTX_GRX_P13 N29 P27 PCIE_CRX_C_GTX_P13 0.1U_0402_10V2

PCIE_CTX_GRX_N13 M28 P26 PCIE_CRX_C_GTX_N13 2 1 PCIE_CRX_GTX_N13

M30 PCIE_RX14P P24 2 1
PCIE_CTX_GRX_N14 PCIE_TX14P PCIE_CRX_C_GTX_N14 PCIE_CRX_GTX_N14
L31 P23
PCIE_CTX_GRX_P15 L29 M27 PCIE_CRX_C_GTX_P15 0.1U_0402_10V2

PCIE_CTX_GRX_N15 K30 N26 PCIE_CRX_C_GTX_N15 2 1 PCIE_CRX_GTX_N15
0.1U_0402_10V7K C303
CLOCK
T48 PAD
CLK_PCIE_VGA
<15> CLK_PCIE_VGA AK30 PCIE_REFCLKP
<15> CLK_PCIE_VGA# CLK_PCIE_VGA# AK32 PCIE_REFCLKN
T49 PAD
CALIBRATION
<25> VGA_PW RGD VGA_PWRGD Y22 1.27K_0402_1% 1 2 R298
PCIE_CALRP
2 R299 1 N10 PCIE_CALRN AA22 2K_0402_5% 1 2 R300 +1.0VGS

PWRGOOD
A 10K_0402_5% A
<18> VGA_RST# AL27 PERSTB

Data
216-0774207-A11ROB_FCBGA631 2010/07/12 2012/07/11 Title

Issued Deciphered
Date Date RobsonXT-S3 PCIE/LVDS
PCIE LANE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE
COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT
CONTAINS
Date: Friday, November 26, 2010 Sheet 23 of 59
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL
ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
Transmitter Power Saving Enable U8B CONFIGURATION STRAPS RECOMMENDED SETTINGS

TX_PWRS_ENB GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop) ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE 0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X = DESIGN DEPENDANT
PCI Express Transmitter De-emphasis Enable TXCAP_DPA3P
AF2
VGA_HDMI_CLK+ <33>
NA = NOT APPLICABLE
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled for mobile mode TXCAM_DPA3N AF4 VGA_HDMI_CLK- <33>
1: Tx de-emphasis enabled (Defailt setting for desktop) T52 Y11
T53 AE9 DVCLK
DVCNTL_0 AG3 VGA_HDMI_TX0+ <33> RECOMMENDED
TX0P_DPA2P
T54 L9 AG5 STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS SETTINGS

T55 DVCNTL_1 TX0M_DPA2N VGA_HDMI_TX0- <33>
N9 DVO DPA
DVCNTL_2
AH3
TX1P_DPA1P AH1 VGA_HDMI_TX1+ <33>
T50 AE8 TX1M_DPA1N VGA_HDMI_TX1- <33> TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X
DVDATA_12
T56 AD9
DVDATA_11
T57
AK3 VGA_HDMI_TX2+ <33>
+1.8VGS +DPC_VDD18 TX2P_DPA0P AK1 TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED X
AC10 DVDATA_10 TX2M_DPA0N VGA_HDMI_TX2- <33>
T51 AD7
DVDATA_9
L8 150mA T58 AC8
2 1 +DPC_VDD18 T59 DVDATA_8
AC7 AK5
BLM15BD121SN1D_0402 DVDATA_7 TXCBP_DPB3P RESERVED 0
T60 AB9 AM3 RSVD GPIO2
10U_0603_6..3V6M
1U_0402_6..3V4Z
0..1U_0402_10V6K
D DVDATA_6 TXCBM_DPB3N D
C305
C304
C306
1 1 1 T61 AB8 DVDATA_5

Change to 0 ohm T62 AB7
AB4
DVDATA_4
TX3P_DPB2P
AK6
DVDATA_3 RSVD GPIO8 RESERVED 0
P/N T70
VRAM_ID2
AB2 DVDATA_2 DPB
TX3M_DPB2N AM5
2 2 2 <29> VRAM_ID2 VRAM_ID1
<29> VRAM_ID1 Y8 AJ7

VRAM_ID0 Y7 DVDATA_1 TX4P_DPB1P
<29> VRAM_ID0 DVDATA_0 AH6 BIF_VGA DIS GPIO9 VGA ENABLED 0
TX4M_DPB1N
AK8
TX5P_DPB0P
AL7 RSVD GPIO21 RESERVED 0

TX5M_DPB0N
+DPC_VDD18 DPC BIOS_ROM_EN GPIO_22_ROMCSB ENABLE EXTERNAL BIOS ROM X

+DPC_VDD18 W6
DPC_PVDD
+1.0VGS +DPC_VDD10 V6 V4
DPC_PVSS TXCCP_DPC3P
L9 +DPC_VDD18 U5 ROMIDCFG(2:0) GPIO[13:11] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XX
110mA +DPC_VDD18 AC6
DPC_VDD18#1
TXCCM_DPC3N
2 1 +DPC_VDD10 AC5
X
DPC_VDD18#2
BLM15BD121SN1D_0402 W3
1U_0402_10V6K
10U_0603_6..3V6M
1U_0402_6..3V4Z
TX0P_DPC2P
C308
C309
C307
1 1 1 +DPC_VDD10 +DPC_VDD10 AA5 TX0M_DPC2N V2 VIP_DEVICE_STRAP_ENA V2SYNC IGNORE VIP DEVICE STRAPS 0
DPC_VDD10#1
Change to 0 ohm AA6 DPC_VDD10#2
Y4
P/N TX1P_DPC1P
W5 RSVD H2SYNC 0
2 2 2 TX1M_DPC1N
U1
DPC_VSSR#1 AA3
0..
W1 DPC_VSSR#2 TX2P_DPC0P RSVD GENERIC 0

U3 DPC_VSSR#3 Y2
Y6 TX2M_DPC0N
DPC_VSSR#4 1 R305 2 AUD[1] AUD[0]
AA1 DPC_VSSR#5 J8 150_0402_1% VGA_CRT_R AUD[1] C 0 0 No audio function 11
DPC_CALR
0 1 Audio for DisplayPort and HDMI if dongle is detected
VGA_CRT_G AUD[0] 1 0 Audio for DisplayPort only
HSYNC 1 1 Audio for both DisplayPort and HDMI
I2C VGA_CRT_B
R318 1
R320 1
+3VGS VSYNC
150_0402_1%
150_0402_1%
2
R541 1
150_0402_1%
AMD RESERVED CONFIGURATION STRAPS
@ 1R307 4..7K_
20402_5% VGA_SMB_DA2_R VGA_SMB_DA2_R R3
SDA RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
2
GENERAL PURPOSE I/O R
AM26 VGA_CRT_R VGA_CRT_R <32> NOT CONFLICT DURING RESET C
C AK26
GPIO_0
8/13 update to @ GPU_GPIO1
GPU_GPIO2
U10
T10
GPIO_1 G
AL25 VGA_CRT_G
VGA_CRT_G <32>
GPIO21 H2SYNC GENERICC GPIO2 GPIO8
GPIO_2 AJ25
GB
D3 U8
CH751H-40PT_SOD323-2 @ GPIO_3_SMBDATA
U7 AH24 VGA_CRT_B VGA_CRT_B <32> +AVDD +1.8VGS
1 2 GPU_GPIO5 GPIO_4_SMBCLK B AJ27
<16,40,47> ACIN T9 AG25
T8
GPIO_6
R662 VGA_ENBKL VGA_ENBK
L VGA_HSYNC +AVDD
1 2 <31> VGA_ENBKL T7 P10 AH26 VGA_HSYNC <32> 1 2
10K_0402_5% GPU_GPIO8 GPIO_7_BLON HSYNC VGA_VSYNC BLM15BD121SN1D_0402 2 1
VGA_VSYNC <32>
0..1U_0402_10V6K
1U_0402_6..3V4Z
10U_0603_6..3V6M
P4 2 1
C311
C310
GPU_GPIO9
C312
GPIO_8_ROMSO VSYNC 1 1 1
@
P2 GPIO_9_ROMSI Change to 0 ohm
GPU_GPIO11 GPIO_10_ROMSCK
R312 2
2 2 2
GPU_GPIO0 R309 @ 10K_0402_5%
N6 AD22 1 GPU_GPIO1 R310 2 1 10K_0402_5%
GPU_GPIO12 GPIO_11 RSET 499_0402_1% P/N GPU_GPIO2 R311 2 1 10K_0402_5%
GPU_GPIO5 R308 @ 10K_0402_5%
GPIO_12 +AVDD
GPU_GPIO13 N3 GPIO_13 AVDD AG24 GPU_GPIO8 R313 2 @
+AVDD
GPU_GPIO9 R314 @ 1 10K_0402_5%
Y9 AE22 2 1 10K_0402_5%
GPU_VID0 GPIO_14_HPD2 AVSSQ GPU_GPIO11 R315 2
<52> GPU_VID0 T63 GPIO_15_PW RCNTL_0 GPU_GPIO12 R316 @ 1 10K_0402_5%
M4 GPIO_16_SSIN AE23 +VDD1DI +VDD1DI
THM_ALERT# R6 VDD1DI 2 1 10K_0402_5%
GPIO_17_THERMAL_INT AD23
VSS1DI GPU_GPIO13 R317 @ 1 10K_0402_5%
W 10 VGA_HSYNC R548 12 DIIS@
R319 10K_0402_5 GPIO_18_HPD3 +VDD1DI 10K_0402_5%
+1.8VGS VGA_VSYNC R549 DIIS@
1 M2 2
GPU_VID1 P8 GPIO_19_CTF
<52> GPU_VID1 GPIO_20_PW RCNTL_1 AM12 110mA L11 2
P7 R2 AK12 +VDD1DI
GPIO_21_BB_EN R2B 1 2 1 10K_0402_5%
10U_0603_6..3V6M
0..1U_0402_10V6K
1U_0402_6..3V4Z
8/5 Add For DIS HDMI audio strap
C313
C314
C315
PEG_CLKREQ# N7 AL11 1 1 1
+3VGS <15> PEG_CLKREQ# GPIO_23_CLKREQB G2
GPIO24_TRST L6 G2B
AJ11 Change to 0 ohm
JTAG_TRSTB
1 R321 102K_0402_5% GPIO24_TRSTB B
L5
JTAG_TDI B2
AK10 P/N +3VGS
1 R322 102K_0402_5% GPIO25_TDI L3 AL9 2 2 2
GPIO25_TDI
GPIO26_TCK
JTAG_TCK B2B
1 R323 102K_0402_5% GPIO27_TMS GPIO27_TMS L1 VGA_HDMI_SCL R714 2 DIIS_HDM1I@ 10K_0402_5%
1 R324 102K_0402_5% GPIO26_TCK T64 GPIO28_TDO JTAG_TMS VGA_HDMI_SDA R713 2 DIIS_HDM1I@ 10K_0402_5%
K4
2 1 TEST_EN K7 JTAG_TDO AH12 VGA_LVDS_SCL R712 2 DIIS@ 1 10K_0402_5%

C VGA_LVDS_SDA R711
R326 T65 TESTEN AM10 2 DIIS@ 1 10K_0402_5%
AF24
10K_0402_5% TESTEN_LEGACY Y
AJ9 VGA_DDCCLK R621 2 DIIS@ 1 10K_0402_5%
COMP +VDD2DI +1.8VGS VGA_DDCDATA R426 2 DIIS@ 1 10K_0402_5%
AB13 GENERICA DAC2 2mA L12
+VDD2DI
W8 AL13 1 2
+1.8VGS +DPLL_PVDD GENERICB H2SYNC AJ13 BLM15BD121SN1D_0402
W9
B GENERICC V2SYNC +3VGS B
L14 75mA W7 1 1 1
2 D_0402
1 GENERICD
+DPLL_PVDD AD10 Change to 0 ohm
10U_0603_6..3V6M
GENERICE_HPD4
1U_0402_6..3V4Z
0..1U_0402_10V6K
1 1 1
C317
C318
C316
BLM15BD121SN1 AD19 +VDD2DI +VDD2DI P/N
10U_0603_6..3V6M
1U_0402_10V6K
1U_0402_6..3V4Z
VDD2DI
C323
C324
C325
<33> HDMI_DETECT_VGA AC14 AC19
PX_EN HPD1 VSS2DI 2 2 2 +3VGS
2 2 2 <25> PX_EN AB16 PX_EN
1
1 2 R613 AE20 +A2VDD R327 R328 8/14 change P/N to
0..
4.. 7K_0402_5% A2VDD +A2VDD 10K_0402_5% 10K_0402_5%
2
2
0.60 V level, Please AE17 +A2VDDQ DMN66D0LDW-7_SOT363-6
+A2VDDQ
21
A2VDDQ
VREFG Divider ans +A2VDD +3VGS
(SB00000DH00)
+1.8VGS AE19
cap close to ASIC A2VSSQ
100mA L13 VGA_SMB_CK2_R 1 6 EC_SMB_CK2 <15,37,40>
2 R329 1499_0402_1% +VREFG_GPU AC16 +A2VDD 1 2
5
1U_0402_6..3V4Z
0..1U_0402_10V6K
C320
C319
+1.0VGS +DPLL_VDDC VREFG AG13 1 R330 2 BLM15BD121SN1D_0402 Q64A
R2SET
L16 125mA 2 R331 1249_0402_1% 715_0402_1% 1 1 1 2N7002DW-T//R7_SOT363-6
2 1 +DPLL_VDDC Change to 0 ohm VGA_SMB_DA2_R 4 3 EC_SMB_DA2 <15,37,40>
10U_0603_6..3V6M
C321
D_0402
BLM15BD121SN1 1 1 1 2 1
P/N
10U_0603_6..3V6M
1U_0402_6..3V4Z
1U_0402_10V6K
C322 0..1U_0402_10V6K DDC/AUX AE6 VGA_HDMI_SCL Q64B

C331
C330
C332
PLL/CLOCK DDC1CLK VGA_HDMI_SDA VGA_HDMI_SCL <33> 2 2 2 2N7002DW-T//R7_SOT363-6

DDC1DATA AE5
+DPLL_PVDD VGA_HDMI_SDA <33>
+DPLL_PVDD AF14
DPLL_PVDD AD2
AE14 AUX1P AD4
DPLL_PVSS AUX1N
+3VGS
AC11 VGA_LVDS_SCL
+DPLL_VDDC +DPLL_VDDC AD14 DDC2CLK
DPLL_VDDC DDC2DATA AC13 VGA_LVDS_SDA VGA_LVDS_SCL <31> +A2VDDQ +1.8VGS
VGA_LVDS_SDA <31>
130mA L15 2 VGA Thermal
2 2 2 Sensor
XTALIN XTALIN AM28 AD13 +A2VDDQ 1 2 C329
0..
XTALIN AUX2P
+1.8VGS +TSVDD
@
Voltage Swing: 1.8 V XTALOUT AK28
XTALOUT AUX2N
AD11 BLM15BD121SN1D_0402 0..1U_0402_16V4Z
EMC1402-1 Closed to GPU
L17 20mA 1 1 1
10U_0603_6..3V6M
0..1U_0402_10V6K
1U_0402_6..3V4Z
C326
C327
C328
1
2 1 +TSVDD 2 R332 10_0402_5% AC22 AD20 Change to 0 ohm
XO_IN DDCCLK_AUX3P
BLM18AG121SN1D_0603 2 R333 10_0402_5% AB22 AC20 U9
DDCDATA_AUX3N P/N
10U_0603_6..3V6M
1U_0402_6..3V4Z
0..1U_0402_16V4Z
XO_IN2
C335
C336
C334
1 1 1 1 8 VGA_SMB_CK2_R
2 2 2 VDD SCLK
2 2 2 AE16
DDCCLK_AUX5P
@
GPU_THERMAL_D+ VGA_SMB_DA2_R
@
AD16 2 7
DDCDATA_AUX5N D+ SDATA
AC1 VGA_DDCCLK 1 2 3 6
GPU_THERMAL_D+ THERMAL DDC6CLK VGA_DDCDAT VGA_DDCCLK <32> C333 D- ALERT#
T4 AC3 A
DPLUS DDC6DATA VGA_DDCDATA <32>

A L17 GPU_THERMAL_D- 2200P_0402_50V7K THM_ALERT# A
T2 4 5
DMINUS GPU_THERMAL_D- THERM# GND
R334 2.. 61K_0402_5%
1 2 R5 1 R335 2 EMC1402-2-ACZL-TR MSOP 8P 2 R336 1
AD17
+TSVDD TSVDD
XTALOUT R337 XTALIN TSVSS 4..7K_0402_5%
0_0603 5% 1M_0603_5% EMC1412-A (SA00003YA00)
@
Y3
SD013000080 2 1 216-0774207-A11ROB_FCBGA631
S IC EMC1412-A-ACZL-TR MSOP 8P SENSOR
27MHZ_16PF_X5H027000FG1H Securiity Cllassiifiicatiion Compal Secret Data Compal Electronics, Inc.
C337 C338
18P_0402_50V8J 18P_0402_50V8J
THIIS SHEET OF ENGIINEERIING DRAW ING IS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, INC.. AND CONTAIINS CONFIIDENTIIAL
RobsonXT-S3 Main Generic/MSIC
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D Sii ze Documentt Number Rev
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS C 0..2
MAY BE USED BY OR DII SCLOSED TO ANY THII RD PARTY WII THOUT PRII OR WRII TTEN CONSENT OF COMPAL ELECTRONII CS,, I NC..
Datt e:: Frii day,, November 26,, 2010 Sheett 24 off 59
5 4 2 1
3
5 4 3 2 1
@ 0_0402_5%
<52> VGA_CORE_PG 1 2 VGA_PW RGD VGA_PWRGD <23>
R689
VGA_CORE_PG +3VGS +5VS +5VS

D D
1
0.1U_0402_10V6K
R338
1
@
10K_0402_5%
C339
1 R339 BACO@
10K_0402_5%
2
BACO@ VDDC_ON#
2
2
1.0V_ON#
5
+3VGS 1 R612 2 U10
D D
1
10K_0402_5% 2 BACO@
@ R692 B
P
BACO@ 2N7002H_SOT23-3 2N7002H_SOT23-3
Y 4 2
G Q66
2
G Q67
+3VS 1 R340 2 1 2 PX_MODE 1 A
S Change footprint S Change footprint
G
@ 10K_0402_5% 0_0402_5% MC74VHC1G08DFT2G SC70 5P 20100814 20100814
3
BACO@
3
BACO@
D 1
2N7002H_SOT23-3 C382
1
1 2 2 C386
<24> PX_EN Q68
R341 G 0.1U_0402_10V6K @ 0.1U_0402_10V6K
0_0402_5% S Change footprint 1 2 2 @
20100814 +3VGS Q69 Q70
BACO@
U37 AO3414_SOT23-3 AO3414_SOT23-3
3
C BACO@ +1.0VGS +BIF_VDDC +VGA_CORE C

2 3 1 1 3
5
B PX_MODE
4 PX_MODE <26,52>
D
Y
S
+3VGS
P
1 BACO@ BACO@
C731 A
1 2
1 2 BACO@ 1.0V_ON# R342
G
@ MC74VHC1G08DFT2G SC70 5P
2
1
0.1U_0402_10V6K
0_0402_5% BACO@ 0.1U_0402_10V6K
BACO@ C343
DIS@ R872 Q71 Q72
1
20K_0402_5% AO3414_SOT23-3 AO3414_SOT23-3

@ +VGA_CORE 2
1 NC 3 1 1 3
5
4 RUNPW ROK
Y
S
PE_GPIO1 1 2 2 BACO@ BACO@
P
<15,18,26,52> PE_GPIO1
2
D28 A U40
CH751H-40PT_SOD323-2 SN74LVC1G07DCKR_SC70-5 VDDC_ON#
G
G
BACO@ 1
G
2
2
Add when verify BACO
3
C732
1U_0603_10V4Z
2 2 1
@
R873
0_0402_5% BACO@ 9/28 modify to AO3414
B
D28 with leakage need to check B
A A

PARK-S3 Main Generic/MSIC
2 INC. 1
5 4 3 2 1
Short J2 for control sequence at PWM

+VGA_PCIE TO +1.0VGS
+VGA_PCIE +1.0VGS +1.8VS @ +1.8VGS

@
+1.8VS TO +1.8VGS 2 1
2 1
2MM J5
D 2MM J2 D
U14 @ U13
DMN3030LSS-13_SOP8L-8 DMN3030LSS-13_SOP8L-8
1
1
8 1 10U_0805_10V4Z 1U_0603_10V4Z 8 1
1 7 2 1 7 2 1 1
6 3 1 1 6 3
C346 5 C375 C368 R664 C348 5 C349 C350
10U_0805_10V4Z 470_0603_5% 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R348
2 2 2 2 470_0603_5%
4
2 2 @ @
1 2
1 2
@
+VSB D +VSB D
1
0_0402_5% 2N7002H_SOT23-3
S 2 S 2
3
R640 1 2 Q75
G G
R687 Change
@ footpr int C hange footprint
3
1
@ @ 20100814 2 0100814
20K_0 330K_0402_5%
R350
2
402_5 %
PE_GPIO1# N7002H_SOT23-3 1 C730
1 R352 2
D
2
2
2
G Q 85 0.1U_0603_25V7K 0_0402_5% PE_GPIO1#
S@ D 1
3
1
Change footprint @ 2 PE_GPIO1# R354 C352
20100814 PE_GPIO1# 2 0_0402_5% 0.1U_0603_25V7K
G Q78 @
S 2
3
Change footprint
1
20100814 2N7002H_SOT23-3
C C
+1.5VS TO +1.5VGS
+1.5V +1.5VGS
2 1
2MM J3 @
U11
+3.3VS TO +3.3VGS +3VS +3VGS DMN3030LSS-13_SOP8L-8
1 2
@ 8 1
2 1 10U_0805_10V4Z 1U_0603_10V4Z 1 7 2 1 1
1
6 3 C341 C342
1
2MM J4 1 1 C340 5 10U_0805_10V4Z 1U_0603_10V4Z R343

C376 C377 R686 10U_0805_10V4Z 470_0603_5%
470_0603_5% 2 2 2 @
3 1
4
@
Change footprint 2 2
D
12
+5VALW 20100814 Q65 +VSB
D
2
AP2301GN-HF_SOT23-3 2N7002H_SOT23-3 S
2
Q73 G
2N7002H_SOT23-3 S @ Change footprint
2 R344
20100814
3
Q77 G 20K_0402_5%
R641 R688 @ Change footprint
20100814
3
DIS@ 0_0402_5% R345

402_5%
2
20K_0 20K_0402_5% PE_GPIO1# 1 2 2 @ 0_0402_5%
D
1
2 R674 _0402_1% 1 PE_GPIO1# 1 2

G 1 0_0402_5% R346 R680
1
S
3
2N 200K
D
1
C351 PE_GPIO1# PX_MODE# 1 2 2 0_0402_5% C344 @ 0_0402_5%
B Q7 4 @ PX_MODE# 1 B
PE_GPIO1 0.1U_0603_25V7K R677 G 0.1U_0603_25V7K 2
Q86 BACO@ S 2 R681
1
2 2N7002H_SOT23-3
Change footprint
20100814
7002H_SOT23-3 Add when verify Change footprint
BACO 20100814
DIS@
0_0402_5%
1 2 PE_GPIO1
<10,40,44,49,51,52> SUSP#
R744
+3VALW
+3VALW
1
1
100K_0402_5%
R718
2
PX_MODE#
R676
100K_0402_5%
2
PE_GPIO1#
Q121
1
DTC124EKAT146_SC59-3
PX_MODE 23-3
2
OUT
<25,52> PX_MODE
G
1
Change footprint
GND
20100814 PE_GPIO1 2
<15,18,25,52> PE_GPIO1 IN
R719
100K_0402_5%
2
A A
3
Security Classification Compal Secret Data Compal Electronics,
PARK-S3 Inc.
Main Generic/MSIC
THII S SHEET
IssuedOFDate 2010/07/12
Deciphered Date CONFII DENTII AL Tiitlle
0.1
Custom
LA-6751P
5 4 3 2 1
5 4 3 2 1
+1.8VGS +DPEF_VDD18 +DPAB_VDD18

+1.8VGS L18 total:440mA@LVDS
L19
total:300mA@DP total:300mA
0.1U_0402_10V6K
0.1U_0402_10V6K
C355
C357
10U_0603_6.3V6M
10U_0603_6.3V6M
C353
C354
C358
C359
1U_0402_6.3V4Z
1U_0402_6.3V4Z
D
2 1 2 1 D
1 1 1 1 1 1
MBK1608121YZF_0603 U8G MBK1608121YZF_0603
2 2 2 2 2 2
Change to 0 ohm DP E/F POWER DP A/B POWER
Change to 0 ohm
P/N 130mA P/N
+1.0VGS AG15 AE11 +DPAB_VDD18
AG16 DPE_VDD18#1 DPA_VDD18#1 AF11
DPE_VDD18#2 DPA_VDD18#2 +1.0VGS
+DPEF_VDD10 +DPAB_VDD10
L20 total:240mA@LVDS 110mA L21
total:220mA@DP total:220mA
2 1 AG20 DPE_VDD10#1 DPA_VDD10#1 AF6 1 2
0.1U_0402_10V6K
0.1U_0402_10V6K
10U_0603_6.3V6M
10U_0603_6.3V6M
C361
C362
C356
C364
C360
C363
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1 1 1 AG21 DPE_VDD10#2 DPA_VDD10#2 AF7 1 1 1
ChMaBnKg
1608121YZF_0603
e to 0 ohm MBK1608121YZF_0603
P/N 2 2 2
AG14 DPE_VSSR#1 DPA_VSSR#1 AE1
2 2 2
Change to 0 ohm
AH14 AE3
AM14
DPE_VSSR#2 DPA_VSSR#2
AG1 P/N
DPE_VSSR#3 DPA_VSSR#3
AM16 DPE_VSSR#4 DPA_VSSR#4 AG6
AM18 DPE_VSSR#5 DPA_VSSR#5 AH5
130mA
AF16 AE13 +DPAB_VDD18
DPF_VDD18#1 DPB_VDD18#1
AG17 DPF_VDD18#2 DPB_VDD18#2 AF13
C C
110mA
AF22 AF8 +DPAB_VDD10
DPF_VDD10#1 DPB_VDD10#1
AG22 DPF_VDD10#2 DPB_VDD10#2 AF9
AF23 AF10
AG23 DPF_VSSR#1 DPB_VSSR#1 AG9
DPF_VSSR#2 DPB_VSSR#2
AM20 DPF_VSSR#3 DPB_VSSR#3 AH8
AM22 DPF_VSSR#4 DPB_VSSR#4 AM6
AM24 DPF_VSSR#5 DPB_VSSR#5 AM8
R355
2 1 AF17 DPEF_CALR DPAB_CALR AE10 1 R356 2
150_0402_1% 150_0402_1%
20mA 20mA
+DPEF_VDD18 AG18 DP PLL POWER AG8 +DPAB_VDD18
DPE_PVDD DPA_PVDD
AF19 DPE_PVSS DPA_PVSS AG7
20mA 20mA
B +DPEF_VDD18 AG19 AG10 +DPAB_VDD18 B
DPF_PVDD DPB_PVDD
AF20 DPF_PVSS DPB_PVSS AG11
216-0774207-A11ROB_FCBGA631
A A

RobsonXT-S3 DP PWR
COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS
2 INC. 1
5 4 3 2 1
+1.5VGS
2.3A(RMS)/2.8A(Peak)
22U_0805_6..3V6M
22U_0805_6..3V6M
10U_0603_6..3V6M
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
C365
C366
C369
C370
C371
C372
C373
C374
C389
C390
C391
C381
C392
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
+PCIE_VDDR +1.8VGS
9/28 Reserved for VGA_CORE
504mA L22
U8D +PCIE_VDDR 2 1
10/8 change to B2 size U8E
MEM I/O 1 1 1 1 MBK1608121YZF_0603
0..1U_0402_10V6K
1U_0402_6..3V4Z
1U_0402_6..3V4Z
10U_0603_6..3V6M
C385
C387
C388
C380
PCIE Change to 0 ohm
D
H13 AB23 +VGA_CORE AA27 A3 D
H16
VDDR1#1 PCIE_VDDR#1
AC23 P/N AB24
PCIE_VSS#1 GND#1
A30
H19 VDDR1#2 PCIE_VDDR#2 AD24 AB32 PCIE_VSS#2 GND#2 AA13
J10 VDDR1#3 PCIE_VDDR#3 AE24 2 2 2 2 AC24 PCIE_VSS#3 GND#3 AA16
VDDR1#4 PCIE_VDDR#4 1 PCIE_VSS#4 GND#4
J23 AE25 AC26 AB10
220U_B2_2..5VM_R35
C736
J24 VDDR1#5 PCIE_VDDR#5 AE26 + AC27 PCIE_VSS#5 GND#5 AB15
J9 VDDR1#6 PCIE_VDDR#6 AF25 @ AD25 PCIE_VSS#6 GND#6 AB6
K10 VDDR1#7 PCIE_VDDR#7 AG26 +1.0VGS AD32 PCIE_VSS#7 GND#7 AC9
K23 VDDR1#8 PCIE_VDDR#8 2 AE27 PCIE_VSS#8 GND#8 AD6
VDDR1#9 PCIE_VSS#9 GND#9
K24
K9
VDDR1#10
L23
1920mA AF32
AG27
PCIE_VSS#10 GND#10 AD8
AE7
L11 VDDR1#11 PCIE_VDDC#1 L24 AH32 PCIE_VSS#11 GND#11 AG12
L12 VDDR1#12 PCIE_VDDC#2 L25 K28 PCIE_VSS#12 GND#12 AH10
VDDR1#13 PCIE_VDDC#3 1 1 1 1 1 PCIE_VSS#13 GND#13
+1.8VGS +VDDC_CT
L20 M22 L27 B10
10U_0603_6..3V6M
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
VDDR1#15 PCIE_VDDC#5 PCIE_VSS#15 GND#15
C398
C399
C383
C403
C384
L23 110mA L21 VDDR1#16 PCIE_VDDC#6 N22 M32 PCIE_VSS#16 GND#16 B12
2 2 2 2 2
1 2 L22 VDDR1#17 PCIE_VDDC#7 N23 N25 PCIE_VSS#17 GND#17 B14
BLM15BD121SN1D_0402 N24 N27 PCIE_VSS#18 B16
+3VGS PCIE_VDDC#8 GND#18
1 1 1 PCIE_VDDC#9 R22 P25 PCIE_VSS#19 GND#19 B18
Change to 0 ohm LEVEL PCIE_VDDC#10
T22
U22
P32
R27 PCIE_VSS#20 GND#20
B20
B22
P/N TRANSLATION PCIE_VDDC#11 +VGA_CORE PCIE_VSS#21 GND#21
0..1U_0402_10V6K
10U_0603_6..3V6M
1U_0402_6..3V4Z
V22 T25 PCIE_VSS#22 B24

C405
C408
C404
PCIE_VDDC#12 GND#22
1 1 1 17mA AA20 VDD_CT#1 T32 PCIE_VSS#23 GND#23 B26
@
AA21
AB20
VDD_CT#2
AA15
11.8A(RMS)/12.9A(Peak) U25 PCIE_VSS#24
U27 PCIE_VSS#25
GND#24 B6
B8
VDD_CT#3 CORE VDDC#1 GND#25
AB21 N15 V32 PCIE_VSS#26 C1
10U_0603_6..3V6M
VDD_CT#4 VDDC#2 GND#26
1U_0402_6..3V4Z
1U_0402_6..3V4Z
2 2 2 N17 W 25 PCIE_VSS#27 C32
C409
C410
C411
VDDC#3 1 1 1 1 1 1 1 1 1 1 1 1 GND#27
VDDC#4 R13 W 26 PCIE_VSS#28 GND#28 E28
I/O R16 W 27 PCIE_VSS#29 F10
VDDC#5 GND#29
60mA AA17
VDDR3#1 VDDC#6
R18 Y25
PCIE_VSS#30 GND#30
F12
AA18 Y21 2 2 2 2 2 2 2 2 2 2 2 2 Y32 PCIE_VSS#31 F14
10U_0603_6..3V6M
10U_0603_6..3V6M
22U_0805_6..3V6M
22U_0805_6..3V6M
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
2 2 2 VDDR3#2 VDDC#7 GND#31
C413
C414
C415
C416
C417
C418
C419
C420
C423
C424
C425
C426
AB17 VDDR3#3 VDDC#8 T12 GND#32 F16
AB18 VDDR3#4 VDDC#9 T15 GND#33 F18
L24 T17 F2
VDDC#10 GND#34
1 2 170mA V12 VDDR4#1 VDDC#11 T20 GND#35 F20
BLM15BD121SN1D_0402 Y12 VDDR4#2 VDDC#12 U13 M6 GND#56 GND#36 F22
U12 VDDR4#3 VDDC#13 U16 N11 GND#57 GND#37 F24
Change to 0 ohm 1 1 AA11 VDDC#14
U18
V21 7/22 modify N12
N13 GND#58 GND#38
F26
F6
P/N
GND
AA12 NC#1 VDDC#15 V15 N16 GND#59 GND#39 F8
NC#2 VDDC#16 GND#60 GND#40
V17 N18 G ND#61 G10
V11 VDDC#17 V20 N21 GND#41 G27
U11 NC#3 VDDC#18 Y13 P6 GND#62 GND#42 G31
NC#4 VDDC#19 GND#63 GND#43
0..1U_0402_10V6K
1U_0402_6..3V4Z
VDDC#20 Y16 P9 GND#64 GND#44 G8

C Y18 R12 H14 C
POWER
VDDC#21 GND#65 GND#45
C429
C430
VDDC#22 M11 R15 GND#66 GND#46 H17

L25 M12 R17 H2
1 2 MEM CLK VDDC#23 R20 GND#67 GND#47 H20
BLM15BD121SN1D_0402 GND#68 GND#48
L17 NC_VDDRHA T13 GND#69 GND#49 H6
12 12 1 T16 J27
L16 NC_VSSRHA
+BIF_VDDC T18 GND#70
GND#71
GND#50
GND#51 J31
+1.8VGS T21 GND#72 K11
GND#52
T6 GND#73 GND#53 K2
For Seymour, PCIE_PVDD is PCIE_VDDR. PLL 1 1 U15 GND#74 K22
GND#54
AM30 PCIE_PVDD U17 GND#75 GND#55 K6
BIF_VDDC#1 R21 U20 GND#76
BIF_VDDC#2 U21 U9 GND#77
+MPV18 75mA L8 NC_MPV18 V13 GND#78
10U_0603_6..3V6M
1U_0402_6..3V4Z
0..1U_0402_10V6K
V16 GND#79
C447
C446
C449
L26 V18 GND#80

1 2 +SPV18 75mA H7 SPV18 Y10 GND#81
BLM15BD121SN1D_0402 ISOLATED Y15 GND#82
12 12 12 +SPV10 120mAH8 CORE I/O M13 Y17 GND#83 A32
SPV10 VDDCI#1 R745 VSS_MECH#1
1U_0402_6..3V4Z
1U_0402_6..3V4Z
M15 +VDDCI +VGA_CORE Y20 AM1
C451
C452
+1.0VGS J7 VDDCI#2 M16 0_0603_5% R11 GND#84 VSS_MECH#2 AM32
L28 SPVSS VDDCI#3 GND#85 VSS_MECH#3
VDDCI#4 M17 1 2 T11 GND#86
1 2 M18
BLM15BD121SN1D_0402 VDDCI#5 M20
VDDCI#6 1 21 21 1
N20
VDDCI#8 216-0774207-A11ROB_FCBGA631
2 2 2 2
10U_0603_6..3V6M
0..1U_0402_10V6K
1U_0402_6..3V4Z
C454
C455
C453
216-0774207-A11ROB_FCBGA631
2 2 2
10U_0603_6..3V6M
1U_0402_6..3V4Z
1U_0402_6..3V4Z
1U_0402_6..3V4Z
C459
C460
C461
C466
0..1U_0402_10V6K
10U_0603_6..3V6M
1U_0402_6..3V4Z
C457
C458
C456
2 2 2
B B
A A
Securiity Cllassiifiicatiion Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/07/12 Deciiphered Date 2012/07/11 Tiitl e
RobsonXT-S3 PWR/GND
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D C 0.. 2
DEPARTMENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS
5 4 3 2 1
5 4 3 2 1
U8C +1.8VGS
<30> M_DA[63..0] GDDR5/DDR3 GDDR5/DDR3 R357 X76@ 2 10K_0402_5% VRAM_ID0
1 VRAM_ID0 <24>
M_MA[13..0] M_DA0 K27 K17 M_MA0 R358 1 X76@ 2 10K_0402_5%
<30> M_MA[13..0] DQA0_0/DQA_0 MAA0_0/MAA_0
M_DA1 J29 J20 M_MA1 R359 1 X76@ 2 10K_0402_5% VRAM_ID1 VRAM_ID1 <24>
M_DQM[7..0] M_DA2 DQA0_1/DQA_1 MAA0_1/MAA_1 M_MA2 R360 X76@ 2 10K_0402_5%
<30> M_DQM[7..0] H30 DQA0_2/DQA_2 MAA0_2/MAA_2 H23 1
M_DA3 H32 G23 M_MA3 R361 1 X76@ 2 10K_0402_5% VRAM_ID2 VRAM_ID2 <24>
M_DQS[7..0] M_DA4 DQA0_3/DQA_3 MAA0_3/MAA_3 M_MA4 R362 X76@ 2 10K_0402_5%
<30> M_DQS[7..0] G29 DQA0_4/DQA_4 MAA0_4/MAA_4 G24 1
M_DA5 F28 DQA0_5/DQA_5 MAA0_5/MAA_5 H24 M_MA5
M_DQS#[7..0] M_DA6 M_MA6
F30 DQA0_7/DQA_7 MAA0_7/MAA0_7 K19
M_DA8 C30 J14 M_MA8
D M_DA9 DQA0_8/DQA_8 MAA1_0/MAA_8 M_MA9 D
F27 DQA0_9/DQA_9 MAA1_1/MAA_9 K14
M_DA10 A28 DQA0_10/DQA_10 MAA1_2/MAA_10 J11 M_MA10
M_DA11 C28 J13 M_MA11
M_DA12 DQA0_11/DQA_11 MAA1_3/MAA_11 M_MA12
E27 DQA0_12/DQA_12 MAA1_4/MAA_12 H11 Vendor VRAM_ID0 VRAM_ID1 VRAM_ID2
M_DA13 G26 G11 M_BA2 M_BA2 <30>
M_DA14 DQA0_13/DQA_13 MAA1_5/MAA_13/BA2 M_BA0
D26 DQA0_14/DQA_14 MAA1_6/MAA_14/BA0 J16 M_BA0 <30>
INTERFACE
M_DA15 F25 L15 M_BA1 M_BA1 <30>
M_DA16 DQA0_15/DQA_15 MAA1_7/MAA_15/BA1 Hynix 512MB
A25 DQA0_16/DQA_16
M_DA17 C25 DQA0_17/DQA_17 W CKA0_0/DQMA_0 E32 M_DQM0
PN:SA000032460 R357 R360 R362
M_DA18 E25 E30 M_DQM1
M_DA19 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 M_DQM2
D24 A21
MEMORY
M_DA20 DQA0_19/DQA_19 W CKA0_1/DQMA_2 M_DQM3
M_DA21
E23 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 C21
M_DQM4
Samsung 512MB
F23 DQA0_21/DQA_21 W CKA1_0/DQMA_4 E13 R358 R359 R362
M_DA22 D22 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 D12 M_DQM5 PN:SA000035700
M_DA23 F21 E3 M_DQM6
M_DA24 DQA0_23/DQA_23 W CKA1_1/DQMA_6 M_DQM7
E21 F4
M_DA25 D20
DQA0_24/DQA_24 WCKA1B_1/DQMA_7 Hynix 1GB
M_DA26 DQA0_25/DQA_25 M_DQS0 R357 R360 R361
M_DA27
F19 DQA0_26/DQA_26 EDCA0_0/RDQSA_0 H28
M_DQS1
PN:SA00003VS20
A19 DQA0_27/DQA_27 EDCA0_1/RDQSA_1 C27
M_DA28 D18 A23 M_DQS2
M_DA29 DQA0_28/DQA_28 EDCA0_2/RDQSA_2 M_DQS3 Samsung 1GB
F17 DQA0_29/DQA_29 EDCA0_3/RDQSA_3 E19
M_DA30 A17 E15 M_DQS4 R358 R359 R361
M_DA31 C17
DQA0_30/DQA_30 EDCA1_0/RDQSA_4
D10 M_DQS5 PN:SA00003MQ20
+1.5VGS M_DA32 DQA0_31/DQA_31 EDCA1_1/RDQSA_5 M_DQS6
E17 DQA1_0/DQA_32 EDCA1_2/RDQSA_6 D6
+1.5VGS M_DA33 D16 G5 M_DQS7
M_DA34 DQA1_1/DQA_33 EDCA1_3/RDQSA_7
F15 DQA1_2/DQA_34
C M_DA35 A15 M_DQS#0 C
DQA1_3/DQA_35 DDBIA0_0/W DQSA_0 H27
R365 M_DA36 D14 M_DQS#1
R363 40.2_0402_1% M_DA37 DQA1_4/DQA_36 DDBIA0_1/W DQSA_1 A27 M_DQS#2
F13 DQA1_5/DQA_37 DDBIA0_2/W DQSA_2 C23
40.2_0402_1% M_DA38 A13 M_DQS#3
DDBIA0_3/W DQSA_3 C19
1
M_DA39 DQA1_6/DQA_38 M_DQS#4

C13 DDBIA1_0/W DQSA_4 C15
1
M_DA40 DQA1_7/DQA_39 M_DQS#5

E11 DQA1_8/DQA_40 DDBIA1_1/W DQSA_5 E9
M_DA41 A11 M_DQS#6
M_DA42 DQA1_9/DQA_41 DDBIA1_2/W DQSA_6 C5 M_DQS#7
C11 DQA1_10/DQA_42 DDBIA1_3/W DQSA_7 H4
M_DA43
2
A9 L18 VRAM_ODT0 <30>

DQA1_12/DQA_44 ADBIA0/ODTA0
2
100_0402_1% 0.1U_0402_16V4Z
MVREFDA 100_0402_1% 0.1U_0402_16V4Z
MVREFSA M_DA45 VRAM_ODT1
F9
2 2 DQA1_14/DQA_46
1
M_DA47 D8 DQA1_15/DQA_47 CLKA0 H26 M_CLK0 M_CLK0 <30>

1 1 M_DA48 M_CLK#0
E7 DQA1_16/DQA_48 CLKA0B H25 M_CLK#0 <30>
M_DA49 A7
M_DA50 DQA1_17/DQA_49 M_CLK1
C7 DQA1_18/DQA_50 CLKA1 G9 M_CLK1 <30>
M_DA51 F7 H9 M_CLK#1 M_CLK#1 <30>
M_DA52 DQA1_19/DQA_51 CLKA1B
A5
2
DQA1_20/DQA_52
PARK SCL has different M_DA53 E5 G22 M_RAS#0 M_RAS#0 <30>
M_DA54 DQA1_21/DQA_53 RASA0B M_RAS#1
C3 DQA1_22/DQA_54 RASA1B G17 M_RAS#1 <30>
recommand 9/28 change P/N to SD034100A80 M_DA55 E1 DQA1_23/DQA_55
M_DA56 G7 G19 M_CAS#0 M_CAS#0 <30>
M_DA57 DQA1_24/DQA_56 CASA0B M_CAS#1
R369 G6 DQA1_25/DQA_57 CASA1B G16 M_CAS#1 <30>
R366 10_0402_1% M_DA58 G1
DRAM_RST M_DA59 DQA1_26/DQA_58 M_CS#0
<30> DRAM_RST# 2 1 2 1 G3 DQA1_27/DQA_59 CSA0B_0 H22 M_CS#0 <30>
M_DA60 J6 DQA1_28/DQA_60 CSA0B_1 J22
B 49.9_0402_1% M_DA61 B
J1 DQA1_29/DQA_61
1 M_DA62 J3 G13 M_CS#1 M_CS#1 <30>
DQA1_30/DQA_62 CSA1B_0
C469 R371 M_DA63 J5 DQA1_31/DQA_63 CSA1B_1 K13
120P_0402_50V8J 4.99K_0402_1%
MVREFDA K26 K20 M_CKE0 M_CKE0 <30>
2 +1.5VGS MVREFSA MVREFDA CKEA0 M_CKE1
J26 MVREFSA CKEA1 J17 M_CKE1 <30>
R368
1
1 243_04022_1% J25 G25 M_WE#0

M_WE#0 <30>
MEM_CALRN0 WEA0B M_WE#1
1 2 K25 MEM_CALRP0 WEA1B H10 M_WE#1 <30>
R370
243_0402_1%
MAA1_8 G14
GDDR5
2
G20 M_MA13
DRAM_RST L10 MAA0_8
DRAM_RST
1R372@ 51.12_0402_1% 1C470@20.1U_0402_16V4Z K8 CLKTESTA
1 2 1 2 L7 CLKTESTB
R373@ 51.1_0402_1% C471@ 0.1U_0402_16V4Z
Route 50ohms single-ended/100ohm diff and keep short 216-0774207-A11ROB_FCBGA631
A A
debug only, for clock observation,if not need, Security Classification Compal Secret Data Compal Electronics, Inc.
DNI. Issued Date 2010/07/12 2012/07/11 Title
Deciphered Date
RobsonXT-S3 MEM Interface
2 INC. 1
5 4 3 2 1
M_DA[63..0]
<29> M_DA[63..0]
M_MA[13..0]
<29> M_MA[13..0]
M_DQM[7..0]
<29> M_DQM[7..0]
<29> M_DQS[7..0] M_DQS[7..0]
M_DQS#[7..0]
<29> M_DQS#[7..0]
U19 U20 U18 U21
VREFC_A1 M9 E4 M_DA22 VREFC_A2 M9 E4 M_DA25 VREFC_A3 M9 E4 M_DA35 VREFC_A4 M9 E4 M_DA52

VREFD_Q1 VREFCA DQL0 M_DA20 VREFD_Q2 VREFCA DQL0 M_DA28 VREFD_Q3 VREFCA DQL0 M_DA34 VREFD_Q4 VREFCA DQL0 M_DA48
H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8 H2 VREFDQ DQL1 F8
ZZZ ZZZ F3 M_DA19 F3 M_DA27 F3 M_DA36 F3 M_DA54
M_MA0 N4 DQL2 M_DA18 M_MA0 N4 DQL2 M_DA31 M_MA0 N4 DQL2 M_DA37 M_MA0 DQL2 M_DA50
A0 DQL3 F9 A0 DQL3 F9 A0 DQL3 F9 N4 A0 DQL3 F9
M_MA1 P8 A1 DQL4 H4 M_DA21 M_MA1 P8 A1 DQL4 H4 M_DA24 M_MA1 P8 A1 DQL4 H4 M_DA32 M_MA1 P8 A1 DQL4 H4 M_DA53
D M_MA2 P4 A2 DQL5 H9 M_DA17 M_MA2 P4 A2 DQL5 H9 M_DA29 M_MA2 P4 A2 DQL5 H9 M_DA38 M_MA2 P4 A2 DQL5 H9 M_DA49 D
M_MA3 N3 A3 DQL6 G3 M_DA23 M_MA3 N3 A3 DQL6 G3 M_DA26 M_MA3 N3 A3 DQL6 G3 M_DA33 M_MA3 N3 A3 DQL6 G3 M_DA55
M_MA4 P9 A4 DQL7 H8 M_DA16 M_MA4 P9 A4 DQL7 H8 M_DA30 M_MA4 P9 A4 DQL7 H8 M_DA39 M_MA4 P9 A4 DQL7 H8 M_DA51
Hyniix Samsung M_MA5 P3 M_MA5 P3 M_MA5 P3 M_MA5 P3
H1G@ S1G@ M_MA6 R9 A5 M_MA6 R9 A5 M_MA6 R9 A5 M_MA6 A5
A6 A6 A6 R9 A6
X7624938L01 X7624938L02 M_MA7 R3 A7 DQU0 D8 M_DA3 M_MA7 R3 A7 DQU0 D8 M_DA14 M_MA7 R3 A7 DQU0 D8 M_DA47 M_MA7 R3 A7 DQU0 D8 M_DA60
M_MA8 T9 C4 M_DA1 M_MA8 T9 C4 M_DA10 M_MA8 T9 C4 M_DA42 M_MA8 T9 C4 M_DA58
A8 DQU1 A8 DQU1 A8 DQU1 A8 DQU1
0706 update M_MA9 R4
M_MA10 L8 A9 DQU2 C9 M_DA0
M_DA5
M_MA9 R4
M_DA11
M_MA9 R4
M_DA41
M_MA9
M_MA10
R4 A9 DQU2 C9 M_DA56
M_DA61
C3 C3 C3 L8 C3
M_MA11 R8 A10/AP DQU3 M_DA6 M_MA11 R8 A10/AP DQU3 M_DA12 M_MA11 R8 A10/AP DQU3 M_DA43 M_MA11 A10/AP DQU3 M_DA63
update X76 PN M_MA12 N8 A11 DQU4 A8
A3 M_DA7 M_MA12 N8 A11 DQU4 A8
A3 M_DA8 M_MA12 N8 A11 DQU4 A8
A3 M_DA40 M_MA12
R8
N8
A11 DQU4 A8
A3 M_DA62
M_MA13 T4 A12 DQU5 M_DA2 M_MA13 T4 A12 DQU5 M_DA13 M_MA13 T4 A12 DQU5 M_DA46 M_MA13 A12 DQU5 M_DA57
A13 DQU6 B9 A13 DQU6 B9 A13 DQU6 B9 T4 A13 DQU6 B9
T8 A14 DQU7 A4 M_DA4 T8 A14 DQU7 A4 M_DA9 T8 A14 DQU7 A4 M_DA44 T8 A14 DQU7 A4 M_DA59
M8 A15/BA3 M8 A15/BA3 M8 A15/BA3 M8 A15/BA3
ZZZ ZZZ +1.5VGS +1.5VGS +1.5VGS +1.5VGS
M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3 M_BA0 M3 B3

<29> M_BA0 M_BA1 N9 BA0 VDD D10 M_BA1 N9 BA0 VDD D10 M_BA1 N9 BA0 VDD D10 M_BA1 N9 BA0 VDD D10
<29> M_BA1 BA1 VDD BA1 VDD BA1 VDD BA1 VDD
M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8 M_BA2 M4 G8
<29> M_BA2 BA2 VDD K3 BA2 VDD K3 BA2 VDD K3 BA2 VDD K3
VDD VDD VDD VDD
Hyniix Samsung K9 K9 K9 K9
H512@ S512@ VDD VDD VDD VDD
N2 N2 N2
X7624938L03 X7624938L04 M_CLK0 VDD M_CLK0 VDD M_CLK1 VDD M_CLK1 VDD
N2
<29> M_CLK0 J8 N10 J8 N10 <29> M_CLK1 J8 N10 J8 N10
M_CLK#0 K8 CK VDD R2 M_CLK#0 K8 CK VDD R2 M_CLK#1 K8 CK VDD R2 M_CLK#1 K8 CK VDD R2
<29> M_CLK#0 CK VDD CK VDD <29> M_CLK#1 CK VDD CK VDD R10
<29> M_CKE0 M_CKE0 K10 R10 M_CKE0 K10 R10 <29> M_CKE1 M_CKE1 K10 R10 M_CKE1 K10
CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS CKE/CKE0 VDD +1.5VGS
VRAM_ODT0K2 A2 VRAM_ODT0 K2 A2 VRAM_ODT1K2 A2 VRAM_ODT1 K2 A2

<29> VRAM_ODT0 M_CS#0 L3 ODT/ODT0 VDDQ A9 M_CS#0 L3 ODT/ODT0 VDDQ A9 <29> VRAM_ODT1 M_CS#1 L3 ODT/ODT0 VDDQ A9 M_CS#1 L3 ODT/ODT0 VDDQ A9
<29> M_CS#0 M_RAS#0 J4 CS VDDQ C2 M_RAS#0 J4 CS VDDQ C2 <29> M_CS#1 M_RAS#1 J4 CS VDDQ C2 M_RAS#1 J4 CS VDDQ C2
<29> M_RAS#0 M_CAS#0 K4 RAS VDDQ C10 M_CAS#0 K4 RAS VDDQ C10 <29> M_RAS#1 M_CAS#1 K4 RAS VDDQ C10 M_CAS#1 K4 RAS VDDQ C10
<29> M_CAS#0 CAS VDDQ CAS VDDQ <29> M_CAS#1 CAS VDDQ CAS VDDQ
M_WE#0 L4 D3 M_WE#0 L4 D3 M_WE#1 L4 D3 M_WE#1 L4
<29> M_WE#0 WE VDDQ E10 WE VDDQ E10 <29> M_WE#1 WE VDDQ E10 WE VDDQ D3
VDDQ F2 VDDQ F2 VDDQ F2 VDDQ E10
M_DQS2 VDDQ M_DQS3 VDDQ M_DQS4 VDDQ M_DQS6 VDDQ F2
F4 DQSL VDDQ H3 F4 DQSL VDDQ H3 F4 DQSL VDDQ H3 F4 DQSL VDDQ H3
M_DQS0 C8 DQSU VDDQ H10 M_DQS1 C8 DQSU VDDQ H10 M_DQS5 C8 DQSU VDDQ H10 M_DQS7 C8 DQSU VDDQ H10
M_DQM2 E8 A10 M_DQM3 E8 A10 M_DQM4 E8 A10 M_DQM6 E8 A10

M_DQM0 DML VSS M_DQM1 DML VSS M_DQM5 DML VSS M_DQM7 DML VSS
D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4 D4 DMU VSS B4
VSS E2 VSS E2 VSS E2 VSS E2
VSS G9 VSS G9 VSS G9 VSS G9
M_DQS#2 G4 DQSL VSS J3 M_DQS#3 G4 DQSL VSS J3 M_DQS#4 G4 DQSL VSS J3 M_DQS#6 G4 DQSL VSS J3
C
M_DQS#0 B8 J9 M_DQS#1 B8 J9 M_DQS#5 B8 J9 M_DQS#7 B8 J9 C
DQSU VSS M2 DQSU VSS M2 DQSU VSS M2 DQSU VSS M2
VSS VSS VSS VSS
VSS M10 VSS M10 VSS M10 VSS M10
P2 P2 P2 P2
VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS DRAM_RST# T3 VSS
<29> DRAM_RST# T3 RESET VSS P10 RESET VSS P10 RESET VSS P10 RESET VSS P10
VSS T2 VSS T2 VSS T2 VSS T2
L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10 L9 ZQ/ZQ0 VSS T10
J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2 J2 NC/ODT1 VSSQ B2

R374 L2 NC/CS1 VSSQ B10 R375 L2 NC/CS1 VSSQ B10 R376 L2 NC/CS1 VSSQ B10 R377 L2 NC/CS1 VSSQ B10
243_0402_1% J10 NC/CE1 VSSQ D2 243_0402_1% J10 NC/CE1 VSSQ D2 243_0402_1% J10 NC/CE1 VSSQ D2 243_0402_1% J10 NC/CE1 VSSQ D2
L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9 L10 NCZQ1 VSSQ D9
VSSQ E3 VSSQ E3 VSSQ E3 VSSQ E3
A1 NC VSSQ E9 A1 NC VSSQ E9 A1 NC VSSQ E9 A1 NC VSSQ E9
A11 NC VSSQ F10 A11 NC VSSQ F10 A11 NC VSSQ F10 A11 NC VSSQ F10
T1 NC VSSQ G2 T1 NC VSSQ G2 T1 NC VSSQ G2 T1 NC VSSQ G2
T11 G10 T11 G10 T11 G10 T11 G10
NC VSSQ NC VSSQ NC VSSQ NC VSSQ
100-BALL 100-BALL 100-BALL 100-BALL
1
1
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM
DDR3
64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA 64MX16 H5TQ1G63BFR-12C FBGA
X76@ X76@ X76@ X76@
2
2
+1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS +1.5VGS
R378 R379 R380 R381 R382 R383 R384 R385

4.. 99K_0402_1% 4..99K_0402_1% 4..99K_0402_1% 4..99K_0402_1% 4..99K_0402_1%
4.. 99K_0402_1% 4..99K_0402_1% 4..99K_0402_1%
B R386 R387 R388 R389 R390 R391 R392 R393 B

4.. 99K_0402_1% 4..99K_0402_1% 4..99K_0402_1% 4..99K_0402_1% 4..99K_0402_1%
1
1
2 2 2 2 2 2 2 2
2
2
M_CLK0 1 2 VREFD_Q1 VREFC_A1 VREFC_A2 VREFD_Q2 VREFC_A3 VREFD_Q3 VREFC_A4 VREFD_Q4
R394 56_0402_1%
1
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
C472
C479
C473
C474
C475
C476
C477
C478
1 1 1 1 1 1 1 1
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
0..1U_0402_10V6K
M_CLK#0 1 2
+1.5VGS R396 56_0402_1% +1.5VGS
1 1U_0402_6..3V4Z 1U_0402_6..3V4Z
C506 1U_0402_6.. 3V4Z 1U_0402_6..3V4Z 1U_0402_6.. 3V4Z 1U_0402_6..3V4Z 1U_0402_6..3V4Z
2
2
0.. 01U_0402_16V7K +1.5VGS 10U_0603_6.. 3V6M 10U_0603_6..3V6M 10U_0603_6..3V6M 1U_0402_6..3V4Z 1U_0402_6.. 3V4Z 1U_0402_6.. 3V4Z
2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C488 C489 C490 C480 C491 C481
2 2 2 2 2 2 @ 2 2 2 2 2 2 2 2 @ 2 2 @
10U_0603_6..3V6M 10U_0603_6..3V6M10U_0603_6.. 3V6M 2 2 2 2 2 2 2 2 2 2 1U_0402_6..3V4Z 1U_0402_6..3V4Z 1U_0402_6..3V4Z
1U_0402_6.. 3V4Z 1U_0402_6..3V4Z 1U_0402_6..3V4Z 1U_0402_6..3V4Z 1U_0402_6..3V4Z
M_CLK1 1 2 1U_0402_6..3V4Z
1U_0402_6..3V4Z R395 56_0402_1%
M_CLK#1 1 2
R397 56_0402_1% 1
C507
C500
C501
C484
C485
C486
C502
C503
C504
C505
C487
0.. 01U_0402_16V7K
C492
C482
C483
C493
C494
C495
C496
C497
C498
C499
2
ref 139-02 recommand VRAM P/N :
A A
add off page Hynix : SA000041S10 (S IC D3 64MX16 H5TQ1G63BFR-11C FBGA C38! ) Securiity Cllassiifiicatiion Compal Secret Data Compal Electronics, Inc.
Park SCL recommand pu 60.4 ohm to Samsung : SA000041T10 (S IC D3 64MX16 K4W1G1646E-HC11 FBGA C38! ) Issued Date 2010/07/12 Deciiphered Date 2012/07/11 Tiitl e
16
0.51V9GuSpdate update VRAM PN 0619 update THIIS SHEET OF ENGIINEERIING DRAW ING IS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, INC.. AND CONTAIINS CONFIIDENTIIAL
RobsonXT-S3 VRAM
5 4 3 2 1
5 4 3 2 1
INVPW M
+LEDVDD B+
1 R398 2 0_0805_5%
DISPOFF#
470P_0402_50V7K
470P_0402_50V7K
1 1
C508
C509 680P_0402_50V7K C512
@ 4.7U_0805_25V6-K
1 1 2 2
LCD POWER CIRCUIT C511
JLVDS1
+3VS_CMOS
2 2 2 1
2 1 USB20_N5
+LCDVDD +5VALW
4 4 3 3 USB20_P5
USB20_N5 <18> CMOS
(60 MIL) 6 6 5 5 USB20_P5 <18>
D
For EMI +LCDVDD_CONN 8 8 7 7 CONN_LVDS_A0# D
10 10 9 9
+3VS CONN_LVDS_A0
W=60mils 12
14
12 11 11
+3VS 14 13 13 CONN_LVDS_A1#
R400 R401 1 <40> CE_EN 16 15
150_0603_1% 100K_0402_5% Change footprint C513 @ INVPW M 16 15 CONN_LVDS_A1
1 2 18 17 17
1
680P_0402_50V7K 1 <40> INVT_PW M 18
20100814 4.7U_0603_6.3V6K 0_0402_5% DIS@ DISPOFF# 20
C514 20 19 19 CONN_LVDS_A2#
R402 22 22 21 21
2 Change footprint 24 CONN_LVDS_A2
20100814 2 24 23 23
R403 220K_0402_5% Q80 @ 26 25
2N7002H_SOT23-3 CONN_LVDS_SCL 26 25 CONN_LVDS_ACLK#
D R404 2.2K_0402_5%
2
2 1 2 2 28 27
3
+3VS
Q79 G
CONN_LVDS_SDA 28 27 CONN_LVDS_ACLK
R405 2.2K_0402_5% 30 29 30 29
@
Change footprint S DTC124EK 1 AP2301GN-HF_SOT23-3
3
32 31
1
20100814 C515 GNDGND
0.1U_0402_16V4Z
W=60mils Pull high at chipset/VGA side ACES_87142-3041-BS
OUT
1
2 +LCDVDD +LCDVDD_CONN ME@
L29
<17> PCH_ENVDD R406 2 1 0_0402_5% LCD_ENVDD 2
PX@ IN
1 2
GND
5
Q81 FBMA-L11-201209-221LMA30T_080 C516
R407 2 0_0402_5% DTC124EKAT146_SC59-3 1
<23> VGA_ENVDD 1 1
1
DIS@ C517
3
R408 @ 4.7U_0603_6.3V6K <24> VGA_LVDS_SCL VGA_LVDS_SCL 0_0402_5% 2 DIS@ 1 R409 CONN_LVDS_SCL
100K_0402_5% 0.1U_0402_16V4Z <24> VGA_LVDS_SDA VGA_LVDS_SDA 0_0402_5% 2 DIS@ 1 R410 CONN_LVDS_SDA
2 2
Change footprint VGA_LVDS_A0 0_0402_5% 2 DIS@ 1 R411 CONN_LVDS_A0
20100814 <23> VGA_LVDS_A0
VGA_LVDS_A0# 0_0402_5% 2 DIS@ 1 R412 CONN_LVDS_A0#
2
<23> VGA_LVDS_A0#
VGA_LVDS_A1 0_0402_5% 2 DIS@ 1 R413 CONN_LVDS_A1
<23> VGA_LVDS_A1 VGA_LVDS_A1# 0_0402_5% 2 DIS@ 1 R414 CONN_LVDS_A1#
<23> VGA_LVDS_A1#
VGA_LVDS_A2 0_0402_5% 2 DIS@ 1 R415 CONN_LVDS_A2
<23> VGA_LVDS_A2 VGA_LVDS_A2# 0_0402_5% 2 DIS@ 1 R416 CONN_LVDS_A2#
C
<23> VGA_LVDS_A2# C
VGA_LVDS_ACLK 0_0402_5% 2 DIS@ 1 R417 CONN_LVDS_ACLK
<23> VGA_LVDS_ACLK VGA_LVDS_ACLK#0_0402_5% CONN_LVDS_ACLK#
<23> VGA_LVDS_ACLK# 2 DIS@ 1 R418
<17> EDID_CLK EDID_CLK 0_0402_5% 2 PX@ 1 R419 CONN_LVDS_SCL

<17> EDID_DATA EDID_DATA 0_0402_5% 2 PX@ 1 R420 CONN_LVDS_SDA
<17> LVDS_A0 LVDS_A0 0_0402_5% 2 PX@ 1 R421 CONN_LVDS_A0

+3VS LVDS_A0# 0_0402_5% 2 PX@ 1 R422 CONN_LVDS_A0#
<17> LVDS_A0#
LVDS_A1 0_0402_5% 2 PX@ 1 R423 CONN_LVDS_A1
<17> LVDS_A1 LVDS_A1# 0_0402_5%
<17> LVDS_A1# 2 PX@ 1 R424 CONN_LVDS_A1#
U22
1 LVDS_A2 0_0402_5% 2 PX@ 1 R425 CONN_LVDS_A2
NC INVPW M <17> LVDS_A2 LVDS_A2# 0_0402_5%
<17> PCH_PW M 2 4 <17> LVDS_A2# 2 PX@ 1 R427 CONN_LVDS_A2#
A Y
5
LVDS_ACLK 0_0402_5% 2 PX@ 1 R428 CONN_LVDS_ACLK

<17> LVDS_ACLK
P
TC7SZ14FU_SSOP5 LVDS_ACLK# 0_0402_5% 2 PX@ 1 R429 CONN_LVDS_ACLK#

<17> LVDS_ACLK#
@
G
3
PX@
1 R430 2
0_0402_5%
1 INVPW M 2 R431 1 +3VS

2
10K_0402_5% @
G
3
Change footprint
S
2N7002H_SOT23-3
@ Q82 20100814
D
B B
For GMCH DPST
(20 MIL)
R539
CMOS Camera Conn (20 MIL)
0_0603_5%
+5VS @ 1 2 Change footprint
R596 20100814 +CMOS_PW +3VS_CMOS
0_0603_5%
+3VS 1 2 3 1
+3VS
1 1
CMOS@ Q83 CMOS@ CMOS@
1 2 R433 @ +5VALW AP2301GN-HF_SOT23-3 0.1U_0402_16V4Z 10U_0805_10V4Z
4.7K_0402_5% 4.7V
D4
1
BKOFF# 1 2 DISPOFF# CMOS@ R435 CMOS@

<40> BKOFF#
150K_0402_5% C520
2
@ CH751H-40PT_SOD323-2 R543 CMOS@ 0.1U_0402_16V4Z
2
0_0402_5%
R716
@
2
10K_0402_5%
1
2
1
<40> CMOS_OFF# IN
1
Q84
OUT
2
R436 DIS@ 0_0402_5% CMOS@
2
<24> VGA_ENBKL 1 2 ENBKL <40>
GND
PX@
<17> PCH_ENBKL R437 1 2 0_0402_5%
A A
3
2
R438
100K_0402_1%
LVDS/CAMERA
1
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D B 0.2
5 4 3 2 1
A B C D E
+5VS +5VS +5VS +5VS +5VS
3 3 3 3 3
1 BLUE 1 GREEN 1 RED 1 JVGA_HS 1 JVGA_VS
2 2 2 BAT54S-7-F_SOT23-3 2 2
@ @ @ @ @
D5 D6 D7 D8 D9
BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3
CRT Connector 1
2 1 1 2
1
DAC_RED 1 2 CRT_R RB491D_SC59-3
<17> DAC_RED
R439 PX@ 0_0402_5% 1.1A_6V_SMD1812P110TF C521

DAC_GRN 1 2 CRT_G 0.1U_0402_16V4Z
<17> DAC_GRN
R440 PX@ 0_0402_5% FCM1608CF-121T03 0603 W=40mils 2
<17> DAC_BLU DAC_BLU 1 2 CRT_B CRT_R 1 2 RED
R441 PX@ 0_0402_5% L30
FCM1608CF-1
CRT_G 1
21T03 0603
1
2 GREEN
L31
DIS only FCM1608CF-121T03 0603
BLUE
JCRT1
CRT_B 1 2 T67 PAD 6
L32 @ 11
1
VGA_CRT_R 1 2 CRT_R 1 1 1 RED 1
<24> VGA_CRT_R 1 1 1
VGA_CRT_ 1 2 CRT_G R445 R443 R446 C522 C523 C524 C525 C526 C527 CRT_DDC_DAT_CON 12
G CRT_B 2 2 2 2 2 2 N
1 2 8 G 16
2
<24> VGA_CRT_B
2
VGA_CRT_B
R447 DIS@ 0_0402_5% JVGA_HS 13 17

10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J10P_0402_50V8J BLUE G
3
CLOSE TO CONN 9
JVGA_VS 14
4
10
2 5 2
+CRT_VCC 1
R448 C528 CONTE_80431-5K1-152
1 2
1 100P_0402_50V8JME@
2
C529 1K_0402_5%
0.1U_0402_16V4Z
2
1
5
PX@ FCM1608CF-121T03 0603
OE#
R449 1 2 0_0402_5% HSYNC_G 2 4 CRT_HSYNC_1 1 2 JVGA_HS
<17> CRT_HSYNC A Y
DIS@
G U23
L33
Check CRT footprint 7/20_OTIS
R450 0_0402_5%
3
1 2 SN74AHCT1G125DCKR_SC70-5 1
<24> VGA_HSYNC
@
C530
10P_0402_50V8J
+CRT_VCC 2
R451
1 2
1
1K_0402_5%
C531
0.1U_0402_16V4Z
2
1
5
PX@ FCM1608CF-121T03 0603

P
OE#
R4521 2 0_0402_5% VSYNC_G CRT_VSYNC_1 JVGA_VS

<17> CRT_VSYNC 2 A Y 4 1 2
3 L34 3
DIS@
G
U24 1
3
R4531 2 0_0402_5% SN74AHCT1G125DCKR_SC70-5

<24> VGA_VSYNC
@ C532
10P_0402_50V8J
2
+3VS +3VGS
7/21 modify
2
R736 R735
+3VS 0_0402_5% 0_0402_5% +CRT_VCC
Pull high at chipset/VGA side PX@ DIS@
1
1
1
1
1
@ @
R454 R455
2.2K_0402_5% 2.2K_0402_5% R456 R457
5
2.2K_0402_5% 2.2K_0402_5%
2
CRT_DDC_DATA 2 PX@ 1 CRT_DDC_DATA_R 4 3 CRT_DDC_DAT_CONN

<17> CRT_DDC_DATA
VGA_DDCDATA R458 0_0402_5% 2N7002DW -T/R7_SOT363-6
2 DIS@ 1
2
<24> VGA_DDCDATA R459 0_0402_5% Q62B
<17> CRT_DDC_CLK CRT_DDC_CLK 2 PX@ 1 CRT_DDC_CLK_R 1 6 CRT_DDC_CLK_CONN
R460 0_0402_5% 1 1
4 <24> VGA_DDCCLK
VGA_DDCCLK 2 DIS@ 1 2N7002DW -T/R7_SOT363-6 @ 4
R461 0_0402_5% Q62A C533 C534
100P_0402_50V8J 68P_0402_50V8K
2 2
1 UMA only +CRT_VCC

+5VS
8/14 change P/N to D10
DMN66D0LDW-7_SOT363-6 Security Classification Compal Secret Compal Electronics,
F1
Inc.
Data
(SB00000DH00) Issued 2010/07/12 2012/07/11 Tiitlle

Deciphered
Date Date CRT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siize Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6751P
A B C D E
5 4 3 2 1
HDMI_CLK+_CONN 1 2 @ L35
R462 UMA_HDMI@ 680_0402_1% HDMI_CLK+_CK 1 HDMI_CLK+_CONN
2
R463 UMA_HDMI@ 680_0402_1% HDMI_CLK+_CK HDMI@ R464 1 2 0_0402_5% HDMI_CLK+_CONN
<17> HDMI_CLK+_CK
HDMI_TX0+_CONN 1 2 <17> HDMI_TX0+_CK HDMI_TX0+_CK HDMI@ R466 1 2 0_0402_5% HDMI_TX0+_CONN
R472 UMA_HDMI@ 680_0402_1% <17> HDMI_TX0-_CK HDMI_TX0-_CK HDMI@ R467 1 2 0_0402_5% HDMI_TX0-_CONN W CM-2012-900T_4P
HDMI_TX0-_CONN 1 2 HDMI_TX1+_CK HDMI@ R468 1 2 0_0402_5% HDMI_TX1+_CONN
<17> HDMI_TX1+_CK
R473 UMA_HDMI@ 680_0402_1% <17> HDMI_TX1-_CK HDMI_TX1-_CK HDMI@ R469 1 2 0_0402_5% HDMI_TX1-_CONN @ L36
D <17> HDMI_TX2+_CK HDMI_TX2+_CK HDMI@ R470 1 2 0_0402_5% HDMI_TX2+_CONN HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN D

HDMI_TX1+_CONN HDMI_TX2-_CK HDMI@ R471 1 0_0402_5% HDMI_TX2-_CONN 1 2
1 2 <17> HDMI_TX2-_CK 2
R474 UMA_HDMI@ 680_0402_1%
HDMI_TX1-_CONN 1 2 HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN
4 3
2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_CLK+_CK
C537 1
R475 UMA_HDMI@ 680_0402_1% C535
<24> VGA_HDMI_CLK+ C538 11 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0+_CK
C539 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX0-_CK
C540 1 2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1+_CK
2 DIS_HDMI@ 0.1U_0402_16V7K HDMI_TX1-_CK
HDMI_TX2+_CONN 1 2 <24> VGA_HDMI_TX0+
R476 UMA_HDMI@ 680_0402_1% @ L37
<24> VGA_HDMI_TX0- HDMI_TX1+_CK 1
HDMI_TX2-_CONN 1 2 2 HDMI_TX1+_CONN
UMA_HDMI@ <24> VGA_HDMI_TX1+ 1 2
R477 680_0402_1%
D <24> VGA_HDMI_TX2+
1
2 +3VS
Q95 G W CM-2012-900T_4P
S Change footprint
3 20100814 @ L38
+3VS +3VGS HDMI_TX2+_CK 1 2 HDMI_TX2+_CONN
1 2
2
8/6 Modify HDMI_TX2-_CK HDMI_TX2-_CONN
4 4 3 3
R738 R739 W CM-2012-900T_4P

0_0402_5% 0_0402_5%
UMA_HDMI@ DIS_HDMI@
1
C +5VS +5VS
Pull up R for PCH OR VGA SIDE C
2
HDMI@ 3 3
5
<17> HDMICLK_NB R478 1 2 0_0402_5% 1 6 HDMICLK_R 1 HDMIDAT_R 1 HDMICLK_R
UMA_HDMI@
R479 1 2 0_0402_5% HDMI@ 2N7002DW -T/R7_SOT363-6 2 @ 2 @
<24> VGA_HDMI_SCL DIS_HDMI@ Q63A D11 D12
<17> HDMIDAT_NB R480 1 2 0_0402_5% 4 3 HDMIDAT_R BAT54S-7-F_SOT23-3 BAT54S-7-F_SOT23-3

UMA_HDMI@
R481 1 2 0_0402_5% Q63B 2N7002DW -T/R7_SOT363-6
<24> VGA_HDMI_SDA DIS_HDMI@
RB491D_SC59-3 D13 F2
2 1 +5VS_HDMI_F 1 2
+5VS
8/14 change P/N to
1.1A_6V_SMD1812P110TF
DMN66D0LDW-7_SOT363-6 HDMI@ HDMI@
(SB00000DH00)
R482 9/27 add F2 for safty
0_0805_5%
@
+5VS_HDMI
2
+3VS
1 C543
+5VS 0.1U_0402_16V4Z
2
B HDMI@ B
2
R485 R483 R484
1
1M_0402_5% 2.2K_0402_5% 2.2K_0402_5%
UMA_HDMI@ 1 HDMI@ HDMI@
2
G
1
TMDS_B_HPD# R486 1 0_0402_5% @

S
<17> TMDS_B_HPD# 3 1 2
UMA_HDMI@ D14
Change footprint BAT54S-7-F_SOT23-3 JHDMI1
HP_DET
2
+5V
DDC/CEC_GND
SDA
SCL
2
Reserved
CEC
1
A
20
1
HDMI_CLK+_CONN
CK- Q28 DIS_HDMI@
G1 21
MMBT3904_G_SOT23-3
CK_s
22
hield
3
G2
CK+
1
23
D G3
1
D0-
DIS_HDMI@ G4
D0_s
hield
2
3
D
+5VS 0
+
D
1
-
D
1
_
s
h
i
e
l
d
D
1
+
D
2
-
D
2
_
s
h
i
e
l
d
D2+
A
SUYIN_100042GR019M23DZL
Change footprint
20100814
1
R874
100K_0402_5%
DIS_HDMI@ Security Classification Compal Secret Data Compal Electronics,Ltd.
2010/07/12 2012/07/11 Tiitlle
Issued Date
2
DIS_HD4M9I9@
_0402_1% Deciphered Date
HDMI CONN
NEAR CONNECT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Siize Document Number
Custom
Rev
0.2
LA-6751P

5 4 3 2 1
2N7002H_SOT23-3 20100814 HDMI_DET 19

Q93 18
UMA_HDMI@ 17
R696 +3VS HDMIDAT_R 16
0_0402_5% HDMICLK_R 15
@ 14
R697 DIS_HDMI@ 13
150K_0402_5% R488 HDMI_CLK-_CONN 12
2 1 2 100K_0402_5% 11
B HDMI_CLK+_CONN 10
E HDMI@ HDMI_TX0-_CONN 9
<24> HDMI_DETECT_VGA 8
1 2 HDMI_TX0+_CONN 7
R489 DIS_HD4M
9I9@
_0402_1% HDMI_TX1-_CONN 6
HDMI_CLK-_CONN 1 2 R698 DIS_HDMI@ 5
R490 DIS_HD4M
9I9@
_0402_1% 10K_0402_5% HDMI_TX1+_CONN 4
HDMI_TX0+_CONN 1 2 HDMI_TX2-_CONN 3
R491 DIS_HD4M
9I9@
_0402_1% Q94 2
HDMI_TX0-_CONN 1 2 2N7002H_SOT23-3 HDMI_TX2+_CONN 1
R492 DIS_HD4M
9I9@
_0402_1% 2
HDMI_TX1+_CONN 1 2 G
R493 DIS_HD4M
9I9@
_0402_1% S
HDMI_TX1-_CONN 1 2
R494 DIS_HD4M
9I9@
_0402_1%
HDMI_TX2+_CONN 1 2
R495 DIS_HD4M
9I9@
_0402_1%
HDMI_TX2-_CONN 1 2
R496
A B C D E
Mini-Express Card for

WLAN/WiMAX(Half)
1 1
+1.5VS
1
+3VALW +1.5VS_CONN
+3VS +3VS_WLAN
@
J6
1 0.1U_0402_16V4Z
1 1
Mini-Express Card(WLAN/WiMAX)
@
J7 @2 @2
2
11 2 2
C544 C545 C546
@
JUMP_43X79
0.1U_0402_16V4Z 0.1U_0402_16V4Z
2
JUMP_43X79 2
JWLN1
PCIE_WAKE# R514 1 2 0_0402_5% 1 2
<16,35> PCIE_WAKE# BT_ACTIVE WAKE# 3.3V
<42> BT_ACTIVE R497 1 2 @ 0_0402_5% 3 4
NC GND +1.5VS_CONN
5 NC 1.5V 6
W LAN_CLKREQ1# 7 8 LPC_FRAME#_R
<15> WLAN_CLKREQ1# CLKREQ# NC LPC_AD3_R
9 GND NC 10
11 12 LPC_AD2_R
<15> CLK_PCIE_W LAN1# REFCLK- NC LPC_AD1_R
<15> CLK_PCIE_W LAN1 13 14
REFCLK+ NC LPC_AD0_R
15 16
PCI_RST#_R GND NC
17 NC GND 18
CLK_PCI_DB 19 20 R498 1 2 0_0402_5% WL_OFF# <18>
2 NC NC 2
21 GND PERST# 22 BUF_PLT_RST# <18,35,40>
23 24 R499 1 2 @ 0_0402_5%
<15> PCIE_PRX_DTX_N2 PERn0 +3.3Vaux R500 1 0_0402_5% +3VALW
<15> PCIE_PRX_DTX_P2 25 PERp0 GND 26 2 +3VS
27 GND +1.5V 28
29 30 R501 1 2 @ 0_0402_5%
GND SMB_CLK R502 1 SMB_CLK_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_N2 31 PETn0 SMB_DATA 32 2 @ 0_0402_5% SMB_DATA_S3 <12,13,15>
<15> PCIE_PTX_C_DRX_P2 33 PETp0 GND 34
35 GND USB_D- 36 USB20_N9 <18>
+3VS_W LAN 37 38
NC USB_D+ USB20_P9 <18>
39 NC GND 40
41 42 0_0402_5% 2 @ 1 R503
NC LED_WWAN# 0_0402_5% W LAN_LED#
43 44 2 1 R504 WLAN_LED# <56,57>
100_0402_1% NC LED_WLAN# @
45 46
R505 NC LED_WPAN#
47 NC +1.5V 48
<40,41> EC_TX_P80_DATA EC_TX_P80_DATA 1 2 49 50
EC_RX_P80_CLK NC GND
<40,41> EC_RX_P80_CLK 1 2 51 NC +3.3V 52
R506
100_0402_1% 53 54
GND GND
2
TAITW_PFPET0-AFGLBG1ZZ4N0
For EC to detect ME@
R507
debug card insert. 100K_0402_5%
3 3
Reserve for SW mini-pcie debug card.

Series resistors closed to KBC side.
LPC_FRAME#_R R508 1 @ 2 0_0402_5% LPC_FRAME#
LPC_FRAME# <14,40>
LPC_AD3_R R509 1 @ 2 0_0402_5% LPC_AD3
LPC_AD3 <14,40>
LPC_AD2_R R510 1 @ 2 0_0402_5% LPC_AD2
LPC_AD2 <14,40>
LPC_AD1_R R511 1 @ 2 0_0402_5% LPC_AD1 LPC_AD1 <14,40>
LPC_AD0_R R512 1 @ 2 0_0402_5% LPC_AD0
PCI_RST#_R R513 @ 0_0402_5% LPC_AD0 <14,40>BUF_PLT_RST#
1 2
CLK_PCI_DB
4 CLK_PCI_DB <15> 4
2010/07/12
Compal Secret Data
2012/07/11
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
Mini-Card/NEW Card/SIM
Size Document Number Rev
CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE 0.2
A B MAY BE USED BY OR DISCLOSED TO ANY THIRDC PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
D INC. E
5 4 3 2 1
Power On
Pin strapping Description Chip
+3VALW +3V_LAN +1.7_VDDCT +1.7_LX H:Over Clock Enable Default
Close together LED0 H
L:Over Clock Disable *
H:SWR Switch mode regulator
1000P_0402_50V7K
chip as possible.
10U_0805_10V4Z
0.1U_0402_16V4Z
J8
+1.7_VDDCT 2 +1.7_LX
1 LED2 --
C548
@ C549
C547
4.7UH_SIA4012-4R7M_20%
1 1 2 2 Select *
1 1
AR8151 Pin23=LED2.
@
JUMP_43X79
Note: Place Close to LAN
D
chip AR8152, Pin23 is CLKREQ D
2 2 L39 DCR< 0.15

ohm
Atheros request can't disable LAN power Rate current >
1A
Close to
Pin40
U26 8152@
C C
S IC AR8152-AL1E QFN 40P E-LAN CTRL
no overclocking
PD 5.1K
Place Close to Chip U26 LED0,1,2 intel Pull UP 1 2 0402_1%
C5531 20.1U_0402_16V7K PCIE_PRX_C_DTX_N129 38 ACTIVITY

R515 5.1K_0402_5%
Place Close 402_1%
to
2 LAN1 chip
<15> PCIE_PRX_DTX_N1 TX_N LED_0 ACTIVITY <36>
C5521 20.1U_0402_16V7K PCIE_PRX_C_DTX_P130
Atheros LED_1 39
23
LAN_LINK#
1 8152@ 2
LAN_LINK# <36>
CLKREQ_LAN# MDI0+ R526 1
49.9_0402_1%
2
2
402_1%
1@
1@ 2 C574 1000P_0402_50V7K
<15> PCIE_PRX_DTX_P1 TX_P LED_2
8151-AL1A R516 0_0402_5% 49.9_ 2
MDI0- 1
<15> PCIE_PTX_C_DRX_N1 36 R527 1 402_1% 2 C575 0.1U_0402_16V4Z
RX_N 12 MDI0- 49.9_0
TRXN0 MDI0+ MDI0- <36> MDI1+ R528 1 2 1@
<15> PCIE_PTX_C_DRX_P1 35 RX_P TRXP0 11 MDI0+ <36> 2 C576 1000P_0402_50V7K
15 MDI1- 49.9_0402_1%
TRXN1 MDI1- <36> 2
<15> CLK_PCIE_LAN# 2R517 0_10402_5% CLK_PCIE_LAN#_C32
REFCLK_N TRXP1 14 MDI1+
MDI1+ <36>
MDI1- R529 1 1 2 C577 0.1U_0402_16V4Z
4> PCIE_W AKE#
<15> CLK_PCIE_LAN 2R518 0_10402_5% CLK_PCIE_LAN_C 33 18 MDI2-
MDI2- <36>
49.9_0 0402_1%
1R5 REFCLK_P TRXN2 MDI2+ MDI2+
0> LAN_W AKE# 17 R530 1 2 1@ 2 C580 1000P_0402_50V7K
TRXP2 MDI2+ <36>
<18,34,40> BUF_PLT_RST# BUF_PLT_RST# 2 PERST# TRXN3 21 MDI3- MDI3- <36> GIGA@49.9_0 0402_1%
TRXP3 20 MDI3+ MDI3+ <36> MDI2- R531 1 2 1 2 C581 0.1U_0402_16V4Z
<16,3 1R519 @ 0_20402_5% PCIE_W AKE#_R 3 W AKE# GIGA@ 49.9_ GIGA@
21 0_20402_5% Close Pin 10
MDI3+ R532 1 2 C582 1000P_0402_50V7K
C554
C555
C557
@ C558
<4
10U_0805_10V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
10U_0805_10V4Z
25 10 LAN_RBIAS 1 2 +3V_LAN GIGA@ 49.9_
SMCLK RBIAS
26 SMDATA R522 2.37K_0402_1% C554 & C555 Close pin1 < 200mil MDI3- R533 1 2
C583 0.1U_0402_16V4Z
+3V_LAN
C557 & C558 Close2 pin
2 < 400mil
2 2 GIGA@ GIGA@
28 1
TEST_RST VDD33
27 TESTMODE 1 1 1 1 Note 1 : 8152 no mount MDI3+, MDI3-, MDI2-, MDI2+
+1.7_LX
resister and
40 +1.7_LX
cap
LAN_XTALO LX
1 2 8152@ 7 XTLO
B C559 0.1U_0402_16V4Z LAN_XTALI 8 XTLI Note 2 : C574, C576, C580, C582, reserved for EMI. B
5 +1.7_VDDCT
VDDCT +1.7_VDDCT
R525 GIGA@ 1 2C561
CLKREQ_LAN# 1 2 CLKREQ_LAN#_R 4 0.1U_0402_16V4Z
<15> CLKREQ_LAN# CLKREQ#
0_0402_5% 24 +1.1_DVDDL
DVDDL 37 +1.1_DVDDL
C566
C567
C568
C569
C564
C565
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.1_AVDDL DVDDL_REG
13
C570
GIGA@ C573
C562
C560
C571
C572
C563
AVDDL
1U_0402_6.3V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.1_AVDDL 19
+1.1_AVDDL AVDDL +2.7_AVDDH
31 AVDDL AVDDH 16
+1.1_AVDDL +2.7_AVDDH
2 2
GIGA@
GIGA@
6 9
AVDDL_REG AVDDH_REG 2 2 2 2
1 1 1 1 1 1
41 1 1 1 1 1 1 2
GND
AR8151-AL1A_QFN40_5X5
2 2 2 2 GIGA@
LAN_XTALI 2 2 1
27P_0402_50V8J
27P_0402_50V8J
LAN_XTALO
C578
C579
Y4
1 2
Near Near Near Near Near 25MHZ_20PF_7A25000012
Near Near Near Near Near
Pin13 Pin19 Pin31 Pin34 Pin6 Pin9 Pin22 Pin16 Pin37 Pin24
1 1
2 2
A A
Configure Configur
e
Pin4 R525 C559 Pin23
R516 Security Classification Compal Secret Data Compal Electronics, Inc.
AR8152 VDDCT_REG * CLKREQn * Issued Date 2010/07/12 Deciphered Date 2012/07/11 Tiitlle
LAN-AR8151/8152
AR8151 CLKREQn * LED[2] AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D
Siize
Custom
Document Number
LA-6751P
Rev
0.1
Date: Frii day, November 26, 2010 Sheet 35 of 59
5 4 3 2 1
5 4 3 2 1
8/23 Change T1,T2 P/N to SP050006E00
+1.7_VDDCT T1
D D
2
C435 GIGA@ MDI3+ 1 MDO3+
<35> MDI3+ TD+ TX+ 16
R304 0.1U_0402_16V4Z MDI3- 2 MDO3-
<35> MDI3- TD- TX- 15 MCT3
2 1 3 14 2 R534 1 GIGA@
1 CT CT
0_0603_5% 4 13
75_0402_5% NC NC
1 5 NC 12
NC 11
@ C427 1 6 MCT2 2 R535 1 GIGA@
CT CT
MDI2+ 7 MDO2+ 75_0402_5%
C436 GIGA@
<35> MDI2+
MDI2- RD+ RX+ 10 MDO2-
<35> MDI2- 8 RD- RX- 9
1U_0402_6.3V4Z 2 0.1U_0402_16V4Z
2
BOTHHAND_NS0013LF
GIGA@
6/23 update
1 2
T2 C585
2 1000P_1206_2KV7K
Place Close to T2 C438 <35> MDI0+ MDI0+ 1
TD+ TX+
16 MDO0+
0.1U_0402_16V4Z MDI0- 2 15 MDO0-
<35> MDI0- TD- TX- MCT0
3 14 2 R536 1
1 CT CT
4 13
75_0402_5% MDI1- NC NC
NC 5NC 12
C 6 MCT1 2 R537 C
1
MDI1+ 7 CT CT 11 MDO1+ 75_0402_5%
1
MDI1+ C440 <35> MDI1+ MDI1- 8 RD+ RX+ 109 MDO1-
<35> MDI1- RD- RX- 1 1
D31 0.1U_0402_16V4Z
2 C643 C644
TCLAMP3302N.TCT_SLP2626P10-10 BOTHHAND_NS0013LF 22U_1206_10V7K 22U_1206_10V7K
2 2
10
6
7
8
9
@ @
6
7
8
9
10
11 R02
GND
Reserve gas tube for EMI go rural solution
20101006
5
4
3
2
1
JRJ2
LAN_LINK#
5
4
3
2
1
<35> LAN_LINK# 12 Green LED-

1 220_0402_5%
@ +3V_LAN 2 1 11
Green LED+
MDI0- C378 R699 16
MDO3- 8 SHLD2
470P_0402_50V7K2 PR4-
MDI0+ 15
MDO3+ SHLD1
7 PR4+
@ MDO1- 6 PR2-
Reserve D1 for EMI go rural solution MDO2- 5 PR3-
B
20101006 B
MDO2+ 4
PR3+
MDO1+ 3 PR2+
MDO0- 2 PR1- 14
MDO0+ SHLD2
1 PR1+
SHLD1 13
10 Yellow LED-
ACTIVITY R538 2 1 220_0402_5% 9
<35> ACTIVITY Yellow LED+
1 LIYO_101007-08203-033
@
C379 ME@
470P_0402_50V7K
2
A A

LAN_Transformer
LA-6751P
2 INC. 1
5 4 3 2 1
D D
+3VS REMOTE1+ Close to DDR

Close U20 SMSC thermal sensor C
1
1
1
@
1
REMOTE1+
+3VS placed near by VRAM R540
C586
100P_0402_50V8J
2
2
B
Q97
MMST3904-7-F_SOT323-3
E
2
10K_0402_5%
3
C587 @ REMOTE1-
2200P_0402_50V7K U27
2 REMOTE1-
1 10 EC_SMB_CK2
VDD SMCLK EC_SMB_CK2 <15,24,40>
REMOTE2+ 2
REMOTE1+ 2 DP1 SMDATA 9 EC_SMB_DA2
EC_SMB_DA2 <15,24,40>
REMOTE2+
Under WWAN
1 REMOTE1- 3 8 1
DN1 ALERT#
1
C590 @ C @
DP2 THERM# 7
DN2 GND 6
C588 @ 0.1U_0402_16V4Z REMOTE2+ 4 C589 2 Q98
2200P_0402_50V7K 1 100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 REMOTE2- REMOTE2- 5 2 E
3
REMOTE2-
EMC1403-2-AIZL-TR_MSOP10
REMOTE1,2+/-:
C Address 1001_101xb Trace width/space:10/10 mil C
10/5 change P/N to SA000046C00 Trace length:<8"
B B
FAN1 Conn
+5VS
JFAN1
1 1
<40> EC_TACH 2 2
<40> EC_FAN_PW M 3 3
4 4
2 5
6 G5
G6
C591
10U_0805_10V4Z ACES_85205-04001
1 ME@
A A
EMC1403_Thermal sensor/FAN
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6751P
5 4 3 2 1
A B C D E F G H
Left USB Conn.

+USB_VCCB
W=80mils JUSB1
1
USB20_N1 1 @ 2 USB20_N1_C 2 VCC
1 <18> USB20_N1 D-
C592 R661 0_0402_5% 4 GND
220U_6.3V_M C593 8/27 change to @
470P_0402_50V7K 5
3
2 2 GND1
PJDLC05_SOT23-3
D16 6 GND2
7 GND3
USB20_N1 W CM-2012-900T_4 P USB20_N1_C 8
1 4 3 GND4 1
9/27 change C592 to 4 3
SUYIN_020173GR004M58BZL
C
4.2H SF000002Y00 USB20_P1 USB20_P1_
1 2 ME@
L65
8/271 change 2 to
1
stuff
+5VALW +USB_VCCB
E-SATA
COMBO
U29
RIGHT USB
1 8
PORT
GND OUT
C594 0.1U_0402_16V4Z 2 IN OUT 7
2 1 3 IN OUT 6
USB_ON# 4 5 USB_OC0#
<40,42,56,57> USB_ON# EN OC# USB_OC0# <18,56,57>
APL3510BKI_SO8
Low Active
1
C595
@ 1000P_0402_50V7K
2
SATA HDD Conn.

2 2
JHDD1
1 GND
SATA_ITX_DRX_P0 2
<14> SATA_ITX_DRX_P0 SATA_ITX_DRX_N0 RX+
<14> SATA_ITX_DRX_N0 3 RX-
4 GND
SATA_DTX_C_IRX_N0 C596 1 2 0.01U_0402_16V7K SATA_DTX_IRX_N0 5
<14> SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_P0 SATA_DTX_IRX_P0 TX-
<14> SATA_DTX_C_IRX_P0 C597 1 2 0.01U_0402_16V7K 6 TX+
7 GND
83.3V
+3VS 93.3V
103.3V
11GND
12GND
13GND
145V
+5VS 155V
165V
17GND
18Reserved
19GND
+5VS +3VS 20 23
12V GND
2112V GND 24
2212V
1 1 1 1 1 1
@ SUYIN_127043FB022G278ZR
C598 C599 C600 C601 C602 C603
1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0603_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2
@ @
3 3
ODD Power Control

@ J9
1 2
1 2
+5VS JUMP_43X79 +5V_ODD
3 1
1
Change footprint Q99
20100814 C604
R552 AP2301GN-HF_SOT23-3 0.1U_0402_16V4Z
1
10K_0402_5% 2
C607
0.01U_0402_16V7K 1
1 R675 2 1 2
2
100K_0402_5% C608
10U_0805_10V4Z
2
2
1
2
OUT
<19> ODD_EN IN
Q100
4
3GND 4

HDD/ODD Connector
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D B 0.2
A B C D E F G H
5 4 3 2 1
CX20671
High Definition Audio Codec SoC
EMI
HDA_RST_AUDIO#
With Integrated Class-D Stereo
HDA_SYNC_AUDIO
Amplifier.
An integrated 5 V to 3.3 V Low-dropout HDA_SDOUT_AUDIO_
voltage regulator (LDO). 1 2 HDA_BITCLK_AUDIO
33_0402_5% R556
An integrated 3.3 V to 1.8V Low-dropout @
voltage regulator (LDO). 9/27 Update U30 P/N to 1 1 1 1
22P_0402_50V8J
SA00003K410
C61
1
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
C60
C61
C61
9
2
0
2 2 2 2
D D
@ @ @ @
+3VS
10U_0805_10V4Z
0..1U_0402_16V4Z
0..1U_0402_16V4Z
1 1 1
C614
C615
C613
+LDO_OUT_3.3V
2 1 +VAUX_3.3
+3VS 2 2 2
0_0402_5% R557
1U_0603_10V4Z
10U_0805_10V4Z
0..1U_0402_16V4Z
0..1U_0402_16V4Z
2 @ 1 @ 1 1 1 1 AVDD_3.3 pinis output of
10U_0805_10V4Z
0..1U_0402_16V4Z
+3VALW
C621
R558
C619
C620
0_0402_5% 1 1
C618
internal LDO. NOT connect
C617
C616
6/24 change +3VS To support W ake-on-Jack or W ake-on-Ring, the CODEC 2 2 2 2
to external supply.
VAUX_3.3 & VDD_IO pins must be powerd by a rail that 2 2
is not removed unless AC power is removed.
*DSH page42 has more detail.
9/28 Change to R879 for 21Z

2 1 +CLASSD_5VS
+3VS
C626
0_0402_5% R560 1 R879 2
2 @ 1 0_0805_5%
+3VALW +5VS
1U_0603_10V4Z
0..1U_0402_16V4Z
0_0402_5% R561
0..1U_0402_16V4Z
0..1U_0402_16V4Z
1 1 10K only needed if supply to VAUX_3.3
1 R562 2 @
C622
C623
is removed during system re-start.
C627
C628
+5VS
10U_0805_10V4Z
0..1U_0402_16V4Z
1 1
C625
C624
10U_0805_10V4Z
10U_0805_10V4Z
C629
0..1_1206_1%
2 2 2 2 1 1 1 1
Layout Note:Path from +5VS to LPW R_5.0
10U_0805_10V4Z
1
0..1U_0402_16V4Z
10K_0402_5%
1 1 RPW R_5.0 must be very low

C631
C630
R563 2 2 2 2 resistance (<0.01 ohms)
27
28
26
HDA_RST_AUDIO#
<14> HDA_RST_AUDIO#
0..1U_0402_16V4Z
C 2 2
C
18
29
1
2
HDA_BITCLK_AUDIO
3
7
2
C632
<14> HDA_BITCLK_AUDIO U30
FILT_1.8
VAUX_3.3
DVDD_3.3
VDD_IO
FILT_1.65
AVDD_3.3
AVDD_5V
AVDD_HP
Please bypass caps very close to device.
2
<14> HDA_SYNC_AUDIO
HDA_SYNC_AUDIO 8/10 update LPW R_5.0
12
RPW R_5.0 15
+3VS 9 17
2
G
RESET# CLASS-D_REF
R564 1 2 5..11K_0402_1% +VAUX_3.3
0_0402_5% 2 R578 1 HDA_BITCLK_AUDIO_R 5 BIT_CLK Sense resistors must be
R565 1 2 10K_0402_1% MIC_JD <43> Port C connected same power
S
8 36 R567 39..2K_0402_1%
SENSE_A
R566 33_0402_5% SYNC
<14> HDA_SDIN0 1 2 6
SDATA_IN PLUG_IN <43> Port A that is used for VAUX_3.3
HDA_SDOUT_AUDIO 1 3 HDA_SDOUT_AUDIO_R 4 1 2
<14> HDA_SDOUT_AUDIO Change footprint SDATA_OUT
35 MIC_INR
D
20100814 PORTB_R MIC_INL

PORTB_L 34 Internal MIC
2N7002H_SOT23-3 33
B_BIAS +MICBIASB
Q9 PC_BEEP 10 R568 2..2K_0402_5% +MICBIASC
PC_BEEP R569 2..2K_0402_5%
1R669 @ 2 32
C_BIAS +MICBIASC
PORTC_R 31 C633 1 2 2..2U_0603_6..3V4Z R570 100_0402_1%
EXT_MIC_R <43>
2 2..2U_0603_6..3V4Z
R571
0_0402_5% 30 C634 1
0_0402_5% PORTC_L 100_0402_1% EXT_MIC_L <43> External MIC
1 2 R572 38
<40> EAPD EC_MUTE# GPIO0/EAPD#
2 1 37
<40> EC_MUTE# GPIO1/SPK_MUTE# R575 15_0402_5%
0_0402_5% R573 23 HP_OUTR_R 1 2
PORTA_R HP_OUTR <43>
22 HP_OUTL_R R574 1 2 15_0402_5% Headphone

PORTA_L HP_OUTL <43>
40
DMIC_CLK 24 Changed from 5.1ohm to 15ohm
1 NC
DMIC_1/2
NC 25 for "zi zi"noise.

39
NC
SPK_L2+ 11
LEFT+
SPK_L1- 13
EAPD active low LEFT- 21
Internal SPEAKER AVEE
0=power down ex AMP FLY_P 19
C637 @ 20
SPK_R2+ 16
1 2 1=power up ex AMP 1 2
10U_0805_10V4Z
0..1U_0402_16V4Z
C639
C641
GND
0.. 1U_0402_16V4Z SPK_R1- RIGHT+ FLY_N

14 C638 1U_0603_10V4Z 1 1
1
RIGHT- 2 2
C640 @ +3VS
1 2
B B
0.. 1U_0402_16V4Z CX20671-21Z_QFN40_6X6
41
R576 @ R351
1 2 @ 4..7K_0402_5%
0_0402_5% +MICBIASB
R577 @
2
1 2
1
0_0402_5%
2
1
R579 @
HDA_RST_AUDIO#
R580
4..7K
1 _040
C584 2_5
@ %
2
100P_0402_50V8J MIIC1 C642
2
1 2 MIC_INR
1 2..2U_0603_
6..3V4Z
2 GNDA
GND GNDA MIC_INL
WM-64PCY_2P
8/10 update 45@
8/10 update for vendor suggestion
R720
0_0402_5%
R598
2 1 @
wide 20MIL
FBMA-L11-160808-121LMA30T
R721
EC Beep <40> BEEP# 2 1
D17 RB751V_SOD323 JSPK1

R582 SPK_R1- R720 2 @ 1 0_0603_5% SPK_R1-_CONN 1
1 1
ICH Beep <14> HDA_SPKR 2 1PC_BEEP1 1 2 1 2 PC_BEEP SPK_R2+ R721 2 @ 1 0_0603_5% SPK_R2+_CONN 2
2
33_0402_5% C645 0..1U_0402_16V4Z FBMA-L11-160808-121LMA30T SPK_L1- R722 2 @ 1 0_0603_5% SPK_L1-_CONN 3
SPK_L2+ @ SPK_L2+_CONN 3
D30 RB751V_SOD323 R723 2 1 0_0603_5% 4 4
R722
5
GND1
6
PC Beep R585 GND2
1000P_0402_50V7K
A
A 10K_0402_5% 1 1 1 1
C649
2
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
C650
C647
C651
ACES_88231-04001
ME@
FBMA-L11-160808-121LMA30T 8/24 update 2 2 2 2
R723
10/08 update
FBMA-L11-160808-121LMA30T
Securiity Cllassiifiicatiion Compal Secret Data Compal
Electronics,Ltd.
2010/07/12 2012/07/11 Tiitl e
CX20671 Codec
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D Sii ze Documentt Number Rev
C 0..1
LA-6751P
5 4 2 1
3
+3VALW
Vcc 3.3V +/- 5%
+EC_AVCC
1 1 1 1 1 1 R694 100K +/- 5%
0.1U_0402_16V4Z
C653
0.1U_0402_16V4Z
C654
0.1U_0402_16V4Z
C662
0.1U_0402_16V4Z
C655
1000P_0402_50V7K
C657
1000P_0402_50V7K
C658
L44 1 2
+3VALW +EC_AVCC
FBM-11-160808-601-T_0603 2 1
Board ID R695 V min V V max
0.1U_0402_1
C656
C659 2 2 2 2 2 2 0 0 0 V 0 V 0 V MP
111
125
22
33
96
67
1 ECAGND 2
1 8.2K +/- 0.216 V 0.250 V 0.289 V PVT
9
1 2 U31
L45 FBM-11-160808-601-T_0603
5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
2 18K +/- 5% 0.436 V 0.503 V 0.538 V DVT
Change to 0 ohm P/N
CPU1.5V_S3_GATE
3 33K +/- 5% 0.712 V 0.819 V 0.875 V EVT
1 21 CPU1.5V_S3_GATE <10>
<19> GATEA20 KB_RST# GA20/GPIO00 INVT_PW M/PW M1/GPIO0F BEEP#
<19> KB_RST# 2 KBRST#/GPIO01 BEEP#/PW M2/GPIO10 23 BEEP# <39>
3 26 PCH_DPW ROK
<14> SERIRQ SERIRQ# FANPW M1/GPIO12 ACOFF PCH_DPW ROK <16>
<14,34> LPC_FRAME# 4 LFRAME# ACOFF/FANPW M2/GPIO13 27 ACOFF <45,47>
LPC_AD3 5
<14,34> LPC_AD3 LAD3
LPC_AD2 7 PWM Output
2
<14,34> LPC_AD2 LPC_AD1 LAD2 BATT_TEMP
8 63
1
<14,34> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <46>
LAD0 LPC & MISC
LPC_AD0 10 64
2 1 2 1 <14,34> LPC_AD0 BATT_OVP/AD1/GPIO39 65
ADP_I/AD2/GPIO3A ADP_I <46,47>
@ C660 22P_0402_50V8J @ R589 10_0402_5% <18> CLK_PCI_LPC 12
13 PCICLK AD Input AD3/GPIO3B 66
75 BRDID IMVP_IMON <53>
<18,34,35> BUF_PLT_RST# PCIRST#/GPIO05 AD4/GPIO42
1
1 2 EC_RST# 37 76 EC_FAN_PW M
+3VALW ECRST# SELIO2#/AD5/GPIO43
2
R590 47K_0402_5% EC_SCI# 20
2
<19> EC_SCI# BATT_LEN# SCI#/GPIO0E
2 <46> BATT_LEN# 38 CLKRUN#/GPIO1D 68
DAC_BRIG/DA0/GPIO3C CHG_ON#
C661 EN_DFAN1/DA1/GPIO3D 70 CHG_ON# +5VALW
0.1U_0402_16V4Z
1 11/16 Modify DA Output IREF/DA2/GPIO3E 71 IREF IREF <47>
KSI0 55 KSI0/GPIO30 DA3/GPIO3F 72 CHGVADJ <47> +3VALW
KSI1
1
56 KSI1/GPIO31
KSI2 57 EC_MUTE# R593 1 2 10K_0402_5%
KSI2/GPIO32
<56,57> KSO[0..15]
KSO[0..15]
<56,57> KSI3
KSI3 58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <39> 6/19
<56,57> KSI4 KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 USB_ON# USB_ON# <38,42,56,57> USB_ON# R594 1 2 10K_0402_5%
KSI[0..7] KSI5 60 85
<56,57> KSI[0..7] KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 CMOS_OFF# <31>
KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK TP_CLK <56,57> TP_CLK R591 1 2 4.7K_0402_5%
+3VALW KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <56,57>
R595 1 2 47K_0402_5% KSO1 KSO1 40 7/23 Modify
TP_DATA R592 1 2 4.7K_0402_5% KSO1/GPIO21
KSO2 41
R597 1 2 47K_0402_5% KSO2 KSO3 42 KSO2/GPIO22 97
KSO3/GPIO23 SDICS#/GPXOA00 SYS_PW
@ ROK_EC <16>
KSO4 43 98 CE_EN_EC 2 1 CE_EN <31>
KSO4/GPIO24 SDICLK/GPXOA01
ENE UPDATE 08/10/21 KSO5
KSO6
44
45
KSO5/GPIO25 Int. K/B SDIDO/GPXOA02
99
109 LID_SW #
0_0402_5% R746
ME_FLASH <14>
+3VALW BATT_TEMP
C663
1 2
100P_0402_50V8J
KSO6/GPIO26 Matrix SDIDI/GPXID0 LID_SW # <56,57>
KSO7 46
KSO7/GPIO27
SPI Device Interface FRD#SPI_SO 2 1 ACIN 1 2
+3VS +3VALW KSO8 47 100K_0402_1%@ R599 C664 100P_0402_50V8J
KSO9 KSO8/GPIO28 FRD#SPI_SO
48 KSO9/GPIO29 SPIDI/RD# 119 FRD#SPI_SO <41>
R600 EC_SMB_CK1 KSO10 49 KSO10/GPIO2A FW R#SPI_SI FSEL#SPICS#
KSO11 SPIDO/W R# 120 SPI_CLK
FW R#SPI_SI <41> 2 1
2.2K_0402_5% 50 KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK <41> 100K_0402_1%@ R603
KSO12 51 KSO12/GPIO2C 128 FSEL#SPICS#
EC_SMB_DA1 KSO13 SPICS# FSEL#SPICS# <41>
R601 R602 R604 52 KSO13/GPIO2D
2.2K_0402_5% KSO14 R737
54 73
KSO15/GPIO2F CIR_RX/GPIO40
KSO16 81 74 H_PECI_R R665 1 2 43_0402_1% VR_HOT# 2 1 H_PROCHOT#
<57> KSO16 KSO16/GPIO48 CIR_RLC_TX/GPIO41 H_PECI <6,19> <46,53> VR_HOT#
EC_SMB_CK2 KSO17
90
BATT_CHGI_LED#/GPIO52 CHARGE_LED0# <56,57> D
CAPS_LED# CAPS_LED# <43>
1
EC_SMB_CK1 CAPS_LED#/GPIO53 H_PROCHOT#_EC
@ @
<46> EC_SMB_CK1 77 SCL1/GPIO44 GPIO BATT_LOW _LED#/GPIO54 92 PW R_LED# <43,56,57> 2 Q37
C665 C666 EC_SMB_DA1 CHARGE_LED1# G 2N7002H_SOT23-3
<46> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 CHARGE_LED1# <56,57>
100P_0402_50V8J 100P_0402_50V8J EC_SMB_CK2 79 SM Bus 95 SYSON S Change footprint
2 2 <15,24,37> EC_SMB_CK2 EC_SMB_DA2 SCL2/GPIO46 SYSON/GPIO56 SYSON <44,49> 20100814
80 121
3
<15,24,37> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 ACIN VR_ON <53>
127 ACIN <16,24,47>
AC_IN/GPIO59
0_0402_5% R747
<16> SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <16> 2 1
+3VS
<16> SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT#
EC_LID_OUT# <15> 7/23 Modify @ 7/28 Modify
EC_SMI# EC_ON @
16 103 BATT_SEL_EC <47>
LID_SW #/GPIO0A EC_SW I#/GPXO06 PCH_POK_EC PCH_POK
17 SUSP#/GPIO0B ICH_PW ROK/GPXO06 104 1 2 PCH_POK <6,16>
1
18
PBTN_OUT#/GPIO0C
GPO BKOFF#/GPXO08
105 BKOFF#
BKOFF# <31>
R605
<16> SUSW ARN#
SUSW ARN# 19 EC_PME#/GPIO0D GPIO W L_OFF#/GPXO09 106 RF_LED#
RF_LED# <56,57> 1 2 1 2 +3VS
10K_0402_5% INVT_PW M 25 107 PCH_APW ROK <16> R607 0_0402_5% R608 10K_0402_5%
<31> INVT_PW M EC_TACH EC_THERM#/GPIO11 GPXO10
<37> EC_TACH 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 SA_PGOOD <50> @
EC_TACH ODD_DA# 29
<18,56,57> ODD_DA# EC_TX_P80_DATA FANFB2/GPIO15
30
2
<34,41> EC_TX_P80_DATA EC_RX_P80_CLK EC_TX/GPIO16

<34,41> EC_RX_P80_CLK 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 SLP_S4# <16>
32 112 +3VALW
<43> ON/OFF# EC_FAN_PW M ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL <31>
<37> EC_FAN_PW M 34 PW R_LED#/GPIO19 GPXID3 114 EAPD <39>
36 GPI 115 NOVO#
<43> NUM_LED# NUMLED#/GPIO1A GPXID4 NOVO# <43>
116 SUSP#
GPXID5 PBTN_OUT# SUSP# <10,26,44,49,51,52>
R606
117
2
GPXID6 PBTN_OUT# <16>
118 10K_0402_5%
EC_RTCX1 GPXID7
122
SUSCLK_R XCLK1
<16> SUSCLK 2 1 123 XCLK0 V18R 124
0_0402_5% R611 1 C667
4.7U_0603_6.3V6K
1
AGND
2 1
GND
GND
GND
GND
GND
2 LAN_W AKE# <35>

1
R740 C93 KB930QF A0 LQFP 128P 0_0402_5% R609

20P_0402_50V8
1
100K_0402_5%
2 1
11
24
35
94
113
69
0_0402_5%@ R610
2
8/23 modify EC_PME#

2
1 3
ECAGND
2N7002H_SOT23-3 @ PCI_PME# <18>
S
Q102
Change footprint +3VALW
20100814
EC_RTCX1 1 @ 2 R708 0_0402_5%
G
PCH_RTCX1_OUT <14>
2
1 2 SUSCLK_R 1 @ 2 R709 0_0402_5% PCH_RTCX2_OUT <14>
R120 10M_0402_5%
@
6/24 Update R708,R709 must be close Y5
Y5
32.768KHZ_12.5PF_9H03200413
1 1
1
4
18P_0402_50V8J
C367
C347 18P_0402_50V8J
OSC
OSC
2 2 @
@
@
NC
NC
2

BIOS & EC I/O Port
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D 0.2
8/23 change to reserved DEPART MENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS
Custom
LA-6751P
FOR EC 128KB SPI ROM
(150mil PACKAGE)
SA00003FL10
SA00003JD00
+3VALW
20mils
1
1
C699
0.1U_0402_16V4Z R617
2 10K_0402_5% S SUPPRE_ KC FBMA-10-100505-101T 0402
U33
2
<40> FSEL#SPICS#
FSEL#SPICS# 1 8
CS# VCC
FRD#SPI_SO R618 1 2 15_0402_5% SPI_SO 2 7 HOLD# R619 @ 0_0402_5%
<40> FRD#SPI_SO DO HOLD#
3 W P# CLK 6 SPI_CLK_R 1 2 SPI_CLK SPI_CLK <40>
4 GND DIO 5
MX25L2005CMI-12G SOP SPI_SI_EC 1 2 15_0402_5% FW R#SPI_SI

FW R#SPI_SI <40> SPI_CLK_R
R620
Colse to EC
1
@
EC DEBUG PORT C700
10P_0402_50V8J
2
+3VALW 1
JP3
1
EMI
<34,40> EC_TX_P80_DATA EC_TX_P80_DATA 2
EC_RX_P80_CLK 3 2
<34,40> EC_RX_P80_CLK 3
4
4
ACES_85205-0400
ME@
FD1 FD2
1 1
H_3P8
H1 H2 H3 H4
HOLEA HOLEA HOLEA HOLEA
1
H_3P3 H_3P0x4P5N H_3P0N H_6P0
H6 H5
HOLEA H15 H16 HOLEA H17
HOLEA HOLEA HOLEA
1
1
1
H_2P8
H12 H11 H10 H9 H13 H8 H7 H_5P5N
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA H14
HOLEA
1
LED/EC SPI ROM
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVIISIION OF R&D 0.2
B
A B C D E
8/27 change to stuff

1 1
WCM-2012-900T_4P
USB20_N2 4 4 3 USB20_N2_C
3
USB20_P2 1 2 USB20_P2_C
1 2
L63
+USB_VCCC W=80mils JUSB2

1 VCC
USB20_N 2 R862 @1 USB20_N2_ 2
<18> USB20_N2
2 0_0402_5% C
3
2 1 3
PJDLC05_SOT23
D+
4 GND
C702 8/27 change to @
2
470P_0402_50V7 5 GND1
+USB_VCC E-SATA COMBO 2
K D21 6 GND2
C 7
U34 RIGHT USB PORT @
8
GND3
1 GND GND4
8
-3
2 1 3 OUT SUYIN_020173GR004M58BZL
IN
6
OUT
USB_ON# 4
1
<38,40,56,57> OC# 5 USB_OC1# <18>
USB_ON#
EN
APL3510BKI_SO8 ESATA and USB ME@

Low Active
2
1
C704
Conn. 2
@ 1000P_0402_50V7
K +USB_VCCC
+USB_VCCC
W=80mils
2
1
USB20_N3_ 8/27 change to stuff 1 8/27 change to @
C
WCM-2012-900T_4P
220U_6.3V_
M
470P_0402_50V7K
USB20_N3
@ 1 VBUS
USB USB
USB20_P3_ 2 R865 1USB20_N3_C 2
3
USB20_N3 USB20_N3_ 2 2 <18> USB20_P @ USB20_P3_C D-

C USB20_N3 3
PJDLC05_SOT23
4 3 1 3
D22
@
4 3 <18>
USB20_P3
0_0402_5% R864 4
D+
GND A+ = RXP
USB20_P3 1 USB20_P3_C
2 5
1
L64
2
<14> SATA_ITX_DRX_ R627 1 ESATA@2 0_0402_5% 6
GND
A+ ESATA A- = RXN
-3
SATA_ITX_DRX_P4 P4 R628 SATA_ITX_DRX_P4_R

<14> SATA_ITX_DRX_
N4 1 2 0_0402_5%
SATA_ITX_DRX_N4 SATA_ITX_DRX_N4_R
ESATA@ ESATA@ ESATA_DET#_CON

N 7
SATA_DTX_C_IRX_N4 0.01U_0402_16V7K 2 1 C707 SATA_DTX_IRX_N4
R629 1 ESATA@2 0_0402_5% A-
SATA_DTX_C_IRX_P4 SATA_DTX_IRX_N4_R 8 12
2 GND SHIELD
0.01U_0402_16V7K 9 13
<14> SATA_DTX_C_IRX_N4 B- SHIELD

<14> SATA_DTX_C_IRX_P4 1 C708 SATA_DTX_IRX_P4 1 2 0_0402_5% 10 B+ 14
SHIELD
R630 SATA_DTX_IRX_P4_R ESATA@
ESATA@
1
11 15
GND SHIELD
B- = TXN
+5VALW 0_0402_5 2 R866 1
<19> % ESATA_DET#_CONN B+ = TXP
1
ESATA_DET#
2
1
ESATA@
BT MODULE C735 2 R867 1
CONN
2
3
100K_0402_5% 1 R632 C709
1 2
2 0.1U_0402_16V4Z
7/31 Add 2 @ 0_0402_5%
3
@
100K_0402_5 +3VS +3VS

% BT@ BT@
@ R877
2
0_0402_5 +3VS_BT 1 2
% R633
2
2 +3VS BT@ 0.1U_0402_16V4 0.01U_0402_16V7 4.7K_0402_5 4.7K_0402_5%
<19> BT_OFF IN Z
Q103 30mils 2 @ 1 @K % @
GND
1
# U35
DTC124EKAT146_SC59 3 1 @
1
-3
1 7 VCC 6
Change footprint EN
2
Q104 0.1U_0402_16V4 VCC 10
3
20100814 Z SATA_ITX_DRX_
P4
C712
2
1 16
2
AP2301GN- BT@ SATA_ITX_DRX_ RX_0P VCC
2
<56,57> HF_SOT23-3 N4
Q105 JBT1 5 9
TX_1P D0
1
BT_LED# 4 8
DTC124EKAT146_SC59 1 SATA_DTX_IRX_ TX_1N D1
-3 2 1 P4
@ SATA_DTX_IRX_
OUT
N4
USB20_P13 3 3 15 SATA_ITX_DRX_P4
<18> USB20_P1 2 GND TX_0P
_R R636 R637
<18> 3 3
USB20_N13
USB20_N1 SATA_ITX_DRX_N4
3 _R
GND TX_0N 14
2 BTON_LE 4 0_0402_5 0_0402_5%
IN D 4 GND %
<34> BT_ACTIV SATA_DTX_IRX_N4_
R @
GND
BT_ACTIV
E 5 7
5 G1 @
E
1
6 6 G2 8 13 GND RX_1N 12 SATA_DTX_IRX_P4_R
17
18
GND RX_1P 11
19
ACES_87213-0600G PAD
ME@ 21
4 4
3
SN75LVCP412RTJR_QFN20_4
X4
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
USB ports/BT/E-SATA
CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE
Size Document Number
COMPETENT DIVISION OF R&D Rev
Custo 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT m LA-6751P
CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL
ELECTRONICS, INC.
Date: Friday, November 26, Sheet 42 of 59
A B D 2010 E
C

ON/OFF switchSW 3 @
1 3
Power Button 2
Power Bottom Board Conn. 8pin
4
SMT1-05_4P
6
5
+3VALW
TOP Side J11 +5VALW
2
1 2
JPW RB1
D23 100K_0402_5% 1 1
<40> NUM_LED# 2
1
2
3 ON/OFF# 3
ON/OFFBTN# 1
2 51_ON#
ON/OFF# <40> <40> CAPS_LED#
<40,56,57> PW R_LED# 4
5
3
4 Card Reader/Audio Jack SB CONN
51_ON# <45> 5
NOVO_BTN# 8/5 modify
6 6
DAN202UT106_SC70-3 ON/OFFBTN# 7
8 7
8
JCR1
9 GND HP_OUTL 1
10 <39> HP_OUTL HP_OUTR 2 1
GND 2
<39> HP_OUTR
4 4
D
1
EXT_MIC_L 5 5
2N7002H_SOT23-3 <39> 6
EC_ON 2 EXT_MIC_R 6
<40,48> EC_ON EXT_MIC_L
<39> EXT_MIC_R
G Q106 ACES_88058-080N MIC_JD 7

<39> MIC_JD 7
3 S 0_0402_5% 8
8
2
Change footprint +3VS USB20_P11 2 R871 1 USB20_P11_C 9

20100814 ME@ <18> USB20_P11 USB20_N11 2 R870 USB20_N11_C10 9
R639 1 10
<18> USB20_N11
10K_0402_5% 0_0402_5% 11 11
12 12
13
GND
1
14
1000P_0603_50V7K
GND
W CM-2012-900T_4P
C635
USB20_N11 4 3 USB20_N11_C ACES_88058-120N
4 3
2
USB20_P11 1 2 USB20_P11_C
1 2
NOVO_BTN# ON/OFFBTN# L67 @
+3VALW
2
2
D24
PJSOT24C 3P C/A SOT-23
R642 @
100K_0402_5%
1
D26
1
NOVO# 2
<40> NOVO#
1 NOVO_BTN#
51_ON# 3
DAN202UT106_SC70-3
EMI REQUEST 1ST = SCA00000E00
2ST = SCA00000R00
Security Classification Compal Secret Data Compal Electronics,Ltd.
2010/07/12 2012/07/11 Tiitlle
other IO connector
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-6751P
A B C D E
Change footprint +1.5V to +1.5VS Change footprint

+5VALW TO +5VS 20100814 20100814
+1.5V +1.5VS
+3VALW TO +3VS
+5VALW U38 +5VS +3VALW U39 3

+3VS DMN3030LSS- 1
8 1 13_SOP8L-8
1 Q8
1
8 1
1
C723 7 2 1 1
4
1 7 2 1 1 6 3 C717 C718 C719
10U_ C724 C725 10U_0805_10V4 AP2301GN-HF_SOT1203U- 1U_0603_10V4 R643
6 3 2 5
2
C720 C721 C722 0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z R645 2Z 3_0805_10V4Z 470_0603_5%
5
2 2 2 2Z
470_0603_5%
+V @
4
10U_0805_10V4 10U_0805_10V4Z 1U_0603_10V4 R644 D @
SB 1
1
1 2Z 2 2 470_0603_5
Z 2N7002H_SOT23-3
nt 2
2
%
1 2
Q108 G +3VALW
D SUSP D
1
+VSB 2N7002H_SOT23 SUSP
R647 20100814 -3 2
1
1 2
2N7002H_SOT23 2 SUSP G
47K_0402_5%
1
-3 Q109
S S
3
Q107 G SUSP 2 C727 Change footprint @
Change 0_0402_5
@ G D % Q111 1
0.1U_0603_25V7K @ S Change 20100814
footpri
3
R646 S 2N7002H_SOT 23-3 @ 2 100K_0402_5
20100814 footprint
3
20K_0402_5% rint % R648
20100814
2
5VS_GATE2 15VS_GATE_R 2 R651 1.5VS_GATE
1
R649 1 1D 1 1
1
1
D
1
SUSP S SUSP# S 0_0402_5
2 C726 C728 C729
3
3
G Q110 0.1U_0603_25V7 2 % Q112
0.1U_0603_25V7K
2N7002H_SOT23 K G 2N7002H_SOT23 2 2
2 -3
-3
Change Change Change footprin0t.1U_0603_25V7K

footprint footp 20100814
20100814
2 2
+RTCVCC +5VAL
W +5VALW
1
+1.8VS +1.5V +0.75VS @
+1.05VS R652 R65 @
1
100K_0402_5 3 R65
1
% 100K_0402_5 4
2
SUSP % 100K_0402_5%
1
<6,10,51> SUSP
2
R655 R656 R658 R659 SYSON#
470_0603_5% 470_0603_5% 22_0603_5 470_0603_5 Q117 Q119
1
@ @ % % DTC124EKAT146_SC59- DTC124EKAT146_SC59-3
1 2
1 2
@ 3 @
OU
D D D D
1 2
OU
T
2N7002H_SOT23
T
2 SUSP 2
SYSON# -3
2 SUSP 2 SUSP
S S S S
3
GN
GN
D
3
D
3 3
Q113 G Q114 G Q115 G Q116 G 2 SYSON 2
3
<10,26,40,49,51,52> SUSP# IN <40,49 SYSON IN
>
31 2
@ Change footprint Change Change @ 2N7002H_SOT23-3

3
@ footprint footprint
20100814 20100814 20100814 Change footprint

2N7002H_SOT23 20100814
-3 2N7002H_SOT23
-3
For Intel S3 Power Reduction.

4 4

DC Interface
THIIS SHEET OF ENGIINEERIING DRAWIING2010/07/12 2012/07/11
I S THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, I NC.. AND CONTAIINS Tiitlle
CONFIIssued
IDENTII ALDate Deciphered Date Siize Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT Rev
DIVISION OF R&D
Custo 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION m LA-6751P
IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF
COMPAL ELECTRONICS, INC.
Date: Friiday, November 26, Sheet 44 of 59
A B C D 2010 E
5 4 3 2 1
DC030006J00 VIN
Precharge detector
PF101 PL101
15.97V/14.84V FOR
7A_24VDC_429007.W RML SMB3025500YA_2P
4 APDIN 1 2 APDIN1 1 2
ADAPTOR
4
3
3
1000P_04 02_50V7K
02_50V7K
100P_0402_50V8J
100P_0402_50V8J
2
2
1
D 1 D
1
@ TP0610K-T1-E3 _SOT23-3
1000P_04
2
2
PC101
PC102
PC103
PC104
JDCIN1 @ 1K_1206_5% PD102
1 2 2 1 3 1
VIN
PR103 @ LL4148_LL34-2
@ 1K_1206_5%
1 2
@ 100K_0402_ 1%
1
1
@ 100K_0402_1%
PR104
PR1 05
06
@ 1K_1206_5%
PR1
1 2
PR107
2
@ 1K_1206_5%
1 2
VIN
@ 100K_0402_1%
1
PD103 PQ103
LL4148_LL34-2 @ DDTC115EUA -7-F_SOT323-3
1
1
@ DDTC11 5EUA-7-F_SOT3 23-3

PD101
1 2
LL4148_LL34-2 2
2 1 <40,47> ACOFF 1 2
1
BATT+
1
3
PR109 PR110 <48> +5VALW P
P 04
68_1206_5% 68_1206_5% @ RB715F_SOT323-3
PQ101 VS
2
3
C TP0610K-T1-E3_SOT23-3 C
2
2
N1 3
0.22U_0603_25V7K
3
1
PR101 PC106
PC105
100K_0402_5% 0.1U_0603_25V7K
B+
2
2
PR111
2
2
22K_0402_5% PR112
1 2 @ 2.2M_0402_5%
<43> 51_ON#
2 1
VL
VS
K_0402_1%
@ 0.01U_0402_25V7K
1
@ 100K_0402_1%
1
PR114
1
PC107
PD105
2
2
@
2
8
@ RB715F_SOT323-3 LM393DG_SO8
2
P
<46,48> MAIN PW ON 1 1 O
@ 499K _0402_1%
@ 205K_0402_1%
2
02_25V7K
3 -
AC ON
1
- + +RTCBATT <47>
@ 0.1U_0603_25V7K
1
JRTC1 PR117 PR118
PR115
@1000P_0402_50V7K
P R116
P C110
4
1
1
560_0603_5% 560_0603_5%
+RTCBATT
PC108
PC109
2 1
0.01U_04
1 2 1 2 +CHGRTC
2
B B
PRG ++ 2
2
2
@2N 7002W-T /R7_SOT323-3
ML1220T13RE
@
45@
1 2 PR119 PR 120
+3VLP D <47> PACIN
1
@ 34K_0402_1% @ 47K_0402_5%
PQ1 05
2 1 2 2 1
PD106 G
6251VREF
1
RB751V-40_SOD323-2
S
@ DTC115EUA_SC 70-3
2
@ 66.5K_ 0402_1%
P Q106
P R121
+5VALWP
3
ACIN BATT ONL Y
Precharge dete ctor Precharge detector
Min. typ. Max. Min. typ. Max.
L-->H 14.991V 15.381V 15.782V L-->H 7 .196V 7.349V 7.505V
A A
H-->L 13.860V 14.247V 14.621V H-->L 6 .138V 6.214V 6.056V

2010/01/25 2010/12/31 Tiitlle
Issued Date Deciphered Date PWR DCIN / Vin Detector /Pre-charg e
Custom 0.1
DEPART MENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS PIWG1/G2(LA-6751P/LA-6753P)
5 4 3 2 1
5 4 3 2 1
PH201 under CPU botten side :

VMB2 VMB
PF201 PL201 CPU thermal protection at 92 degree C
JBATT1
1 1
12A_65V_451012MRL
2
SMB3025500YA_2P
1 2
Recovery at 56 degree C
1 BATT+
2
2
3 EC_SMCA
D 3 4 EC_SMDA
D
4
5 5
6
6
1
7 PC201 PC202
7 VL
1
8 1000P_0402_50V7K 0.01U_0402_25V7K
GND ADP_I
100_0402_1%
100_0402_1%
<40,47>
2
9
GND
TYCO_1775789-1 VL
PR201
PR202
2
2
@
1
3.48K_0402_1%
PC203 PR203 PR204
2
PR222
0.1U_0603_25V7K @ 10K_0402_1% 21.5K_0402_1% PR205
VL @ 100K_0402_1%
2
PU201
2
100K_0402_1%
1 8
1
1
EC_SMB_CK1 <40> VCC TMSNS1
PR221
<40,53> VR_HOT# 2 7
2
GND RHYST1
2N7002KW_SOT323-3
PR206
3 6 9.76K_0402_1%
D OT1 TMSNS2
2
1
PQ204
1 2 +3VALW 2 4 5
G OT2 RHYST2
43.2K_0402_1%
PR2 07
1
2
6.49K_0402_1% S G718TM1U_SOT23-8
PR223 PH201
1
PR208
@ 0_0402_5% 100K_0402_1%_TSM0B104F4251RZ
3
1
PR209
2 BATT_TEMP <40> A/D
10K_0402_5%
1
MAINPW ON <45,48>
2
PH202
1
C C
100K_0402_1%
2
VS
+3VALW +3VS
0.01U_0402_25V7K
VMB2
1
PC204
PR210 PR211
2
100K_0402_1% 10K_0402_1%
PR212 PR213
2
649K_0402_1% 5.1M_0402_5%
1 2 BATT_OUT <47>
2
PQ202
1
PR214 TP0610K-T1-E3_SOT23-3
10K_0402_1% D
2N7002KW_SOT323-3
1 2 5
+
7 2 B+ 3 1 +VSBP
8
O
6 G
1
PQ201
P
PR215 LM393DG_SO8
-
G
2
100K_0402_1%
B B
0.22U_0603_25V7K
232K_0402_1% PU101B S PC206
3
1
0.1U_0603_25V7K
4
1
PR216
PC205
2 1 PR218
6251VREF D VL 22K_0402_1%
1
2
PR217 2 1 2
2N7002KW_SOT323-3
<40> BATT_LEN#
10K_0402_1% G
2
S
1
PR219
PQ205
100K_0402_1%
2
3
1K_0402_5% PJ201
1 2 2 203 @ JUMP_43X39
<48> SPOK G 02W -T/R7_SOT323-3 2
+VSBP 2 +VSB
D
1
1
PQ
2N70 1
1
1U_0402_6.3V6K S
3
1
PC207
2
A A

PWR-BATTERY CONN/OTP
DEPART MENT EXCEPT AS AUTHORIIZED BY COMPAL ELECTRONIICS,, INC.. NEIITHER THIIS SHEET NOR THE INFORMATIION IT CONTAIINS PIWG1/G2(LA-6751P/LA-6753P)
5 4 3 2 1
5 4 3 2 1
P3
B+
P2 65W:0.020
PQ301 PQ302 90W:0.015
AO4407A_SO8 SI4459_SO8
8 1 1 8 PR302 PL302
VIN 7 2 2 7 0.020_1206_1% 1.2UH_1231AS-H-1R2N=P3_2.9A_30% CHG_B+
1
4
6 3 3 6
2
PQ303
@ 10U_0805_25V6K
5 5 1 4 1 2
AO4407A_SO8
PC325
VIN 2 3 1 8
PC324
1 2 2 7
3 6
2
0.1U_0603_25V7K
PQ304 5600P_0402_50V7K
4
5
1
D D
K_0402_1%
47K_0402_1%
PC301
PR304
1
PR303
1
1
2
@ 0.1U_0603_25V7K
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
200K_0402_1%
CSIN DISCHG_G
PR301
DTA144EUA_SC70-3 @47K_0402_1%
3
2
CSIP
PC306
PC302
PC304
PC305
PR305
4.7U_0805_25V6-K
1
PQ317B 47K_0402_1%
2
VIN PreCHG
1
2
2
2 @ 2N7002KDW -2N_SOT363-6 1 2
2
VIN
PC303
2ACOFF-1
2
BATT_OUT <46>
1
2 5 PR308
1
10K_0402_1%
1HG_G-1
PR306
PD302
2
@ 191K_0402_1%
1
4
1SS355_SOD323-2 PR309
PR307
1DISC
BATT_ON PQ317A PD301
2
2 P2-1 200K_0402_1%
2
PQ305 @ 2N7002KDW -2N_SOT363-6 6251_VDD RB751V-40_SOD323-2 PQ306
DTC115EUA_SC70-3
1
1 1
DTC115EUA_SC70-3 PR310
191
0_0402_5% PD303
1 2
3
2.2U_0603_6.3V6K
ACSETIN
6
2
PC308
FST2
C HG 1 PR311 14.3K_0402_1% PC307 1SS355_SOD323-2
1
<40> FSTCHG
1
2200P_0402_50V7K
21
10_1206_5% PR312 1000P_0402_25V8J 2 1 2
1
1
2
@ 100K_0402_5%
1
2
PC322
PR313
150K_0402_1%
3
2
PR316
PU301 PC309 PQ309
PR314
PR315
10K_0402_1%
0.1U_0603_25V7K
2
12
1
D
1
2
D
2N7002W -T/R7_SOT323-3
0.1U_0603_25V7K
1 24 6251_DC2IN 1
2 2 PACIN
2
1
S G BATT_OUT <46> G
PC310
3
100K_0402_1%
2
ACSETIN 2 23 S
@2N7002W-T/R7_SOT323-3
ACPRN <48>
3
PQ308 ACSET ACPRN PR317
BATT_ON
P2-2
C 6251_CSON CSON C
6251_EN 3 22 1 2 D
5
6
7
8
PQ307A EN CSON
1
1
PQ310
AO4466L_SO8
PC311
2 2N7002KDW -2N_SOT363-6
3
PQ311
CELLS 4 21 6251_CSOP 1 2 CSOP G
1
2
CELLS CSOP
PQ307B PR318 S
3
2N7002KDW -2N_SOT363-6 PC312 6800P_0402_25V7K 20_0402_5% 4
2
4
<45> PACIN
1 2 6251_ICOMP 5 20 6251_CSIN 2 1
PR319
47K_0402 _1%
<45> ACON PACIN 1 2 5
PC314 PR321 10K_0402_1% 0.1U_0402_16V7K 20_0402_5%
1
3
2
1
VCOMP CSIP PR322 10U_LF919AS-100M-P3_4.5A_20% 0.02_1206_1%
BATT+
1
0.01U_0402_25V7K 2_0402_5%
1
PQ312
DTC115EUA_SC70-3
1 26251_ICM 7 18 LX_CHG 1 2 C1
HG 4
PR323 ICM PHASE
PR325
1 2ACOFF-1 2 <40,46> ADP_I
100_0402_1% 2 3
1
<40,45> ACOFF
10U_0805_25V6K
PQ313
AO4466L_SO8
4.7_1206_5%
PR326
1
10U_0805_25V6K
10U_0805_25V6K
10K_0402_5% DH_CHG
1
8 17
PC318
VREF UGATE
162512_SN
PR327 1 2 6251VREF PR328 PC316
5
6
7
8
1
PC317
PC323
2
154K_0402_1% PC315 0_0603_5% 0.1U_0603_25V7K
2
PR343 2 1 0.1U_0402_16V7K 6251_CHLIM 9 16 BST_CHG 1 2 BST_CHGA 2 1
<40>
3
0_0402_5% IREF PR329 CHLIM BOOT 4

21K_0402_1% PD304
1
2N7002KW_SOT323-3
0.01U_0402_25V7K
1 2 6251_ACLIM 10 15 6251_VDDP RB751V-40_SOD323-2

2
ACLIM VDDP
3
2
1
6251VREF
1
PC319
PQ3 PR330
2
1 2 6251_VDD
2
1
1
100K_0402_1% 6251_VAD1J1 14 DL_CHG

1
PR332 VADJ LGATE PR331

2
2
2
<46> BATT_OUT
G 2.2K_0402_1% 4.7_0402_5%
2
12 13 PC321
14
D
GND PGND 4.7U_0805_6.3V6K

S
3
<40>
B PR333
Connect to EC A/D Pin. CHGV
15.4K_0402_1%
ADJ 1 2
ISL6251AHAZ-T_QSOP24
B
PR334
31.6K_0402_1%
6251_VDD 6251_VDD
3cell : GND
CP mode for 65W adapter
4cell : VDD
2
CHGVADJ=(Vcell-4)/0.10627 Vaclim=2.39*(2.2K/(2.2K+21K))=0.2515V 6251_VDD
2
Vcell CHGVADJ
4V 0V
1
Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) PR339 PR335 PR336
4.2V 1.882V
1
where Vaclim=0.2515V, Iinput=2.76A 10K_0402_1% @ 100K_0402_1%@ 100K_0402_1%
4.35V 3.2935V
3
1
1 2 ACIN <16,24,40>
PR338
PR337 10K_0402_1% CELLS
2
CC=0.25A~3A PACIN
1 2
Vaclim=2.39*(3.9K/(3.9K+25.5K))=0.0.3544V
IREF=1.016*Icharge Iinput=(1/0.015)((0.05*Vaclim)/2.39+0.05) PR340
1
IREF=0.254V~3.048V where Vaclim=0.3544V, Iinput=3.827A PR341
PR342 @ 0_0402_5%
4
VCHLIM need over 95mV 2 <40> BATT_SEL_EC
1
2
14.3K_0402_1%
PQ316
PQ315A PQ315B
DTC115EUA_SC70-3 @ 2N7002KDW -2N_SOT363-6 @ 2N7002KDW -2N_SOT363-6
3
A A

CHARGER
THIIS SHEET OF ENGIINEERIING DRAWIING IS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIICS,, INC.. AND CONTAIINS CONFIIDENTIIAL
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVII SIION OF R&D Siize Document Number Rev
PIWG1/G2(LA-6751P/LA-6753P) 0.2
5 4 3 2 1
PC401
0.1U_0603_25V7 K
2 1
2
2
@ JUM
PC403
0.1U_0603_25V7K
2 1
3 1 PC404
4.7U_0805_25V6-K
2 1
PC405
4.7U_0805_25V6-K
3 1 2 1
PC406
PQ406 2200P_0402_50V7K
2N7002W-T/R7_SOT323-3 2 1
2 1 PC415 PR409
PR417 1 6
40.2K_0402_1%
680P_0603_50V7K 4.7_1206_5%
2 1 2 1 2 1
PC421
2.2U_0603_10V7K 1 8 1 8
2 7 2 7
3 6 3 6
5 5
3 1
4 3
PC407
4.7U_0805_10V6K
2 1
PR413
100K_0402_1%
2 1
PC418
1U_0603_10V6K
2 1
VREG3
13 6 ENTRIP2 PC402
EN ENTRIP2 1U_0603_10V6K
14 SKIPSEL FB2 5
2 1
15 GND TONSEL 4
2 1 16 3
PC420 VIN REF
0.1U_0603_25V7K 2 1 17 2
VREG5 FB1
PC419 18 1
4.7U_0805_10V6K NC ENTRIP1
ENTRIP1
OD
PC408
4.7U_0805_25V6-K
2 1
PC409
4.7U_0805_25V6-K
2 1
PC410
2200P_0402_50V7K
2 1
PC411
0.1U_0603_25V7K
2 1
5 5
3 6 3 6
2 7 2 7
1 8 1 8
2 1 2 1
PC417 PR410
680P_0603_50V7K 4.7_1206_5%
3VALWP/5VALWP
150U_B2_6.3VM_R45M 2
4.7UH +-20% PCMC063T-4R7MN 5.5A
A B C D
1 1
PJ505
1
2 1
2 B+
5
6
7
8
@ JUM P_43X118
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
1
1
PC502
@ PC504
PC503
PQ501 680P_0402_50V7K
AO4406AL 1N SO8
2
2
PR503
267K_0402_1% 4
PR501 1 2
0_0402_5%
1 2
<40,44> SYSON
3
2
1
2
47K_0402_5%
PR504 PC505 PL502

PR505
15
1
0_0603_5% 0.1U_0603_25V7K 1UH_PCMC063T-1R0MN_11A_20%
14
PU501 BST_1.5V 2BST_1.5V-1 +1.5VP
1
1 1 2 1 2
PC501 @
BOOT
EN/DEM
.1U_0402_16V7K
1
2 13 DH_1.5V
TON UGATE
1
3 12 LX_1.5V 1
PHASE
5
6
7
8
VOUT PR506
VFB=0.75V + PC506
2
11 +5VALW PQ502 4.7_1206_5%
NC
4 CS
VDD AO4456_SO8 220U_6.3V_M
1000P_0603_50V7K
1
PC508
2 2
5 10
FB VDDP 2
6 9 DL_1.5V 4
PGOOD LGATE
PGND
PR507
GND
1
9.76K_0402_1%
100_0603_5%
PR508
1 2 @ PC509 PC507
+5VALW
2
7
3
2
1
2
1
47P_0402_50V8J RT8209BGQW _W QFN14_3P5X3P5 4.7U_0805_10V6K
2
1 2
PC510
4.7U_0603_6.3V6K
2
PR509
+1.5VP OCP(min)=15.6A
1 2
1.8VSP max current=4A
10K_0402_1%
1
PR510
10K_0402_1%
2
PJ501
2 1
2 1
@ P_43X118
JUM02 +1.5V
+1.5VP
PJ5
1
@2 JUMP_43X118
2 1
3 3
1
PU502 PL503 PJ504
4
2 1
2 1
PG
1
+5VALW 2 1 10 2 LX_1.8V 1 2
2 1 PVIN LX +1.8VSP @ JUMP_43X118
@ JUMP_43X118
68P_0402_50V8J
9 3
PVIN LX
1
680P_0603_50V7K 4.7_1206_5%
1
PC512
8
SVIN
PR511
22U_0805_6.3VAM PR512
6 30K_0402_1%
2
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
2
1 2
EN
1
NC
NC
TP
FB=0.6Volt
PC514
PC515
PC513
1
11
2
2
<10,26,40,44,51,52> SUSP# EN_1.8V

1 2
0.1U_0402_10V7K
2
PC516
PR513 100K_0402_1%
SY8033BDBC_DFN10_3X3
1
PR514
2
1M_0402_5%
1
FB_1.8V
1
4
PR515 4
14.7K_0402_1%
2
Issued Date 2010/01/25 2010/12/31 Tiitlle
Deciphered Date
PWR-+1.5VP/+1.8VSP
Custom
PIWG1/G2(LA-6751P/LA-6753P) 0.1

A B C D
5 4 3 2 1
D D
B+
@ PJ601
51117_VCCSAP_B+ 2 1
2 1
JUMP_43X118
4..7U_08 05_25V6-K
4..7U_0805_25V6-K
PC602
PC603
1
1
5
6
7
8
PQ601
2
AO4466L_SO8
PR602 4
C 280K_0402_1% C
1 2
+VCCSAP OCP(min)=6.28A
EN_VCCSAP BST_VCCSAP
3
2
1
PR601 PR603 PC604 PL601
15
14
1
<51> VCCPPWRGOOD 1 2 1 2 BST_VCCSAP-11 2 1 2 +VCCSAP

NC
BOOT
EN/DEM
1
TON UGATE
1
47K_0402_5% PC601 1
1
3 VOUT PHASE 12
PR605 + PC605
2
+5VALW 4.. 7_1206_5% 220U_6..3V_M
5
6
7
8
2
5 10 AO4712_SO8 2
PR606 FB VDDP PJ602
2
100_0603_1% +3VS 6 9 LG_VCCSAP 4 PR607 +VCCSAP +VCCSA
1 1
2
PGOOD LGATE PC606 PR608
+5VALW 1 2 0_0402_5%
1
470P_0603_50V8J 1 2 VSSSA_SENSE <10> @2 JUMP_43X118
2
0_0402_5%
PGND
GND
RT8209BGQW_WQFN14_3P5X3P5 PC607
4..7U_0805_10V6K
2
2
1
PR610
10K_0402_5%
1
1
PC608 0_0402_5% 13K_0402_1

7
3
2
1
1
PR609
4.. 7U_0603_6..3V6K PR611
2
2 1 SA_PGOOD <40>
2
PR612
%
PR613
2
2K_0402_1%
1 2 1 2 VCCSA_SENSE <10>
VFB=0.75V
10_0402_5%
+3VS
B B
PR615
PR614 15K_0402_1%
30K_0402_1% PR616
1
10K_0402_5%
1
D 2N7002W-T//R7_SOT323-3 10K_0402_5% PMBT2222A_SOT23-3

2 2 1
G PQ604 PR619
2
S 0_0402_5%
2
1
PC609 PR618 @ VCCSA_SEL <10>

@ 4700P_0402_25V7K 100K_0402_5%
PR620
@ 10K_0402_5%
1
1
3
1
2
3
2
VID[0] VID[1] VCCSA Vout Require on 2011/ 2012 Required

0 0 0.9 V Yes/Yes
0 1 0.8 V Yes/Yes
1 1 0.725V No/Yes
1 1 0.675V No/Yes
Note:Use VCCSA_SEL to switch High & Low Level for

A
VID[1] A
(ie. VCCSA_SEL) due to the VID[0] is don't care for this
setting.
Securiity Cllassiifiicatiion
2010/01/25
Compal Secret Data
2010/12/31 Tiitl e
PWR +VCCSAP
PIWG1/G2(LA-6751P/LA-6753P)
5 4 3 2 1
5 4 3 2 1
+1.5V
1
PJ701
1
D JUMP_43X118 D
@
2
2
PU701
1 VIN VCNTL 6 +3VALW PJ702
+0.75VSP 2 1 +0.75VS
PC701 2 1
1
1
2 5
GND NC
4.7U_0805_6.3V6K @ JUMP_43X118
3 7 PC702
VREF NC
PR701
2
1
1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
TP 9
2
PQ701 PJ703
1 1
2N7002W -T/R7_SOT323-3 G2992F1U_SO8
0.1U_0402_16V7K
2
1
1
2 4 +1.05
PC703
1
1K_0402_1%
@ JUM 1
D +0.75VSP
1
20K_0402_1% +1.05VS_VCCPP PJ7 0 VS
10U_0603_6.3V6M
<6,10,44> SUSP 1 2 2 2
10U_0603_6.3V6M
2
1
G
PC716
PC705
2
2
1
S PR703 @ JUMP_43X118
3
PC704
0.1U_0402_16V7K
C C
+1.05VS_VCCPP OCP(min)=20.75A
PJ705
1.05VS_B+ B+
2 1 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2 B+
@ JUMP_43X118
1
1
1
@ PC708
100U_25V_M
1
PC706
PC707
680P_0402_50V7K
5
6
7
8
+
PC717
PR704
2
2
2
267K_0402_1% PQ702
1 2 AO4406AL 1N SO8 2
PR705
120K_0402_1% 4
1 2
,40,44,49,52> SUSP#
1
PR706 PC710
@ 10K_0402_1%
15
2
PC709 PU702 0_0603_5% 0.1U_0603_25V7K PL702
3
2
1
PR716
14
2
B
EN/DEM
NC
BOOT
2 1 +1.05VS_VCCPP
1
1
DH_1.05VS_VCCP B
2 TON UGATE 13
3 12 LX_1.05VS_VCCP
VOUT PHASE
5
6
7
8
PR707
4 11 +5VALW PQ703 4.7_1206_5% 1

VDD CS
1000P_0603_50V7K
1 2
330U_X_2VM_R6M
5 VFB=0.75V 10 +
PC712
FB VDDP
PC711
PR709 6 9 DL_1.05VS_VCCP 4
PGOOD LGATE 2
PGND
2
100_0603_5% PR708
GND
1 2 0_0603_5%
+5VALW
1
1
13.7K_0402_1%
3
2
1
7
PR710
RT8209BGQW _W QFN14_3P5X3P5
1
@ PC715 PC714
PC713 47P_0402_50V8J 4.7U_0805_10V6K
2
2
4.7U_0603_6.3V6K 1 2
2
PR711
4.02K_0402_1%
1 2
PR714
1
10_0402_5%
<50> VCCPPW RGOOD PR713 2 1 VCCIO_SENSE <9>
PR712 1 2 +3VS
10K_0402_1%
2
10K_0402_1%
PR715 @
10K_0402_1%
Data
1
2010/01/25 2010/12/31 Tiitlle
Issued Date Deciphered
Date PWR +1.05VS_VCCPP/+0.75VSP
Custom 0.1
5 4 3 2 1
5 4 3 2 1
PD804
RB751V-40_SOD323-2
1 2
+3VS
PR801
@ 0_0402_5%
D <25,26> PX_MODE
2
2 1
PR803
PD805 PR802 205K_0402_1% PJ801
RB751V-40_SOD323-2 @ 10K_0402_5% VGA_TON 1 2 VGA_IN 2 1
2 1 B+
4.7U_0805_25V6-K
05_25V6-K
1 2
TPCA8065-H 1N PPAK56
PD801 @ JUMP_43X118
1
PC802
803
PR804 1SS355_SOD323-2
1 2 VGA_EN 1 2 +5VALW
PQ801
<15,18,25,26> PE_GPIO1
1
120K_0402_1%
1
PC801 PR805 PC804
PR832
2
PC
0_0603_5%
4.7U_08
2 1 0.1U_0402_16V7K 4
3
2
1
<10,26,40,44,49,51> SUSP# BST_VGA 1 1-1
2BST_VGA 2
2
2
PR831
15
14
10U_0805_6.3V6M
@ 120K_0402_1% 0.1U_0603_25V7K
@ 10K_0402_1%
PX4.0
5
PL801
PC808
1
PR801 120K PU801 0.88UH +-20% PCMC104T-R88MN 20A
PR804 @ 1 2
EN/DEM
NC
BOOT
+VGA_CORE
2 13 UG_VGA
TON UGATE
1
PR807 3 12 SW _VGA
10U_0805_6.3V6M
1
1
VOUT PHASE
PC809
PR806
10U_0805_6.3V6M
100_0603_1%
1VGA_SNB
2
1
1 2 VGA_V5FILT 4 11 V1
GA_TRIP 2 +5VALW
+5VALW
TPCA8059-H 1N PPAK56-8
VDD CS +
1
PC807
PR808
2
680P_0603_50V7K @ 4.7_1206_5%
PQ802
2
VGA_FB 5 10 9.1K_0402_1%
FB VDDP
330U_D2_2.5VY_R15M
1 2 PR834
GND
PC806
2
2 1 6 9 LG_VGA 2
+3VS PGOOD LGATE 4
PGND
PC805 10K_0402_1%
PC811
4.7U_0603_6.3V6K
2 PR829 1
<25> VGA_CORE_PG 0_0402_5% RT8209BGQW _W QFN14_3P5X3P5 PC810
C
3
2
1
2
C 4.7U_0805_6.3V6K
2
PR830
PC812 @ 10K_0402_1%
@ 47P_0402_50V8J @
1 2
1
1 2
PR809
2K_0402_1%
1 2
+3VALW PR810
10K_0402_1%
PR811
30K_0402_1%
1
1 2
10K_0402_1%
PR812
GVID1-2
PR813
10K_0402_1%
2
2 1GVID1-1 2 PQ803A
PQ803B 2N7002KDW -2N_SOT363-6
1
3
2N7002KDW -2N_SOT363-6 PR814 PR815

1
@ 10K_0402_5% 8.66K_0402_1%
2
2 1 5 0.022U_0402_16V7K
<24> GPU_VID1 PR816 +3VALW
VGA_PWRSEL0 VGA_PWRSEL1 Robson XT
1
GPU_VID0 GPU_VID1 Core Voltage Level

10K_0402_1%
PR818
PR817 PJ804
3K_0402_5% 2 1
2
+VGA_PCIEP 2 1 +VGA_PCIE
1 1 0.9V
2
2
1 0 0.95V
1
B @ JUMP_43X118 B
+1.5V
6
0 0 1.12 V
2 1GVID0-1 2 PQ804A
PR819 PC814 2N7002KDW -2N_SOT363-6 +5VALW
1
1
2_16
1
3
1
PQ804B 10K_0402_1% 0.022U_040 V7K
2
2N7002KDW -2N_SOT363-6 PR820 PJ805

@ 10K_0402_5% 1 JUMP_43X79
2
2 1 5 +5VALW
4
@
<24> GPU_VID0
2
PR821
2
10K_0402_1% <15,18,25,26> < 40,44,49,51> SUSP#

PR822 PE_GPIO1 1
1
3K_0402_5% 0,
NTL
818
6,
P 1U_0 402_6.3V6K
D
2
8
1
0
2 PR823 P
SUSP# C
6
RB751V- 8 PU802
40_SOD323-2 1 5 1
1
VIN 6
2
POK 4.7U_0805_6
VOUT +VG
4PR8 .3V6K
2
2 A_P
47K_0 CIE
4 PE_GPIO1 VOUT
1
4 P
3
0 EN
2 FB
1
_ 2 @ 0_0402_5%
GND
5 @ 47K_0402_5 % APL591
% 9
VIN
2
2 P 7
2
2-KAC- R
1
TRL_SO8 8
P 2
R _5% 6
8 2 1.15K_0402_1% 8
1
2
2
1
5V7
5
PC8
@ 0_0402 PR827
1 2
1
K
19
0 PD8
0.1U_0603_2
3 1
@ RB751V-40_SOD323-2 PC817
22U_0805_6.3V6M
0.01U_0402_25V7K
A A
PR828
4.53K_0402_1%
2
2009/01/06 2010/01/06 Tiitlle

Issued Date Deciphered Date PWR +VGA_CORE/PCIE
0.1
5 4 2 1
3
VGA_PCIE 1.0V 1.1 V
PR828 4.53K 3K
5 4 3 2 1
Alert# PU resister need close CPU, PC902 @ 470P_0402_50V7K CPU_B+ 1

PL901
2 B+
NTCG
4.7U_0805_25V6-K
05_25V6-K
so the PU resister in HW schematic. 2 1
1
1
PC903
904
PH901 B+ HCB4532KF-800T90_1812
but DAT and CLK need close PWM-IC, PC917 PR915 PR902 2 1 PQ901
so the PU resister in POWER schematic. 2 1 2 1 3.83K_0402_1%
5
1 2
8.06K_0402_1%
100U_25V_M
100U_25V_M
2 1 1 1
PC
4.7U_08
1
@ 470P_0402_50V7K @ 4.99K_0402_1%
2
1000P_0402_50V7K
470KB_0402_5%_ERTJ0EV474J + +
PC914
PC905
PR903
UGATEG 4
1
PR904 2 2
27.4K_0402_1%
PC901
PL902
3
2
1
2
+VGFX_CORE .36UH 20% PCMC104T-R36MN1R105 30A +VGFX_CORE
1
PR905 PHASEG 4 1
2 1 PC907 1
10K_0402_1%
@ TPCA8057-H 1N PPAK56-8
330P_0402_50V7K
PC906 10_0402_1% PQ902 PQ903
1
D BOOTG 2 PR906 1 2 1 3 2 D
+
470U_X_2VM_R4.5M
1 2 2.2_0603_5%
PC910
PC911 PC912 _50V7K 0.22U_0603_10V7K
1 2PR907
PR901 @ 39P_0402_50V7K PR909 680P_0402_50V7K 330P_0402 C909 VCC_AXG_SENSE <10> @ PR908
PR910
1
680P_0603_50V7K
2
PC915
4.7_1206_5%
499K_0402_1% 1_0402_5% 2
2 1
1
2 1 2 P
3
2
1
2
2
PC908
1
422_0402_1% VSS_AXG_SENSE <10> LGATEG
2
PC913 PH902
2
150P_0402_50V8J 1000P_0402_50V7K PR913 0402_5% ERTJ0ER103J
10K_
1 PR914 21
2 1 2 1 2 1 2 1 7.5K _0402_1% 2
PR911 PR912 10_0402_1%
3
2
1
475K_0402_1% 2.55K_0402_1%
1 PR917 2 .1U_0402_16V7K
ISPG
GFXVR_IMON 11K_0402_1%
1
PR919 PC919
+1.05VS_VCCPP 1 2
0.047U_0603_16V7K
ISNG
@ 16.5K_0402_1%
18.2K_0402_1%
.1U_0402_16V7K 1 2
1
LGATEG 37
PC918
@.1U_0402_16V7K
PC916
45
UGATEG
PHASEG
921 100_0402_1%
BOOTG
PC
PC920
470P_0402_50V7K
PR918
NTCG
@ PR922
1
2
130_0402_1%
2
2 PR920 1
54.9_0402_1%
2
1
1
2
1 2
@ 43_0402_1%
PC922
@ 0.01U_0402_16V7K
PR921
<10> VSS_AXG_SENSE
PR967
ISPG
1
1
2 PR924 1
590_0402_1%
+3VS
Parallel and tune length For shortage changed
2
+5VS
43
42
41
40
39
38
2
2
@
1.91K_0402_1%
49
48
47
46
44
1
UG
2 PR925 1ISNG
G
<9> VR_SVID_DAT
PROG
COMP
@ 0_0402_5%
BOOT
VSEN
RTN
GN
ISP
ISN
FB
PH
LG
G
G
G
D
G
BOOT2
G
<9> VR_SVID_ALRT# 1 36
VWG BOOT2
G
G
2
G
2 35 UGATE2
<9> VR_SVID_CLK IMONG UG2
PR927
NTC
3 34 PHASE2 PR928
PH2
G
PGOODG
PR926
2
+3VS 1 2 1 2 +5VS
SVID_SDA 4 VSSP2
1.91K_0402_1% GFX_CORE_PWRGD SDA 0_0402_5%
33
SVID_ALERT# 5 LGATE2
C PR931 C
32
SVID_SCLK ALERT# LG2 1 2
<9> VSSSENSE
VGATE <16>
6 VDDP
PR933 SCLK PWM3 0_0402_5%
1
31
2
2.2U_0603_10V6K
PC927
1
1 2 7
<40> VR_ON VR_ON PWM3
30
0.047U_0603_16V7K
0_0402_5% 8 LGATE1
PGOOD
2
29.4K_0402_1%
IMVP_IMON ISL95831CRZ-T_TQFN48_6X6 29
1
LG1
9
IMON
PC926
VSSP1
PR936
10 PHASE1
28
VR_HOT# UGATE1
27
2
For shortage changed PH1

11
NTC BOOT1
26
20 ISUM
UG1
ISEN3/
181 VSE
<40,46> VR_HOT# 12 CPU_B+

PC929 @ VW
RT
16 ISEN
17 ISEN
COM
1
25
FB2
4.7U_0805_25V6-K
05_25V6-K
PROG
BOOT1
ISUM
FB
5
P
VIN
VD
D
P
1
13
14
15
PC930
931
PR938 2 4710P_0402_50V7K
1 2 PQ907
19
24
PU901
21
22
23
499_0402_1% PH903
PR939
2
@ 1 2 1 2
+1.05VS_VCCPP
1000P_0402_50V7K
3.83K_0402_1% 470KB_0402_5%_ERTJ0EV474J
UGATE2 4
4.7U_08
PC
PC928 2 1
1
2
PR942
1.69K_0402_1%
8.06K_0402_1%
change from 43P to 47P 1 2 PL904

1
CPU_B+
1
(Ipeak=54A) .36UH 20% PCMC104T-R36MN1R105 30A

PC932
3
2
1
2
for shortage problem

PR943
PHASE2 4 1
2010-03-15 PC933
0_0603_5% +CPU_CORE
22P_0402_50V8J PR945 2.2_0603_5% 3 2
4.7_1206_5%
5
5
0.22U_0603_25V7K
PR944 PQ908 PQ909
2 1 +5VS
2
PC935
1
1
PR946
2 1 BOOT2 2 1 2 1
1_0603_5%
1U_0603_10V6K
ISEN2
ISEN1
B @ 10K_0402_1% 10K_0402_1% B
ISEN3
PC934
680P_0603_50V7K
PC936
2.61K_0402_1%
1 2
0.068U_0402_16V7K
0.22U_0402_6.3V6K PC937 @ 0.22U_0603_10V7K PR947 PR948
PC939
1
2
1
1 2
PC955
3
2
LGATE2 4 4 1 ISEN2 2 2 1ISEN1
3
2
1
2 1
PR957
PC938 1
10P_0402_50V8J PC941
2
6
PR950 PR949 PC940 VSUM- 2 1 VSUM+ 3.65K_0402_1% 1_0402_5%
0.22U_0402_6.3V6K
1 2 2 1 2 1 2 1 PR951 PR952
499_0402_1% PC942 VSUM+ 2 1 2 1 VSUM-

@ 499K_0402_1% 470P_0402_50V7K 2 1
PR953
PC943 PR954 PR955 0.22U_0402_6.3V6K @
2 1 2 1 2 1
0.068U_0402_16V7K
3.32K_0402_1%
0.22U 10V K X7R 0603
11K_0402_1%
150P_0402_50V8J 316K_0402_1% CPU_B+
2 1 2 1 PR956
2 1 PQ910
1
1
1
PH904
PC945
PC944
+CPU_CORE
2
2
2
PC923 PR916 @ 10_0402_1% 10K_0402_5% ERTJ0ER103J
2
@ 680P_0402_50V7K @ 2K_0402_1% PC947
330P_
2 1 PR958
330P_0402_50V7K
1
.1U_0402_16V7K
0402_50V7K VSUM-
1
2 1
PC952
2
PC946
<9> VCCSENSE PC950
2
1.47K_0402_1% UGATE1 4
2
1 PC951 PR959
<9> VSSSENSE
2 1 2 1
PR960 1000P_0402_50V7K @ 100_0402_1%
2 1 @ 330P_0402_50V7K PL905
@ 10_0402_1% .36UH 20% PCMC104T-R36MN1R105 30A
PHASE1 4 1 +CPU_CORE
PC
4.7U_08
5
2
PR961 PQ911 PQ912 10K_0402_1% 3 2 10K_0402_1%
2.2_0603_5% PC953 PR963 PR964
3
2
1
BOOT1 2 1 2 1 ISEN1 2 1 2 1 ISEN2
*Iccmax in Turbo Mode for SV (35W) is 53A
4.7_1206_5%
1
0.22U_0603_10V7K
PR962
LGATE1 4 4 @ 3.65K_0402_1% 1_0402_5%
+CPU_CORE +VGFX_COREP PR965 PR966
680P_0603_50V7K
1 2
3
2
1
3
2
1
VSUM+ 2 1 2 1 VSUM-
PC954
A A
Icc-max=53A Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A
Rdson=3.6~4.5m ohm Rdson=3.6~4.5m ohm
2
DCR=1.1m ohm DCR=1.1m ohm
HW output cap: HW output cap:
@
(1)10U_0805_4V *10 (1)22U_0805_6.3V *12
(2)22U_0805_6.3V *15 (2)470U_D2_2V *2(ESR=4.5m ohm)
(3)470U_D2_2V *4(ESR=4.5m ohm) Security Classification Compal Secret Compal Electronics, Inc.
Data
2010/01/25 2010/12/31 Tiitlle

Issued Date Deciphered Date PWR +CPU_CORE/+VGFX_CORE
*OCP setting value=71.5A *OCP setting value=37A THIIS SHEET OF ENGII NEERII NG DRAWIING I S THE PROPRII ETARY PROPERTY OF COMPAL ELECTRONIICS,, I NC.. AND CONTAIINS
CONFIIDENTII AL
AND TRADE SECRET I NFORMATII ON.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT
DII VII SII ON OF R&D
Custom 0.1
DEPART MENT EXCEPT AS AUTHORII ZED BY COMPAL ELECTRONIICS,, INC.. NEII THER THIIS SHEET NOR THE PIWG1/G2(LA-6751P/LA-6753P)
I NFORMATII ON IT CONTAII NS MAY BE USED BY OR DIISCLOSED TO ANY THIIRD PARTY WIITHOUT PRIIOR
WRIITTEN CONSENT OF COMPAL ELECTRONIICS,, IINC..
5 4 3 2 1
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase
To reduce charger ripple 47 Add PC323 DVT

1 2010.08.15
D D
Change +VGA_PCIE enable signal from PX_MODE to PE_GPIO1
2 PR804:120K
51 PR831,PR801,PR825 UN-POP 2010.08.15
HW request for power sequence DVT
PR824:47K
PC819:0.2uF
3 Change Vboot setting 52 Change PR942 as 4.32K 2010.08.15 DVT
4 Change OCP setting 52 Change PR958 as 1.47K 2010.08.15 DVT
5 Add PC955 for loadline adjust 52 Add PC955 2010.08.15 DVT
6 Reserve pull low resistor 51 Add PR718,PR832 2010.09.29 PVT
7 Remove jump 51 Remove PJ802,PJ803 2010.09.29 PVT

C C
Pop PR222,PR208,PH202,PR221,PQ204 2010.09.29 PVT
8 Adapter protect circuit 46 Un-Pop PR223,PR203
Remove PJ301
9 EMI Request Add PL302 and reserve PC324 2010.09.29 PVT
47
10
11
B B
12
13
14
15
16
17
A A

2009/01/06 ICS,, INC.. AND CONTAII2009/01/06 Tiitlle
PIR (PWR)
IssuedOFDate
THIIS SHEET ENGIINEERIING DRAWIING IS THE PROPRIIETARY PROPERTY OF COMPAL ELECTRONIDate
Deciphered NS CONFIIDENTIIAL
AND TRADE SECRET INFORMATIION.. THIIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIIVII SIION OF R&D
Custom 0.1
PIWG1/G2
5 4 3 2 1
V
V V
VV
V
V
SYS_PWRO
K
13
V
PM_DRAM_PWRGD
14
V V
V
H_CPUPWRGD
CPU
PLT_RST# 15
V
V
V
+3VSDGPU
Q6 11
V
VGATE
+1.5VSDGPU
U40
V
+1.8VSDGPU VGA
U37
V
+1.0VSDGPU
PU28
V
+VGA_CORE
PU998
V
V
PU9 PU7
+1.05VS_VCCP +VCCSA
VGA_PWROK 8b(DIS)
U47
PU1000 CK505
10
V
+CPU_COR
E
Power sequence
5 4 3 2 1
INT_KBD Conn. ME@ +3VALW 1

R614
2
0_0402_5%
+VCC_LID R615 1 2 100K_0402_5% Kill
KSI[0..7]
KSI[0..7] <40,57>
STATUS
ACES_88514-2401
KSO[0..15]
KSO[0..15] <40,57> 26 GND2
1,2(LOW) OFF
2
25 GND1
1
S-5711ACDL-M3T1S_SOT23-3
2,3(HI) ON
VDD
KSI1 24 24
KSO2 C668 1 KSI7 23 23 C694
KSO15 C670 1 2 @ 100P_0402_50V8J

KSI6 22 0.1U_0402_16V4Z 3
KSO6 22 2 OUTPUT LID_SW # <40,57>
C672 1 2 @ 100P_0402_50V8J KSO9 21 21
D
KSO8 C674 1 2 @ 100P_0402_50V8J
KSI4
KSI5
20
19
20 Lid Switch 2 Kill Switch D
GND
KSO13 C676 1 2 @ 100P_0402_50V8J
KSO1 C669 1 KSO0 19 +3VALW
18 18
KSO12 C678 1 2 @ 100P_0402_50V8J KSI2 17 U32 C695 100K_0402_5% LSSM12-P-V-T-R_3P
1
KSO7 C671 1 17 10P_0402_50V8J
KSI3 16
16 2 R616 1 3 3
KSO11 C680 1 2 @ 100P_0402_50V8J KSO5 15 1
KSI2 C673 1 15
2 @ 100P_0402_50V8J KSO1 14 2
KSO10 C682 1 2 @ 100P_0402_50V8J
KSO5 C675 1 14 <14,57> KILL_SW # 2
KSO3
2 @ 100P_0402_50V8J KSI0 13 13 KILL_SW#
C684 1 2 @ 100P_0402_50V8J KSO2 12
KSI3 C677 1 12 1
2 @ 100P_0402_50V8J KSO4 11 1
KSO4 C686 1 2 @ 100P_0402_50V8J KSO7 11
10
KSO14 C679 1 10
KSI0
2 @ 100P_0402_50V8J KSO8 9
9 8/23 Change LED1/LED3/LED4 P/N to SC50000A300
C688 1 2 @ 100P_0402_50V8J KSO6 8
KSI7 C681 1 KSO3 8 SW 2
2 @ 100P_0402_50V8J 7
KSO0 C690 1 2 @ 100P_0402_50V8J
KSI6 C683 1
2 @ 100P_0402_50V8J
KSO12
KSO13
6
5
7
6 LED White
LED1
2 @ 100P_0402_50V8J
KSI5 C685 1
2 @ 100P_0402_50V8J KSO14 5
4 4 <40,43,57> PW R_LED# 1 2 2 1 +5VALW
KSI4 C687 1 KSO11 3 300_0402_5% R622
2 @ 100P_0402_50V8J KSO10 2
3
KSO9 C689 1
2 @ 100P_0402_50V8J
KSI1 C691 1 KSO15 2 19-213A-T1D-CP2Q2HY-3T_W HITE
1
2 @ 100P_0402_50V8J 1
Reserve for ESD. 2 @ 100P_0402_50V8J Orange LED2
JKB1
BATT_LOW_LED#
2 @ 100P_0402_50V8J
<40,57> CHARGE_LED1# 1 2 2 1 +3VALW

ZZZ
+5VS Right --> Orange Change design to two LED
C C
1 2 2 1
To TP/B Conn. C696 ACES_88058-060N
DAZ0GL00100
<40,57> CHARGE_LED0#
BATT_CHG_LED# 300_0402_ 765
+5VALW
White
8 19-213A-T1D-CP2Q2HY-3T_W HITE
7 GND
0.1U_0402_16V4Z GND ZZZ1 ZZZ2 ZZZ3
TP_CLK 5 6
<40,57> TP_CLK 5 D19 LED3
TP_DATA 4 @ White
<40,57> TP_DATA 4
3
1 1 SW /L 3 <34,57> W LAN_LED# 1 2 1 2 2 1 +5VS

@ @ SW /R 2 PCB PCB PCB 300_0402_5% R625
2
C697 C698 1 RB751V_SOD323

100P_0402_50V8J 100P_0402_50V8J 1 DA80000KF10 DA40000VV10 DA40000VS10 19-213A-T1D-CP2Q2HY-3T_W HITE
2 2 JTP1 @
3
DA8@ DA4@ DA4@ <42,57> BT_LED# 1 2
RB751V_SOD323
<40,57> RF_LED# 1 2
+5VALW
6
5
SMT1-05_4P TP_CLK LED4

2 4 TP_DATA White
SW /L <14,57> HDD_LED# 1 2 2 1 +5VS
1 3 +USB_VCCA 300_0402_5% R626
2
U36
SW 4
D15 1
GND OUT
8 RIGHT USB PORT X1 19-213A-T1D-CP2Q2HY-3T_W HITE
PSOT24C_SOT23-3 C713 0.1U_0402_16V4Z 2 7

IN OUT
1
@ 2 1 3 6
B USB_ON# IN OUT B
1
<38,40,42,57> USB_ON# 4 EN OC# 5 USB_OC0# <18,38,57>
Right USB Conn.

6
5
SMT1-05_4P APL3510BKI_SO8
2 4 1
+USB_VCCA
SW /R C716 W=80mils 8/27 change to @
1 3 @ 1000P_0402_50V7K JUSB3
2 1
SW 5 CONN PIN define need double check <18,57> USB20_N0 USB20_N0 2 R868 @1 0_0402_5% USB20_N0_C 2 2
4
JODD1 470P_0402_50V7K G5
6
1 2 ACES_85205-04001
GND
SATA_ITX_DRX_P2_CONN 2 ME@
SATA ODD Conn. <14,57> SATA_ITX_DRX_P2_CONN
<14,57> SATA_ITX_DRX_N2_CONN SATA_ITX_DRX_N2_CONN 3
A+
A-
4 8/27 change to stuff
<14,57> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 C606 1 6 B-
<14,57> SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 B+ 8/23 change C714 P/N to SGA00002N80 USB20_N0_C
W CM-2012-900T_4P
2
USB20_N0 4 3 USB20_N0_C USB20_P0_C
4 3
PJDLC05_SOT23-3
9 USB20_P0 1 2 USB20_P0_C D25
+5V_ODD +5V 1 2
+5V L66
ODD_DA# 1 2 11 MD
<18,40,57> ODD_DA# R554 0_0402_5% 12
GND GND 15
R555 13 14
A +3VS 1 2 A
10K_0402_5%
ALLTO_C18518-11305-L
8/13 update JODD1 symbol ME@

Deciphered Date
KB /SW /LPC Debug Conn.
B 0.2
LA-6751P
5 4 3 2 1
5 4 3 2 1
JKB1 ZZZ ZZZ1 ZZZ2 ZZZ3 ZZZ4 ZZZ5

KSI1 1 1
KSI7 2
KSI[0..7] 2
INT<_40K
KSI[0..7] ,56>BD Conn.
KSI6
KSO9
3
4
3
4
KSO[0..17] KSO16 C693 1 KSI4 5
KSO[0..17] <40,56> 5
KSI5 6 DAZ0GM00100 PCB PCB PCB PCB PCB
6
KSO17 C692 1 2 @ 100P_0402_50V8J KSO0 7
KSI2 7
8 DA80000KG10 DA40000VV10 DA40000VS10 DA40000VT10 DA40000VU10
KSO2 C668 1 8
2 @ 100P_0402_50V8J KSO1 C669 1 2 @ 100P_0402_50V8J KSI3 9 9
KSO5 10 DA8@ DA4@ DA4@ DA4@ DA4@
KSO15 10
C670 1 2 @ 100P_0402_50V8J KSO7 C671 1 2 @ 100P_0402_50V8J KSO1 11 11
D KSI0 12 D
KSO6 12
C672 1 2 @ 100P_0402_50V8J KSI2 C673 1 2 @ 100P_0402_50V8J KSO2 13
KSO4 13
14 14
KSO8 C674 1 2 @ 100P_0402_50V8J KSO5 C675 1 2 @ 100P_0402_50V8J KSO7 15 15
KSO8 16
KSO13 KSO6 16
C676 1 2 @ 100P_0402_50V8J KSI3 C677 1 2 @ 100P_0402_50V8J 17 17
KSO3 18 18 +5VALW
KSO12 C678 1 2 @ 100P_0402_50V8J KSO14 C679 1 2 @ 100P_0402_50V8J KSO12 19
KSO13 19
20 20
KSO11 C680 1 2 @ 100P_0402_50V8J KSI7 C681 1 2 @ 100P_0402_50V8J KSO14 21 21
KSO11 22
KSO10 22 +USB_VCCA
KSO10 C682 1 2 @ 100P_0402_50V8J KSI6 C683 1 2 @ 100P_0402_50V8J 23
KSO15 23
24 U36
KSO3 C684 1 2 @ 100P_0402_50V8J KSI5 C685 1 2 @ 100P_0402_50V8J
KSO4 C686 1 KSI4 24
2 @ 100P_0402_50V8J C687 1 2 @ 100P_0402_50V8J <40> KSO16
KSO16 25
26
25 1 GND OUT 8 RIGHT USB PORT X1
KSO17 C713 0.1U_0402_16V4Z 2 7
KSI0 C688 1 2 @ 100P_0402_50V8J KSO9 C689 1 2 @ 100P_0402_50V8J
KSO0 C690 1 2 @ 100P_0402_50V8J KSI1 C691 1 2 @ 100P_0402_50V8J <40> KSO17 26 IN OUT
27 27 2 1 3 IN 6
USB_ON# 4 OUT
2 @ 100P_0402_50V8J 28 5
28 <38,40,42,56> USB_ON# EN OC# USB_OC0# <18,38,56>

29 31
30 29 GND 32
30 GND APL3510BKI_SO8
1
ACES_88514-3001 C716
@ 1000P_0402_50V7K
CONN PIN define need double check Reserve for ESD. ME@ 2
+5VS
C Right USB Conn. C
To TP/B Conn. C696 +USB_VCCA

W=80mils 8/27 change to @
JUSB3
0.1U_0402_16V4Z +USB_VCCA 1
JTP1 2 1
<18,56> USB20_N0
USB20_N0 2 R868 @1 0_0402_5% USB20_N0_C 2
TP_CLK 2 2 4 4
<40,56> TP_CLK 3 C714 + 5
<40,56> TP_DATA TP_DATA 3 C715 G5
1 1 SW /L 4 470P_0402_50V7K 6 G6
@ @ 4 2
SW /R 5 220U_6.3V_M
C697 C698 6 5 2 ACES_85205-04001

6
100P_0402_50V8J 100P_0402_50V8J ME@
2 2 7
8 GND
GND 8/14 change to OSCAN 220U 8/27 change to stuff
ACES_88058-060N USB20_N0_C
W CM-2012-900T_4P
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00) USB20_N0 4 3 USB20_N0_C USB20_P0_C
2
PJDLC05_SOT23-3
ME@ 4 3
6
5
3
SMT1-05_4P TP_CLK
2 4 TP_DATA USB20_P0 1 2 USB20_P0_C D25
1 2
SW /L @
L66
1 3
2
3
D15
SW 4
PSOT24C_SOT23-3
@
1
B B
1
6
5
SMT1-05_4P
2 4
SW /R
1 3
JP13
SW 5 CONN PIN define need double check D19
<34,56> W LAN_LED# 1 2 RF_LED#_R +3VALW 2 2
RB751V_SOD323 <40,56> LID_SW # 4 4

5
SATA ODD FFC Conn. JP2
@
D20
<40,43,56> PW R_LED# 6
5
6
<42,56> BT_LED# 1 2 <40,56> CHARGE_LED1# 7 7

<14,56> SATA_ITX_DRX_P2_CONN SATA_ITX_DRX_P2_CONN 1 <40,56> CHARGE_LED0# 8 8
1
SATA_ITX_DRX_N2_CONN 2 RB751V_SOD323 RF_LED#_R 9
<14,56> SATA_ITX_DRX_N2_CONN 2 9
3 10
SATA_DTX_C_IRX_N2 C605 1 2 0.01U_0402_16V7K 3 <40,56> RF_LED# 1 2 <14,56> HDD_LED# 10
C606 1 SATA_DTX_IRX_N2 4 R679 0_0402_5% 11
<14,56> SATA_DTX_C_IRX_N2 SATA_DTX_C_IRX_P2 2 0.01U_0402_16V7K SATA_DTX_IRX_P2 4 11
5 12
<14,56> SATA_DTX_C_IRX_P2 R710 1 5 <14,56> KILL_SW # 12

ODD_DETECT# 2 0_0402_5% 6 6
7
+5V_ODD 7
8 13
ODD_DA# 9
For 15" M/B to LED/B
1 2 10 9 14
<18,40,56> ODD_DA# R554 0_0402_5% 10
R555 GND1
+3VS 1 2 11 GND
10K_0402_5% 12 GND KILL_SW # R884 1 @ 2 100K_0402_5% +3VALW R615 1 2 100K_0402_5%
ACES_88514-01201-071
A
ACES_87056-01001-001 11/16modify LID_SW #
7/22 modify A
ME@
ME@

Deciphered Date
B 0.2
LA-6751P
5 4 3 2 1
5 4 3 2 1
PHASE PAGE Modification list PURPOSE

0.2 P31 Change CRT Symbol For CRT footprint issue
0.2 P31 Del C510 For Non-used part

0.2 P39 change C610 pin 1 net name change C610 pin 1 net name to correct
0.2 P35 U25 change to U26 For co-lay 10/100 and GIGA
0.2 P32 Add R735,R736 For DIS only SMBus pull high
0.2 P33 Add R738,R739 For DIS only SMBus pull high
D D
0.2 P33 Change Q63 BOM structure to HDMI@ For DIS HDMI function
0.2 P40 Add R740, C93 For EC request
0.2 P18 Change R215 pin1 net name Change R215 pin1 net name to correct
0.2 P18 Add R741 Add R741 for Reserved PE_GPIO0
0.2 P16 Add R742, R743 For PCH power sequence

0.2 P38 Del U28, R542~R551 , J12 Del USB charger circuit
0.2 P40 Add EC pin 97,98,103 Add EC pin 97 for SYS_PWROK_EC , pin 98 for CE_EN , pin 103 for BATT_SEL_EC
0.2 P24 Change R662 pin 2 net name Change R662 pin 2 net name to correct
0.2 P28 Del C421,C422,C431,C432,C433, L27, Add R745, U8 pin N11,N12 change to NC For AMD new document suggestion
0.2 P26 Add R744 Add R744 for control PE_GPIO1 from SUSP#
0.2 P39 Change J10 footprint and Add J13 Change J10 footprint by DFx request and Add J13 by vendor suggestion
0.2 P39 Change PC_Beep circuit Change PC_Beep circuit
0.2 P6 Add R161, R182, R192 BOM structure hange to @ Follow ORB circuit
0.2 P58/59 Add R615 in 15" and 17" page Pull high LID_SW# at M/B side
C 0.2 P31 Add Q83 pin 1 power net name +CMOS_PW For power trace net C
0.2 P56/57/58 Change JP21 to JKB1 Change connector to standard name

0.2 P56/57/58 Change JP4 to JTP1 Change connector to standard name
0.2 P43/60 Change JP6 to JPWRB1 Change connector to standard name
0.2 P34 Change JP1 to JWLN1 Change connector to standard name

0.2 P42 Change JP5 to JBT1 Change connector to standard name
0.2 P43/60 Change JP7 to JCR1 Change connector to standard name
0.2 P19 Add R542 For ESATA detect function
0.2 P42 Add R886, R887 , C735 For ESATA detect function
0.2 P31 Add R543 For reserve EC control directly
0.2 P39 Change J10 footprint, Del C635, C636 Change J10 for DFx and Del component for layout
0.2 P42 Add R877 For reserve EC control directly

0.2 P42 SW3 BOM structure change to @ For ME ASSY concern
0.2 P24 R324 BOM structure change, del @ For AMD update
0.2 P25 Change Q69,Q70,Q71,Q72 to BSS138, change Q66,Q67 pin 1 net name, D28 change to @ For Change BACO part follow AMD reference DATA ,D28 change to @ for leakage
B B
0.2 P42 Change ESATA from port 5 to port 4 For intel risk
0.2 P15 Add R544,R545 For Pull high SMBus
0.2 P12/13 Del R74~R80,R82 R88~R94,R96 For DDR3 DM Bus to GND
0.2 P16 Add R182,R546 Add 186 for reserve sequence, Add R546 for follow CRB & ORB
0.2 P20 Del Add J12, R257 change to @ For voltage drop
0.2 P26 R161 Change Q6 to U14 Change SI2301 to SI4800 for loading current
P6 R161 change to 100K Follow CRB
0.2
0.2 P19 Add R547 , R250 change to @ Follow Module and CRB
0.2 P18 WLAN USB port for port8 to port9 For debug port
P25 AND Gate power change to +3VGS For VGA circuit
0.2
P24 Add R548, R549 For DIS HDMI audio strap
0.2
P39 Del J13 For layout space
0.2
P20,39,42 Add C395 , R581 , R583 , R584 , R586 , R587 For customer request reserved
0.2
P20 Add C129, C396 , Del R264 For reserved
0.2
A A
0.2 P40 Add PIN 66 , R740,C93 change to @ Add IMVP_IMON
0.2 P9 Add R74 For VCCIO_SENSE / VSSIO_SENSE differential routing

Deciphered Date
B 0.2
LA-6751P
5 4 3 2 1
5 4 3 2 1

0.2 P33 Del RQ51 ~ Q54 Add Q95 For DIS HDMI
0.2 P39 Del J10, C637,C640,R576,R577,R579 change to @ , L40~L43 change to R720~R723 For Vendor suggestion and EMI
Del C643, R578 , MIC_INR connect MIC_INL , Add R578 Del C653, R578 connect MIC_INR/L for vendor suggestion , Add R578 for EMI
0.2 P20 Add L75 , R264 , C917, R259 C226 change to @ For intel PDDG update
0.2 P20 Change JCR1 pin define , MIC change with HP For correct ID
0.2 P9 Add C394, C397 ,C400 ,Add R75 For CPU_CORE power reserved at Bottom side, Add R75 for reserved at cpu side and pwr side
D D
0.2 P26 Add R688 change to 20k, R345 change to 200k , R350 change to 330k , Q65 stuff For VGA power sequence
0.2 P42 Change C706 P/N to SF000001500 Change to H=6 OSCAN
0.2 P10 Change C128 to @ For Reserved
0.2 P26 Change D3 change to @ For VGA leakage
0.2 P25 Change BIF_VDDC control pin net name For correct behavior
0.2 P56 Update JODD1 symbol For ME update drawing
0.2 P16 D29 change to @ For AC detect issue
0.2 P24 R548,R549 change to DIS@ For AC detect issue
0.2 P10 C128 change to stuff For test on DVT
0.2 P44 Del Q118, R657 For not need
0.2 P57 Change 15" C714 to OSCAN For ME Space ok
0.2 Change R513, R516 ,R667 P/N and from 0805 to 0603 For common part
0.2 Change C633, C634 , C642 For common part
0.2 Change D3, D29 P/N and symbol For common part
C 0.2 Change U3,U11,U13,U14,U38,U39 P/N and symbol For common part C
0.2 Change U3,U11,U13,U14,U38,U39 P/N and symbol For common part

0.2 Change Q8,Q65,Q80,Q83,Q99,Q104 P/N and symbol For common part
0.2 Change Q1,Q37,Q93 P/N and symbol For common part
0.2 Change Q94, Q95 P/N and symbol For common part
0.2 Change Q3,Q4,Q7,Q9,Q66,Q67,Q68,Q73,Q74,Q75,Q76,Q77,Q78, For common part
Q79,Q82,Q85,Q86,Q87,Q102,Q106,Q107,Q108,Q109,Q110,Q111,Q112,Q113,Q114,Q115,Q116
P/N and symbol
0.2 P43 Change C635 part and change to @ For EMI
0.2 P18 Reserved R551 Reserved

0.2 P9 Change C53,C85,C86,C87 ,C394,C397,C400 to stuff and For CPU_CORE
change C48,C80,C81,C82,C89,C90,C91 to @
0.2 P10 Change C110,C111,C112,C113 to stuff For VGFX_CORE
0.2 P56 Change LED1/LED3/LED4 P/N to SC50000A300 Change P/N
0.2 P36 Change T1,T2 P/N to SP050003N00 For test pass part
B B
0.2 P40 Change R611,R740,C93 to stuff and change Y5,C347,C367 to @ For SUS_CLK
Change R695 to 18K, Q37 change to @, R747 change to stuff, R695 for Board ID, Q37, R747 for VR_HOT
0.2 P41 Change U33 P/N to SA00003FL10 For BIOS ROM
0.2 Change C509,C511,C635 to stuff For EMI request
0.2 P56 Change 14" C714 P/N to SGA00002N80 For Sourcer request
0.2 P39 Change R720,R721,R722,R723 P/N to SM01000BZ00(Bead), and For EMI request
Change C647,C649,C650,C651 to Stuff
0.2 P19 Change R303 to Stuff, and change R542 to @ For BIOS ESATA detect function
0.2 P56 Change U32 P/N to SA000031C00 For common part
0.2 P36 Change T1,T2 P/N to SP050006E00 For correct part
0.2 P10 R688 change to stuff , R687 ,Q7 change to @ For S3 power reduction
0.2 Change R660,R661,R862,R863,R864,R865,R868,R869 to @ , change For EMI
L63,L64,L65,L66 to stuff , change R619 to Bead (SM01000DI00)
0.2 P20 Change L75 symbol For common part
A A
2010/07/12 2012/07/11
Tiitlle
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D HW-PIR
B 0.2
LA-6751P
5 4 3 2 1
5 4 3 2 1
0.3 P10 Update Q5 symbol For update symbol

0.3 P33 Add F2 For safty request
0.3 P39 Update U30 P/N to SA00003K410 and Add R879 For Audio update to 21Z
0.3 P10 Change C128 to D2 size and @ Change size for M/E issue
0.3 P14 Add reserve R878 For Intel DG 1.5
D 0.3 P37 C592 change P/N to SF000001500 (H=6) For ME Z high ok D
0.3 P25 Update Q69~Q72 to AO3414 ,D28 R873 change to BACO@ , U40 change to @ For PX4.0
0.3 P28 Add reserve C94 For reserve VGA_CORE
0.3 P29 R369 P/N change to SD034100A80 For GP part
0.3 P18 R553,R691,R684,R682,U12 change to PX@ For PX 4.0
0.3 P6 Reserved R880 to SYS_PWROK Follow ORB
0.3 P10 R62,R63 change to 1K Follow CRB
0.3 P19 R303 change to @, Change M/B ID to PX4.0 For ESATA and PX4.0
0.3 P25 Q69~Q72 change to BACO @ For PX4.0
0.3 P26 R719 change to stuff, R744 change to @ , R677 change to BACO@ For PX4.0
0.3 P33 R483,R484 change connect to +5V_HDMI_F For Add F2
0.3 P37 Change U27 P/N to SA000046C00 For Fintek
0.3 P40 Change R594 pull high to +5VALW For leakage issue
0.3 P19 R881 change to Dtuff, R244 change to @ For intel MRC Rev0.9
0.3 P14 R878 change to stuff For intel DG 1.5
C C
0.3 P31 Del R432 For non-used part
0.3 P36 Reserved D31 , C643 , C644 For reserved EMI parts

0.3 P38 Change C592 P/N to SF000002Y00 For M/E Z high limlt
0.3 P39 Del R584, R586 , R587 For non-used part
0.3 P40 Change R600, R604 to 2.2K Change R695 to 8.2k Change R600, R604 for Battery SMBus, R695 for Board ID
0.3 P6 Reserved R882 connect to PCH_PWROK Reserved for intel
0.3 P56 R765 change to 300 ohm For LED
0.3 P25 R324, R744 , R674 change DIS@ For DIS only sku
B B
A A

Deciphered Date
HW-PIR
B 0.2
LA-6751P
5 4 3 2 1

Compal confidential schematics for G470/G570 motherboards

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Compal confidential schematics for G470/G570 motherboards

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A B C D E

G470/G570 DIS+UMA+Muxless M/B Schematics Document

Security Classification Compal Secret Data Compal Electronics,

Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)

Page39 Audio Jacks

WiMAX Page34 USB2.0 *1(Right)

Int. KBD USB2.0 *2(Left)

SATA ODD Page38

Security Classification Compal Secret Data Compal Electronics, Inc.

Full ON HIGH HIGH HIGH HIGH ON ON ON ON

+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

SMBUS Control Table Unpop @

Security Classification Compal Secret Data Compal Ele

Without BACO option :

Global ASIC Reset

Security Classification Compal Secret Data Compal Electronics, Inc.

FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_C_N5 C11 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N5

F26 PCIE_CTX_GRX_C_N1 C15 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_N1

PCIE_CTX_GRX_C_P11 C21 1 2 0.1U_0402_10V6K PCIE_CTX_GRX_P11

Security Classification Compal Secret Data Compal Electronics, Inc.

AP29 XDP_PRDY# +1.05VS

R27 1 2 PM_DRAM_PW RGD_R V8 SM_DRAMPW ROK

10/12 reserve R880 / R882

0_0402_5% R880 R30

74AHC1G09GW _TSSOP5 R34 U2

R33 BUF_CPU_RST# 1 2 BUFO_CPU_RST# 4 NC

Security Classification Compal Secret Data Compal Electronics, Inc.

SA_CLK[0] AB6 M_CLK_DDR0 <12> SB_CLK[0] AE2 M_CLK_DDR2 <13>

DDR SYSTEM MEMORY

DDR SYSTEM MEMORY

DDR_A_D60 AL14 SA_DQ[56] DDR_B_D60 AT12 SB_DQ[56]

Sandy Briidge_rPGA_Rev1p0 Sandy Briidge_rPGA_Rev1p0

<6> H_DRAMRST# H_DRAMRST# 3 1 1 2 DDR3_DRAMRST# <12,13>

Date: Friiday, November 26, 2010 Sheet 7 of 59

CFG Straps for Processor

JCPU1E PEG Static Lane Reversal - CFG2 is for the 16x

AR35 1 : Disabled; No Physical Display Port

C30 RSVD16 VCC_DIE_SENSE AH27 PAD T13

1: (Default) PEG Train immediately following

0: PEG Wait for BIOS for training

Security Classification Compal Secret Data Compal Electronics, Inc.

AC26 VCCIO38 A12

VCC61 H_CPU_SVIDALRT# R47 2 43_0402_5%

C394 C397 C400 U33 VCC73

VCC96 0_0402_5% VSSIO_SENSE 1 2

Issued Date 2010/07/12 Deciphered 2012/07/11 Tiitlle

Date PROCESSOR(5/7) PWR,BYPASS

Date: Friiday, November 26, 2010 Sheet 9 of 59

DDR3 -1.5V RAILS

6/9 change 330U to 22U X2

Security Classification Compal Secret Data

Sandy Briidge_rPGA_Rev1p0 Sandy Briidge_rPGA_Rev1p0

Security Classification Compal Secret Data Compal Electronics, Inc.

+VREF_DQ_DIMMA +1.5V +1.5V +1.5V

205 206 0.65A@0.75V

<7> DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB

127 VSS27 VSS28 128

DDR_B_D33 131 DQ33 DQ37 132 DDR_B_D37 1

B DDR_B_D34 141 DQ34 DQ39 142 DDR_B_D39 B

R97 10K_0402_5% VTT1 VTT2 0.65A@0.75V SMB_DATA_S3 <12,15,34> @ @

Datte:: Friiday,, November 26,, 2010 Sheett 13 off 59

PCH_RTCX1 1 @ 2 R663 0_0402_5% PCH_RTCX1_OUT <40>