ELEN E4312

Fall 2010
Y. Tsividis DESIGN PROJECT v1

Here is a TENTATIVE description of the design project. This information may have to
be fine-tuned over the next several weeks, so it may be changing often.

Design a CMOS op amp with the following specs (all at 27º C):

Power supply voltage: ±1.5 V.

Biased through a single reference current source.

Transfer characteristic (Vout vs. Vin): monotonic.

Output linear range (output swing): At least ±1.2 V.

“Systematic” equivalent input offset voltage: Sufficiently small, so that with

Vin1=Vin2=0, the output is within its high-gain range. (In a real op amp, the input offset
would typically be much larger due to mismatches.)

Input common mode range: At least -1 to +0.5 V.

Low-frequency gain: At least 82 dB

CMRR: Greater than 60 dB.

Output load: a 2 pF capacitance.

Unity-gain frequency: At least 30 MHz.

Frequency compensation: appropriate for unity-gain feedback applications, with at least

50 degrees phase margin in the presence of the above load.

0.1% settling time (time it takes for output to settle to within ±0.1% of final value, in a
unity-gain configuration): Less than 80 ns for input steps of ±0.5 V.

Total supply current: As small as possible; this is the performance parameter that
you should try to minimize.

Minimum channel length: 0.5 µm; minimum channel width: 1 µm.

The device models we will use are for a very conservative fabrication process. I have
chosen this so that you can use a rather large supply voltage, in order to make the
situation similar to those in the homework; also, in order to make some of the model
parameters semi-recognizable.
Spice model parameters:

.model CMOSN NMOS LEVEL=2 TOX=7.200E-09

+TPG=1 VTO=0.58
+UO=300 GAMMA=0.5863
+NSUB=2.7470E+16 NFS=1.98E+12 KF=1.4E-24 AF=0.8
+CGDO=4.0241E-10 CGSO=4.0241E-10
+CGBO=3.6144E-10 CJ=3.8541E-04 MJ=1.1854 CJSW=1.3940E-10
+MJSW=0.125195 PB=0.8

.model CMOSP PMOS LEVEL=2 PHI=0.600000 TOX=7.500E-09

+VTO=-0.675
+UO=109 GAMMA=0.4863
+NSUB=1.8900E+16 NFS=3.46E+12 KF=3E-24 AF=1.2
+CGDO=5.3752E-11 CGSO=5.3752E-11
+CGBO=3.3650E-10 CJ=4.8447E-04 MJ=0.5027 CJSW=1.6457E-10
+MJSW=0.217168 PB=0.85

Note: The above parameters are not necessarily equal to parameters with similar names
used in hand analysis. To see the values for those, do an “operating point” analysis
(which can also be part of an AC analysis); most of the parameters Spice will then give
you (e.g., VTH) have names similar to ones we use for hand analysis.

Spice will calculate automatically the gate overlap capacitances, from the W and L
values. Since we do not do layout in this class, and thus we do not have the source and
drain geometric details, Spice does not have enough information to calculate the junction
capacitances. This is OK for this introductory project.

Suggestions

Since this may be your first op amp design, you may want to proceed carefully, as
follows:

• Come up with a preliminary design by hand; take into account relevant specs
given, to help come up with preliminary W and L values.

• If you choose the right W/L ratios as explained in class, the offset spec should be
satisfied, at least if all devices have the same channel length. If you use different
channel lengths, the Early effect may change slightly the current ratios, and you
may need to adjust slightly a W in order to compensate for this.

• Thoroughly verify with Spice. A document describing how to simulate an op amp

has been posted. In particular, do the following simulations:

• DC operating point.
 • DC transfer curve and DC small-signal gain.

• Common-mode small-signal gain at DC. Make sure the output stays in its
linear region for any simulation you use to determine this.

• AC analysis. Do this first with the load capacitance in place, but without a
frequency compensation capacitor. Obtain Bode plots for magnitude and
phase of the differential gain.

• Add appropriate elements to compensate the amplifier, to satisfy the specs

given. Do an AC analysis to verify proper compensation.

• In order to further make sure your amplifier is properly compensated, connect

it in a unity-gain buffer configuration (with the load capacitance still
connected). Drive the input with a 0.5 V step voltage. Check to make sure the
output settles at the value you expect. Determine the 0.1% settling time.
Repeat for a -0.5 V step.

Put your measurement results in the form of a table.

Working in pairs: You are supposed to work in pairs (this may not be possible with
CVN students, so their work will be judged accordingly). You need only hand in one
report per pair. The project grade for each partner will be calculated as follows: [Max.
grade possible] x [Partner’s contribution percentage]. For this reason you are asked to
state, on the first page of your report, the approximate percentage of each partner’s
contribution.

GUIDELINES FOR PROJECT REPORTS

Length limit: Same as that imposed for brief papers in the IEEE Journal of Solid-State
Circuits; not more than about 1800 words, plus a few figures. For typed reports, this
corresponds to no more than six double-space typewritten pages, plus figures.

Style: Similar to that of brief papers in the above journal; see recent issues in the library
for examples. Be concise and to the point; give important results, but avoid showing
details of lengthy calculations. In general, write your report as if you were to submit it for
publication in the above journal. This means, among other things, that the report should
be self-sufficient; all important results from computer simulations should be transferred
to the report (e.g., in the form of plots), so that the reader can get the picture without
having to examine your computer printouts.

Spice files: Spice files should not be included in your report, but should be submitted
electronically. Your TA will contact you as to the format.
Computer printouts / screen dumps: Although, as mentioned above, the report should
be self-sufficient, computer printouts or screen dumps containing useful information
(which you may have used to evaluate your design) should be submitted separately; these
will help us form a clearer picture for grading purposes.

Your original report will not be returned. Make a copy before you hand it in.

REPORT DUE DATE: November 22. No late reports can be accepted.

EXTRA CREDIT

The following concerns only those who decide to try for extra credit (details in class).

Make a simple op amp in the lab using MOS transistors from 4007 chips, each of which
contains three identical nMOS and three identical pMOS transistors with various
connections between them. You can connect transistors of the same type in parallel in
order to obtain the equivalent of a larger W; thus all your Ws will be integer multiples of
the width of a single transistor.

You can find data for this chip at:

http://www.us.oup.com/us/pdf/microcircuits/students/logic/CD4007-national.pdf
http://focus.ti.com/lit/ds/symlink/cd4007ub.pdf

Supply voltages: ±5 V

Load: A 20 pF capacitor.

Bias using a single reference resistor, so that the resistor current is about 100 µA.

Compensate to achieve stability in a unity-gain configuration.

Measure the following:

• DC transfer characteristic (open-loop);

• Input equivalent offset voltage;

• Output linear range;

• Open-loop DC gain;

• Slew rate;

• 1% settling time for +1 V and -1 V step inputs in a unity-gain configuration.

Prepare a very brief report with your schematic and a table of measurement results.

Parts will be provided to on-campus students. You can use the Student Projects Lab in
1212 Mudd. See http://www.cisl.columbia.edu/spl/. Use a proto board for breadboarding.
Be aware that the capacitance between adjacent rows of holes on those boards can be
several pF, which will affect high-frequency performance. Thus AC behavior will differ
from that predicted by simulations (you are not asked to measure AC performance).

For simulation before breadboarding, you can use the following model for the CD4007:
.model mnmos NMOS (Level=1 Gamma= 0 Xj=0
+ Tox=1200n Phi=.6 Rs=0 Kp=111u Vto=2.0 Lambda=0.01
+ Rd=0 Cbd=2.0p Cbs=2.0p Pb=.8 Cgso=0.1p
+ Cgdo=0.1p Is=16.64p N=1)
*The default W and L is 30 and 10 um respectively and AD and AS
*should not be included.

.model mpmos PMOS (Level=1 Gamma= 0 Xj=0

+ Tox=1200n Phi=.6 Rs=0 Kp=55u Vto=-1.5 Lambda=0.04
+ Rd=0 Cbd=4.0p Cbs=4.0p Pb=.8 Cgso=0.2p
+ Cgdo=0.2p Is=16.64p N=1)
*The default W and L is 60 and 10 um respectively and AD and AS
*should not be included.

This model is very approximate, and data differ from manufacturer to manufacturer.

When working with the demo version of PSpice, instead of connecting several transistors
in parallel, specify a single transistor with the conbined width; otherwise, you will
quickly exceed the maximum number of transistors (10) allowed in this version of the
program.

CVN students can mail us the final schematic for their circuit, including package pins
used, and we will assemble and test the circuit here.

Demo and testing date for extra credit project: To be announced.