Electric Power Systems Research 174 (2019) 105853

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Electric Power Systems Research

journal homepage: www.elsevier.com/locate/epsr

A simple dead-time compensation strategy for grid-connected voltage- T

sourced converters semiconductor switches
Gabriel A. Foglia,b, , Rodolfo L. Vallea, Pedro M. de Almeidaa, Pedro G. Barbosaa
⁎

a
Electrical Engineering Program, Federal University of Juiz de For a, Juiz de Fora, Brazil
b
Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil

ARTICLE INFO ABSTRACT

Keywords: This paper presents a simple strategy to compensate the distorted currents synthesized by a grid-connected
Dead-time compensation strategy voltage source converter due to dead-time, turn-on and turn-off time delays of the semiconductor switches. The
Time-delay compensation scheme algorithm consider only the polarity of the fundamental component of the currents flowing through the con-
Average value compensation verter terminals and the values of the time delays and voltage drops supplied by the manufacturers to the
Voltage sourced converter
semiconductors devices. The presented compensation belongs to the group classified as average value com-
Grid-connected power converter
pensation technique methodology since it does not change the pulse pattern of the converter's semiconductor
switches. A simplified mathematical description of the effects caused by these unwanted time delays is presented
and used to derive a correction factor to be added, in real time, to the converter output controller in order to
compensate for its terminal voltages. The asymptotic stability and robustness of the proposed methodology is
investigated redrawing the converter current controllers, designed in dq-reference frame, as proportional-re-
sonant ones, in the abc coordinates, and adding the effect of the compensating signal in the feedback loop using
the concept of describing function. In addition, the minimum value of the DC bus voltage necessary is also
evaluated to ensure the operation of the converter in the linear modulation region when the compensation
algorithm is active. Experimental results are presented to validate the theoretical analysis and to demonstrate the
effectiveness of the proposed strategy for three different operation conditions of a grid-connected converter: (i)
active power injection; (ii) active power consumption and (iii) reactive power support.

1. Introduction voltages and currents allows changing the pulse-pattern in order to

Voltage sourced converters (VSC) have been widely used in in-
dustrial and grid-connected applications. Kerkman et al. [1] demon-
strated how some of non-linearities such as semiconductor switches
dead-time, time-delays of the gate drives, as well as the voltage drops of
switches and diodes, distort the currents synthesized by the VSC. These
non-linear characteristics have its effects increased when the converters
are driven by high frequency pulse width modulation (PWM) techni-
ques.
The dead-time is the delay during a VSC semiconductor switch ac-
tivation, used to guarantee that the complementary switch of the same
branch is fully deactivated. Different compensation methods have been
proposed in literature to reduce or mitigate the effects of the dead-time
[1–3]. They can be classified according to the way that the converter's
output voltage waveforms compensation is performed. Direct methods
model the non–linearities of VSC semiconductor switches. Thus, the
mathematical understanding of how the dead-time affects the output
compensate for undesired effects [4,5].
Lewicki [3] divided the direct compensation methods into two
groups. The first one was named as pulse-based compensation strate-
gies. In this group, the gate-pulses of the converters’ semiconductors
have its commutation instants changed to compensate the dead-time
and control delays effects. Abronzini et al. [6] proposed a steady-state
compensation technique for a current-controlled grid-connected con-
verter. Their algorithm is based on step-by-step voltage compensation
according to the current error evaluated within each control interval.
Despite of low computational effort, the aforementioned compensation
method has the disadvantage of only be effective for slow-dynamic
applications (e.g. photovoltaic generation systems). Another pulse-
based compensation strategy was proposed by Lee and Ahn [4]. The
authors modify the switching patterns of the space vector modulation
(SVM), according to the converter's output current polarity, compen-
sating the dead-time effect. Modifying only the SVM switching intervals
is a simple strategy without any additional circuitry or sensor. The main

⁎
Corresponding author at: Department of Electronic Engineering, Federal University of Minas Gerais, Belo Horizonte, Brazil.
E-mail address: gabrielfogli@ufmg.br (G.A. Fogli).

https://doi.org/10.1016/j.epsr.2019.04.031
Received 24 July 2018; Received in revised form 7 March 2019; Accepted 25 April 2019
Available online 17 May 2019
0378-7796/ © 2019 Elsevier B.V. All rights reserved.
G.A. Fogli, et al.
disadvantage it is the reduction of the modulation linear region. Con-
sequently the system may operate in the overmodulation region, in-
jecting current harmonics into the grid. Besides, this strategy only
presented satisfactory results under open-loop tests.
The second group of direct compensating methods gather the stra-
tegies in which the voltage error due to the dead-time is compensated
by the addition of a factor in the reference voltage signal [7–9]. These
methods are named volt-second or average value compensation. Zhang
and Xu [10] describes the effects of snubber and parasitic capacitance
on the switching patterns of a VSC. The voltage error due to dead-time
is compensated taking into account the snubber and parasitic capaci-
tance of the switch. The method is effective, in steady-state, if specific
parameters, such as parasitic capacitances, are known.
On the other hand there are the indirect compensation methods.
These methods do not focus on the cause of the voltage distortions but
on their consequences. An error between the reference and the output
voltage or current is fed back to dedicated controllers whose outputs
regulate the output signals to minimize the harmonics content and in-
directly eliminating the dead–time effects. The studies presented in
[11–13] can be included in this group. They are also called feedback
compensation strategies. Tang and Akin [14] propose the use of revised
repetitive controller (RRC) to reduce current harmonics caused by
dead-time, improving the efficiency in permanent-magnet synchronous
motor (PMSM) drives. Despite of good performance in transient and
steady states, the additional harmonic compensation structures in-
creases the complexity of the design and the computational effort of the
whole control algorithm.
This work presents a simple and effective direct method to com-
pensate the dead-time and time-delays of the VSC switches based on the
modelling of these non-linear effects. The compensation strategy uses
the polarity of the converter's output currents to generate a compen-
sation signal to be added to the reference signals supplied by current
controllers. A stability analysis through description function due to
nonlinear system is developed to demonstrate the asymptotically sta-
bility and robustness. The minimum value of the DC voltage bus re-
quired to guarantee that the converter operates in the linear region of
the PWM modulation is also presented. The lower computational effort
and the plug-in characteristic of the proposed scheme makes its use
possible together with any type of controller, without the need of any
additional hardware or sensors. Experimental results are presented to
validate the proposed strategy.
2. Mathematical modelling
Fig. 1 shows a schematic diagram of the three-phase VSC connected
to the ac electric network through a three-phase first-order low-pass
harmonic filter. Where Rf and Lf are the resistance and inductance per
phase, respectively. The input terminals of the converter is connected to
a generic dc-source. The resistance Rp models the losses and self-dis-
charge of the converter's dc-capacitor. The power on the dc-side can be
provided by any conventional or alternative energy source (e.g. wind,
photovoltaic, micro-turbine, etc.) which requires an inverter as the
interface between the primary energy source and the grid. The dc ca-
pacitor is shown split into two parts to make the theoretical analysis
easier to understand. This fictitious point is not accessible in most of
commercial and experimental prototypes.
Ideally, the semiconductor switches of the same leg of the VSC are
commutated in a complementary way. It means that, when the upper
semiconductor is switched on, the lower one is switched off and vice-
versa. However, in real applications, there is a short period of time,
called dead-time, in which both switches are kept open. The dead-time
prevents the short-circuit of the converter dc-side capacitor. During this
period, the current flows through the lower or upper diode of the VSC
leg in accordance with the current polarity. If it is positive, the current
flows through the lower diode, otherwise it flows through the upper
one. Thus, the phase “a” terminal voltage vao , with respect to the
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Electric Power Systems Research 174 (2019) 105853
fictitious dc-centre tap, for a positive current flow is given by:
Vdc
vao = Vce, when S1 is on
(1)
2
and,
Vdc
vao = Vd, when S4 is on
2 (2)
where the Vdc is the total dc-voltage, Vce is the semiconductor switch
voltage drop, Vd is the diode voltage drop.
On the other hand, considering that the current polarity is negative,
the phase “a” terminal voltage can be written as follows:
Vdc
vao = + Vd, when S1 is on
2 (3)
and,
vao =
Vdc
+ Vce, when S4 is on
2 (4)
Fig. 2 shows the waveforms for the phase “a” when a real switching
pattern is considered. The gate signals S1 and S4 were drawn for two
consecutive switching periods Ts [15]. The effect of dead-time (tΔ) is
illustrated by the dashed rectangles in Fig. 2(a) and (b). It is also pos-
sible to evaluate how tΔ, the turn-on (ton) and turn-off (toff) time–delays
affect the output voltage vao .1 The ton time is composed by the turn-on
delay time (td(on)), the current rise time (tri) and the voltage fall time
(tfv), while the toff is given by the turn-off delay time (td(off)) plus the
voltage rise-time (trv) plus the current fall time (tfi) [16].
It is clear from Fig. 2(c) that when ia > 0, the voltage drops Vce and
Vd reduce the “average instantaneous value”2 of vao when S1 and S4 are
high, respectively. The voltage vao also has its averaged instantaneous
value reduced during the (tΔ + ton) period and increased during the toff
period. On the other hand, when ia is negative, vao has its averaged
instantaneous value increased by the voltage drops Vce and Vd when S1
and S4 are low, as well as its average value is increased and decreased
during the (tΔ + ton) and toff periods as shown in Fig. 2(d).
Based on Fig. 2, the reduction of the VSC output voltage due to the
aforementioned time-delays can be estimated as follows,
V=
t + ton toff
(Vdc Vce + Vd ).
2Ts (5)
where ΔV is the output voltage reduction averaged value for two con-
secutive switching periods.
Although the modelling of the dead-time was performed for the
phase “a”, the methodology presented here can be easily extend to the
other legs of the converter. Thus, assuming that the VSC synthesize
sinusoidal currents at its terminals, the three-phase distortion voltages
due the time delays, with respect to the dc-centre tap of Fig. 1, are given
by:
v ko, = V sign (ik ), (6)
where sign (·) represents the signal function and k {a, b , c } .
Fig. 3(a)–(c) show the three-phase distortion voltages according to
the output current polarity. Notice that the voltages vao, , v bo, and vco,
are π rad phase-lagged with respect to the phase currents, respectively.
The output currents were plotted normalized in relation to the VSC
rated value. The high frequency harmonics due to commutation were
neglected. That is, it was considered that the output filter effectively
attenuate those harmonics.
The previous voltage waveforms are similar to those from a six-
pulse inverter. Thus, assuming a balanced operation, the phase-to-
neutral voltages are given by [16],
1
The dead-time tΔ should be chosen greater than ton and toff.
2
The terminology average instantaneous value is used here to denote the
average value calculated during one switching period Ts.
G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 1. Three-phase grid-connected VSC system under study.

Fig. 2. Switching waveforms for phase “a”: (a) S1 gate signal, (b) S4 gate signal, (c) output voltage vao for ia > 0 and, (d) output voltage vao for ia < 0.

2 1 1 Vh,
v kn, = v ko, v vmo, Ih, =
3 3
o,
3 (7) Zf , h (9)

where k {a, b , c } , {a, b , c } and ℓ ≠ k, m {a , b , c} and where |Zf , h | = Rf2 + (h Lf ) 2 and Zf ,h = tan 1 (h Lf / Rf ) are the inter-
m ≠ ℓ ≠ k. face low-pass filter magnitude and phase, respectively; ω is the system
Fig. 4 shows the phase-to-neutral distortion voltage for the phase fundamental frequency.
“a” of the converter. Similarly voltage waveforms can be drawn for The analysis of (9) shows that the magnitude of the harmonic cur-
phases “b” and “c” by lagging van, of 2π/3 rad and 4π/3 rad, respec- rent Ih,Δ decreases as the harmonic order increases. The reduction oc-
tively. curs not only due the harmonic voltage reduction, but also by the in-
The characteristic harmonics of van, are given by 6h ± 1, while crease of the interface filter impedance. Despite of the amplitude
their amplitude can be calculated by expanding the voltage waveform reduction of high order harmonics, the fifth and seventh order har-
depicted in Fig. 4 on its Fourier series as shown below, monics may not be neglected, depending on the switching frequency.
Therefore, to reduce the output current distortion a compensation
4 3 V 5 strategy is needed.
Vˆh, = cos h cos h ,
3h 6 6 (8)

where V̂h, is the peak-value of phase-to-neutral distortion voltage and
h = 1, 2, 3, ….
Considering the grid-voltages , vb and vc in Fig. 1 are balanced and
free of harmonics, the distortion voltages van, , v bn, and vcn, forces an
harmonic current flow through the interface filter. The rms value of
each harmonic current component, for h ≠ 1, is given by,
3. Dead-time compensation strategy
In order to overcome the undesired effects of the dead-time, turn-on
and turn-off time-delays in a grid-connected power converter, a simple
control strategy is proposed. The compensation scheme is based on the
cancellation of the distortion voltages caused by the aforementioned

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G.A. Fogli, et al.
Fig. 3. Three-phase VSC distortion voltages and output currents: (a) phase “a”, (b) phase “b”, (c) phase “c”.
non-linearities by using its estimation modelled by (5) and (6). Where
the measured value of Vdc is used for on-line calculations of ΔV. This
strategy reduces the influence of Vdc variations on the compensation
[13].
Fig. 5 shows the block diagram used to estimate in real time the
distortion voltages caused by tΔ, ton and toff. Three notch filters N(s)
(Appendix A) are used to extract the fundamental component of ia, ib
and ic. This structure prevents problems regarding the signal function
when the output currents have large ripple or phase shifted due to
harmonics. Since the centre tap of the dc bus is not connected to the
neutral point of electric system, the triplen harmonics of the VSC
terminal voltages will be cancelled. Thus the compensation algorithm
may use the terminal distorted voltages vao, , v bo, and vco, instead of
the phase-to-neutral voltages van, , v bn, and vcn, . This choice reduces
the computation effort of the algorithm.
Fig. 6 shows the complete control block diagram of the grid-con-
nected power converter. Two PI controllers, designed in synchronous
reference frame, regulate the currents synthesized by the VSC [17]. This
strategy is widely used in the literature to control the active and re-
active powers flow at the terminals of grid-connected converters
through the direct id and quadrature iq current components, respec-
tively. The PLL circuit supplies the angle θ used to transform the
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Electric Power Systems Research 174 (2019) 105853
voltages and currents to synchronous reference frame [13]. Since the
time-delays reduce the output voltages of the converter, the distortion
voltages vao, , v bo, and vco, , estimated by the control algorithm shown
in Fig. 5, are inverted and transformed to αβ-coordinates before being
added to the reference voltages of the current controllers, v * . Then, the
resulting voltages are divided by 3 ( 2dc ) to generate the modulation
2 V
signals mαβ that are sent to the space vector modulation (SVM) block.
The factor (2/ 3 ) was associated with the Vdc/2 voltage to normalize
mαβ, avoiding the over-modulation of control signals used generate the
pulse pattern of the converter switches. Although the SVM has been
used herein to control the VSC, other modulation techniques can be
employed without modifications and loss of effectiveness.
The time-delays tΔ, ton = (td (on) + tri + t fv ) and toff = (td (off) + trv + t fi)
used in Fig. 5, as well as the voltage drops Vce and Vd, are obtained from
the manufacturer data sheets of the drive circuits and the semi-
conductor switches, respectively. The analysis of (5) shows that the
weight of tΔ, ton and toff times increases under higher frequencies op-
eration, that is, small switching times Ts.
On the other hand, the influence of Vce and Vd may be neglected in
(5) due to their lower values in comparison to Vdc. Nevertheless a boost
in the DC bus voltage may be require to avoid over-modulation as a
result of the additional ΔV voltage generated by the compensation
Fig. 4. Phase-to-neutral voltage for phase “a”
of the VSC.
G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 5. Block diagram of algorithm used to estimate the distortion voltages.

method. Then, considering that the SVM strategy is used to generate the fundamental component peak value.
converter switching pattern, the following relation yields: The voltage given in (10) corresponds to the length of a rotating
vector with amplitude equal to the radius of the circumference in-
2 Vdc scribed in the hexagon, formed by the switching converter voltages in
Vˆ1,max =
3 2 (10) the αβ-plane [15]. Thus, replacing h by 1 in (5) and substituting the
result in (10) yields:
where V̂1,max is the converter's output phase-to-neutral voltage

Fig. 6. Grid-connected converter with current controller in synchronous reference frame and time-delays compensation.

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G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 7. Layout of experimental setup: (1) DSP; (2) conditioning board; (3) buffer board; (4) SKHI22A H4 drivers; (5) Voltage-sourced converter (SKS50FB6U
+B6CI32V12); (6) Voltage sensors (LV 25P); (7) Current sensors (HAS 50-S.

4 3 Table 2
Vdc = V
(11) VSC semiconductor parameters.

where ΔVdc is the value that the DC voltage level should be increased to Parameter Symbol Value

avoid over-modulation when the compensation algorithm is used. Dead-time tΔ 4.3 μs

Turn-on time-delay ton 1.0 μs
Turn-off time-delay toff 1.0 μs
4. Experimental validation
Switch voltage-drop Vce 1.85 V
Diode voltage-drop Vd 2.2 V
Fig. 7 shows the picture of the experimental set-up of the grid-
connected converter built in laboratory to validate the proposed com-
pensation strategy. The VSC was constructed using three Semikron Commonly, for grid-connected applications, the magnitude and phase
modules SKM100GB128D driven by SKHI22A dual-hybrid IGBT driver. of inverter output voltage must be changed in accordance with the
The control system was implemented in a TMS320F28335 DSP from desired active and reactive power at its terminals. This is performed by
Texas Instruments. Tables 1 and 2 show the parameters of the system changing the modulation signal. The modulation index is used to
and VSC, respectively. modulate the switch duty ratio and has a frequency f1, which is the
Fig. 8 shows the distortion voltages waveforms in the αβ-reference desired fundamental frequency of the inverter voltage output.
frame. These signals were generated by the compensating algorithm Fig. 10 shows the phase “a” modulation index for the operation
implemented in the DSP. Notice that the distortion voltages have wa- modes given in Table 3, with the proposed dead-time compensation
veforms in accordance with the theoretical analysis previously present. algorithm. Notice that the modulation index waveforms change ac-
The use of different dc-bus voltage values, converter switching fre- cording to the phase of the converter's output current, which is directly
quency, among other parameters only changes the amplitude of v , related to the operation mode.
v , , not its waveform. The modulation index has its peak decreased in Fig. 10(a). This
The phase “a” modulation index considering the operation of the behaviour can be explained by the fact the reference voltages v * are in
VSC without the dead-time compensation strategy is depicted in Fig. 9. phase with the voltages v , when the VSC drains active power from
The reference signals for the converter current controllers are id* = 7.0 A the grid (i.e. rectifier operation mode). On the other hand, during the
and iq* = 0 A . This condition implies in approximately 1.33 kW and active power supplying mode, Fig. 10(b), the voltages v * and v , are
0 kvar of active and reactive powers at the converter's terminals. phase-shifted by π rad. The comparison between Fig. 10(a) and (b)
The modulation index is a control signal that varies slowly, com- shows that the modulation index has its amplitude increased in the
pared with switching-frequency triangular waveform. It is the output second case. This condition should carefully evaluated by the designer
controller signal used to determine the switching pattern [18]. to avoid over-modulation according to the following analysis.
Substituting the phase-to-neutral peak voltage value taken from
Table 1 Table 1 into (10), it returns the minimum DC bus voltage for the SVM
System parameters. linear operation, which is 311 V. On the other hand, substituting the
Parameter Symbol Value parameters given in Table 2 into (5), and assuming a switching fre-
quency of 20 kHz, it results in ΔV = 18.08 V. Replacing the previous
AC rms phase-to-neutral voltage Van 127 V value for the distortion voltage in (11) it gives ΔVdc = 39.87 V. Then,
Fundamental frequency f1 60 Hz
the minimum DC bus voltage level, when the proposed compensation
Interface filter inductance Lf 1.25 mH
Interface filter resistance Rf 0.33 Ω
method is used, must be (Vdc + ΔVdc) = 350.87 V. Finally, considering
DC-link voltage Vdc 420 V a safety factor of 20% to compensate for voltage drops in the interface
DC-link capacitance Ceq 4700 μF filter, as well as to avoid over-modulation during transients, the con-
Sampling frequency fs 20 kHz verter DC bus voltage was chosen equal to 420 V.

6
G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 8. Experimental waveforms generated by the dead-time compensation algorithm.

Fig. 9. Phase “a” modulation index for active power injection id* = 7.0 A and iq* = 0 A without dead-time compensation.

Fig. 10. Phase “a” modulation index considering different operation modes for the VSC with dead-time compensation: (a) rectifier operation mode id* = 7.0 A and
iq* = 0 A ; (b) active power supply id* = + 7.0 A and iq* = 0 A ; (c) reactive power support id* = 0 A and iq* = 7.0 A ; (d) reactive power support id* = 0 A and iq* = + 7.0 A .

Table 3
Operation modes for time-delays compensation tests.
Operation mode
Active power drain
Active power supply
Reactive power support
Reactive power support
The last two waveforms of Fig. 10 are obtained for the converter
supporting reactive power to the mains. Fig. 10(c) and (d) show the
Reference currents Time-delay compensation
modulation indexes for the cases when the reference direct current id* is
zero and the reference quadrature current iq* is −7.0 A and +7.0 A,
id* = 7.0 A Enabled respectively.
iq* = 0 A In order to analyse the switching frequency effects on the output
Enabled
current, Fig. 11 shows the phase “a” current waveform considering
id* = + 7.0 A
iq* = 0 A
three different switching frequencies (10, 20 and 25 kHz). In the left
and right columns of Fig. 11 is depicted the current injected into the
id* = 0 A Enabled grid for the operation of the VSC without and with the dead-time
iq* = 7.0 A compensation, respectively. The reference currents are id* = 7 A and
id* = 0 A Enabled iq* = 0 A. In this operation mode the converter injects approximately
iq* = + 7.0 A 1.33 kW into the electric network. Notice that the synthesized current
waveform become more distorted as the switching frequency is

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G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 11. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 7 A and iq* = 0 A and considering different switching frequencies: (a)
without dead–time compensation; (b) with proposed compensation.

Fig. 12. Detail of the dynamic response of dead-time compensation scheme.

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G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 13. Frequency spectrum for the operation under 25 kHz switching frequency: (a) before compensation; (b) after compensation.

Table 4 Fig. 12 shows the transient behaviour of the output current when
Harmonic current based on theoretical analysis and experimental results. the proposed algorithm is enabled. This waveform was obtained under
Order of harmonic Magnitude of current a fs = 25 kHz switching frequency operation. The waveform presents a
small overcurrent and the dead-time effect is fully compensated in
Theoreticala Experimental approximately one period after the proposed is enabled. Fig. 13(a) and
(Eq. (9)) (Fig. 13) (b) show the harmonic spectra for the phase “a” current before and after
5th 0.94 A 0.91 A
the start of the dead time compensation. Note that the fifth and seventh
7th 0.36 A 0.33 A harmonics have their magnitudes decreased, as expected by the theo-
retical analysis. The THD is reduced from 14% to 2.67% complying the
a
Values multiplied by attenuation of current closed-loop transfer function requirements of IEEE-1547 [19].
given in Fig. 14. Table 4 presents a comparison between the experimental values
obtained from Fig. 13(a) and harmonic currents calculated using (9).
increased. This behaviour is due to the fact that the relative weight of The small difference between theoretical and experimental results
the time-delays increases with the reduction of switching period Ts. corroborates to the validation of the mathematical model. Experimental
From (5), and considering the parameters given in Tables 1 and 2, the results are obtained using a closed-loop current controller. Therefore,
distortion voltage ΔV increases from 18.08 V to 22.59 V when the its influence should be taken into account during the analysis. Fig. 14
switching frequency goes from 10 kHz to 25 kHz, respectively. shows the Bode Diagram of the closed-loop current controller, high-
The comparison between the left and right plots of Fig. 11 shows lighting the attenuation in fifth and seventh harmonic components.
that the proposed compensation method improves the waveforms of the These attenuation need to be considered in the harmonic component
current synthesized by the converter, reducing its total harmonic dis- calculation of the output current.
tortion (THD). Nevertheless, although the switching frequency reduc- The current controller closed-loop transfer function is designed to
tion decreases the magnitude of the distortion voltage ΔV, it increases behave as a first order dynamic system, as follows
the output current commutation ripple.

Fig. 14. Closed-loop current controller frequency response.

9
G.A. Fogli, et al.
Fig. 15. Phase “a” grid-voltage (Channel 2) and VSC-current (Channel 1) waveforms for id* = 0 A and iq* = 7 A and considering different switching frequencies for
the converter: (a) without dead-time compensation; (b) with proposed compensation.
*
idq 1 and ωo = 2π60 rad/s.
Gi,CL (s ) = = ,
i dq 1 + is (12)
where τi is the chosen closed-loop time constant. A trade-off between
fast response and attenuation characteristics is important when
choosing an adequate time constant. Yazdani and Iravani [17] suggest a
value between 0.5 ms and 5 ms. In this paper τi was chosen equal to
1.25 ms.
Finally, to analyse the proposed compensation effectiveness under
different operation modes, the system is tested under active power
consumption and reactive power compensation. Figs. 15 and 16 show
the phase “a” grid-voltage and the converter output current when the
VSC compensates reactive power and drains active, respectively. Again,
the results are shown for three different switching frequencies. The
comparison between the left and right columns demonstrates that the
proposed compensation strategy effectively reduces the output current
harmonic distortion caused the time-delays.
The stability analysis of the proposed compensation method can be
performed redrawing the block diagram of Fig. 6 as shown in Fig. 17(a).
The proportional integral controller, originally designed in dq-reference
frame, was replaced by an equivalent proportional resonant controller
Ci (s ) = kp + ki /(s 2 + o2) in abc–reference frame, as described in [20].
The gains kp = R/τi and ki = L/τi were chosen to guarantee a first-order
dynamic behaviour, as shown in (12), for the VSC current closed-loop,
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Electric Power Systems Research 174 (2019) 105853
To perform stability analysis the signal function shown in Fig. 17
can be replaced by its describing function Yf(A) = 4/(πA) [21], where
A is the amplitude of the input signal. Then, the block diagram can be
redraw as shown in Fig. 17b). According to the Nyquist stability ana-
lysis there will be limit cycles if the equation
1
G (j ) = ,
Yf (A) (13)
is satisfied. Where
H (j )
G (j ) = V [1 N (j )].
1 + Ci (j ) H (j ) (14)
The easiest way to solve (13) is to plot both sides of the equation in
a complex plane and find the intersection points of the two curves as
depicted in Fig. 18. As the curves does not intersect, no limit cycle is
expected. Furthermore, as −1/Yf(A) lies completely outside the Ny-
quist curve the oscillations will vanish [21].
It should be pointed out that the oscillations will disappear re-
gardless of the variations in ΔV. This is due the fact that the relative
degree of the transfer function G(s) is two. Limit cycles only appear if
the relative degree of the linear system is higher than three.
G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 16. Phase “a” grid-voltage (Channel 1) and VSC-current (Channel 3) waveforms for id* = 12 A and iq* = 0 A and considering different switching frequencies
for the converter: (a) without dead-time compensation; (b) with proposed compensation.

Fig. 17. (a) Simplified equivalent control block diagram for phase “a”. (b) Simplified equivalent block using describing function.

5. Conclusions
This work presented a simple and effective dead-time delay com-
pensation for grid-connected converters. Based on lag times and voltage
drop effects, it was possible to model the distortion voltage at VSC's
terminals. The main idea of compensation strategy proposed here
consists of adding the estimated distorting voltage due to the dead-time
to the current controller output signal, reducing the undesired effects of
the commutation time-delays.
The compensation method was tested under different switching
frequencies and operation modes: absorbing or supplying active power
and supporting positive or negative reactive power. Experimental
results were present to validate the proposed scheme. A method to re-
fine the compensation voltage can be used. Although, by only using
datasheet informations, it is possible to effectively reduce the harmo-
nics currents caused by dead-time effect and voltage drops. An im-
portant point is to use the fundamental frequency of current to de-
termine the polarity. Harmonic currents affect the process of estimating
the distorting voltages.
The use of proposed compensation strategy has the advantage of
being independent of the switching frequency. This feature allows op-
erating the converter with higher switching frequencies, limited only by
the physical capacity of the semiconductor devices, without compro-
mising the output current quality. As a consequence, smaller output

11
G.A. Fogli, et al. Electric Power Systems Research 174 (2019) 105853

Fig. 18. Describing function analysis.

filters can be used, reducing the cost, volume and weight of the system.
Further advantages are: independence of the operation mode; in-
dependence of control law used to regulate the output currents (plug-in
characteristic); short transient and the fact the system's stability is not
jeopardized when the compensation loop is added.
Acknowledgements
The authors would like to thank the National Council for Scientific
and Technological Development (CNPq), the Coordination for the
Improvement of Higher Education Personnel (CAPES), the State
Funding Agency of Minas Gerais (FAPEMIG), UFMG and UFJF for fi-
nancial support for the development of this research.

Appendix A. Notch filter transfer function

The transfer function of the notch-filter used by the dead-time compensating algorithm to estimate the fundamental frequency of the VSC
currents is:
s 2 + c2
N (s ) = 2
s2 + s Qb + c (A.1)
where ωc is the cut-off frequency, Q is the quality-factor and ( b / Q ) defines the rejection band width of the filter.
Fig. A.19 shows the notch filter frequency response for ωb = 2πfb, fb = 10 Hz, Q = 0.707, ωc = 2πf1 and f1 = 60 Hz.

Fig. A.19. Notch-filter frequency response.

12
G.A. Fogli, et al.
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