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  • Wavekit API For Log Generation PDF

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    vpsampath
    76 vues15 pages
    The document discusses generating logs in Verilog for debugging purposes. It describes running logs during simulation for functional debugging but they have limitations due to language and performance issues. Post-run logs generated after simulation using a Wavekit API can access non-dumped state, use various programming languages, and have faster debugging without re-running simulations. Post-run logs comprise functions to manipulate the reconstructed simulation state and extract signal values and metadata.

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    Wavekit API for log generation.pdf

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    The document discusses generating logs in Verilog for debugging purposes. It describes running logs during simulation for functional debugging but they have limitations due to language and performance issues. Post-run logs generated after simulation using a Wavekit API can access non-dumped state, use various programming languages, and have faster debugging without re-running simulations. Post-run logs comprise functions to manipulate the reconstructed simulation state and extract signal values and metadata.

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    © All Rights Reserved
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    76 vues15 pages

    Wavekit API For Log Generation PDF

    Transféré par

    vpsampath
    The document discusses generating logs in Verilog for debugging purposes. It describes running logs during simulation for functional debugging but they have limitations due to language and performance issues. Post-run logs generated after simulation using a Wavekit API can access non-dumped state, use various programming languages, and have faster debugging without re-running simulations. Post-run logs comprise functions to manipulate the reconstructed simulation state and extract signal values and metadata.

    Droits d'auteur :

    © All Rights Reserved
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 15

    Reconstruct hardware simulation state

    - Functional debug
    - Performance correlation
    - Power analysis

    Aman Mehra
    - aman.mehra@intel.com
    - June 2019, Santa Clara
    - Intel Confidential
    Why generate logs in Verilog?
    Debug logs
    3 purposes, 2 ways

    3 purposes
    - Functional debug
    - Performance correlation
    - Power analysis

    2 ways
    - Run-time log generation
    - Post-run log generation
    Run-time logs
    Flow diagram
    Run-time logs
    Usage, advantages, drawbacks Usage
    mostly functional debug

    Advantages
    access to non-dumped state

    *Drawbacks*
    language limitations
    no open-source libraries

    slow interactive debug loop


    re-run simulation

    limits what we log


    can slow down simulation
    hard to code complex algorithms
    Run-time logs
    Interactive debug loop
    Run-time logs
    Interactive debug loop

    Slow because,
    simulator in the loop
    takes minutes to hours
    Post-run logs*
    Flow diagram

    *Wavekit API based


    Post-run logs*
    Usage, drawbacks, advantages Usage
    functional, performance, power

    Drawbacks
    non-dumped state unavailable

    *Advantages*
    use c++, python, perl, ruby, cpp, node.js
    concise code, more features

    ultra fast interactive debug loop


    no simulation re-run

    richer (and collated) logs


    no simulation slow down
    easy to code complex algorithms
    *Wavekit API based
    Post-run logs*
    Interactive debug loop

    *Wavekit API based


    Post-run logs*
    Interactive debug loop

    Fast because,
    simulator NOT in the loop
    hour long test takes seconds

    database format
    loads only signals of interest

    *Wavekit API based


    Comprises
    - Functions
    - Reconstructed simulator state
    Comprises Functions to
    - Functions - move to simulation time
    - Reconstructed simulator state absolute
    relative
    event-based
    search-based
    - extract signal values & metadata
    - initialize wavekit
    - modify wavekit’s behavior
    - *much more…*
    State includes
    - important times
    - signal values & metadata
    - and more
    Code looks like Verilog
    - makes it easy to relate to
    Complete documentation
    >> firefox /p/hdk/pu_tu/prd/wavekit/latest/doc/build/html/index.html &

    Aman Mehra
    - aman.mehra@intel.com
    - June 2019, Santa Clara
    - Intel Confidential

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