Computer Architecture

EXCEPTIONS AND INTERRUPTS

 Exceptions and Interrupts
 Exception handling is a programming language construct
or computer hardware mechanism designed to handle the
occurrence of some condition that changes the normal
flow of execution. The condition is called an exception.
Alternative concepts are interrupt, signal and event
handling.

 In general, current state will be saved in a predefined

location and execution will switch to a predefined handler
(subroutine/procedure). Depending on the situation, the
handler may later resume the execution at the original
location, using the saved information to restore the
original state. For example, an exception which will usually
be resumed is a page fault, while a division by zero usually
cannot be resolved transparently. (Wikipedia)
 Common Exceptions
 I/O Device Request
 Integer Arithmetic Overflow
 FP Arithmetic Anomaly
 Page Faults
 Memory Protection Violation
 Undefined Instruction
 Power Failure
 etc
 Characterizing Exceptions

 Synchronous vs. Asynchronous

 User Requested (system calls)/coerced
(mouse click)
 Maskable vs. Non-maskable
 Within / Between Instructions
 Resume-able/Terminate
 Resumable

 Shut pipeline by converting all instruction

after the instruction causing exception to
NOP
 Save processor state
 Call Handler
 Resume State

 Precise Exception ???

 Within vs.
Synchronous vs. User request vs. User maskable Resume vs.
Exception type between
asynchronous coerced vs. nonmaskable terminate
instructions
I/O device request Asynchronous Coerced Nonmaskable Between Resume
Invoke operating
Synchronous User request Nonmaskable Between Resume
system
Tracing
instruction Synchronous User request User maskable Between Resume
execution
Breakpoint Synchronous User request User maskable Between Resume
Integer arithmetic
Synchronous Coerced User maskable Within Resume
overflow
Floating-point
arithmetic
Synchronous Coerced User maskable Within Resume
overflow or
underflow
Page fault Synchronous Coerced Nonmaskable Within Resume
Misaligned
Synchronous Coerced User maskable Within Resume
memory accesses
Memory
protection Synchronous Coerced Nonmaskable Within Resume
violation
Using undefined
Synchronous Coerced Nonmaskable Within Terminate
instruction
Hardware
Asynchronous Coerced Nonmaskable Within Terminate
malfunction
Power failure Asynchronous Coerced Nonmaskable Within Terminate
 MIPS Interrupts

 IF – Page Fault, Mem Prot Violation

 ID – Undefined or Illegal Op Code
 EX – Arithmetic
 MEM – Same as IF
 WB – None
MULTIPLE CYCLE
PIPELINES
Single Cycle Computer

(One Big Clock Cycle to Accommodate Longest Latency)

IF ID EXE MEM WB

Single Clock Cycle

 Multiple Cycle Computers

IF ID EX WB IF ID EX WB IF ID EX WB

All Instruction Go through the Processing One-by-One

Classic 5-Stage Integer Pipeline

IF ID EX Mem WB

Almost 1 CPI except for LUD

and Branch Hazards
 A Multiple Cycle Pipeline
Register
File EX
(Integer/FP)

FP ADD
IF ID Mem WB

FP Multiply

Register
Divide File
(Integer/FP)
 FP Pipeline Stages

 Adder, Multiplier, Divider Steps

 Unpack floating point number
 Operand Shift Stage
 A Mantissa Add Stage, Multiply, Divide Stage
 Rounding the result
 Operand shift the result
 Multiple Cycle Floating Point Pipeline
EX

IF ID A A A A Mem WB
1 2 3 4

M M . M
1 2 . 7
Function Unit Latency Initiation
Divide With
forwarding
/Re-Issue
Interval
Integer ALU 0 1
Note:
1.Both FP ADD and SUB use the same A1, A2,-- Pipeline. Load/Store 1 (LUD) 1 (LUD)
2.FP Load/Store go through Integer Pipeline.
FP Add 3 1

FP/Int Multiply 6 1

FP/Int Divide 24 25
Forwarding
ALU/FP
Instructions

EX

IF ID A A A A Mem WB
1 2 3 4

M M . M
1 2 . 7

Divide
 Example 1
1a, FP ALU to ALU
Without Forwarding
ADD.D F10, F11, F12 IF iD A1 A2 A3 A4 ME W
M B
ADD.D F0,F1,F10 IF ID ID ID ID ID ID A A2
1

With Forwarding (needs multiplexer)

ADD.D F10,0(R2) IF iD A1 A2 A4 M W
A3 IF
E B
M
ADD.D F0,F1,F10 IF ID ID ID ID A1
 Example 1b FP Load to ALU
Without Forwarding (ID stall, waiting to be written in register file)
L.D F10,0(R2) IF ID EX ME WB
E M
ADD.D F0,F1,F10 IF ID ID ID A1 A2 A3 A M
4 E
M
With Forwarding (to exe stage through mux)

L.D F10,0(R2) IF ID E M W
X E B
E M
ADD.D F0,F1,F10 IF ID ID A1 A2 A3 A4 M
E
M
 EXAMPLE 2, Concurrent use of
different stages
ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME WB

ADD.D F5,F6,F7 IF ID A1 A2 A3 A4 ME WB

With Dependency

W
ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME
B

M W
ADD.D F5,F6,F0 IF ID ID ID ID A1 A2 A3 A4
E B
 EXAMPLE 3 Cannot be pipelined
1 2 3 4 5 6 7 26 27 28

D D D D
DI DI o
I I I I M
DIV.D F0,F1,F2 IF ID V V o WB
V V V V E
1 2 o
3 4 5 24

o D
I I I I
DIV.D F5,F6,F7 IF ID ID o ID
D D D V
o 1

DIV Unit is not Pipelined. So second instruction

waits in ID stage although it is independent.
 Example 4 - Out Of Order Execution
Note All Instructions Independent

L.D F10,0(R2) IF ID EX ME WB
E M

ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME WB
M

ADDI R5, R5, 10 IF ID EX ME WB

E M

Mul.D F9,F6,F7 IF ID M1 M2 M3 M4 M4 M5 M6 M7 ME WB
M

Add R3,R9,R10 IF ID EX EX ME WB
E E M

Sub R7,R8,R10 IF ID ID EX ME WB
E M

Out Of Order Completion (delay in 4th instruction as two

instructions cannot be in MEM at same time.
Example 4 - Out Of Order Execution
Note All Instructions Independent

L.D IF ID E M W
X E B
F10,0(R2) E M

ADD.D IF ID A1 A2 A3 A4 M W
E B
F0,F1,F2 M

ADDI IF ID E M W
X E B
R5, R5, 10 E M

Mul.D IF ID M M M M M M M M W
1 2 3 4 5 6 7 E B
F9,F6,F7 M

Add IF ID E E M W
X X E B
R3,R9,R10 E E M

Sub IF ID ID E M W
X E B
R7,R8,R10 E M

Out Of Order Completion (delay in 4th instruction as two

instructions cannot be in MEM at same time.
 Example 5 No Data Dependencies

Clock Cycle Number

1 2 3 4 5 6 7 8 9 10 11

Mul.D F0,
F1, F2
Add R1, R2,
R3

SUB R5,
R6,R7
Add.D F4,
F5, F6
OR R10,
R11, R12
AND R20,
R21, R22
L.D F0,
0(R5)
 Example 5

Clock Cycle Number

1 2 3 4 5 6 7 8 9 10 11

Mul.D F0, IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB

F1, F2
Add R1, R2, IF ID EX MEM WB
R3

SUB R5, IF ID EXE MEM WB

R6,R7
Add.D F4, IF ID A1 A2 A3 A4 MEM WB
F5, F6
OR R10, IF ID EXE MEM WB
R11, R12
AND R20, IF ID EXE MEM WB
R21, R22
L.D F0, IF ID EXE MEM WB
0(R5)

Structural Hazard in MEM/WB stage (solution next page)

 Example 5 solution
Clock Cycle Number
1 2 3 4 5 6 7 8 9 10 11

Mul.D F0, IF ID M1 M2 M3 M4 M5 M6 M7 ME WB
F1, F2 M
Add R1, R2, R3 IF ID EX ME WB
M
SUB R5, R6,R7 IF ID EX ME WB
E M
Add.D F4, IF ID A1 A2 A3 A4 A4 MEM WB
F5, F6
OR R10, IF ID EXE MEM WB
R11, R12
AND R20, IF ID EXE ME WB
R21, R22 M
L.D F0, IF ID EX EX EXE ME WB
0(R5) E E M

Structural Hazard solution (could be by stalling in ID which is easy to implement or in the

very last state as shown but may be difficult to implement. We need a special hardware to
monitor when an instruction is going to complete to avoid structural hazard).
 Example 6 - WAW
1 2 3 4 5 6 7 8 9 10 11 12 13

MUL.D F3,F1,F2

ADD.D F1,F5,F4

ADD.D F3,F9,F12
 Example 6 - WAW

1 2 3 4 5 6 7 8 9 10 11 12 13

MUL.D F3,F1,F2 IF I M M M M M M M M W
D 1 2 3 4 5 6 7 E B
M
ADD.D F1,F5,F4 IF I A A A A M W
D 1 2 3 4 E B
M
ADD.D F3,F9,F12 IF I I I I I I I I A A
D D D D D D D D 1 2

Reg Busy bit in Register File

A particular processor – it waits in ID stage in case of WAW not in WB, Page A-54, Paragraph 2
Example 7
 L.D F4, 0(R2)
 MUL.D F0,F4,F6
 ADD.D F2,F0,F8
 S.D F2,0(R2)
Example 8 - EXCEPTIONS

DIV.D F0,F1,F2
ADD.D F10,F10,F8
SUB.D F12,F12,F14
 Data Hazards

 RAW Hazard
ADD.D F3, F1, F2
SUB.D F5, F6, F3
 WAW Hazard
DIV.D F3, F1, F2
SUB.D F3, F6, F5
 WAR Hazard
DIV.D F3, F1, F2
SUB.D F5, F6, F3 #(F3 may read value from ADD)
ADD.D F3, F6, F7
 Problem A-2 Done on Handouts in the
class
 In doing this or similar problems:
 All stalls including WB structural hazards are
in ID/Last stage.
 WAW stalls are also in ID stage.
 Notice a lot of ID stage stalls?
TOO MANY ID
STAGE STALLS
– SOLUTION?