SLOT - I Analog Electronic Circuits Notes

Semiconductors
Conductors Semi-Conductors Insulators
-./0 1. 3 -.4 1. 3
Copyright @IIT Jammu _EEL304_Susanta Sengupta

Band Diagrams
Conduction Band
Energy (E)
Conduction Band
Eg Band gap
Conduction Band
Eg Band gap
Valence Band
Valence Band Valence Band
Semi-Conductors Insulators
Metals
Semiconducctor - Materials
Intrinsic , p-type and n-type
N-type Intrinsic P-type
Group Group Group

III IV V
B C N
Al Si P
Ga Ge As
In Sn Sb
From a pure semi-conductor p-type and n-type semiconductor materials are made
Terminologies
Fermi energy Level (Ef )
Energy -level above which probability of finding an electron is 0.5 (50%)
OR
Energy -level below which probability of finding a hole is 0.5 (50%)
Intrinsic energy Level (Ei)

Fermi energy level of a pure semiconductor is called Intrinsic energy Level
Conduction –band (Ec)

Energy band level above which ‘free electrons’ exist
Valence –band (Ev)

Energy band level below which valence electrons and ‘holes exist

Terminologies
n: Density of electrons (Number of electrons / !"# )

p: Density of holes (Number of holes / !"# )
$% : Density of acceptor atoms (Number of acceptor atoms / !"# )
$& : Density of Donor atoms (Number of donor atoms / !"# )
In a p-type semiconductor number of holes (p) is equal to $%
In a n-type semiconductor number of electrons (n) is equal to $&
Density / Concentration of electrons (n) in the conduction band determine amount of current
that can flow in a n-type conductor.
Density /Concentration of holes (p) in the valence band determine the amount of current
that can flow in a p-type conductor.

Energy band Diagram of Intrinsic (pure) Semi-Conductor
Conduction Band
!$
Fermi Level
!" , !#
!%
Valence Band
Important Note: All band diagrams are drawn for ‘Electron’ energies => applying negative energy will shift the energy
band upwards and applying positive energy shifts the energy band down wards with respect to the reference level
Energy band Diagram
p-type semiconductor n-type semiconductor
Conduction Band Conduction Band

!%
Fermi Level
!"
!$
!$
Fermi Level
!"
!#
Valence Band Valence Band

Fermi-Dirac Function
Distribution of electrons in various energy bands of a semiconductor follow Fermi-Dirac function given by
$
$ ! " = "'"!
"'"! $+& ()
! " $+& ()
T = 0K
f(E) is a probability density function.
1
Substituting E- Ef , the function gives a value of 0.5 (50%)
"'"! "
*! " − "! > -() , ! " ≈ &' () ≈ &' ()
"'"!
"'"!
1−& ()
! " ≈1−& ()
*! " − "! < 3() ,
"!
"

Density of charge carriers in semiconductor materials
* ","! "! ,")
,
$ ∝ ! " > "' ∝ ( + -. /" = + -.
")
Constant of proportionality is Nc which is called
the density of states
! "
"5 ,"!
"! 3"2
4= 15 + -. …..eq.2,
$ = 12 + -. …..eq.1, Similarly ,
For intrinsic case, ni = n = p

"6 3"2 "5 3"2
$6 = 12 + -. = 15 + -. ……. eq.3
+7. # "! ,"6

"# " = $ = $6 + -.
+7. 9
+7. : "6 ,"!
= 4 = $6 + -.
+7. 9
$4 = $:6

Diffusion Current and Drift current
Diffusion current : Diffusion current is the current flowing inside a diode due to movement of carriers
as an effect of difference in their concentration at two different points in the device. Carriers flow from
higher regions of concentration to lower regions of concentration until equilibrium is achieved.
Equations for diffusion current density :

!"($%&'() = −,-" ."
!/($%&'() = ,-/ ./
-" 0"$ -/ 0%1 $&''23&4" 541''1&5&1"(3 , ." 0"$ ./ 0%1 54"51"(%0(&4" 7%0$&1"(3
Drift current : Drift current flows as a result of net motion of charge carriers due to application of
external electric field.
Resistivity / conductivity of a bulk semi conductor material is determined by its drift velocity.

Drift current
!"#$%& = () (drift velocity)
∆+
= !"#$%& = ()
∆&
, = -)
/ ∆1
,. = = ("#$%& 34##5.& "5.6$&7)
0 ∆&0
∆1 = 1.×:;+4<5
∆1 = 1.×∆+0 = 1.!" ∆&0 = (. )∆&0
/ ∆1
,. = = = 1.(. )
0 ∆&0
,. = 1.(. )
Similarly
,= = 1=(= )
,&;&>+ = ,. + ,= = 1=(= + 1.(. ) = -)
A
- = 1 =(= + .(. - Conductivity , @ = - Resistivity
- Sengupta
Copyright @IIT Jammu _EEL304_Susanta
At T = 0 K (room temperature)
P N
Egap = "#$
P N Electrons (ND)
Conduction Band (CB)

%'
%&
%(
Valence Band (VB)

Holes (NA)
Mobile hole Fixed negative ion
Mobile electron Fixed positive ion

At T = -273 K (room temperature) Without Bias
P N
E = "#$ (buit-in potential)
P N
"#$
CB
Electrons (ND)
CB
%&
%'
%(
(VB) (VB)
Holes
Holes(N(N
A) A)
w (VB)
Mobile hole Fixed negative ion "#$
Mobile electron Fixed positive ion

Forward Bias Flow of electrons
E = "#$ − &' P N
P N "#$ - VD
CB Electrons (ND)
CB
()+
()*
(VB) (VB)
Holes (NA)
"#$ - VD
Mobile electron VD Fixed negative ion

Mobile hole Fixed positive ion
Copyright @IIT Jammu _EEL304_Susanta Sengupta Flow of holes
At T = -273 K (room temperature)
Reverse Bias
P N
E = "#$ + )*
P N CB "#$ + VR
Electrons (ND)
%&' CB
%&(
(VB)
Holes (NA) (VB)
"#$ + VR
VD
Mobile electron Fixed negative ion
Mobile hole Fixed positive ion
Copyright @IIT Jammu _EEL304_Susanta Sengupta At T = -273 K (room temperature)
Diode Current Equation
Forward Bias Current
Without bias : 456 78 9:; <=7>9 − 7@ AB9;@97C> across the
junction
56 is the band gap energy
Number of free electrons for a energy level greater than
DEF
E1 is proportional to ;GH
D(456 ) D4(56 DKL )

N 456 < E < 4(56 − KL ) ∝ ; GH − ; GH
D(45 ) (4KL )
6
N 456 < E < 4(56 − KL ) ∝ ; GH F− ; GH
(4KL )
OL = O88 F − ; GH
Reverse Bias Current

OL = −O88
Distribution of electrons /holes with increase /decrease of energy levels
(CB)
E (CB)
n (CB)
e
r (CB)
g
y
(VB) (VB)
(VB)
L
e
v
e (VB)
l
CURRENTS INSIDE THE DIODE
P N
!$%$&'
!#
!"
!" !#
VD
JUNCTION CAPACITANCE (Cj)
At the junction of P and N type material , there is a region which is depleted of movable charges.
When a voltage is applied across the diode ,in the forward or reverse bias conditions, there is a variation in
the width of depletion region.
Also, there is a variation in the density charges at the edges of depletion regions in the p-type or n-type
$%
regions corresponding to !" = .
$&
This is an incremental capacitor which is similar to a parallel plate capacitor.

(Edges of the depletion region act as parallel plates)
Capacitance per unit area across the junction is given by
!" ./)
=
'()* +,-+ 0( + 02

!" +,%
=
#$%& '()' -$ + -/ E = 0CD (buit-in potential)
At the junction an electric field (E) is crested opposing the
P N
movement of carries across the junction
Normal components of Flux (D) are continuous across the
boundary separating p and n regions.
Also, flux emerging out of a closed surface is equal to the
total charge enclosed (Gauss Law)
From these two conditions
012 -/ = 013 -$ (Charge enclosed)
xp xn
w
! = # $(&). )&
+,- &3
$56& = +,- &.
/01 * & =
./012
$56& /01 $56& &3
&3 = *3,56& =
+,- .
$56& /01 $56& &7
&7 = *7,56& =
+,9 .
$56& /01 ,- ,9
&7 + &3 =
+ ,- + ,:
$56& (&3 +&7 ) + ,- + ,:
$56& /01 ,- + ,: *; − *9 = = (&7 + &3 ).
= (&7 + &3 ) . ./01 ,- ,9
+ ,- ,9
+ ,- + ,: ./01 2 2
$56& = (& + &3 ) &7 + &3 = *; − *9 +
/01 7 ,- ,9 + ,- ,:
&'(
!" /$ =
)* + ),
6..8
&'( 0&'( / /
!" /$ = +
-2 3 4$ 45
-. //0 /−
-.
3&'( ..8
/ /
0-. +
4$ 45
!" /$ =
-
/− 2
-.
!"9
!" /$ =
-2
/−
-.

Transistors
Diode is a two terminal device which is used for switching and rectification purposes.
To design an amplifier we need a control terminal in addition to the two terminals.(three terminal device)
Block diagram of a transistor
INPUT OUTPUT
TRANSISTOR
CONTROL
TERMINAL

Transistors
Bipolar Junction Transistor
Input : Emitter
Output : Collector
Control Terminal : Base
Metal – oxide – Semiconductor
Input : Source
Output : Drain
Control Terminal : Gate
By controlling the base current or gate voltage , the device acts as a amplifier .

BIPOLAR JUNCTION TRANSISTOR
n p n
!# !"
Emitter Base !$ Collector
V BE @IIT Jammu _EEL304_Susanta Sengupta

Copyright
VCB
BJT
Energy – Band diagram Without Bias
p
n n

BJT
Energy – Band diagram With Bias
Flow of electrons
(majority carriers)
456 - VBE
456 + VCB
n p
Flow of holes
(minority carriers) Copyright @IIT Jammu _EEL304_Susanta Sengupta
BJT
Operation
BJT has a n-type or p-type material sandwiched between material consisting of opposite kind of majority
carriers. A p-type material is sandwiched between n-type material (n-p-n) / n-type material is sandwiched
between
p-type material (p-n-p) .
Physically it is like two diodes connected back to back. In this process two p-n junctions are formed (base –
emitter junction) and (base – collector junction)

BJT
Operation (n-p-n)
Active Region : Base – emitter junction : Forward Biased , Base –Collector Junction : Reverse Biased
When negative voltage is applied to emitter electrons are injected into the base and holes are injected into
the emitter region. Part of electrons injected into base recombine with holes in base (Emitter-Injection
efficiency). Holes injected from base to emitter region also recombine with the electrons in the emitter
region. (Base Transport Factor). Majority of electrons are swept into the collector terminal due to the
positive voltage applied to the collector.
Emitter Injection efficiency

123
/=
123 + 153
Base transport factor

12<
:; = 123

n p n
*, *+
!"# !"$
()
'
!&#
!%
Emitter Base *- Collector
V BE @IIT Jammu _EEL304_Susanta Sengupta VCB

Copyright
Relation between IB , IE and IC
!" + !$ = !&
"'(()*+ ,-.* = / = 0. /2
!" = /!&
!3
!" + !$ =
/
!3 = 4!$
/
4=
5−/
8$& 8$&
!" = !77 ) 92 −5 ≅ !77 ) 92

Cut-off Region : Base – emitter junction : Reverse Biased , Base –Collector Junction : Reverse Biased
Saturation Region : Base – emitter junction : Forward Biased , Base –Collector Junction: Forward Biased
Important Points
§ Emitter Region is heavily doped (n+) – Because this is the source of electrons
§ Base is very lightly doped (p-) – To reduce recombination
§ Collector is moderately doped (n) – TO not block the electron flow from emitter to collector terminal
§ Base region is very narrow – To avoid recombination , and to reduce the path of travel of electros in p-
region
§ Collector area is higher than base and emitter – To reduce resistance at the terminal
§ Emitter area is slightly lower than collector

I-V Characteristics
IC
∆%# "&$ = (. ./ "

∆"#$ Forward Active Region
"&$ = (. . "
∆%#
∆"#$
"&$ = (. *- "
Saturation Region
"&$ = (. *, "
Cut-off region "&$ < (. * "
VCE

I-V Characteristics
IC !"# = %. *+ ! !"# = %. *+ !
IC
!"# = %. * ! !"# = %. * !
!"# = %. ') ! !"# = %. ') !
!"# = %. '( ! !"# = %. '( !
VCE
VCE VA

Small Signal Model and Equations
Small-signal equations Base Collector

()*
!" = !$$ %&' (+
,- ;<%
.!" !/ ()* !",1
(+ 23 27
,- = = %&' =
.()* (+ (+
45 45
.!) 5 .!" 6
23 = = =
.()* 6 .()* ,- Emitter
45
.!" (8
27 = =
.("* !",1
Collector
45 45 45
.!) .!) .!"
29 = =6 ≅6 ≅ 627 Base
.(") .(") .("*
Copyright @IIT Jammu _EEL304_Susanta Sengupta Emitter

Dynamics – Capacitive effects
$%
!' = $% - charge transported from emitter to base
&%
*$% $% &% - Travel time
= !, − !' −
*+ &"
*$% $% &" - Recombination time

= !" −
*+ &"
$% !' $% &"
!" = = = => ( =
&" ( (&% &%
As a result of these dynamics we have time dependent effects .Also , junctions capacitances at two p-n
junctions also lead to time domain effects.

#$
B C
&' ()*
!" #" !%

MOSFET
Metal –Oxide – Semiconductor Field Effect Transistor
Understanding Metal – Oxide – Semiconductor Junction (pMOS capacitor)
VG
Metal
Oxide
Semi-conductor
n-type

Band Diagrams – pMOS Capacitor
Without Bias ( VG = 0V ) - Flat Band
*-1,,2#
!%&
!∅# !∅$ !χs
*,
!∅'
*+ *+
*+ ()$'
*&
*. /0
*-

Without Bias ( VG = 0V ) - Flat Band
).2--3,
!"# )*, = 567,# 86.69 :* ,6;29
!Ф, = =:7> *3%-;#:% :* ,6;29
!Ф, !χs &Ф+ !"# = )96-;7:% ?**#%#;@ :* A%+392;:7(CD#E6)
!"+ = )96-;7:% ?**#%#;@ :* G6,# H:%E3-;:7
C.B )-
!∅% &Ф+ = =:7> *3%-;#:% :* G6,#-:%E3-;:7
)*, )*+ = & )- − )*+ + &"+
&'(%
)/# )#
)/+ /1 !∅% = )- − )* :* +6,# -:%E3-;:7
). &'(% = )* − )# :* +6,#-:%E3-;:7
V.B )/# = (2%E /2K :* #%+392;:7
)/+ = (2%E /2K :* +6,#-:%E3-;:7
Assumptions : Work functions semiconductor and metal are equal (Ф, − Ф+ ) = 0

Oxide
Copyright @IIT Jammu has infinite
_EEL304_Susanta resistivity / no free charges
Sengupta
V.B
With Bias ( VG > 0 V ) – Accumulation
VG > 0 V
• Oxide layer is a dielectric material between metal
Metal and semiconductor materials and behaves as a
Oxide dielectric layer between capacitive plates .
• When a positive voltage is applied at contact point

(gate terminal ) , positive charges get accumulated
on metal side of the oxide .
Semi-conductor
• Due to this effect, Electrons which are majority
carriers in the n-type material get accumulated on
the semiconductor side of the oxide
n-type

Accumulation
'(%
∆∅ '()
*Ф)
'Ф# !$
∆∅
!"
( VG > 0 V ) !%
!"#
!&

With Bias ( VG < 0 V ) – Depletion
VG < 0 V
• When a negative voltage is applied at contact point (gate

Metal
terminal ) , negative charges get accumulated on metal side
Oxide of the oxide .
• Due to this effect, electrons in n-type semiconductor get

repelled away from the oxide –semiconductor junction.
Semi-conductor • As a result the n-type region next to oxide layer gets

depleted from charges . A depletion region is formed.
n-type • By lowering the voltage further little bit region width of

depletion region increases

Depletion
'(%
∆∅ '()
'Ф# *Ф)
∆∅ !$
!"#
( VG < 0 V )
!"
!%
!&

Band Diagrams – MOS Capacitor
With Bias ( VG < 0 V ) – Inversion
VG < 0 V
• When the negative voltage is further lowered below a

threshold voltage (VT ) at contact point (gate terminal ) , the
material begins to turn to p-type material.
• As the magnitude of VG is increased holes are generated and

keep forms a layer/channel of holes next to the oxide layer
Semi-conductor
• n-type material is converted to p-type material by applying
negative voltage. This process is called inversion
n-type

Depletion
'(%
∆∅ '()
'Ф# *Ф)
∆∅ !$
!"#
( VG < 0 V )
!"
On-set of inversion
!%
!&

Inversion
&'#
2∆∅
&'( )Ф(
&Ф.
2∆∅
!"
( VG < 0 V )
!$
∅$
∅$ !
#
!%
+Q
xd
-Q
x (E(x))Sengupta
Copyright @IIT Jammu0_EEL304_Susanta
Inversion
% = '( (charge density)

+Q
xd charge distribution along
metal-oxide-semiconductor
Copyright 0
x
-Q @IIT Jammu _EEL304_Susanta
(E(x))Sengupta junction
Calculation of Threshold voltage for inversion
%& '%#
67 ! = !# $ () = *+ (Initial electron concentration when material is n-type )

%# '%&
, = !# $ () (Hole concentration after inversion)

.∅&
*+ = ! = !# $ ()
∆69: ∅& =
() *
/! + (energy for the onset of inversion)
. !#
∅0
∅0 = 2∅& (energy for complete inversion )
67 = ∆69: + ∅0 Charge in the inversion layer
+Q
xd
-Q 0
x (E(x))
Charge at the surface of metal
∆∅4" = 54" !4"

$%& " − "(
! " = &*+ = &4"
)*+
)*+ !*+ = )4" !4"
−$%& "(
!,-" =
)*+
" 0 )*+ !*+ 0$%& )*+ ∅*
$%& " − "( !4" = =
∅ " = − / ! " (" = )4" )4"
"( 0)*+
54"
$%& "0( ∆∅4" = 0$%& )*+ ∅*
)4"
∅* =
0)*+
0$%& )*+
∆∅4" = ∅*
0)*+ ∅* 64"
"( =
$%&
0$%& ∅* )*+
!,-".2+ =
)*+

#$%& '()
!=
*+,
∆∅+, = ! ∅(
/01 = ∆∅+, + ∅( = ! ∅( + ∅( = ! #∅3 + ∅3 = /54+
7
∅6( = Ф − ∅(
$ 6
:(( :,
/4+ = ∅6( − − + /54+
*+, *+,
/4+ = /;< + /54+
:)=>
= *+, /0 − /4+
?
:)=> = @A*+, /0 − /4+
As a consequence of inversion , a layer ofCopyright

holes @IIT
(pmos ) and
Jammu electrons
_EEL304_Susanta (nmos ) is formed in a MOS configuration
Sengupta
3- terminal control device – MOSFET - nmos
!"# − !% > !'# (Linear Region)
!"#
!'#
!# =0
metal
oxide
Source n-channel Drain
p -substrate

3- terminal control device – MOSFET - nmos
!$# − !& < !"# (pinch-off)
!$#
!"#
!# =0
metal
oxide
Source n-channel Drain
p -substrate

N-MOS Current equation
!" = $% & "*

-+ = $% 2/01 *3, − * 1 − *5
( () "1
'= = ( *+,
!" $% *+,
: -+ "1 = : $% 2/01 *3, − * 1 − *5 "*
. $% /01 2 ; ;
-+ = = *3 − *5 *+,
' ( )
*+,
* 1
.(1) -+ ( = $% 2/01 (*3, −*5 )*(1) − <
= /01 *3, − * 1 − *5 )
8 ;
"9 = 2/01 *3, − * 1 − *5 "1 Linear $% 2/01 *+, )

-+ = (*3, −*5 )*+, −
"1 "1 "1 "1) Region ( )
"' = = = =
!" $% & $ "* $% "* 2=>% *+, = *3, − *5
% "1
"9 2/01 *3, − * 1 − *5 "1

-+ = = Pinch off/ $% 2/01
"' "1) -+ = *3, − *5 ?
Saturation )(
$% "* Copyright @IIT Jammu _EEL304_Susanta Sengupta
Region
I-V Characteristics
"#$ ≤ "&$ − "- "#$ ≥ "&$ − "-

ID
∆%# "&$ = ,"

∆"#$ Saturation/Pinch-off
"#$ = "&$ − "-
Region
"&$ = +"
∆%#
∆"#$
"&$ = *"
Linear/Triode Region
"&$ = )"
Cut-off region "&$ < "-
VDS

MOSFET Small signal equations
E=
$% &'() 5!" =
!" = (-./ −-1 )* D( = =
*+ 5-/7 F!"
+G<< = +H − IH -"/
5!" $% &'() &
34 = = -./ − -1 = *$% '() ! $% &'()
5-./ + + " !" = (-./ −-1 )*
*+G<<
5!" $% &'() 5-1
346 = = -./ − -1 = 34 8 5!" $% &'() HIH !" HIH
5-7/ + 5-7/ = (-./ −-1 )* =
5-"/ *+G<< H-"/ +G<< H-"/
-1 = -1( + : *∅< + -/7 − *∅< !"
-@ =
5!"
5-1 : = *>?@ ABC 5-"/
−8 = − =− =
5-7/ *∅< + -/7 '() *∅< + -/7 = !" +G<<
-@ = = =
F(+) 5!" HIH
346
8= 5-"/ H-"/
34

N-MOS Small signal Model

Capacitance
!"#
!$#
!#
%&'
n-channel
Source Drain
dx %()

Channel Capacitance
!"# = % &'
&' = (&)*+) ,-. − , ) − ,0 ,-. 8,0

45 (*+) 7 − ,-. − , ) − ,0 ;
&' &, !"# = <
12 = = 45 (*+) ,-. − , ) − ,0 12 ;
&3 &) 6
&, 45 (*+) 7 (,-. −,0 )

12 = 45 (*+) ,-. − , ) − ,0 !"# =
&) ;45 (*+)
(,-. −,0 )7
7?
&,
&) = 45 (*+) ,-. − , ) − ,0 7
12 !"# = *+) (?(,-. −,0 )
;
!"# 7 ,-. 8,0
45 (*+)
% &' = % ,-. − , ) − ,0 &, 7
6 12 6 *"# /: = *
; +)

High –Frequency Model
G !"$
D
!"# %$
"& '"#

Slides from Susanta to cover the following Topics:
Channel Formation
Fabrication
Large Signal – DC currents
Small signal
Equivalent model
Example circuits

Diode
metal metal
SiO2
n+ p+
p-substrate
• Can we add a control gate to make it a transistor?

© Susanta Sengupta
NMOS Transistor D
G Sub
GATE (G)
SUB SOURCE (S) DRAIN (D)
metal
metal metal
Poly Silicon gate
metal S
SiO2
p+ n+ n+
p-substrate

© Susanta Sengupta
PMOS Transistor S
G
B
GATE (G)
SUB BULK (B) SOURCE (S) DRAIN (D)
metal
metal metal metal
Poly Silicon gate
metal D
SiO2
p+ n+ p+ p+
n-well
p-substrate

© Susanta Sengupta
NMOS Transistor Vd=0
Vg=0
Vd=0 Vg=0
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• Assume source (S) and p-substrate (SUB) are shorted together to GND.
• Assume we start with Vg = 0 and Vd = 0 (thus all terminals are at GND)
• The channel between S and D is full of holes. Where as, the S and D are full of electrons. We don’t expect any drain
current to flow here. But, we have two diodes we need to watch out for - one from S-SUB and the other from D-SUB.
Given 0 voltages on all terminals, we don’t expect any diode reverse saturation currents.

© Susanta Sengupta
NMOS Transistor Vd
Vg < VT
Vg<VT
Vd
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• Let’s call VT as the “threshold voltage” that we are commonly used to calling it when the MOS device turns on. Let’s try to
understand what does it mean.
• As we increase Vg, a voltage drop Vgs starts to develop across the SiO2. This causes a vertical electric field inside SiO2 that
starts to attract electrons from the p-substrate.
• This Vgs tends to start lowering the barrier at the S-channel junction such that electrons can be injected into the channel.
• We have a thin film of electrons injected from the Source end. Now, if we apply a small Vd, electrons start flowing from
source to drain terminal.
© Susanta Sengupta
NMOS Transistor Vd
Vg > VT
Vg>VT
Vd
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• As you can see,Vg is acting as a control voltage to turn on the channel

• As we increase Vg more, there comes a point where the drain current becomes almost 1 uA. This used to be the metric to
define VT where the gate voltage is enough to sustain 1 uA drain current. The MOS device equations have become much
more complicated now and there really isn’t a well define VT point anymore (courtesy BSIM models)
• As we increase Vg further (>VT), more and more electrons are injected from the source side and the channel becomes
more rich with electrons, thus causing an increase in drain current.
• We now have a linear resistor formedCopyright
with electrons from source-channel-drain. Holding Vgs constant, as we increase Vds,
@IIT Jammu _EEL304_Susanta Sengupta
we would expect the current to increase linearly (Ohm’s law). This is referred as “linear” region of MOS operation.
© Susanta Sengupta
MOS Linear Region
Ids
SATURATION Vgs
LINEAR
•Resistor
/ •Switch
K
0 Vd(sat)
Vds
~ (Vgs-VT)
• In linear region, it is just acting like an “n-type” doped resistor. The resistance is primarily due to how many electrons are
formed in the n channel.
• When Vgs is small, less electrons means higher resistance. As we increase Vgs, more electrons are in the channel and thus
the resistance goes down. Copyright @IIT Jammu _EEL304_Susanta Sengupta
© Susanta Sengupta
NMOS Transistor Vd
Vg> VT
Vg>VT
Vd
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• But, the process of current increase with Vds can not go on indefinitely and soon, a saturation effect kicks in where the
channel gets “Pinched Off”. For higher values of Vds, it causes a significant “horizontal” electrical field near the drain region.
• As it gets large, the electrons traveling through this region suffer from velocity saturation (their speed gets maxed out). This
causes the drain current to become almost constant over Vds, and this region is called the “saturation” region.
• Thus, we can summarize two key effects:
1. Turning ON of the channel is dependent on Vgs (and not so much on Vds).
2. For a certain Vgs, as we increase Vds, the channel first acts as a linear resistor and then the current gets saturated for higher
Vds values. © Susanta Sengupta
NMOS Transistor Vd
Vg> VT
Vg>VT
Vd
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• Next, as we increase Vgs further, we expect more injection of electrons into the channel from the source side.
• This increases the current in the “linear” region. With more carriers, the conductivity of the channel goes up.
• Again, as we hold Vgs constant and increase Vds, we will run into a velocity saturation effect which will limit the drain
current in the “saturation” region.

© Susanta Sengupta
MOS Drain Current
Ids
SATURATION Vgs
LINEAR
•Resistor •Current source

/ •Switch •Amplifier load (for gain)
K /
K
0 Vd(sat)
Vds
~ (Vgs-VT)
•In saturation, it has square law dependency on Vgs
• Channel length modulation effect in the saturation region - the drain current varies slightly with Vds and is not completely
constant as one might expect.
© Susanta Sengupta
MOS Drain Current
Vgs3
SATURATION
Ids
Vgs2
LINEAR
Vgs1
0
Vds

© Susanta Sengupta
MOS Drain Current (Long vs Short Channel Length)
Short channel
Ids
Long channel
LINEAR SATURATION
• In short channel devices, there isn’t a prominent saturation region

• Vds has a strong effect on the formation of the channel as also the
drain current in the so called saturation region
• Even in saturation region, they act almost like resistors (current is
proportional to Vds).
• Just to give an idea on how bad the Early voltages are - using long
channel devices, one can get >50V where as with very short
channel (like 28nm), they fall below 1V.
• One of the key takeaways - when doing analog design, avoid short
channel lengths at places where you require good current source
or gain.... more on this later.
0 Vd(sat)
Vds
~ (Vgs-VT)
© Susanta Sengupta
MOS Drain Current (Small vs Long channel lengths)
L=28nm
L=1um
Vds
• As we talked about previously, for very short channel lengths, one can’t make out between linear and saturation
regions. It all looks like a linear resistor.
© Susanta Sengupta
Some Key Formulae
• For hand calculations, we will use these simple formulae to determine W/L of the MOS devices.
• These are true for long channel devices only, so when using shorter channel lengths, they provide
an initial starting point that needs to be refined through simulation
• In saturation,
• Make sure Vds > (Vgs-VT) + 100mV, this will ensure the device remains in saturation.
• To calculate W/L for a certain drain current Id and a certain (Vgs-VT) (also called a gate overdrive
voltage), we can use the formula below
• For example, if
• Id = 100uA,
• K’ = 200uA/V^2,
• (Vgs-VT) = 0.2V
• W/L = 25

© Susanta Sengupta
NMOS Transistor in Weak Inversion Vd
Vg<VT
Vg<VT
Vd
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• What happens when Vgs < VT, which is often referred to as “weak inversion”? The MOSFET acts like a Bipolar device (BJT)
• The channel is weakly inverted but the drain current is not 0 (but some small value). Here also, we have the same two
regions of operation - linear and saturation regions.
• Folks often tend to get confused here with the region of weak inversion. Remember, it is very similar to the previous
discussion of Vgs>VT (strong inversion region) - it has a linear region and a saturation region

© Susanta Sengupta
MOS Drain Current (strong and weak inversion)
SATURATION
Vgs3 (strong inversion)
Ids
LINEAR
Vgs<VT (weak inversion)
0
Vds
• In weak inversion, the slope of current over Vds, in the so called saturation region, is larger.
© Susanta Sengupta
NMOS Transistor in Triple Well D
G B
?
G Sub
SUB ? B S D
metal
metal metal metal metal
Poly Silicon gate
metal S
SiO2
p+ p+ n+ n+
n+
p-well
DNWELL (Deep n-well)

• Different flavors of VT like
eLVT, LVT, SVT, HVT, eHVT.
Different wells are needed to
control doping of these devices.
• Helps avoid body effect p-substrate

© Susanta Sengupta
NMOS Transistor with BODY Effect
Vg
Vs (not 0) Vd=0
SUB S
GND(0 V) metal
metal metal metal
Poly Silicon gate
SiO2
p+ n+ n+
p-substrate
• Assume we had a case where the source terminal of the NMOS device is not at GND (but the p-substrate is grounded).
• The diode is further reversed biased (n side at the source terminal is at positive voltage while the p-substrate is at
GND).
• Now, to turn on the channel, we need an even bigger Vg than before as we have to overcome the initial reversed biasing
due to Vs voltage.
• This causes an increase in the threshold voltage (VT) of the MOS device. It has other implications that we will study later.
© Susanta Sengupta
How to Extract /
K VT VA
VT
• It can be extracted straight from the simulator.
• Note various VT values vs channel lengths
VA L=28nm
• The Early voltage term can be extracted from a
plot like shown.
1. Take the device (say NMOS) of the desired channel
length.
L=1um
2. Ground the source terminal. Apply a DC voltage a
gate such that Vgs is 200mV above VT.
3. At drain, put a DC source and sweep it from 0 to
VDD. Plot the drain current going through this DC
source. It would look something like the yellow plot
(this is for L = 28nm).
4. If we extended the yellow line all the way back to
find “x” intercept, we will get ~ (-0.7)V. This is the
Early voltage term for this device.
5. One can also take an operating point, say at 0.7V
and from the simulator, print “dc operating points”.
It will give “Ids” and “rds”. Early voltage is simply the
product of these two terms.

© Susanta Sengupta
How to Extract /
K VT VA
/
K
• Now that we know VT and VA, we can find K/
• The drain current equation is as follows:
/ W 2 VDS
Ids = K ( VGS - VT
)(1 + )
2L VA
L=28nm
• We can now extract /
K
• Make sure you do it for different channel lengths
and see if they match up. / is teh product of
K oxide capacitance
mobility and Cox. While the
L=1um
term would not vary over channel length,
mobility suffers degradation as channel length
reduces and we should be able to see that effect.

© Susanta Sengupta
Going to the Simulator
• Simulation is a key part of design today - but first, we should do designs on paper before jumping
to the simulator
• Cadence tools are mostly used in the industry. Here, we will focus on their “schematic capture”
tool and for simulation, it will be ADE (Analog Design Environment) tool. Shown below are two
sample pictures for these two tools.
Schematic capture
ADE tool
tool

© Susanta Sengupta
NMOS connected as a diode
• First, we will take a simple NMOS
device and DC bias it.
• The NMOS device is connected as a
diode and a bias current of 100uA is
pushed through it.
• Question - how would you calculate
the W/L of the NMOS device?

© Susanta Sengupta
MOS Small-signal model

MOS Small-signal Model
• As you will find out later, most of the time, we operate the MOS device in saturation.
• While its in saturation, what happens when we cause a “small change” in the Vgs? How does the
drain current change?
• We can always write the square-law equation for the drain current and solve for it, but it will
quickly become cumbersome to solve these equations if we had many MOS devices in a circuit.
• That’s when we derive a “linear small-signal” model for the MOS device and it is much easier to
solve for multiple devices in a circuit.
Vgs + V
Vgs
Id
Ids Vgs - V
Id
SATURATION

0
MOS Small-signal Model
• Let’s start with the equation of the drain current in saturation
• To capture the effect of small changes in Vgs on Id, we derive gm (transconductance) as the
derivative of Id with respect to Vgs
•
• We also know that Vds has a slight effect on the drain current - increasing Vds causes an increase in
the drain current. We can model it as a linear resistor whose value could be found by taking
derivative of drain current with Vds.
• Small signal change in id can be given as ..... where vgs, vds are small signal
changes from DC quiescent values
id D
G
D
G vgs rds
gm.vgs
S S
© Susanta Sengupta
Some Key Formulae
Large Signal Small Signal
2I D
gm =
( VGS - VT )
VA
rds =
ID

© Susanta Sengupta
gm vs Ids
• Let’s look at an important relationship between gm and Ids.
• If you knew a certain value of gm that was needed, how can you quickly back calculate an
estimated value for Ids?
• Typically, if we assume we would operate a MOS device in strong inversion where
( VGS - VT ) ~ 0.2V
2I ds
gm =
( VGS - VT )
gm ~ 10 I
• If we wanted more gmdsfor the same drain current, we will need to increase W/L. It will help
increase gm and the device will also start to go from strong inversion in weak inversion.
• In such a scenario, the MOS device will start to act like a bipolar device whose drain current has an
exponential dependence on Vgs.
( VGS - VT ) < 0.2V
I ds
gm ~
2Vt
gm ~ 20 I ds

© Susanta Sengupta
Some Key Concepts
• DC bias voltage = small-signal wise, it is 0 V, and we VDD
call it “AC ground”
R1
DC voltage = AC ground
Vout
VDC
M2
vin M1
• A DC current source = 0 ac small-signal current
• Always look for small-signal voltages at G and S
terminals

© Susanta Sengupta
Simple Amplifiers
Applying small-signal model to them

Example Circuit #1
• This is a CS amplifier
VDD
• Find its gain
Ibias
• I would like for you to NOT draw out the
small-signal model OR write small-signal
equations to solve for gain !! Vout
vin M1
gm, rds

© Susanta Sengupta
Circuit 1

Example Circuit #2
• CS amplifier
VDD
• Find gain
R1
Vout
vin M1
gm, rds

© Susanta Sengupta
Circuit 2

Example Circuit #3
• CG amplifier
VDD
• Find gain
R1
Vout
VDC
M1
gm, rds
vin
Ibias

© Susanta Sengupta
Circuit 3

From the equivalent circuit,
If gmrds >> 1 then

Av~ gmR1
Example Circuit #3
• We will design this circuit on paper and find
out the values of R1, W/L, VDC and Ibias. VDD
• Assume
• VDD=1.2V R1
• VT = 0.5V
• / = 200uA/V^2 for NMOS Vout
K
• Va = 10V
VDC
• We want from this circuit M1
gm, rds
• Gain = 20dB (10 V/V)
vin
• gm = 20mS (why??)
• Let’s start designing it on paper !! Ibias
• Ibias = ?
• W/L = ?
• VDC = ?
• R1 = ?

© Susanta Sengupta
Example Circuit #3
• Assumptions first - We start with simple
equations and assume we can operate in VDD 1.2V
strong inversion with 200mV of (Vgs - VT).
And, also spare enough Vds across the device
to keep it in saturation. R1 500
• In such a case, we know that gm ~ 10.(Ibias)
• Thus, for gm=20mS, Ibias = 2mA Vout
0.2V
• Next, we can find W/L = 500
VDC
M1 W/L=500
gm, rds =20mS, 5000
vin
• For Av = 10V/V, gm = 20mS, we will need R1
= 500 Ohms. Note that we neglected rds
Ibias 2mA
here, because with Va=10V, Id=2mA, we will
get rds =5KOhms. Thus, it is 10X bigger than
R1 and can be neglected.
• But, here comes the problem - IR drop in R1
will be 1V. This will force DC operating point
at Vout to be 0.2V. This is not enough to
maintain M1 in saturation or allow enough
voltage across the ideal bias current source.
• So, we need to iterate now
© Susanta Sengupta
Example Circuit #3
• We need to reduce the voltage drop across
R1 VDD 1.2V
• Let us cut Ibias to 1mA. To get the same gm,
we can increase W/L from 500 to 1000.
R1 500
• While we do this, we can calculate Vdsat or
(Vgs-VT) again and it will come to around
100mV. This means the device is getting Vout
0.7V
pushed towards weak inversion and the
strong inversion formulae are only
VDC
approximations now - this is still good 0.9V M1W/L=1000
gm, rds=20mS, 10000
enough for a hand design on paper - we will
refine it further in the simulator. vin
• Now, IR drop in R1 is 500mV, which allows 0.3V
700mV to drop across Vds of M1 and across Ibias 1mA
the ideal current source.
• Let us assume we allow Vds = 400mV across
M1 to keep it in good saturation and 300mV
across the ideal current source.
• We can now find VDC as Vgs + DC operating
point at Vin = 0.6V + 0.3V = 0.9V.
• Now, we have a first cut design to take to
simulator
© Susanta Sengupta
Example Circuit #4
• Source follower
• Find gain
VDD
vin M1
gm, rds
Vout
Ibias

© Susanta Sengupta
Example Circuit #5
• Source follower
• Find gain
VDD
vin M1
gm, rds
Vout
R1

© Susanta Sengupta
Circuit 5

BJT transistor ! – equivalent model
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%"#
−""# + − () %*+ = -
&'
%"#
−""# + + () %"# = -
&'
%"# .
=
""# .
&' + ()
.
() = , &' = /&)
&)
%"# /&)
= = 1&)
""# /+1

Circuit 5
/22 /22
B2 C2
-*+,
R R '(# !"# $%&#
$*+, $*+, '*# R $*+,
/%-01 3*+, E2
T2 T2 C1
B1
!") $%&) '*)

$-. '()
$-. $-.
T1 T1
E1

!"#$ %&' '()*+,-'.% /*"/)*%
+0'1 = 3
+#)% = "#4 *#)% − 6$ +0'4 + *#)% "#1
B2 C2 *#)% "81 "#1
−+0'4 = *#)%
+#)% "81 + "#4
"84 6$4 +0'4 "81 "#1
"#4 R +#)% = "#4 *#)% + 6$ *#)% + *#)% "#1
"81 + "#4
E2 +#)% "81 "#1 "#4
C1 = "#4 + "#1 + 6$
B1 *#)% "81 + "#4
+#)% 9"$ "#1 "#4
6$1 +0'1 "#1 = "#4 + "#1 + 6$
"81 *#)% "81 + "#4
:&'. ;1 ,.< ;4 ,"' *<'.%*/,- %",.=*=%#"=
"#1 = "#4 = "# ,.< "81 = "84 = "8
E1
+#)% 9"4#
= 4"# +
*#)% "8 + "#
"# ≫ "8
+#)% 9"4# +#)%

= 4"# + => ≅ 9"#
*#)% "# *#)%
!"# = !%&
B2 C2 '(")"#* + #,-& &./+)",# +) #,-& 012
",/) 012
*3 !"# + + ",/) = 7
(5; (5 // (,
*3; !%&;
(,; R !,/) !,/)
",/) =
8
E2
(5 // (, ≅ (5
B1 C1
−!%&; = 012
*32 !%&2 (,2 012 = !,/) + (, *3 !%& + ",/)
(52
!"# 012 = !,/) + (, −*3 012 + ",/)
(,
E1 012 2 + *3 (, = !,/) 2 +
8
(,
!,/) 2 + !,/)
*3 !"# + 8 + =7
(5 // (, 2 + *3 (, 8

!"#$ −*+ ,(./ // ." )(2+*+ ." )
= .
!&' 42+ "5,+(./ // ." )(2+*+ ." )
,
!" // !% ≅ !"
! + #$ %& ≅ #$ %&
$
!" = $!% =
&%
!"#$ −)* +,- )* ,"
=
!%& + + ," + ,- )* ,"
!"#$ −)* +/,"
=
!%& + + ," + /,"
/+0≅/
!"#$ −)* +/,"
=
!%& + + /,"
!"#$
= −)* (+///," )
!%&
Circuit 6
$++
$++
E2
,-. !%/. 0(.

01.
B2
$%"&' T2 C2
$%"&' T2 "()*
B1 C1
!()*
!()*
,-2 !%/2 0(2
012
!"# T1 3()* !"#
!"# T1 !()*
E1

+9'8 = :
E2
;#. 1'( = "#=
0$8 +9'8 "#8
"38 !"#$ %&' '()*+,-'.% /*0)"'
+*.
B2 1*. = = "3
C2 **.
1'(
*#)%
B1 C1
+#)%
0$4 +9'4 "#4 1#)% = = "#4
"34 *#)%
+*. +#)%
+#)% 5+ = = −0$4 "#4 // 1'(
+*.
E1 +#)%
5+ = = −0$4 "#4 // "#8
+*.

Diode connected BJT
C C B
C B C B
!" #$%
&' &(
&" &' &( ≅ &"
B
E E
E
E

!$$ %&'
!" = !$$
%&" + %&'
*9 *; !" = !&) + %) *) ≃ !&) + *$ %)

%&9 %8
GHI64>33H, !&),/0 ≅ 0.7!
C !$$
*, ≪ ./ 0123145602 *, , *" =
%&" + %&'
B
E </= > ?6@1A *" B1 4>0 ?60A 5C1 D>3E1 /? %&" + %&'
%&:
%) </= > A1.6=1A D>3E1 /? %) B1 4>0 /,5>60 !"
<=/F 5C6. B1 4>0 /,5>60 5C1 D>3E1 /? %&' >0A 5C10 %&"

!"" − #) *) − (!", + #, *, ) = 0
*) 12 34567 42 386 9431:median of the voltages 4)9:22 *)

)4I)JI436K 43 386 6L396M6 67K2 :N 386 I:4K I176
42 28:O7 17 386 N1PJ96
!", + #, *, ≅ #, *, ≅ 2#",% *,
R76 6L396M6 12 O867 #" = 0 , S:J3 = !""

Small signal voltage
swing across R c
R3869 6L396M6 12 O867 #" = 2#",% , S:J3 = 2#",% *,
#" ≅ '#",% !"" − (!", + #, *, )

*" = M1KT:173 :N
#",% (mid point) '#",%
!"" V '#",% *, ) !"" V '#",% *, )

#" ⇒ M1KT:173 #",%
= '#",%
!""
!"
)!!
!!
#"%
#!
!! C
#& !"
!" C B
#& B
E
!' #! #$
E #"%
#$ #"( #'
#"(
#'
!'

ü !" #$ %&' #(%')(*+ )'$#$%*(,' -. %&' $/*++ $#0(*+ $-1),' ,-((',%'2 %- %&' #(31%
ü 4- *5-#2 %&' 67 ,-/3-('(% -. $/*++ $#0(*+ 5-+%*0' #(%').')#(0 8#%& %&' 67 "#*$ , * +*)0' "+-,:#(0
7*3*,#%-) (7B )#$ *22'2 -( %&' #(31% $#2' %- #$-+*%' %&' %8-
A
ü =/3'2*(,' -. 7*3*,#%-) #$ 0#5'( "> ?, =
BC7
ü .-) 67 -3')*%#-( C = 2E. = 0 => ?, = ∞
ü 8&'( 7 #$ 5')> +*%0' .-) *, -) $/*++ $#0(*+ -3')*%#-( *$ 7 → ∞ , ?, → 0
ü J#/#+*)+> *% %&' -1%31% %- ,-13+' %&' $/*++ $#0(*+ *, $#0(*+ %- %&' -1%31% *(2 %- "+-,: 2, ,-/3-(*(%
-. %&' -1%31% $#0(*+ #( #(%').')#(0 8#%& %&' ('K% $%*0' , * ,-13+#(0 ,*3*,#%-) 77 #$ *22'2 %- %&' -1%31%

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Semiconductors

Conductors Semi-Conductors Insulators

Copyright @IIT Jammu _EEL304_Susanta Sengupta

N-type Intrinsic P-type

Group Group Group

Intrinsic energy Level (Ei)

Conduction –band (Ec)

Valence –band (Ev)

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n: Density of electrons (Number of electrons / !"# )

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p-type semiconductor n-type semiconductor

Conduction Band Conduction Band

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For intrinsic case, ni = n = p

+7. # "! ,"6

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Equations for diffusion current density :

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Conduction Band (CB)

Valence Band (VB)

Mobile hole Fixed negative ion

Mobile electron Fixed positive ion

Mobile electron Fixed positive ion

Mobile electron VD Fixed negative ion

D(456 ) D4(56 DKL )

Reverse Bias Current

This is an incremental capacitor which is similar to a parallel plate capacitor.

Capacitance per unit area across the junction is given by

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012 -/ = 013 -$ (Charge enclosed)

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Block diagram of a transistor

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Bipolar Junction Transistor

Metal – oxide – Semiconductor

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Emitter Base !$ Collector

V BE @IIT Jammu _EEL304_Susanta Sengupta

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Emitter Injection efficiency

Base transport factor

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V BE @IIT Jammu _EEL304_Susanta Sengupta VCB

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∆%# "&$ = (. ./ "

Cut-off region "&$ < (. * "

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!"# = %. ') ! !"# = %. ') !

!"# = %. '( ! !"# = %. '( !

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Small-signal equations Base Collector

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*$% $% &" - Recombination time

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!∅# !∅$ !χs

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Assumptions : Work functions semiconductor and metal are equal (Ф, − Ф+ ) = 0

• When a positive voltage is applied at contact point

"9 = 2/01 3, − 1 − 5 "1 Linear $% 2/01 +, )

"9 2/01 3, − 1 − *5 "1