Académique Documents
Professionnel Documents
Culture Documents
ADS7056
SBAS769 – MARCH 2017
• Sonar Receivers (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Optical Line Cards and Modules
• Thermal Imaging Typical Application
• Ultrasonic Flow Meters
• Motor Controls
SONAR TX
• Handheld Radios
• Environmental Sensing AVDD
AVDD used as Reference for
+
AINP
Device
SONAR RX C
AINM
GND
RUG (8)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS7056
SBAS769 – MARCH 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 16
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 19
3 Description ............................................................. 1 9 Application and Implementation ........................ 23
4 Revision History..................................................... 2 9.1 Application Information............................................ 23
9.2 Typical Applications ................................................ 23
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 3 10 Power Supply Recommendations ..................... 30
10.1 AVDD and DVDD Supply Recommendations....... 30
6.1 Absolute Maximum Ratings ..................................... 3
10.2 Optimizing Power Consumed by the Device ........ 30
6.2 ESD Ratings.............................................................. 3
6.3 Recommended Operating Conditions....................... 4 11 Layout................................................................... 31
6.4 Thermal Information .................................................. 4 11.1 Layout Guidelines ................................................. 31
6.5 Electrical Characteristics........................................... 4 11.2 Layout Example .................................................... 31
6.6 Timing Requirements ................................................ 6 12 Device and Documentation Support ................. 32
6.7 Switching Characteristics .......................................... 6 12.1 Documentation Support ........................................ 32
6.8 Typical Characteristics .............................................. 8 12.2 Receiving Notification of Documentation Updates 32
7 Parameter Measurement Information ................ 14 12.3 Community Resources.......................................... 32
7.1 Digital Voltage Levels ............................................. 14 12.4 Trademarks ........................................................... 32
12.5 Electrostatic Discharge Caution ............................ 32
8 Detailed Description ............................................ 15
12.6 Glossary ................................................................ 32
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 15 13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
DATE REVISION NOTES
March 2017 * Initial release.
RUG Package
8-Pin X2QFN
Top View
AINM
8
CS 1 7 AINP
SDO 2 6 AVDD
SCLK 3 5 GND
4
Not to scale
DVDD
Pin Functions
PIN
NAME NO. I/O DESCRIPTION
AINM 8 Analog input Analog signal input, negative
AINP 7 Analog input Analog signal input, positive
AVDD 6 Supply Analog power-supply input, also provides the reference voltage to the ADC
CS 1 Digital input Chip-select signal, active low
DVDD 4 Supply Digital I/O supply voltage
GND 5 Supply Ground for power supply, all analog and digital signals are referred to this pin
SCLK 3 Digital input Serial clock
SDO 2 Digital output Serial data out
6 Specifications
6.1 Absolute Maximum Ratings (1)
MIN MAX UNIT
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP to GND –0.3 AVDD + 0.3 V
AINM to GND –0.3 0.3 V
Input current to any pin except supply pins –10 10 mA
Digital input voltage to GND –0.3 DVDD + 0.3 V
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(1) Ideal input span; does not include gain or offset error.
(2) See Figure 32, Figure 33, and Figure 34 for statistical distribution data for INL, offset error, and gain error.
(3) LSB means least significant bit.
(4) See the OFFCAL State section for details.
(7)
At Isource = 500 µA 0.8 DVDD DVDD
VOH High-level output voltage V
At Isource = 2 mA DVDD – 0.45 DVDD
At Isink = 500 µA 0 0.2 DVDD
VOL Low-level output voltage (7) V
At Isink = 2 mA 0 0.45
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage 2.35 3 3.6 V
DVDD Digital I/O supply voltage 1.65 3 3.6 V
AVDD = 3.3 V, fSAMPLE = 2.5 MSPS 1050 1250
AVDD = 3.3 V, fSAMPLE = 100 kSPS 48 50
IAVDD Analog supply current AVDD = 3.3 V, fSAMPLE = 10 kSPS 5 µA
AVDD = 2.5 V, fSAMPLE = 2.5 MSPS 750
Static current with CS and SCLK high 0.02
DVDD = 1.8 V, CSDO = 20 pF,
630
output code = 2AAAh (8)
IDVDD Digital supply current µA
DVDD = 1.8 V, static current with CS
0.01
and SCLK high
(5) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale,
unless otherwise noted.
(6) Calculated on the first nine harmonics of the input frequency.
(7) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Parameter Measurement Information
section for details.
(8) See the Estimating Digital Power Consumption section for details.
Sample
A+1
Sample
A tph_CS
tCYCLE
tACQ
tCONV
CS
SCLK 1 2 3 15 16 17 18
tCLK
tph_CK tpl_CK
td_CKDO
tsu_CSCK tht_CKCS
tht_CKDO
tden_CSDO tdz_CSDO
SDO
0 0
-30 -30
-60 -60
Amplitude (dB)
Amplitude (dB)
-90 -90
-120 -120
-150 -150
-180 -180
0 250 500 750 1000 1250 0 250 500 750 1000 1250
Frequency (kHz) D001
Frequency (kHz) D002
SNR = 75.2 dB, THD = –90.25 dB, ENOB = 12.18 bits SNR = 74.3 dB, THD = –87.9 dB, fIN = 250 kHz
-30 -30
-60 -60
Amplitude (dB)
Amplitude (dB)
-90 -90
-120 -120
-150 -150
-180 -180
0 250 500 750 1000 1250 0 250 500 750 1000 1250
Frequency (kHz) D003
Frequency (kHz) D004
SNR = 74.2 dB, THD = –90.25 dB, fIN = 500 kHz SNR = 73.9 dB, THD = –87.1 dB, fIN = 1000 kHz
75 75
SNR, SINAD (dB)
SNR, SINAD (dB)
74 74
73 73
72 72
-40 -7 26 59 92 125 0 250 500 750 1000
Free-Air Temperature (qC) Input Frequency (kHz) D006
D005
Figure 7. SNR and SINAD vs Temperature Figure 8. SNR and SINAD vs Input Frequency
-84
74
-86
73
-88
SNR
SINAD
72 -90
2.35 2.6 2.85 3.1 3.35 3.6 -40 -7 26 59 92 125
Reference Voltage (V) D007
Free-Air Temperature (qC) D008
Figure 9. SNR and SINAD vs Reference Voltage (AVDD) Figure 10. THD vs Temperature
95 -80
Spurious-Free Dynamic Range (dB)
-84
91
-86
89
-88
87
-90
85 -92
-40 -7 26 59 92 125 0 250 500 750 1000
Free-Air Temperature (qC) D009
Input Frequency (kHz) D010
95
Total Harmonic Distortion (dB)
-82
93
-84
91
-86
89
-88
87
85 -90
0 250 500 750 1000 2.35 2.6 2.85 3.1 3.35 3.6
Input Frequency (kHz) D011
Reference Voltage (V) D012
Figure 13. SFDR vs Input Frequency Figure 14. THD vs Reference Voltage (AVDD)
93 24000
21000
Number of Hits
91 18000
15000
89 12000
9000
87 6000
3000
85 0
2.35 2.6 2.85 3.1 3.35 3.6 8188 8189 8190 8191 8192 8193 8194 8195 8196
Reference Voltage (V) D013
Code D014
Standard deviation of codes = 0.94 LSB, VIN = AVDD / 2
Figure 15. SFDR vs Reference Voltage (AVDD) Figure 16. DC Input Histogram
2 2
Calibrated Calibrated
Uncalibrated Uncalibrated
1 1
Offset (LSB)
Offset (LSB)
0 0
-1 -1
-2 -2
-40 -7 26 59 92 125 2.35 2.6 2.85 3.1 3.35 3.6
Free-Air Temperature (qC) D015
Reference Voltage (V) D016
Figure 17. Offset vs Temperature Figure 18. Offset vs Reference Voltage (AVDD)
0.1 1
Calibrated
Uncalibrated
Differential Nonlinearity (LSB)
0.05 0.5
Gain Error (%FS)
0 0
-0.05 -0.5
-0.1 -1
-40 -7 26 59 92 125 0 3300 6600 9900 13200 16500
Free-Air Temperature (qC) D017
Code D019
1.5 0.5
0 0
-1.5 -0.5
-3 -1
0 3300 6600 9900 13200 16500 0 3300 6600 9900 13200 16500
Code D020
Code D021
AVDD = 2.35 V
1.5 0.5
0 0
-1.5 -0.5
-3 -1
0 3300 6600 9900 13200 16500 -40 -7 26 59 92 125
Code D022
Free-Air Temperature (qC) D023
AVDD = 2.35 V
0.5 1.5
0 0
-0.5 -1.5
-1 -3
2.35 2.6 2.85 3.1 3.35 3.6 -40 -7 26 59 92 125
Reference Voltage (V) D024
Free-Air Temperature (qC) D025
1.095
Integral Nonlinearity (LSB)
1.5
-1.5
1.05
-3 1.035
2.35 2.6 2.85 3.1 3.35 3.6 -40 -7 26 59 92 125
Reference Voltage (V) D026
Free-Air Temperature (qC) D027
Figure 27. INL vs Reference Voltage Figure 28. AVDD Current vs Temperature
1200 1200
960 1080
Supply Current (µA)
720 960
480 840
240 720
0 600
0 500 1000 1500 2000 2500 2.35 2.6 2.85 3.1 3.35 3.6
Throughput (Ksps) D028
Supply Voltage (V) D029
Figure 29. AVDD Current vs Throughput Figure 30. AVDD Current vs AVDD Voltage
1500 3500
3250
3000
1200 2750
2500
IAVDD Static (nA)
2250
Frequency
900 2000
1750
1500
600
1250
1000
300 750
500
250
0 0
0
0
5
1
5
2
5
3
-3
-2
-1
.5
.5
.5
-40 -7 26 59 92 125
0.
1.
2.
-2
-1
-0
Figure 31. Static AVDD Current vs Temperature Figure 32. Typical INL Distribution
4000
1000
3500
800 3000
Frequency
Frequency
2500
600
2000
400 1500
1000
200
500
0 0
0
0
6
5
02
03
04
05
-2
-1
.5
.5
.5
.0
.0
.0
.0
.0
0.
1.
2.
3.
4.
5.
0
-2
-1
-0
0.
0.
0.
0.
0.
-0
-0
-0
-0
-0
6000 Devices
6000 Devices
VOH
DVDD-0.45V
SDO
0.45V
VOL
0V
Digital Inputs
DVDD + 0.3V
VIH
0.65DVDD
CS
SCLK 0.35DVDD
VIL
-0.3V
DVDD = 1.65 V to 1.95 V
8 Detailed Description
8.1 Overview
The ADS7056 is a 14-bit, 2.5-MSPS, analog-to-digital converter (ADC). The device includes a capacitor-based,
successive-approximation register (SAR) ADC that supports a wide analog input voltage range (0 V to AVDD, for
AVDD in the range of 2.35 V to 3.6 V). The device uses the AVDD supply voltage as the reference voltage for
conversion of analog input to digital output and the AVDD supply voltage also powers the analog blocks of the
device. The device has integrated offset calibration feature to calibrate its own offset; see the OFFCAL State
section for details.
The SPI-compatible serial interface is controlled by the CS and SCLK signals. The input signal is sampled with
the CS falling edge and SCLK is used for conversion and serial data output. The device supports a wide digital
supply range (1.65 V to 3.6 V), enabling direct interface to a variety of host controllers. The ADS7056 complies
with the JESD8-7A standard for a normal DVDD range (1.65 V to 1.95 V); see the Digital Voltage Levels section
for details.
The ADS7056 is available in 8-pin, miniature, X2QFN package and is specified over extended industrial
temperature range (–40°C to 125°C). Miniature form-factor and extremely low-power consumption make this
device suitable for space-constrained, battery-powered applications.
AINP
CS
CDAC Comparator
SCLK
Serial
AINM
Interface SDO
SAR
SW1 Rs1
AINP
Cs1
GND
V_BIAS
AVDD
Cs2
SW2 Rs2
AINM
GND
During the acquisition process, both positive and negative inputs are individually sampled on CS1 and CS2,
respectively. During the conversion process, the device converts for the voltage difference between the two
sampled values: VAINP – VAINM.
Each analog input pin has electrostatic discharge (ESD) protection diodes to AVDD and GND. Keep the analog
inputs within the specified range to avoid turning the diodes on.
The full-scale analog input range (FSR) is 0 V to AVDD and the absolute input range on the AINM and AINP pins
is –0.1 V to AVDD + 0.1 V.
AVDD
CAVDD
GND
CDVDD
DVDD
PFSC
ADC Code (Hex)
MC + 1
MC
NFSC+1
NFSC VIN
VREF V REF VREF ± 1 LSB
1 LSB 1LSB
2 2
ACQ
or
n
tio
ra
a lib f CS
tC eo -U
p
ffse Edg er
O w
of ng Po
d isi on
En R
Falling Edge of CS
io n
at
l i br
Ca
End of Conversion
OFFCAL
Ca
lib
ra
tio
Op n du
e r ri n
at g
io N
n or
m
al
CONV
CS
SCLK 1 2 3 15 16 17 18
CS
SCLK 1 2 3 4 24
SDO 0 0 0 0 0 0
(1) In addition to the timing specifications of Figure 41 and Table 2, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration on power-up.
tACQ
CS
SCLK 1 2 3 4 16 17 64
Table 3. Timing Specifications for Offset Calibration During Normal Operation (1)
MIN TYP MAX UNIT
tcycle Cycle time for offset calibration on power-up 64 × tCLK + tACQ ns
tACQ Acquisition time 95 ns
fSCLK Frequency of SCLK 60 MHz
(1) In addition to the timing specifications of Figure 42 and Table 3, the timing specifications described in Figure 2 and the Timing
Requirements table are also applicable for offset calibration during normal operation.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
1uF GND
3.3uF
OPA_VDD
(+5V)
± 33 AVDD 33
SCLK
VIN
+ 33
CS Host
+ OPA836 Device Controller
33
VSOURCE ± SDO
680pF GND
GND
- RFLT SW
VIN + CSH
CFLT
1
f-3dB =
2 Œ x RFLT x CFLT
For ac signals, the filter bandwidth must be kept low to band-limit the noise fed into the ADC input, thereby
increasing the signal-to-noise ratio (SNR) of the system. Besides filtering the noise from the front-end drive
circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage
of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs. This capacitor helps reduce the
sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold
capacitors during the acquisition process. As a rule of thumb, the value of this capacitor is at least 20 times the
specified value of the ADC sampling capacitance. For this device, the input sampling capacitance is equal to
16 pF. Thus, the value of CFLT is greater than 320 pF. Select a COG- or NPO-type capacitor because these
capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying
voltages, frequency, and time.
Driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier
marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of
the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a
result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance,
input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability
and distortion of the design.
0 0
-50 -50
Amplitude (dB)
Amplitude (dB)
-100 -100
-150 -150
-200 -200
0 250 500 750 1000 1250 0 250 500 750 1000 1250
Frequency (kHz) D036
Frequency (kHz) D037
SNR = 75.8 dB, THD = –90.1 dB, SINAD = 75 dB SNR = 75 dB, THD = –88.7 dB, SINAD = 74.3 dB
Figure 45. Test Results for the ADS7056 and OPA836 for a Figure 46. Test Results for the ADS7056 and OPA836 for a
2-kHz Input 100-kHz Input
1uF GND
3.3uF
499Ÿ
VDD(+6V)
499Ÿ
± 10 AVDD 33
SCLK
+ AINP
VSOURCE 33
+ CS Host
± THS4031 470pF
Device Controller
33
VCM SDO
(+0.825 V) VSS(-6V) AINM
GND
0 0
-50 -50
Amplitude (dB)
Amplitude(dB)
-100 -100
-150 -150
-200 -200
0 250 500 750 1000 1250 0 250 500 750 1000 1250
Frequency (kHz) D035
Frequency (kHz) D038
SNR = 74.2 dB, THD = –90.4 dB, SINAD = 73.5 dB SNR = 73.5 dB, THD = –87.8 dB, SINAD = 73 dB
Figure 48. Test Results for the ADS7056 and THS4031 for Figure 49. Test Results for the ADS7056 and THS4031 for
a 500-kHz Input a 1000-kHz Input
AVDD
Sensor
RSOURCE AVDD
AINP
+
± TI Device
In applications such as environmental sensors, gas detectors, and smoke or fire detectors where the input is very
slow moving and the sensor can be connected directly to the device operating at a lower throughput rate, a DAQ
circuit can be designed without the input driver for the ADC. This type of a use case is of particular interest for
applications in which the primary goal is to achieve the absolute lowest power, size, and cost. Typical
applications that fall into this category are low-power sensor applications (such as temperature, pressure,
humidity, gas, and chemical).
Table 5 lists the acquisition time for the above two cases for a throughput of 10 kSPS. Clearly, case 2 provides
more acquisition time for the input signal to settle.
12
11.5
ENOB (Bits)
11
10.5
33Ohm, 680pF
330Ohm, 680pF
10 3.3kOhm, 680pF
10kOhm, 680pF
20kOhm, 680pF
9.5
2 22 42 62 82 100
Sampling Speed(kSPS) D039
Figure 51. Effective Number of Bits (ENOB) Achieved From the ADS7056 at Different Throughputs
Table 6 shows the results and performance summary for this 14-bit, 10-kSPS DAQ circuit application.
Table 6. Results and Performance Summary for a 14-Bit, 10-kSPS DAQ Circuit for DC Sensor
Measurements
DESIGN PARAMETER GOAL VALUE ACHIEVED RESULT
Throughput 10 kSPS 10 kSPS
SNR at 100 Hz 74 dB 75 dB
THD at 100 Hz –85 dB –89 dB
SINAD at 100 Hz 73 dB 74.3 dB
ENOB 12 12.05
Power 20 µW 17 µW
AVDD
CAVDD
GND
CDVDD
DVDD
11 Layout
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
PACKAGE OUTLINE
RUG0008A SCALE 7.500
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
1.55
B A
1.45
C
0.4 MAX
SEATING PLANE
0.05
0.00 0.08 C
SYMM
0.35
2X (0.15)
0.25 0.45
4 2X TYP
0.35
3
5
SYMM
2X
1
4X 0.5 0.25
2X
0.15
7
1
0.3
8 4X
0.2
PIN 1 ID 0.4 0.1 C A B
(45 X0.1) 6X
0.3 0.05 C
4222060/A 05/14/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Links: ADS7056
ADS7056
SBAS769 – MARCH 2017 www.ti.com
2X (0.3) 2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
(R0.05) TYP 4
SYMM
(1.35)
SOLDER MASK
METAL
OPENING
UNDER
SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
4222060/A 05/14/2015
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
34 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
2X (0.3)
2X (0.6)
8
6X (0.55)
1
7
4X (0.25)
SYMM
(1.3)
4X (0.5)
2X (0.2)
3
5
SYMM
(1.35)
4222060/A 05/14/2015
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2017, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: ADS7056
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
ADS7056IRUGR ACTIVE X2QFN RUG 8 3000 Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM -40 to 125 5I
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Feb-2018
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 2-Feb-2018
Pack Materials-Page 2
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