1) Define timeplates for each clock domain with domain-specific settings like frequency, pulse widths, and period.
2) Write named capture procedures for each clock domain, calling the corresponding timeplate and pulsing the domain clock while holding other clocks low and scan_en low.
3) The example shows separate testproc files for the clk1 and clk2 domains with unique timeplates and identical capture procedures tailored for each domain's clock.
1) Define timeplates for each clock domain with domain-specific settings like frequency, pulse widths, and period.
2) Write named capture procedures for each clock domain, calling the corresponding timeplate and pulsing the domain clock while holding other clocks low and scan_en low.
3) The example shows separate testproc files for the clk1 and clk2 domains with unique timeplates and identical capture procedures tailored for each domain's clock.
1) Define timeplates for each clock domain with domain-specific settings like frequency, pulse widths, and period.
2) Write named capture procedures for each clock domain, calling the corresponding timeplate and pulsing the domain clock while holding other clocks low and scan_en low.
3) The example shows separate testproc files for the clk1 and clk2 domains with unique timeplates and identical capture procedures tailored for each domain's clock.