11 Chapter 1

Deposition and characterization of high-k dielectric thin films for MOS capacitors
Chapter 1: Introduction
1.1. Evolution of Semiconductor devices and MOSFET scaling overview
The remarkable performance improvements in microelectronics over the past

few decades have been accomplished by severe reduction in the size of memory and
logic devices. The development of semiconductor technology has brought enormous
changes to our life and society. Higher density of integration and faster processors
pushes to the high miniaturization to the electronic devices. The first vacuum tube
was invented by L. D. Forest in 1906, which was used for rectifying, amplifying, and
switching electrical signals. Vacuum tubes had been widely applied to electrical
devices, and had played an important role in the improvement of electronics, prior to
the advent of the semiconductor transistor. However, even small vacuum tubes
significantly consume a huge amount of power and have size of several cubic
centimeters [1].
Two significant things i.e. the invention of the transistor and the invention of
the integrated circuit overturned the world of vacuum tubes. In 1947, W. Schockley, J.
Bardeen and W. H. Brattain invented the bipolar transistor at Bell Laboratories,
Murray Hill, New Jersey [2-3]. The transistor is the fundamental building block of
modern electronic devices, and is everywhere in modern electronic systems. The
transistor is the heart of almost all electronic systems and so it is one of the most
important inventions of the 20th century. Junction field-effect transistor (JFET) was
invented by W. Shockley in 1951 [4]. JFET was an innovative replacement of the
vacuum tube by a solid-state device. Following its development in 1947; the transistor
revolutionized the field of electronics, and covered the way for smaller and
cheaper radios, calculators and computers, among other things. The transistor sparked
a new era of modern technical accomplishments from manned space flight and
computers to portable radios and stereos. The invention of the transistor, a solid state
amplifier, resulted in enormous efforts in the field of semiconductor devices. The
integration of semiconductor devices on a single chip was one of the consequences of
these combined efforts. J. Kilby at Texas Instruments first demonstrated the concept
of Integrated Circuits (IC) in 1959 [5]. Figure 1.1 shows the picture of first integrated
circuit developed by J. Kilby. The succeeding big step, the invention of the integrated
circuit, took place concurrently at Fairchild and Texas Instruments from 1957 to 1959.
Mr. Anil Gulabrao Khairnar, Department of Electronics, N.M.U., Jalgaon, Ph.D. Thesis 2014 1.1
Figure 1.1: Jack Kibly's IC - picture is provided by Texas

Instruments.
In 1959 D. Kahng and M. M. Atalla at Bell Labs achieved the first successful
insulated-gate field-effect transistor (FET) [6], which had been long predicted by
Lilienfeld, Heil, Shockley and others (1926 Milestone) by defeating the "surface
states" that blocked electric fields from penetrating into the semiconductor material
[7]. This idea together with the fabrication of the first Metal Oxide Semiconductor
Field-Effect Transistor (MOSFET) by D. Kahng and M. M. Attala in 1960 offered the
foundation for the advancement of the microelectronics industry. Investigating
thermally grown silicon-dioxide layers, D. Kahng and M. M. Atalla found these states
could be markedly reduced at the interface between the silicon and its oxide in a
sandwich comprising layers of metal-oxide-silicon (MIS/MOS) thus the name
MOSFET, popularly known as MOS. The experimental confirmation of the surface
field effect, conversely, could not be demonstrated for more than 30 years. Since
afterward, the MOSFET became by far the most important electronic device for Very
Large Scale Integrated (VLSI) circuits such as in microprocessors and semiconductor
memories. The minimum device dimension has been reduced from ~10 µm in the
1960’s to sub µm features in the 1990’s. Currently, researches are being occupied
towards integration of sub 32 nm CMOS devices by numerous groups all around the
world. The introduction of alternative gate dielectrics with a high dielectric constant
or so called high-k dielectrics is a part of these research efforts.
The continuous evolution of semiconductor technology has been made
possible by the downsizing of transistors or “scaling”. The device feature size
decreases by approximately 0.7x in every two or three years and the number of
transistors on a VLSI chip doubled in every eighteen to twenty four months shown in
Figure 1.2. This trend is called as “Moore’s Law” which was first stated by Gordon
Moore [8]. As shown in table 1.1, through the scaling rule, when the device
Figure 1.2: Moore’s Law.
dimension is scaled down with factor α, the supply voltage of MOSFETs should be
reduced by the same factor α. The doping concentration should be increased by the
same factor α, keeping the electric field in MOSFETs constant. Moreover, power
dissipation per circuit is reduced by α [9].
Table: 1.1 Scaling of MOSFET by a scaling factor of α.
Quantity After Scaling (α >1)

Channel Length L/α
Channel Width W/α
Device Area A/α2
Gate Oxide Thickness tox/α
Gate Capacitance per Unit Cox*α
Area
Junction Depth Xj/α
Power Supply Voltage VDD/α
Threshold Voltage Vth/α
Delay Time td/α
Required Power VDD*I/α2
Doping Densities NA*α or ND*α
By the scaling method and Moore’s Law, transistor size has shrunk to obtain
high device density, significantly higher device switching speeds, faster circuits and
low fabrication costs.
Table 1.2 shows the evolution of logic complexities in integrated circuits over
the decades. The Semiconductor industry has evolved from the first ICs of the early
1970s and matured rapidly since then. Early Small Scale Integration (SSI) ICs
contained a few (1-10) logic gates such as NAND, NOR, gates amounting to few tens
of transistors. The era of Medium Scale Integration (MSI) increased the range of
integrated logic available to counters and similar logic functions. The era of Large
Scale Integration (LSI) packed even larger logic functions such as the first
microprocessors, into single chip. The era of Very Large Scale Integration (VLSI)
offers 64-bit microprocessors, complete with cache memory well over million
transistors on a single piece of silicon. As CMOS process technology improves,
transistor continues to get smaller and ICs hold more and more transistors (~10-100
Million) known as Ultra Large Scale Integration (ULSI) [10].
Table: 1.2 Evolution of logic complexity in integrated circuits.
Year Era/Technology Complexity (# Logic blocks per chip)
1947 Single transistor <1

1960 Unit Logic (one gate) 2-4
1961 Small Scale Integration (SSI) 10
Medium Scale Integration
1966 100-1000
(MSI)
1971 Large Scale Integration (LSI) 1000-20,000
Very Large Scale Integration
1980 20,000-1,000,000
(VLSI)
Ultra Large Scale Integration
1990 >1,000,000
(ULSI)
As transistors become smaller, they switch faster, dissipate less power, and are
cheaper to fabricate. In spite of the ever rising challenges, process advances have
actually step up in the past decade. Such scaling is unprecedented in the history of
technology. However, scaling also aggravates noise and reliability issues and
introduces new problems. The realization of such high-performance, multifunctional

systems call for novel, innovative and revolutionary practices in functional block
integration and packaging [11].
1.2. Manufacturing of Integrated Circuits
Today, ICs are the complex devices with millions of individual components
that are fabricated on a single silicon crystal and interconnected by tiny wires that are
microns wide. Figure 1.3 shows the first silicon IC chip made by Robert Noyce. The
fabrication of a modern IC in the CMOS process involves hundreds of sequential
steps and can last up to 30 days of processing time. The following basic process steps
are used [12-14]:
Lithography: A lithography step is used to transfer the layout information to the
wafer. For instance, one photo mask can define the source/drain areas for n-MOS
transistors. Ultraviolet light is typically applied to project the patterns defined by the
mask to the photoresist layer which has been deposited on the wafer surface. The
structure defined by the mask remains after the development process, if a positive
photoresist is used.
Figure 1.3: First Silicon IC chip made by Robert Noyce of Fairchild camera in
1961.
Deposition: Layers of various materials (semiconductors, metals, insulators,
photoresist) are deposited on the wafer surface during the IC manufacturing process.
Mainly two techniques are applied for deposition processes: Physical Vapor
Deposition (PVD) and Chemical Vapor Deposition (CVD).
Etching: Etching processes are used either to remove complete material layers or to
transfer the patterns in the photoresist layer (generated by a lithography step) into the
underlying layer. Etching can be performed by a chemical attack (wet etching), by
particles in a plasma chamber (dry etching), or by a combination of both.
Chemical Mechanical Polishing: A non-planar surface is produced by process steps
which modify the topography of the wafer (deposition, etching, oxidation). The
planarization for the next step is performed by Chemical Mechanical Polishing
(CMP).
Oxidation: Silicon dioxide is used for isolation purposes in devices and integrated
circuits (e.g. shallow trench isolations between MOS transistors) and as mask or
scattering layers for ion implantation processes. There are two silicon dioxide growth
methods, dry and wet oxidation, depending on whether oxygen or water vapor is used.
Ion Implantation: This is the primary technology in IC manufacturing to introduce
impurities (dopant atoms) into semiconductors. An ion implanter is used to accelerate
the dopant ions to high energies and to direct the beam of ions onto the wafer.
Diffusion: Dopant diffusion occurs during any thermal processing step either as an
intended or unwanted effect. Due to the requirement of very shallow junctions in
advanced devices rapid thermal annealing (RTA) processes with very little diffusion
(e.g. Flash-assisted RTA or Laser-anneal) are used to repair the ion implantation
induced damage in the crystal.
The manufacturing process of IC can be sub-divided into two parts one is the
Front-End-of-Line (FEOL) and the other is Back-End-of-Line (BEOL) [15-16]. FEOL
is the first part of IC fabrication and deals with the manufacturing of Metal Oxide
Semiconductor (MOS) transistors that work as switch. FEOL processing refers to the
formation of the transistors directly in the silicon. The raw wafer is engineered by the
growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most
advanced logic devices, prior to the silicon epitaxy step, tricks are performed to
improve the performance of the transistors to be built. FEOL generally covers
everything up to (but not including) the depositions of metal interconnect layers; it
contains all processes of CMOS fabrication needed to form fully isolated CMOS
elements. Reduction in the transistor size leads to electrical stresses, which cause
transistors to leak such that they may never totally turn off. Shrinked gate oxide
thickness causes gate leakage called as sub-threshold leakage. Ion implants are
obligatory to alter the threshold voltage of the transistor to make sure there is gate
control. BEOL is the second part of IC fabrication where the individual devices
(transistors, capacitors, resistors etc.) get interconnected with wiring on the wafer i.e.
deals with the manufacturing of interconnects. BEOL includes contacts, insulating
layers (dielectrics), metal levels and bonding sites for chip-to-package connections.
Even though packing of more number of transistors in the same area is possible by its
scaling, metal width and pitch needed to be reduced along with an efficient metal
stack to wire all these transistors. The reduction of metal width increases resistance,
which is compensated by vertical scaling. But, this leads to increased coupling
capacitance which results in more crosstalk between signal lines. Yield can be
affected by crosstalk which could cause glitches on data or clock resulting in
intermittent failures which can be impossible to debug if not caught early in the
design. Scaling transistor’s dimensions has been the main tool to power the
development of silicon integrated circuits. The more an IC is scaled, the higher it’s
packing density, packaging costs are decreased, interconnect paths shrink, and power
loss in I/O drivers is reduced [17]. The aggressive scaling lead to a two-fold increase
in die/wafer and two-fold increase in speed every two years leading to an improved
performance and decline in manufacturing costs [18]. The devices used in CMOS
technology are described by the following characteristics known as figures of merit
[19]:
1. Minimum feature size
2. Number of gates on one chip
3. Die size
4. Gate delay
5. Power dissipation
6. Maximum operational frequency
7. Reliability, and
8. Production cost
These figures of merit can be enhanced by reduction of dimensions of
transistors, interconnections and separation between features. However, there are
additional complexities in limitations of design, interconnect, lithography, reliability
and materials used. Accordingly, over the past few decades, much effort has been
directed toward the advancement of process technology and the consequential scaling
down of feature size and devices.
1.3. IC Fabrication-Challenges and Prospects:
An integrated circuit is created by stacking layers of various materials in a pre-

specified sequence. Both the electrical properties of the material and the geometrical
patterns of the layer are important in establishing the characteristics of devices and
networks. Most layers are created first, and then patterned using lithographic
sequence. Thus, IC fabrication has collection of some typical steps and these are same
for digital and analog IC [15, 20]. A designing and fabrication of IC starts with the
need of particular requirement of application specific integrated circuits (ASICs).
Based on fabrication limits/design rules the designer makes circuit design that
includes transistors, resistors and capacitors with their specific values called as
blueprints. The designer gives his blueprints to IC fabricator as a set of photomask.
This photomask is actual representation of design that is produced according to layout
rule. The information of design must be transferred from photomask to the wafer
along with its length and width. This work is done by lithography [21-22].
The complexity of microcircuit is limited by three factors:
1) Ingenuity of circuit designer in reducing number of devices required to perform
any given electronics function.
2) Maximum size of chip that can be made with a reasonable processing yield
because of number of materials and process technologies have strong bearing on
this size.
3) Size of minimum feature which can be placed on the chip is determined by
lithographic techniques which are used in conjunction with pattern transfer
processes to delineate the various regions in a microcircuit.
Basically, fabrication of IC requires semiconductor wafer, deposition of thin
films on wafer, lithography and etching tools for pattering, diffusion and ion
implantation processes for doping. As the lithography techniques tend closer to the
fundamental laws of optics, achieving high accuracy in doping concentrations and
etched wires is becoming more complex and prone to errors due to variation with
continued miniaturization. To mitigate this, designers have started to simulate across
multiple fabrication process corners before the chip is certified ready for production.
Due to lithography and etch issues with scaling, design rules for layout have became
much more tough. Designers have to keep more of these rules in mind while laying
out custom circuits. The overhead for custom design is now reaching a tipping point,
with many design houses now opting to switch to electronic design automation (EDA)
tools to automate their design process. Each extra manufacturing step adds a risk for
defects. In order for ICs to be commercially viable, defects should be repaired or
tolerated, or defect density should be least. Thus to achieve high overall yield and
reduce costs, separate testing of independent dies is essential [23].
1.4. Dielectric thin films used in CMOS technology:
Dielectric materials are the essential part in the fabrication of IC’s. The term
dielectric material or insulator used in nanoelectronics generally refers to a material
that exhibits low thermal or electrical conductivity, but an efficient supporter of
electrostatic field. In other words, dielectric is an electrical insulator that can be
polarized by an applied electric field when placed in an electric field such as within a
parallel plate capacitor. The development of new electronic and optoelectronic
materials depends not only on material’s engineering at a practical level, but also on a
clear understanding of the properties of materials, and the fundamental science behind
these properties. It is the properties of a material that eventually determine its
usefulness in an application. Dielectric film deposition remains one of the most
challenging applications in the semiconductor, optics, optoelectronics, biocompatible
medical devices, data storage, catalysis and in energy generation and conservation
strategies. The dielectric thin film materials used in fabrication of devices for above
application must satisfy a number of critical thermal, environment, electrical and
optical requirements to meet the required performances criteria for their applications.
These desired attributes include thermal stability, low moisture uptake, high
breakdown voltage, desired dielectric constant or refractive index, high glass
transition temperature and low surface roughness [24-25].
From the beginning, dielectric thin film coating played a vital role in the
development of integrated circuit devices and fiber optic communication network
systems. If we look inside virtually any device used in Very Large Scale Integrated
circuit and optical fiber telecommunication systems you will find dielectric thin film
coatings. The most prominent examples are microprocessors in VLSI and dielectric
thin film filter WDM modules in optical fiber communication system.
In Nanoelectronics, dielectric layer is a film or deposited layer of an insulating
material used for insulation between conducting layer, gate dielectric planarization,
for diffusion and ion implantation mask, for diffusion from doped oxide, for capping
doped films to prevent the loss of dopants, for gettering impurities, and for
passivation to protect device from impurities, moisture and scatches. Ideally, in these
applications a dielectric material should have a surface resistivity more than
1×1013Ω.cm-2 or a volume resistivity of greater than 1×1011Ω.cm-2. However, for
some specific applications lower values may be acceptable. Table 1.3 shows the
different types of dielectric materials used in microelectronics with their deposition
techniques and applications [26]. Following two properties of dielectric films are of
great importance for the above applications. One for isolation and FET gate
applications, a high dielectric strength material is required. Highly integrated with
smaller features semiconducting devices can be fabricated using high dielectric
strength materials. Dielectric is the maximum voltage that an insulating material can
withstand before breakdown occurs. Dielectric strength usually expressed as a voltage
gradient Vcm-1. The dielectric strength varies with spacing between electrodes. The
second important property involves the chemical compatibility, often termed as
passivation, with the semiconducting substrate. Passivation includes protecting the
semiconductor from external contamination as well as electrical stability which
depends on applied electric field.
Table 1.3: Classification with applications of dielectric materials.
Deposition technique
Materials class Applications
CVD Spin-On
Inorganics BPSG - Premetal
Inorganics SiO2, FSG SiO2
Polyphenylene,
Organics PTFE, FLAC
polyarylene, PTFE Interlayer
HSQ, SOG, dielectric (ILD)
Silico-organics SiOC Silsesquioxanes,
siloxanes, others
Inorganics SiNx, Others -
Organics - - Cap/hard
mask/etch stop
Proprietary
Silico-organics SiC layers
polymers
Organics - Polyimide
Passivation
Silico-organics - BCB
1.5. Motivation:
Microelectronics is the branch of electronics which deals with the

miniaturization of integrated circuits. The evolution in microelectronics has resulted
in complex System-on-Chip (SoC) devices that combine logic and memory units
consisting of hundreds of millions of transistors packed on a single silicon chip. The
production of ultra-large scale integrated circuits has become only possible due to the
CMOS technology platform because of low-power and scaling properties.
MOSFET is the key component of the ICs, which consists of source, drain,
channel, gate and gate oxide. In order to keep in pace with the demands of the
semiconductor industry, the IC performance should be continuously improved.
Steady, exponential increase in the performance of silicon based CMOS integrated
circuits has been a reliable feature of semiconductor technology since the integrated
circuit was invented in 1959. During the 1970s the semiconductor industry settled into
a pattern of producing a new generation of integrated circuits every three years, with
each new generation containing four times the number of transistors, four times the
memory, and operating at more than twice the speed of the previous generation. The
manufacturing cost per transistor has also been radically reduced, since successive
technology nodes have had increasing numbers of transistors per chip.
Huge resources have been invested in the search for new materials that can
improve integrated circuit performance without the need for scaling. One of the main
concerns for MOSFETs is the thickness of the gate insulator. With the reduction of
gate lengths and increased channel doping, the gate oxide thickness has been reduced
dramatically in order to maintain gate control over the channel. For high-performance
logic technology, ITRS predicts that a metal gate and high-k (k > 30) stack with an
effective oxide thickness of 5-8 Å and attaining the very low leakage currents and
power dissipation will be required by 2015 [27].
To obtain this scaling, the gate oxide layer, nitrided SiO2 has been downscaled
to as thin as 1.2 nm, or to a thickness of only a few monolayers. This thickness is
already at a level where severe problems occur, and as a result the dielectric is not
able to effectively withstand voltages, as tunneling current through the dielectric is
unfavorable on device performance. Another problem related to the SiO2 scaling is
reliability; the requirements for reliability are even more difficult to meet than the
leakage current requirements. It is unlikely that conventional, thermally-grown silicon
dioxide (SiO2) dielectrics can satisfy this requirement, since quantum-mechanical
tunneling current through the oxide increases exponentially with decreasing physical
thickness [28-29]. Indeed, a physical thickness of 10-15 Å corresponds to only 3-4
atomic monolayers of SiO2. High-k dielectrics have been proposed to improve the
oxide scaling problem [30-33]. Since high-k oxides have a larger dielectric constant
than SiO2, they can have a greater physical thickness without sacrificing gate control.
The increased thickness of the layer diminishes quantum tunneling current.
The goal of studying the MOS system is to improve the performance and
stability of devices such as MOSFETs used in integrated circuits. Since MOS
capacitor is simpler to use for these studies that the use of actual devices used in the
integrated circuits. The MOS capacitor is helpful in such studies because any change
in processing that improves the electrical properties of the MOS capacitor makes the
same improvement on actual devices. Thus the simplicity and versatility of the MOS
capacitor can be exploited with confidence for optimization in performance of
integrated circuits [34-36].
Limitations of Conventional Gate Oxide:
The silicon dioxide (SiO2) was preferred material in all integrated circuits due
to its superb thermal, mechanical, electrical and chemical properties made it the gold
standard insulating material. Owing to these properties, SiO2 has served as the gate
dielectric for integrated circuit (IC) applications for more than 40 years. SiO2 can be
thermally grown on Si with an easy fabrication process and good control of thickness
and SiO2/Si interface quality. The superb properties of the SiO2 gate dielectric
material are shown in Table 1.4, includes a high resistivity, a high melting point, a
high amorphous to crystallization temperature, a large band gap, large electron and
hole band offset, excellent dielectric breakdown strength, and a low defect density
interface with Si substrate [37]. In addition, SiO2 has the combination of some other
required properties for the complementary-metal-oxide-semiconductor (CMOS) field
effect transistor (FET) devices, including high mobility of holes and electrons in
MOSFET devices channel, low electron or hole trapping density, and excellent
CMOS processing [38]. The SiO2/Si interface is the heart of the CMOS gate stack
structure. Since the CMOS devices constitute the building blocks of the integrated
circuit, SiO2 became the most economically and technically important material for the
semiconductor industry. In fact, Si, instead of other semiconductor materials such as
Ge and III-V group compound semiconductors such as GaAs, was selected as the
main material for the microelectronic semiconductor industry due to the lack of a
stable native oxide and a low defect density interface for other semiconductor
materials [39]. In earlier days the improvements in chip performance were achieved
by making very few changes in the design of the ICs using SiO2 as insulator and
aluminium (Al) as metal. This trend continued till the middle of 1990 because
shrinking of the device dimensions always resulted in an improvement of
performance as measured by the intrinsic gate delay as well as signal delay. But, as
the device densities increased, the device dimensions were forced to shrink in order to
accommodate with the increase of device densities. Scaling demanded drastic
decrease of the SiO2 thickness to achieve ever-higher capacitance densities. In order
to continue the high drive current and gate capacitance required of scaled MOSFETs,
the SiO2 gate dielectrics have reduced in thickness from hundreds of nanometers four
Table 1.4: Properties of SiO2.
Density (gm/cc) 2.2-2.3
Melting Point ~1713°C
Crystallization temperature ~1100°C
Resistivity ~1015Ω-cm
Dielectric Strength ~15MV/cm
Energy band gap ~9.1eV
Electron band offset with Si ~3.2eV
low interface (SiO2/Si) state density ~10 eV cm-2 (after FGA)
10 -1
low charge trapping density ~1010cm-2

Thermal conductivity (W/m.K) 1.4
Fracture energy (J/m2) 4.4
Leakage current at 1MV (A/cm2) 1×10-9
decades ago to less than 2 nm today, with a constant endeavor to shrink to a thickness
below 1 nm. However, SiO2 layers thinner than 1.2 nm do not have the insulating
properties required of a gate dielectric. The use of ultrathin SiO2 gate dielectrics gives
rise to a number of problems, including high gate leakage current, reduced drive
current, poor resistance to impurity diffusion, and reliability degradation. Therefore,
alternative gate dielectric materials, with small ‘equivalent oxide thickness’ (EOT) are
required. The equivalent oxide thickness of a material is defined as the thickness of
the SiO2 layer that would be required to achieve the same capacitance density as a
given physical thickness of an alternative dielectric layer:
(1.1)
Where tox the physical thickness of the film of interest, kx is the k value for the
film of interest and kSiO2 the k value of SiO2. From (1.1), a film with a k value of 7
could be almost twice as thick as a SiO2 film with a k of 3.9 and still have the same
control over MOSFET.
Solution Alternate Gate Dielectrics:
In order to be well-prepared with options to continue scaling during such a

scenario, nearly a decade of research and development has been conducted by various
research groups. The different approaches include introduction of high-k gate
dielectric, replacement of bulk silicon with strained silicon-on-insulator (SOI), high
mobility channel material like germanium, GaAs, graphene etc. and non planar
CMOS device structures like FinFET.
If the thickness of the standard SiO2 based gate dielectric drops below the
tunneling limit, gate leakage current will increase tremendously. For an oxide
thickness of 1.5 nm at 1.5 V the leakage current density would be 100A/cm2 which is
obviously undesirable for low power applications. To prevent tunneling currents,
physically thicker dielectric layers are required. As the gate dielectric become
physically thicker, transistor requires a material with high dielectric constant to
maintain its electrical characteristics. Table 1.5 lists the different high-k dielectrics
that are being studied as an alternate gate dielectric to SiO2 in the advanced CMOS
technology [31, 33].
Table 1.5: Parameters of SiO2 and mostly used high-k dielectrics.
Dielectric Bandgap Interface trap

Material Crystallinity
constant (eV) density (eV-1cm-1)
SiO2 3.9 9.0 ≤1×1010 Amorphous
Gd2O3 12 5.0 1.2×1013 Crystal (T>400°C)
Al2O3 12.5 8.8 4.1×1011 Amorphous (T<700°C)
Y2O3 15 6.0 1.3×1012 Crystal (T>400°C)
CeO2 26 5.5 2×1011 Crystal (T>400°C)
HfO2 22-25 5.6 1×1011 Crystal (T>400°C)
ZrO2 20-25 4.7-5.7 3×1011 Crystal (T>700°C)
TiO2 80 3.5 1×1011 Rutile
La2O3 27 5.8 1.6×1011 Amorphous
1.6. Metal Gate Technology:
Polycrystalline silicon (poly-Si) has been used as a MOSFET gate material for
several decades. One of the primary reasons for this is its high compatibility with
CMOS processing [40]. The major problem of the conventional poly-silicon gate
electrode is the depletion of carriers within the polysilicon in the MOS inversion
region, which will result in loss of current drive and transconductance of the
transistor. This poly-silicon depletion is a serious problem for sub micron CMOS
devices because the active poly-silicon dopant concentration is low at the poly-
silicon/gate oxide interface as a result of shallow junctions. In addition, the sheet
resistance of the poly-silicon increased drastically with the continuous scaling of the
device dimensions, which would limit the MOSFET circuit’s speed. Boron dopant
penetration through the thin gate oxide during the activation thermal cycle is another
problem for the conventional poly-silicon gate electrode, which leads to a shift of the
threshold voltage [41]. Replacing the conventional poly-silicon gate electrode with a
metal gate electrode may potentially eliminate all of the limitations of poly-silicon.
Using a metal gate electrode may also minimize the interaction between a high-k gate
dielectric and the poly-Si. In addition, the use of a metal gate electrode may also
avoid the high temperature poly-Si dopant activation annealing and hence lower the
overall thermal budget of the CMOS fabrication flow.
The threshold voltage controllability of conventional poly-Si gated MOSFETs
is closely related to Fermi level pinning phenomena. Especially for PMOS transistors
with poly-Si gate, the threshold voltage is fixed at a relatively high value due to Fermi
level pinning, creating a serious problem for practical application. Some methods of
modifying the poly-Si gate/high-k gate interface have been proposed, but they are not
fully effective. In order to eliminate Fermi level pinning effects, the introduction of
metal gates with appropriate work functions is required. Metal gate technology will
also be effective in eliminating gate depletion effects, and boron penetration observed
with conventional poly-Si gate MOSFETs. However, the integration of a metal gate
electrode into the conventional CMOS fabrication process flow will also impose some
serious manufacturing and reliability challenges because the metal electrodes should
have excellent thermal/chemical stability and process compatibility with high k
dielectrics and conventional CMOS processing sequences [42-44].
Metal Candidates:
Candidate gate materials must fulfill numerous criteria in order to be feasible

for use in a Si based CMOS fabrication process. These materials must be highly
conductive and must have very high melting points in order to withstand the high
thermal budgets commonly used in CMOS processing. It is also important that these
materials lend themselves easily to conventional metal thin film deposition (physical
or chemical vapor deposition) and reactive ion etching (RIE) techniques. The
deposition technique used to deposit the gate electrode affects a number of important
properties of the gate electrode. The morphology of the gate electrode is important for
several reasons. An amorphous gate electrode is likely to have a work function
significantly different from that of a crystalline one. These requirements will ensure
that advanced gate CMOS devices can still be fabricated using conventional tools.
The new gate materials also need to have thermal expansion coefficients that closely
match those of the single crystalline Si substrate in order to ensure that no significant
thermal stresses are introduced in the film during rapid temperatures changes. The
gate metals to be used must be ‘band edge metals’, with work functions equal to the
band edge energies of Si, 4.05 and 5.15 eV. The problems involved in using real
metals are finding a metal with the correct work functions, ensuring the thermal
stability of that metal in contact with the oxide, whether SiO2 or a high-k oxide, and
generally ensuring a process compatibility. Generally, PMOS metals with large work
functions will be too noble and difficult to etch, while NMOS metals with small work
functions will be too reactive [45-46]. In this study, the Pt, Ti, and Al gate electrodes
are deposited over different high-k dielectric films for MOS device fabrication.
1.7. Formulation of problem:
Over the last few decades the semiconductor industry has achieved an
exceptional growth, primarily due to the rapid advances in large-scale systems design
and integration technologies. The use of integrated circuits in high performance
computing, telecommunication, and consumer electronics has been increasing at a
very high speed. Typically, the required computational and information processing
power of these applications is the driving force for the fast development of this field.
Thus continuous improvement of integrated circuit performance is a prerequisite for
the success of semiconductor industry in order to enhance the packing density and
device performance in Ultra-Large Scale Integrated circuits. MOSFETs have been
scaled down successfully over the past few decades. Scaling of the gate stack has
been a key for enhancing the performance in complementary metal-oxide-
semiconductor (CMOS) field-effect transistors (FETs) of past technology generations.
Because the rate of gate stack scaling has diminished in recent years, the motivation
for alternative gate stacks structures has increased. The International Technology
Roadmap for Semiconductors (ITRS) states that thin EOTs <0.5 nm will be required
by 2015 to sustain gate terminal control of the charge carrier in the semiconductor
channel, therefore, high-dielectric constant (high-k) materials make sense as an option
for future nanoelectronic devices. Aforementioned description regarding current
scenario in semiconductor research, the introduction of high-k reopened the door for
germanium for high mobility channel MOSFETs. Based on the aforesaid issues
performance in MOS devices can be enhanced by the use of high-k materials. In this
doctoral thesis, we have investigated and studied certain high-k materials as an
alternative to SiO2 to be used as alternative dielectric material in CMOS devices.
Recently, high mobility channel MOSFET with high-k gate dielectric has
attracted attention due to its enhanced carrier mobility and device scaling capability
[47-49]. Instead, elemental semiconductor materials (silicon or germanium), III-V
compounds are promising candidates for high speed low power n-channel transistors
by increasing mobility of electron from 10-30 times. However these materials are
suitable for only n-channel since the mobility of holes is relatively low for p-channel.
The mobility of holes in germanium is four times higher than that in silicon.
Germanium has started to receive attention because it simultaneously offers
significant enhancements in bulk electron and hole mobility relative to silicon [21].
Hence, the emergence of high-k dielectrics gives an opportunity to fabricate
devices having both merits of high-k and Ge. Integration of high-k on Ge not only
allows the continued scaling of semiconductor devices, but also allows higher
mobility to improve device speed [30, 41]. In addition to the increase in mobility,
compared with Si, Ge’s more balanced electron and hole mobility values can lead to
more symmetric design for nMOS and pMOS transistors in the CMOS inverter cell,
allowing smaller area pMOS devices and easy design constraints. Another advantage
of using germanium is its smaller bandgap, being around 0.6 eV compared to 1.2 eV
for Si. Smaller bandgap leads to smaller threshold voltage hence to better VDD scaling,
which is a major limitation in the scaling of Si devices. Also, the smaller band gap
results in smaller Schottky barrier height, which will lead to smaller contact resistance
helping the drive current of MOSFET. However, replacement of Si channel by Ge
requires several critical issues to be addressed in Ge MOS technology. High quality
gate dielectric for surface passivation, low parasitic source/drain resistance and
performance improvement in Ge NMOS are among the major challenges in realizing
Ge CMOS [21, 36]. Therefore, these materials have not been used in real MOSFET
devices due to the difficulty in forming high quality gate dielectrics layer at interface.
To have a high quality high-k gate stack on Ge substrate, the reduction of
GeOx between the high-k and substrate is a critical issue. Since the germanium oxide
is thermally unstable, water soluble and of poor electrical properties, to minimize the
GeOx, the interface engineering is needed for high quality gate stack. We have studied
literature regarding various surface passivation technologies developed so far for
making high quality high-k gate stack on germanium substrate for MOSFETs
applications. These include surface nitridation, silane passivation, ozone treatment,
suplhur passivation and SiO2 passivation layer [50-52]. Nitridation process has been
used in this work for the passivation of germanium surface.
Objectives:
The MOS Field Effect Transistor is fundamental building block of MOS and
CMOS digital integrated circuits. The technological advantages, together with related
simplicity of MOSFET operation, have helped the MOS transistor the most widely
used switching device in LSI and VLSI circuits. This thesis deals with a thorough
investigation of the basic material and electrical properties of Metal Oxide
Semiconductor Systems, upon which the MOSFET structure is based. The ultimate
aim of the research work described in this thesis is to i) Investigate materials
properties of dielectric and electrical performance of high-k materials ii) Develop the
suitable process for the deposition of different high-k gate dielectrics for
complementary metal-oxide semiconductor (CMOS) technology iii) To study
performance of high-k on bulk silicon (Si) substrate and germanium (Ge) for high
channel mobility substrates as novel materials to be employed in advanced
nanoelectronic devices.
1.8. Organization of Thesis:
This thesis is divided into six chapters and arranged as follows. Chapter 1
includes the detailed background, survey of literature and objectives behind the work.
This chapter reviews and in brief discusses the long predictable necessity of
substituting conventional gate oxides (SiO2-based) with the Metal/high-k gate stack
structure in order to continue the scaling down of CMOS devices. The requirements
for metal gates and high-k materials are discussed. Chapter 2 is dealing with brief
history and basic properties of structure of high-k materials as well as their
applications. This chapter further includes the Ideal and Non-ideal MOS structure.
High-k dielectric material deposition techniques are described in chapter 3. The

details fabrication of MOSCAPs as well the basic principles behind all fabrication
equipments is briefly discussed. The measurement setups and characterization
methods used in this study are also mentioned in this chapter. Chapter 4 describes
experimental details, which is followed by results obtained from structural and
electrical characterization of the high-k dielectrics and fabricated metal oxide
semiconductor capacitors (MOSCAPs) in chapter 5. Chapter 6 summarizes the
findings and contributions of this study after the analysis and also defines the future
scope of the study.
Table 1.6 shows the thickness leakage current density, interface trap density
properties of HfO2 thin films deposited by different techniques with the state of the art
reported in the literature.
Table 1.6: Properties of HfO2 deposited by different techniques.

Tox Leakage current
Sr. No. Methods Dit (cm−2 eV−1) Ref.
(nm) density (Acm-2)
1. Sputtering 15–20 1.5×10-6 4.3×1011 [53]
-9 12
2. MOCVD 15.7 1.5×10 5.3×10 [54]
Thermal
3. 50.0 1.0×10-7 5.2×1012 [55]
Evaporation
4. ALD 5.03 1.2×10-5 3.7×1011 [56]
----------------------- x -----------------------
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Deposition and characterization of high-k dielectric thin films for MOS capacitors

The remarkable performance improvements in microelectronics over the past

Figure 1.1: Jack Kibly's IC - picture is provided by Texas

Figure 1.2: Moore’s Law.

Table: 1.1 Scaling of MOSFET by a scaling factor of α.

Quantity After Scaling (α >1)

Year Era/Technology Complexity (# Logic blocks per chip)

1947 Single transistor <1

introduces new problems. The realization of such high-performance, multifunctional

1.2. Manufacturing of Integrated Circuits

1.3. IC Fabrication-Challenges and Prospects:

An integrated circuit is created by stacking layers of various materials in a pre-

1.4. Dielectric thin films used in CMOS technology:

Microelectronics is the branch of electronics which deals with the

Limitations of Conventional Gate Oxide:

low charge trapping density ~1010cm-2

Solution Alternate Gate Dielectrics:

In order to be well-prepared with options to continue scaling during such a

Dielectric Bandgap Interface trap

1.6. Metal Gate Technology:

Candidate gate materials must fulfill numerous criteria in order to be feasible

1.7. Formulation of problem:

1.8. Organization of Thesis:

High-k dielectric material deposition techniques are described in chapter 3. The

Table 1.6: Properties of HfO2 deposited by different techniques.

[19] Kamran Eshraghian, Douglas A. Pucknell and Sholeh Eshraghian, Essentials

[39] A. S. Grove, Physics & Technology of Semiconductor Devices, John Willey

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