VLSIPROJECT ABSTRACTS

Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

1. An Efficient VLSI Architecture of 1D/2D and 3D for DWT Based Image

Compression and Decompression Using a Lifting Scheme
An efficient architecture is proposed in this paper for high speed Discrete Wavelet Transform
computing. The proposed architecture includes Line Buffers, PIPO and Lifting Block. This
architecture works in non-separable fashion using a lifting scheme computes 1D, 2D and 3D-
DWT at different resolution levels. The lifting scheme represents the fastest implementation of
the DWT. A Verilog model is described and synthesized using Xilinx 14.4.The architecture has
regular systolic structure, simple control flow for data extraction and small embedded buffers.

2. An Approach for Area and Power Optimization of Flipping 3-D Discrete Wavelet
Transform
In this work, an approach for optimizing the 3-D Discrete wavelet transform (3-D DWT)
architecture is recommended. Conventional 3-D DWT architectures include basic building
blocks such as 1-D DWT module, 2-D DWT module, transpose memory unit, and temporal
memory unit. Proposed 3- D DWT architecture is designed by suitably interconnecting the
fundamental constituents (1-D DWT and 2-D DWT modules) which do not demand transposition
and temporal memory units. Architecture employing the recommended approach is realized in
gate level Verilog HDL. Design is functionally verified, synthesized using Cadence RC design
compiler, and implemented on 90nm standard cell library. Experimental results exhibit that the
proposed approach for the architecture offers significant gain in both area and power.

3. An Efficient Design for Canny Edge Detection Algorithm using Xilinx System
Generator.
Digital Image consists of some informative pixels and some redundant pixels. Edge Detection is
the process of preserving informative pixels and eliminating redundant data which improves
bandwidth and storage efficiency. A sudden change in pixel intensity level is defined as an
Edge. Theoretically, from the literature it is seen that Canny edge detection is the most accurate
algorithm. It is also insensitive to Noise. The only disadvantage of Canny algorithm is its high
computational complexity which limits its maximum frequency of application with high latency
and low throughput. In this paper, tradeoff between Accuracy and Complexity is studied. An
efficient Canny algorithm is designed using Xilinx System Generator. An accuracy is
compromised in order to make it more efficient in terms of resource utilization than the
conventional one.

4. Impact of Radices for the Design of efficient FFT Processor.

Fast Fourier transform (FFT) is always an accepted topic for research from past many years for
different applications in digital system. Implementation of FFT processor is an active growing
field with possible advances. This work focuses on datapath unit of a FFT processor and
presents low complexity and less area consuming datapath unit of FFT by combining
algorithms, arithmetic and architecture. Implementation of radix-2, radix-4 and radix-2^2 FFT
algorithm will be done using different types of multipliers such as Array multiplier, Vedic
multiplier and different type of adders like Ripple carry adder and Carry save adder which are
represented in fixed point (Q-format) for N=8, 16 points. Synthesize is done to know the
performance of LUTs, delay (ns) and Frequency (MHZ) of different radices. Simulation is
performed using Verilog code on Spartan6 family. Xilinx ISE 14.7.
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

5. Multiplication Techniques for an Efficient FIR Filter Design for Hearing aid
Applications.

This study represents designing and implementation of a Low pass Finite Impulse
Response(FIR) filter of order 10.The set of frequencies utilized are that of a hearing aid.To
optimise filter area different multiplication techniques such as constant multiplier,booth
multiplier, modified booth multiplier and vedic multiplier have been used to multiply filter
coefficient with the input sequence.Adders such as Ripple carry adder ,carry save adder, carry
look ahead adders have been used to add the product terms.A comparision is made between
two different structures ,to know the best structure .The Finite Impulse Response(FIR) filter is
designed in MATLAB using equirriple method the same is synthesised on xilinx 14.7 .

6. A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design

Multiplication is a key fundamental function for many error-tolerant applications. Approximate
multiplication is considered to be an efficient technique for trading off energy against
performance and accuracy. This paper proposes an accuracy-controllable multiplier whose final
product is generated by a carry-maskable adder. The proposed scheme can dynamically select
the length of the carry propagation to satisfy the accuracy requirements flexibly. The partial
product tree of the multiplier is approximated by the proposed tree compressor. An multiplier
design is implemented by employing the carry maskable adder and the compressor. Compared
with a conventional Wallace tree multiplier, the proposed multiplier reduced power consumption
by between 47.3% and 56.2% and critical path delay by between 29.9% and 60.5%, depending
on the required accuracy. Its silicon area was also 44.6% smaller. In addition, results from an
image processing application demonstrate that the quality of the processed images can be
controlled by the proposed multiplier design.

7. Novel High speed Vedic Multiplier proposal incorporating Adder based on Quaternary
Signed Digit number system
This paper presents a high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra of
Vedic mathematics that incorporates a novel adder based on Quaternary Signed digit number
system. Three operations are inherent in multiplication: partial products generation, partial
products reduction and addition. A fast adder architecture therefore greatly enhances the speed
of the overall process. A Quaternary logic adder architecture is proposed that works on a hybrid
of binary and quaternary number systems. A given binary string is first divided into quaternary
digits of 2 bits each followed by parallel addition reducing the carry propagation delay. The
design doesn’t require a radix conversion module as the sum is directly generated in binary
using the novel concept of an adjusting bit. The proposed multiplier design is compared with a
Vedic multiplier based on multi voltage or multi value logic [MVL], Vedic Multiplier that
incorporates a QSD adder with a conversion module for quaternary to binary conversion, Vedic
multiplier that uses Carry Select Adder and a commonly used fast multiplication mechanism
such as Booth multiplier. All these designs have been developed using Verilog HDL.

8. Towards Efficient Modular Adders based on Reversible Circuits

Reversible logic is a computing paradigm that has attracted significant attention in recent years
due to its properties that lead to ultra-low power and reliable circuits. Reversible circuits are
fundamental, for example, for quantum computing. Since addition is a fundamental operation,
designing efficient adders is a cornerstone in the research of reversible circuits. Residue
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

Number Systems (RNS) has been as a powerful tool to provide parallel and fault-tolerant
implementations of computations where additions and multiplications are dominant. In this
paper, for the first time in the literature, we propose the combination of RNS and reversible
logic. The parallelism of RNS is leveraged to increase the performance of reversible
computational circuits. Being the most fundamental part in any RNS, in this work we propose
the implementation of modular adders, namely modulo 2n-1 adders, using reversible logic.
Analysis and comparison with traditional logic show that modulo adders can be designed using
reversible gates with minimum overhead in comparison to regular reversible adders.

9. Efficient Protection of the Register File in Soft-processors Implemented on Xilinx

FPGAs.

Soft-processors implemented on SRAM-based FPGAs are increasingly being adopted in on-

board computing for space and avionics applications due to their flexibility and ease of
integration. However, efficient component-level protection techniques for these processors
against radiation-induced upsets are necessary otherwise as system failures could manifest. A
register file is one of the critical structures that stores vital information the processor uses
related to user computations and program execution. In this paper, we present a fault tolerance
technique for the register file of a microprocessor implemented in Xilinx. A parity-based error
detection and switching logic are added for fault masking against single-bit errors. The
effectiveness of the proposed scheme was tested using fault injection. The fault masking
overhead required in terms of FPGA resources was much lower than a traditional Triple Modular
Redundancy protection. Therefore, the proposed scheme is an interesting option to protect the
register file of soft processors.

10. A Comprehensive Study of Edge Detection for Image Processing Applications

In this paper, a comprehensive study of edge detection methods for image processing
applications is carried out to analyze the various edge detectors and the latest trends in edge
detection. An Edge in image processing can be described as discontinuities in intensity from
one pixel to another. Edge detection is one of the most useful image enhancement techniques
to improve the quality of the image analysis process. The principal objective of the edge
detection is to identify and classify the discontinuities in an image. The edge detection in image
processing considerably lessen the quantity of data (pixel) to represent an image and also filters
out the futile information, while keeping the essential structural assets of an image. However, it
is very
difficult to perform edge detection in noisy images since it is uphill task to distinguish both the
edges and noise in the image because both of them having high frequency components. In the
past few decades, numbers of methods have been proposed for the detection of edges in color
and intensity images. However, the edge detection is application (problem) oriented i.e., we
can’t apply a same algorithm for all types of images (applications). In this paper, an elaborative
comparison of various edge detection methods for various image processing applications is
performed.

11. An Improved Canny Edge Detection Algorithm

The traditional Canny algorithm has been applied to image edge detection. However, this
traditional algorithm can't adaptively determine the filtering threshold value and it can't separate
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

targets from background, when filtering the lower contrast image. Therefore, in response to
these problems, this paper proposed an improved method on Canny algorithm. Two
adaptive thresholds were obtained by doing differential operation on amplitude gradient
histogram. Then we connected edge points to get some generalized chains. After that, it needed
to calculate their mean value to delete generalized chains, which are smaller than the mean
value. Finally, the image edge detection results were got by linear fitting method. Experimental
results show that the improved algorithm is more robust to noise and it can clearly separate
targets from background.

12. Implementation of Combined S-Box and InvS-Box of AES

An implementation of a combinational memory-less S-Box and invS-Box (combinely) for
ByteSub and InvByteSub transformations of AES on a same hardware. This is a part of the
combined architecture of AES in which both encryption and decryption can be performed with
an enable pin. Previously LUTs are used to implement the S-Box and InvS-Box of AES
separately, which causes large amount of memory and area. In this paper, the proposed
architecture is implementing using composite field arithmetic in finite fields GF(28) which is
advantageous than LUT approach on the basis of hardware complexity. As both S-Box and
InvS-Box are implementing on a same hardware, there is large reduction in gate count as well
as in area. The power consumption is also reduced because of the resource sharing of
multiplicative inverse module in both S-Box and InvS-Box.

13. Design of Power and Area Efficient Approximate Multipliers

Approximate computing can decrease the design complexity with an increase in performance
and power efficiency for error resilient applications. This brief deals with a new design approach
for approximation of multipliers. The partial products of the multiplier are altered to introduce
varying probability terms. Logic complexity of approximation is varied for the accumulation of
altered partial products based on their probability. The proposed approximation is utilized in two
variants of 16-bit multipliers. Synthesis results reveal that two proposed multipliers achieve
power savings of 72% and 38%, respectively, compared to an exact multiplier. They have better
precision when compared to existing approximate multipliers. Mean relative error figures are as
low as 7.6% and 0.02% for the proposed approximate multipliers, which are better than the
previous works. Performance of the proposed multipliers is evaluated with an image processing
application, where one of the proposed models achieves the highest peak signal to noise ratio.

14. VERILOG Based Simulation of ASK,FSK,PSK,QPSK Digital Modulation Techniques

This paper presents a general architectural overview regarding elementary method of VERILOG
HDL based code simulation for fundamental and widely used digital modulation techniques such
as Binary Amplitude-shift keying (BASK), Binary Frequency-shift keying (BFSK), Binary Phase-
shift keying (BPSK) and Quadrature Phase Shift Keying(QPSK). In this work the idea of
sinusoidal signals that have been generated is plain sailing in nature and based on
fundamentals of signal sampling and quantization. Such concept of sinusoidal signals
generation is not unfamiliar but somehow simplified using sampling and quantization in time and
amplitude domain, respectively. The whole simulation is done on Model Sim and Xilinx-ISE
using VERILOG Hardware descriptive language. The work has been accomplished on Thirty
two bit serial data transmission with self-adjustable carrier frequency and bit duration length.

15. Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

Reversible logic is the emerging field for research in present era. The aim of this paper is to
realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and
comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is
designed using Fredkin gates with minimum Quantum cost. There are many reversible logic
gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate
and many more. Reversible logic is defined as the logic in which the number output lines are
equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1, X2,
X3,…, Xn) (referred to as (n, k) function) is said to be reversible if and only if (i) n is equal to k
and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and
backward that is the inputs can also be retrieved from outputs. When the device obeys these
two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat.
Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its
applications in various fields which include Quantum Computing, Optical Computing,
Nanotechnology, Computer Graphics, low power VLSI Etc., Reversible logic is gaining its own
importance in recent years largely due to its property of low power consumption. The
comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also
presented. The Circuit has been implemented and simulated using Xilinx software.

16. An Approach for Area and Power Optimization of Flipping 3-D Discrete Wavelet
Transform Architecture

In this work, an approach for optimizing the 3- D Discrete wavelet transform (3-D DWT)
architecture is recommended. Conventional 3-D DWT architectures include basic building
blocks such as 1-D DWT module, 2-D DWT module, transpose memory unit, and temporal
memory unit. Proposed 3- D DWT architecture is designed by suitably interconnecting the
fundamental constituents (1-D DWT and 2-D DWT modules) which do not demand transposition
and temporal memory units. Architecture employing the recommended approach is
realized in gate level Verilog HDL. Experimental results exhibit that the proposed approach for
the architecture offers significant gain in both area and power.

17. Hardware Accelerator using Gabor Filters for Image Recognition Applications.
This paper presents the design of a new hardware accelerator, filtering the input data using
Gabor functions and dedicated to image processing. The proposed design obtains a great
reduction in terms of resources if compared to other stateof-the-art implementations. This is
done exploiting the separability of Gabor filters along certain orientations and through a
reorganization of the arithmetic units and the memory structures, achieved thanks to the
absence of frame buffers to store the entire input image and partially processed data. All the
above reported features allow the design to obtain real-time performances

18. A New Recursive Shared Segmented Split Multiply-Accumulate Unit For High Speed
Digital Signal Processing Applications

A new recursive shared segmented split multiply-accumulate (MAC) unit have been proposed
which can be deployed in high speed DSP applications like Fast Fourier Transform (FFT),
Discrete Cosine Transform (DCT), Wavelet Transform (WT) and digital filtering. This paper
presents two design aspects, the former presents the design of new parallel prefix adder which
is responsible in the generation of partial product addition in PPRT network. The latter explains
the design of recursive shared segmented split MAC. The performance of the proposed parallel
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

prefix adder and MAC unit are tested in terms of Xilinx Simulation. The performance of MAC is
examined in terms of slice- LUT utilization, logical level, combinational and sequential path
delay, power and ST (product of slice utilization and combinational/sequential delay).

19. High-performance VLSI architectures for M-PSK modems

M-PSK (phase shift keying) modulation schemes are used in many high-speed applications like
satellite communication, as they are more bandwidth and power efficient compared with other
schemes. This study presents very large scale integrated circuits (VLSI) architectures for
modulators and demodulators of quadrature phase shift keying (QPSK), 8PSK and 16PSK
systems, based on the principle of direct digital synthesis. The proposed modulators
do not use any multiplier in contrast to the conventional modulators and hence they are
relatively fast and area efficient. Based on the coherent detection technique, this study proposes
new demodulation algorithms for 8PSK and 16PSK systems which can be implemented both in
analogue and digital domains. This study also presents VLSI architectures for all the proposed
algorithms. The proposed architectures are described in. The simulation results verify their
functional validity and implementation results show the suitability of the proposed architectures
for satellite communications.

20. An Efficient VLSI Architecture for Data Encryption Standard

To achieve the goal of secure communication, cryptography is an essential operation. Many

applications, including health-monitoring and biometric data based recognition system, need
short-term data security. To design short-term security based applications, there is an essential
need of high-performance, low cost and area-efficient VLSI implementation of lightweight
ciphers. Data encryption standard (DES) is well-suited for the implementation of low-cost
lightweight cryptography applications. In this paper, we propose an efficient VLSI architecture
for DES algorithm based encryption/decryption engine. Depending upon the
encryption/decryption needs, the same set of architecture performs both encryption and
decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based
architecture is used to implement the substitution operations (SBoxes). The proposed
architecture is modeled in the Verilog design language .

21. Simulation of Complex Multiplier Using Minimum Delay Vedic Real Multiplier
Architecture

Complex numbers multiplication is a key arithmetic operation to be performed with high speed
and less consumption of power in high performance systems such as wireless communications.
Hence, in this paper, two possible architectures are proposed for a Vedic real multiplier based
on the URDHVA TIRYAKBHYAM (Vertically and cross wise) sutra of Indian
Vedic mathematics and an expression for path delay of an N×N Vedic real multiplier with
minimum path delay architecture is developed. Then, architectures of four Vedic real multipliers
solution, three Vedic real multipliers solution of complex multiplier are presented. The
architecture of Vedic real multiplier with minimum path delay is used in the implementation of
complex multiplier. The architectures for the four multiplier solution and three multiplier solution
of complex multiplier for 32 x 32 bit complex numbers multiplication are coded in VHDL and
implemented through Xilinx ISE 13.4 navigator and Modelsim 5.6. Finally, the results are
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

compared with that of the four and three real multipliers solutions using the conventional Booth
and Array multipliers.

22. Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height
Reduction.

In this paper, we describe an optimization for binary radix-16 (modified) Booth recoded
multipliers to reduce the maximum height of the partial product columns to n/4 for n = 64-bit
unsigned operands. This is in contrast to the conventional maximum height of (n + 1)/4.
Therefore, a reduction of one unit in the maximum height is achieved. This reduction may add
flexibility during the design of the pipelined multiplier to meet the design goals, it may allow
further optimizations of the partial product array reduction stage in terms of area/delay/power
and/or may allow additional addends to be included in the partial product array without
increasing the delay. The method can be extended to Booth recoded radix-8 multipliers, signed
multipliers, combined signed/unsigned multipliers, and other values of n.

23. Efficient Implementation of Address Generator for WiMAX Deinterleaver with

Different Modulation Schemes

The allowed Modulation Schemes and code rates for WiMAX Interleaver / Deinterleaver design
demand the superfluity of hardware when integrated in a single electronic device. This paper
focusses on area efficiency and the efficient hardware utilization of resources by the overall
Deinterleaver circuit using resource sharing and proposes an amendment of the designs
suggested by earlier works on WIMAX Deinterleaver. WiMAX (Worldwide Interoperability for
Microwave Access), defined by IEEE 802.16e standard, was created in 2001. In this paper, the
modifications in the implemented circuitry of the algorithm designed by eliminating the Floor
Function have been proposed keeping in view the optimality of the final
design in terms of generalization of the address generator to accept random code rates and the
final hardware efficiency.

24. FinFET Based 4-BIT Input XOR/XNOR Logic Circuit

In this paper a structure for direct 4-BIT XOR/XNOR logic cell is proposed. This structure is
proposed using pass transistor logic with FinFETs. This structure has less delay for the reason
that its critical path consists of a minimum number of transistors. The basic advantage of this
circuit is their symmetry in the logic. This design has a full voltage swing at the outputs and
hence it has the good driving capability. The proposed design produces perfect outputs, even at
low voltages and at high frequencies with the lesser transistor count. The proposed design is
simulated using Cadence 20 nm FinFET technology at various supply voltages assorting from
+0.6 V to +0.9 V. The simulation results illustrate that the proposed design has less delay and
as well as less power consumption.

25. Adiabatic Approach for Charge Restoration in Low Power Digital Circuits
The main idea dominating the current trends in VLSI circuits is to offer large scale integration
coupled with extensive power reduction solutions, even with newer devices and topologies[1]-
[2].However the significant increase in the gate switching energy results in higher power
dissipation and costly heat sinks. At that point, to constrain the dissipation of power, elective
arrangements at various level of deliberation are suggested. The power dissipation is
significantly reduced by the adiabatic logic structure at the expense of circuit complexity to
accomplish low power dissipation, switching procedures are used. Adiabatic logic discussed
VLSIPROJECT ABSTRACTS
Network Security & Cryptographic Sciences, Digital Signal Processing, Arithmetic Core and Digital Electronics,
DigitalCommunications and Information theory, Digital Image Processing, Bus Protocols and System on Chip

here provides an approach to use the energy repeatedly that is put away in the load capacitors.
This paper briefs some of the adiabatic logic families such as PFAL and SAL. It aims at
comparing the effectiveness of adiabatic logic with respect to power dissipation and delay. The
implementation of the 4 bit CLA validates the credibility of the logic .A graph has been plotted to
show the effect of temperature on sub threshold adiabatic logic based 4 bit CLA. The simulation
results obtained from the vituoso environment of cadence tool suggests three folds power
reduction in the ECRL topology as compared to the other existing topology.

26. High-Performance and Energy-Efficient Approximate Multiplier for Error-Tolerant

Applications
Approximate computing in the arithmetic logic has recently emerged as a promising solution for
energy-efficient designs in error-tolerant applications. So not only the performance but also the
error characteristic become important criteria. In this study, we propose a high-performance and
energy-efficient approximate multiplier with suitable error characteristics by using low energy
approximate adders for lower bits. Simulation results of 16x16 multipliers show that area, delay,
and power saving are significantly improved by the proposed multiplier compared to the
conventional binary multiplier. In addition, error metrics of the proposed multiplier have shown
better results than other approximate multipliers.

27. Low-Power and High-Speed Approximate Multiplier Design with a Tree

Compressor
Many applications, such as image signal processing, has an inherent tolerance for insignificant
inaccuracies. Multipliers are key arithmetic functions for many error-tolerant applications.
Approximate multipliers are considered an efficient technique to trade off energy relative to
performance and accuracy. We propose two approximate multiplier designs that demonstrate
lower power consumption and shorter critical path delay than the conventional multiplier by
employing an approximate tree compressor. The proposed compressor halves the height of the
partial product tree and generates a vector to recover accuracy. Compared to the conventional
Wallace tree multiplier, one of the proposed 8-bit approximate multipliers reduces power
consumption and critical path delay by 59.9% and 36.3%, respectively. Furthermore, with 0.28%
normalized mean error distance, the silicon area required to implement the multiplier is reduced
by 50.1%. The proposed approximate multiplier designs outperform previous multipliers relative
to power consumption, critical path delay, and design area.