VINAYAKA MISSIONS UNIVERSITY

V.M.K.V ENGINEERING COLLEGE, SALEM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Regulation - 2012
M.E – Applied Electronic
QUESTION BANK– I SEMESTER
DSP PROCESSORS
UNIT-I
PART-A

1. What is mean by multiple accumulators (MAC)?

2. How many memory accesses/clock period required for the MACD instructions
3. Draw the von-Neumann architecture
4. Draw modified Harvard architecture
5. Define multiple access memory
6. Draw the block diagram of dual port memory and explain
7. Define immediate addressing mode
8. Write short notes on direct addressing mode
9. Write short notes on memory mapped addressing
10. Define on-chip timer
11. Write short notes on serial port in P-DSP
12. Define TDM serial port in P-DSP
13. Write short notes on parallel port in P-DSP
14. Define bit I/O port in P-DSP
15. Give the advantages of RISC
16. List out the advantages of CISC
17. compare RISC and CISC
18. What is VLIW architecture?
19. What are the types of addressing?
20. Draw Harvard architecture.
21. Write about von-Neumann architecture
22. Draw von-Neumann architecture
23. Write about memory access in P-DSP.
24. Write advantages of Harvard architecture
25. What is pipe line process?
PART -B
1. Explain about on-chip peripherals
2. Explain about special addressing modes in P-DSP
3. Explain about VLIW architecture and their pipelining functions
4. Write short notes on multiplier and multiplier accumulator (MAC)
5. Explain about
a. von-Neumann architecture
b. Harvard architecture
6. Explain about Modified Bus Structures - DSP
7. Explain about pipe line process
8. Explain about multiport memory
9. Write about Harvard architecture with diagram
10. Explain pipelining functions in VLIW architecture.
 UNIT-II

PART -A
1. What are the block repeat register and explain each?
2. What you know about memory mapped register?
3. Define on-chip memory protection
4. Define On-chip peripherals in ‘c5x DSP
5. State software programmable wait state generator
6. What is BSP in ‘c5x?
7. Define user mask able interrupt
8. What are the addressing modes in ‘c5x DSP?
9. Define PUSH and POP instructions in ‘c5x DSP
10. write short notes on repeat instructions in ‘c5x DSP
11. Define pipe line conflicts
12. Draw the block diagram of ‘c5x dsp
13. Write a program for Fibonacci series in ‘c5x
14. write short notes on convolution using mad instructions
15. Give the format of timer control register in ‘c5x
16. What are the addressing modes?
17. Write short notes on PUSH instructions.
18. Write short notes on POP instructions.
19. Define non mask able interrupt
20. Define interrupt
21. Write short notes on user mask able interrupt
22. Define convolution.
23. What is control register?
24. Write about pipeline structure.
25. Draw internal architecture of ‘c5x.
PART -B
1. Explain in detail about internal architecture of ‘c5x
2. Explain on chip peripherals in ‘c5x
3. Explain c50-based DSP starter kit
4. Explain program in ‘c5x for processing real time signal
5. Draw the c5x DSK block diagram and explain it
6. Explain on-chip timer in c5x and programming its mode
7. Explain 5x serial port block diagram and its operation
8. Explain an overview of the AIC
9. Write short notes on
i. AIC
ii. Interfacing the DSP and AIC
10. Explain about
i. c5x DSK
ii. c50-based DSP starter kit

UNIT –III
PART -A
1. What are the CPU register files in ‘c3x?
2. Write Short notes on extended-precision register in ‘c3x
3. Write notes about program counter and instructions register in ‘c3x
4. State CACHE memory in ‘c3x
5. What is DMA controller in ‘c3x?
 6. What is data format and give it types?
7. Write Short notes on three operand addressing mode in ‘c3x
8. Write about control addressing modes in ‘c3x
9. What is an interlocked operations instruction in ‘c3x?
10. Write notes on DSK memory map in ‘c3x
11. write a program for ‘c3x for generation and finding sum of series 1^2+2^2+…..+n^2
12. Draw the functional block diagram of c3x timer
13. How to calculate the output frequency of the timer either in clock mode or pulse mode?
14. Draw c3x starter kit block diagram
15. Write short notes on low power control instructions
16. How many addressing modes are there in TMS320C25?
17. What are the major ports are available in TMS320C30?
18. Write short notes on chip memory
19. Write short notes on chip peripherals
20. Define memory accessing.
21. Define pipelining.
22. Draw the TMS320c3x block diagram
23. What is CPU register file?
24. State CACHE memory.
25. What is DMA controller?

PART -B
1. Draw the TMS320c3x block diagram architecture
2. Explain in detail group of addressing in c3x
3. Explain in detail about c3x starter kit
4. Write a program for generation and finding the sum of series
5. Explain about central processing unit in ‘c3x internal architecture
6. Explain CPU register file in ‘c3x
7. Explain memory organization in ‘c3x
8. Explain cache memory in ‘c3x
9. Write notes on
i) Serial ports in ‘c3x
ii) DMA controller in ‘c3x
10. Explain 210XX series of DSP processors.

UNIT –IV
PART –A

1. Define ADSP-2100
2. What type of architecture employed in ADSP-2100?
3. Define program sequencer
4. Draw the block diagram of ALU
5. Define IMASK.
6. What is meant by ICNTL?
7. Define bit memory
8. Define program counter
9. Define stack pointer
10. Define relative addressing mode.
11. Define correlates
12. Define sampling theorem
13. What is meant by repeatability?
14. Define on chip timer
15. Define absolute address
16. List the advantages of Blackfin-processor
17. What is meant by Nested Zero-overhead loop?
18. Application of adaptive Filter
19. Define pipelining
20. What are the advantages of CISC?
21. What is Z-transform?
22. List the advantages of DSP.
23. Define decimation.
24. Give the digital filter classification.

25. What is meant by multi rate signal processing?

PART –B

1. Write notes on
i. ALU
ii. DAG
2. Explain ADSP-21XX with suitable block diagram.
3. Write notes on
i. PMD
ii. PMA

4. With a neat block diagram explain PMD-DMD bus exchange.

5. Discuss about system interface in ADSP-21XX
6. Explain Blackfin DSP processor.
7. Discuss about MAC.
8. Discuss about varies addressing mode.
9. Explain the processor core of Blackfin processor
10. Write notes on assembly language instructions.

UNIT-V
PART-A

1. Write short notes on PMST in c54x?

2. What is the use of temporary register in c54x?
3. What are the on-chip peripherals in c54x?
4. Draw c62x processor block diagram
5. Write about code composer studio
6. Give the format of CCFG register
7. Define implicit reference
8. What is ESSI?
9. Draw the data ALU register of Motorola DSP56301
10. Write short notes on circular buffer size register in c54x?
11. What is Barrel shifter in c54x?
12. Draw CSSU in c54x
13. Write short notes on c54x pipeline?
 14. Write notes on exponent encoder?
15. What is CCFG register?
16. What is the purpose of ALU register?
17. What is meant by PMST?
18. Draw 54x internal memory organization
19. Draw architecture of ‘c62x.
20. What is the purpose of multiplier/adder unit?
21. Write features of TMS320c62x processor.
22. Write short notes on 54x buses.
23. What is internal memory organization?
24. What is CPU register file?
25. State CACHE memory.

PART B

1. write notes on
i.’54x buses
ii.’54x internal memory organization
2. Explain in detail about ALU in ‘54x
3. Explain in detail about ‘c54x multiplier/adder unit
4. Explain in detail about architecture of ‘c62x
5. Explain multiplier/adder unit in c54x
6. Explain about TMS320c62x processor block diagram
7. Explain with block diagram of Motorola DSP563XX.
8. Compare the features of DSP family processors.
9. Write short notes on
i) pipeline operation
ii) code composer studio
10. Explain the architecture of TMS320c62x processor.