-- Esta página en el design

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-- Nombre:
-- Documento:
-- Fecha:
-- Proyecto:
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;

entity contador is
Port ( clk, reset : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (3 downto 0)
);
end contador;

architecture Behavioral of contador is

-- COMPONENTS
-- SIGNALS

signal Q:STD_LOGIC_VECTOR (3 downto 0);

begin
-- DISEÑO

process (clk)
begin
if clk'event and clk='1' then
if reset='1' then
Q <= "0000";
else
Q <= Q+1;
end if;
end if;
end process;

salida <= Q;

end Behavioral;

--- A partir de aquí en el testbech

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Simulacion is
--
end Simulacion;

architecture Behavioral of Simulacion is

component contador
Port ( clk, reset : in STD_LOGIC;
Salida : out STD_LOGIC_VECTOR (3 downto 0)
);
end component;

-- Señales de las entradas

signal clk, reset : STD_LOGIC:= '0';

-- Señales de salidas
signal Salida : STD_LOGIC_VECTOR (3 downto 0);

constant PERIOD : time := 10 ns; -- Antes del begin

begin

-- Después del begin

process begin
clk <= '0';
wait for PERIOD/2;
clk <= '1';
wait for PERIOD/2;
end process;

UO: contador Port map (

clk => clk,
reset => reset,
salida=> salida
);

process begin
--- Estímulos de la simulación wait for 100 ns;
wait for 100 ns;
reset <= '0';
wait for 100 ns;

reset <= '1';

wait for 100 ns;

reset <= '0';

wait for 100 ns;

wait;
end process;

end Behavioral;