b522f Compal LA-8581P PDF

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起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ
D D
Compal Confidential
C
QAQ10/11 C
LA-8581P REV1.0 Schematic

B B
Intel Ivy Bridge/Pather Point

UMA&OPT
2012-04-23 Rev 1.0
A A
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/09/23 Deciphered Date 2011/12/30 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8581
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019IE
Date: Friday, August 24, 2012 Sheet 1 of 60
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Compal Confidential
Model Name : QAQ10/11
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ Fan Control
page 6
File Name : LA-8581P 100MHz PCI-E 2.0x16 5GT/s PER LANE Mobile Ivy Bridge
PEG(DIS)
133MHz
CPU Dual Core
D Memory BUS(DDRIII) D
VGA (DDR3) Socket-rPGA988B/989 Dual Channel 204pin DDRIII-SO-DIMM X2

1.5V DDRIII 1333/1600 BANK 0, 1, 2, 3 page 11,12
37.5mm*37.5mm page 5,6,7,8,9,10
NVIDIA N13P-GLP, 128bit with 1GB/2GB
page 13,14,15,16,17,18,19,20,21 DMI X4 FDI

USB/B Right USB Left Port USB3.0
USB port 3,4 USB port 1,9 USB port 0
USB page 44 page 43 page 40
page 22 OPT & UMA
CRT Intel Smart Card Int. Camera Finger Print
HDMI Conn. USB port 2 USB port 10 USB port 11
page 24 page 23
OPT & UMA Panther Point-M page 39 page 23 page 40
LCD Conn. SATA port 0

989pin FCBGA SATA HDD0
C
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz 5V 1.5GHz(150MB/s) page 34 C
port 4 port 2 port 6 port 3 port 5 port 1 HM76 SATA port 2 SATA ODD
PCIeMini Card 5V 1.5GHz(150MB/s) page 34
WLAN &BT PCIe Mini Card WWAN RTL8111E&Intel 82579
&SIM PCIe port 1
USB Port 13 SATA port 4
PCIe Port 5 E-SATA
PCIe Port 2 5V 1.5GHz(150MB/s) USB port 3 page 43
USB Port 12 page 35,42
page 36 page 36 page 25 ~ 32

HD Audio 3.3V 24.576MHz/48Mhz
25mm*25mm
RJ45 BIOS ROM
page 33
JMB385/388 Card Reader Express Card page 39
LPC BUS HDA Codec
&1394 PCIe Port 3 ALC259
PCIe Port 6 USB port 8 page 38
B page 37 page 39 B
33MHz
USB&Function/B SIO ENE KB9012 TPM 1.2

page 43
Page 47 Int. MIC
page 41 page 34 MIC CONN HP CONN SPK CONN
page 38 page 38 page 38 page 38
Power/B
page 43
Touch Pad Int.KBD

Touch Pad/B page 43 page 40
page 43
RTC CKT.
page 25,47
A
DC/DC Interface A
page 45

Power Circuit DC/DC Issued Date 2011/09/23 Deciphered Date 2011/12/30 Title
page 46,47,48,49,50,51,52,53,54,55,56,57,58 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B
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Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW

B+
SUSP
N-CHANNEL DESIGN CURRENT 4A +5VS
SI4800
SUSP#
DESIGN CURRENT 2A +1.8VS
SY8033BDBC
D D
RT8205
Ipeak=5A, Imax=3.5A, Iocp min=7.7 DESIGN CURRENT 5A +3VALW
WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
N-CHANNEL DESIGN CURRENT 4A +3VS
SI4800
VGA_ENVDD
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413
BT_PWR#
DESIGN CURRENT 180mA +BT_VCC
P-CHANNEL
AO-3413
PCIE_OK
DESIGN CURRENT 100mA +3VS_DELAY
C C
P-CHANNEL
AO-3413
VR_ON
DESIGN CURRENT 52A +CPU_CORE
ISL95831CRZ
DESIGN CURRENT 30A +GFX_CORE
DGPU_PWR_EN / SUSP#
DESIGN CURRENT 26A +VGA_CORE

APW7138
SUSP#
Ipeak=18A, Imax=12.6A, Iocp min=19.8 DESIGN CURRENT 18A +1.05VS_VCCP
G5603RU1U
B B
SYSON
Ipeak=15A, Imax=10.5A, Iocp min=16.5 DESIGN CURRENT 15A +1.5V +1.5V_CPU
G5603RU1U
CPU1.5V_S3_GATE / SUSP

APL5336
SUSP
SI4856
SUSP#
DESIGN CURRENT 6A +VCCSA

A A
G5603RU1U

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B
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Voltage Rails起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ BOM configu table

Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
SKU Description Bom config
BATT+ Battery power supply (12.6V) N/A N/A N/A 1 QAQ10 UMA GIGA W/HDMI DA8@/8111E@/UMA@/TF@/10@/WIN8@/388@/COM@ 4619IE30L01
B+ AC or battery power rail for power circuit. N/A N/A N/A

2 QAQ11 DIS N13PGLP1G W/HDMI DA8@/8111E@/OPT@/TF@/11@/WIN8@/388@/COM@ 4619IE30L11
+VCC_CORE Core voltage for CPU ON OFF OFF
D
DA8@/8111E@/OPT@/030@/13@/WIN8@/388@/COM@ D
+VGA_CORE Core voltage for GPU ON OFF OFF 3 QAQ13 DIS GLP2G W/HDMI/TPM /TPM@/IN_TPM@ 4619IE30L21
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
4
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF 5
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF
6
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF 7
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF
8
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF
DA8@/8111E@/PCH@/UMA@/OPT@/385@/388@/389@/IN_TPM@/TPM@/WB_TPM@/SM@/COM@/030@/TF@
/WIN8@/10@/11@/12@/13@/Rev02@/Rev03@/Rev04@/Rev10@/VPRO@
+3VALW +3VALW always on power rail ON ON ON*
+3VALW_EC +3VALW always to KBC ON ON ON* 388@: with 1394; IN_TPM@: TPM chip from vendor "INFINEON";
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 389@: without 1394. WB_TPM@: TPM chip from vendor "Nuvoton"
With TPM SKUs: mount "TPM@ and IN_TPM@ " or "TPM@ and WB_TPM@".
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON*
+3VS +3VALW to +3VS power rail ON OFF OFF
C If has Vpro@, no 8111E@, Rev02@,Rev03@, Rev04@ and Rev10@. C
+5VALW +5VALWP to +5VALW power rail ON ON ON*
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
X76 AND VGA configu table
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* SKU Description Config
ZZZ SAM1G@ ZZZ HY1G@ QAQ11 DIS N13P-GLP
+RTCVCC RTC power ON ON ON 1 4619IE30L11 SAM 1G Hynix 1G
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 2
ZZZ SAM2G@ ZZZ HY2G@ QAQ13 DIS N13P-GLP
3 4619IE30L21 SAM 2G Hynix 2G
SIGNAL
4
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock 5
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Board ID Rb
Board ID
Table Ra VCC V min Vtyp Vmax PCB Revision
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
0 0 100K +/- 5% 3.3V +/- 5% 0V 0V 0V 0.1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 8.2K +/- 5% 100K +/- 5% 3.3V +/- 5% 0.216 V 0.250 V 0.289 V 0.2
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 2 18K +/- 5% 100K +/- 5% 3.3V +/- 5% 0.436 V 0.503 V 0.538 V 0.3
B B
3 33K +/- 5% 100K +/- 5% 3.3V +/- 5% 0.712 V 0.819 V 0.875 V 0.4
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
4 56K +/- 5% 100K +/- 5% 3.3V +/- 5% 1.036 V 1.185 V 1.264 V 1.0
5 100K +/- 5% 100K +/- 5% 3.3V +/- 5% 1.453 V 1.650 V 1.759 V VPRO
6 200K +/- 5% 100K +/- 5% 3.3V +/- 5% 1.935 V 2.200 V 2.341 V
EC SM Bus1 address EC SM Bus2 address 7 NC 100K +/- 5% 3.3V +/- 5% 2.500 V 3.300 V 3.300 V
Power Device Address Power Device Address

+3VL charger 0x12 +3VS VGA(N13P-GLP) 0X9E
PCH And PCBA table
+3VL Smart Battery 0x16 +3VS PCH 0x96
UPCH1 UPCH1
BD82HM76 SLJ8E C1 BGA 989P PCH 030! BD82QM77 QPRE C1 BGA 989P PCH
PCH 8111E@ VPRO@
PCH SM Bus address ZZZ DA8@ ZZZ DAZ@
Power Device Address

+3VALW PCH
PCB
A +3VS Clock Generator 1101 001x b PCB LA-8581P REV1 M/B PCB QAQ10 A
+3VS DDR DIMMA 1001 000x b

+3VS DDR DIMMB 1001 010x b
+3VS Slot#1--WLAN Security Classification Compal Secret Data Compal Electronics, Inc.
Custom B
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+1.05VS_VCCP
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ JCPU1I
1
RC2
24.9_0402_1%
F22
T35 VSS234 F19
T34 VSS161 VSS235
2
PEG_ICOMPI and RCOMPO signals should be shorted and routed VSS162 E30
with - max length = 500 mils - typical impedance = 43 mohms T33 VSS236 E27
JCPU1A T32 VSS163 VSS237
J22 PEG_ICOMPO signals should be routed with - max length = 500 mils VSS164 E24
PEG_ICOMPI J21 - typical impedance = 14.5 mohms T31 VSS238 E21
PEG_ICOMPO T30 VSS165 VSS239
B27 H22 VSS166 E18
D
DMI_RX#[0] PEG_RCOMPO PEG_COMP T29 VSS240 E15 D
<27> DMI_CRX_PTX_N0 B25 T28 VSS167 VSS241
A25 DMI_RX#[1] VSS168 E13
<27> DMI_CRX_PTX_N1 DMI_RX#[2] K33 T27 VSS242 E10
<27> DMI_CRX_PTX_N2 B24 PEG_RX#[0] PCIE_GTX_C_CRX_N[0..15] <13> T26 VSS169 VSS243
DMI_RX#[3] M35 VSS170 E9
<27> DMI_CRX_PTX_N3 PEG_RX#[1] L34 P9 VSS244 E8
B28 PEG_RX#[2] PCIE_GTX_C_CRX_N0 P8 VSS171 VSS245
B26 DMI_RX[0] J35 PCIE_GTX_C_CRX_N1 VSS172 E7
<27> DMI_CRX_PTX_P0 DMI_RX[1] PEG_RX#[3] J32 P6 VSS246 E6
<27> DMI_CRX_PTX_P1 A24 PEG_RX#[4] PCIE_GTX_C_CRX_N2 P5 VSS173 VSS247
DMI
B23 DMI_RX[2] H34 PCIE_GTX_C_CRX_N3 VSS174 E5
<27> DMI_CRX_PTX_P2 DMI_RX[3] PEG_RX#[5] H31 P3 VSS248 E4
PEG_RX#[6] PCIE_GTX_C_CRX_N4 P2 VSS175 VSS249
<27> DMI_CRX_PTX_P3 G33 E3
G21 PEG_RX#[7] PCIE_GTX_C_CRX_N5 N35 VSS176 VSS250
E22 DMI_TX#[0] G30 PCIE_GTX_C_CRX_N6 PEG signals swapped at VGA side. VSS177 E2
<27> DMI_CTX_PRX_N0 DMI_TX#[1] PEG_RX#[8] F35 N34 VSS251 E1
F21 PEG_RX#[9] PCIE_GTX_C_CRX_N7 N33 VSS178 VSS252
<27> DMI_CTX_PRX_N1 D21 DMI_TX#[2] E34 PCIE_GTX_C_CRX_N8 VSS179 D35
<27> DMI_CTX_PRX_N2 DMI_TX#[3] PEG_RX#[10] E32 N32 VSS253 D32
PEG_RX#[11] PCIE_GTX_C_CRX_N9 N31 VSS180 VSS254
<27> DMI_CTX_PRX_N3 D33 D29
G22 PEG_RX#[12] PCIE_GTX_C_CRX_N10 N30 VSS181 VSS255
D22 DMI_TX[0] D31 PCIE_GTX_C_CRX_N11 VSS182 D26
<27> DMI_CTX_PRX_P0 DMI_TX[1] PEG_RX#[13] B33 N29 VSS256 D20
F20 PEG_RX#[14] PCIE_GTX_C_CRX_N12 N28 VSS183 VSS257
<27> DMI_CTX_PRX_P1 DMI_TX[2] C32 PCIE_GTX_C_CRX_N13 D17
C21 PEG_RX#[15] VSS184 VSS258
PCI EXPRESS* - GRAPHICS

<27> DMI_CTX_PRX_P2 DMI_TX[3] N27 C34
PCIE_GTX_C_CRX_N14 N26 VSS185 VSS259
<27> DMI_CTX_PRX_P3 J33 PCIE_GTX_C_CRX_N15 VSS186 C31
PEG_RX[0] L35 PCIE_GTX_C_CRX_P[0..15] <13> M34 VSS260
VSS187 C28
PEG_RX[1] K34 L33 VSS261
PCIE_GTX_C_CRX_P0 VSS188 C27
PEG_RX[2] H35 L30 VSS262
A21 PCIE_GTX_C_CRX_P1 VSS189 C25
FDI0_TX#[0] PEG_RX[3] H32 L27 VSS263
H19 PCIE_GTX_C_CRX_P2 VSS190 C23
<27> FDI_CTX_PRX_N0 FDI0_TX#[1] PEG_RX[4] G34 L9 VSS264
FDI_CTX_PRX_N0 E19 PCIE_GTX_C_CRX_P3 VSS191 C10
<27> FDI_CTX_PRX_N1 FDI0_TX#[2] PEG_RX[5] G31 L8 VSS265
F18 PCIE_GTX_C_CRX_P4 VSS192 C1
<27> FDI_CTX_PRX_N2 FDI_CTX_PRX_N1 FDI0_TX#[3] PEG_RX[6] F33 L6 VSS266
FDI_CTX_PRX_N2 B21 PCIE_GTX_C_CRX_P5 VSS193 B22
Intel(R) FDI
<27> FDI_CTX_PRX_N3 FDI1_TX#[0] PEG_RX[7] F30 L5 VSS267
FDI_CTX_PRX_N3 C20 PCIE_GTX_C_CRX_P6 VSS194 B19
<27> FDI_CTX_PRX_N4 FDI1_TX#[1] PEG_RX[8] E35 L4 VSS268
D18 PCIE_GTX_C_CRX_P7 B17
<27>
<27>
<27>
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
E17 FDI1_TX#[2]
FDI1_TX#[3]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
E33
F32
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P9
L3
L2
L1
VSS195
VSS196
VSS197
VSS VSS269
VSS270
VSS271
B15
B13
D34 PCIE_GTX_C_CRX_P10 B11
C FDI_CTX_PRX_N7 PEG_RX[12] K35 VSS198 VSS272 C
A22 E31 PCIE_GTX_C_CRX_P11 B9
PEG_RX[13] K32 VSS199 VSS273
G19 FDI0_TX[0] C33 PCIE_GTX_C_CRX_P12 B8
<27> FDI_CTX_PRX_P0 PEG_RX[14] K29 VSS200 VSS274
E20 FDI0_TX[1] B32 PCIE_GTX_C_CRX_P13 B7
<27> FDI_CTX_PRX_P1 FDI_CTX_PRX_P0 PEG_RX[15] K26 VSS201 VSS275
G18 FDI0_TX[2] PCIE_GTX_C_CRX_P14 B5
<27> FDI_CTX_PRX_P2 FDI_CTX_PRX_P1 J34 VSS202 VSS276
B20 FDI0_TX[3] M29 PCIE_GTX_C_CRX_P15 OPT@ C222 1 2 0.1U_0402_16V7K B3
<27> FDI_CTX_PRX_P3 FDI_CTX_PRX_P2 PEG_TX#[0] OPT@ C136 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N[0..15] <13> J31 VSS203 VSS277
FDI_CTX_PRX_P3 C19 FDI1_TX[0] M32 B2
<27> FDI_CTX_PRX_P4 PEG_TX#[1] OPT@ C60 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N0 H33 VSS204 VSS278
FDI_CTX_PRX_P4 D19 FDI1_TX[1] M31 PCIE_CTX_GRX_N0 A35
<27> FDI_CTX_PRX_P5 PEG_TX#[2] PCIE_CTX_C_GRX_N1 H30 VSS205 VSS279
FDI_CTX_PRX_P5 F17 FDI1_TX[2] L32 PCIE_CTX_GRX_N1 A32
<27> FDI_CTX_PRX_P6 PEG_TX#[3] OPT@ C75 1 1
OPT@ C67 22 0.1U_0402_16V7K PCIE_CTX_C_GRX_N2
0.1U_0402_16V7K H27 VSS206 VSS280
FDI1_TX[3] L29 PCIE_CTX_GRX_N2 A29
<27> FDI_CTX_PRX_P7 FDI_CTX_PRX_P6 PEG_TX#[4] PCIE_CTX_C_GRX_N3 H24 VSS207 VSS281
FDI_CTX_PRX_P7 J18 K31 PCIE_CTX_GRX_N3 OPT@ C220 1 2 0.1U_0402_16V7K A26
PEG_TX#[5] OPT@ C118 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N4 H21 VSS208 VSS282
J17 FDI0_FSYNC K28 PCIE_CTX_GRX_N4 A23
<27> FDI_FSYNC0 PEG_TX#[6] PCIE_CTX_C_GRX_N5 H18 VSS209 VSS283
FDI1_FSYNC J30 PCIE_CTX_GRX_N5 A20
<27> FDI_FSYNC1 FDI_FSYNC0 PEG_TX#[7] J28 PCIE_CTX_GRX_N6 OPT@ C62 1 1
OPT@ C59 22 0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_CTX_C_GRX_N6 H15 VSS210 VSS284
FDI_FSYNC1 H20 PEG_TX#[8] OPT@ C115 1 2 0.1U_0402_16V7K VSS211 A3
FDI_INT H29 PCIE_CTX_GRX_N7 PCIE_CTX_C_GRX_N7 H13 VSS285
<27> FDI_INT PEG_TX#[9] OPT@ C70 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N8 H10 VSS212
FDI_INT J19 G27 PCIE_CTX_GRX_N8
PEG_TX#[10] OPT@ C197 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N9 H9 VSS213
H17 FDI0_LSYNC E29 PCIE_CTX_GRX_N9
<27> FDI_LSYNC0 PEG_TX#[11] F27 PCIE_CTX_C_GRX_N10 H8 VSS214
FDI_LSYNC0 FDI1_LSYNC PCIE_CTX_GRX_N10
OPT@ C61 1 2 0.1U_0402_16V7K
<27> FDI_LSYNC1 PEG_TX#[12] D28 OPT@ C223 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N11 H7 VSS215
FDI_LSYNC1 PCIE_CTX_GRX_N11
PEG_TX#[13] F26 PCIE_CTX_GRX_N12 PCIE_CTX_C_GRX_N12 H6 VSS216
PEG_TX#[14] E25 PCIE_CTX_GRX_N13 OPT@ C88 1 1
OPT@ C68 22 0.1U_0402_16V7K PCIE_CTX_C_GRX_N13
0.1U_0402_16V7K H5 VSS217
A18 PEG_TX#[15] PCIE_CTX_GRX_N14 PCIE_CTX_C_GRX_N14 H4 VSS218
A17 eDP_COMPIO OPT@ C209 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_N15 VSS219
M28 PCIE_CTX_GRX_N15 H3
RC4 24.9_0402_1% B16 eDP_ICOMPO PEG_TX[0] PCIE_CTX_C_GRX_P[0..15] <13> VSS220
M33 H2
1 2 eDP_HPD# PEG_TX[1] PCIE_CTX_GRX_P0 OPT@ C66 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P0 VSS221
M30 OPT@ C224 1 2 0.1U_0402_16V7K H1
PEG_TX[2] L31 PCIE_CTX_GRX_P1 PCIE_CTX_C_GRX_P1 G35 VSS222
C15 PEG_TX[3] L28 PCIE_CTX_GRX_P2 OPT@ C89 1 1
OPT@ C69 22 0.1U_0402_16V7K PCIE_CTX_C_GRX_P2
0.1U_0402_16V7K G32 VSS223
+1.05VS_VCCP D15 eDP_AUX PEG_TX[4] PCIE_CTX_GRX_P3 OPT@ C221 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P3 VSS224
K30 G29
EDP_COMP eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_P4 OPT@ C135 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P4 VSS225
K27 G26
2 1 PEG_TX[6] J29 PCIE_CTX_GRX_P5 OPT@ C71 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P5 G23 VSS226
eDP
+1.05VS_VCCP C17 PEG_TX[7] J27 PCIE_CTX_GRX_P6 PCIE_CTX_C_GRX_P6 G20 VSS227

EDP_HPD# eDP_TX[0] PEG_TX[8] VSS228
10K_0402_5% F16 H28 PCIE_CTX_GRX_P7 OPT@ C74 1 1
OPT@ C72 22 0.1U_0402_16V7K PCIE_CTX_C_GRX_P7
0.1U_0402_16V7K G17
C16 eDP_TX[1] PEG_TX[9] G28 PCIE_CTX_GRX_P8 PCIE_CTX_C_GRX_P8 G11 VSS229
B @ R88 B
G15 eDP_TX[2] PEG_TX[10] E28 PCIE_CTX_GRX_P9 C214 1 1
OPT@ C117
OPT@ 22 0.1U_0402_16V7K PCIE_CTX_C_GRX_P9
0.1U_0402_16V7K F34 VSS230
eDP_TX[3] PEG_TX[11] F28 PCIE_CTX_GRX_P10 PCIE_CTX_C_GRX_P10 VSS231
F31
C18 PEG_TX[12] D27 PCIE_CTX_GRX_P11 OPT@ C78 1 2 0.1U_0402_16V7K PCIE_CTX_C_GRX_P11 F29 VSS232
eDP_TX#[0] PEG_TX[13] PCIE_CTX_GRX_P12 PCIE_CTX_C_GRX_P12 VSS233
E16 E26 OPT@ C87 1 1
OPT@ C79 22 0.1U_0402_16V7K
0.1U_0402_16V7K
D16 eDP_TX#[1] PEG_TX[14] D25 PCIE_CTX_GRX_P13 PCIE_CTX_C_GRX_P13
F15 eDP_TX#[2] PEG_TX[15] PCIE_CTX_GRX_P14 2
PCIE_CTX_C_GRX_P14
OPT@ C111 1 0.1U_0402_16V7K
eDP_TX#[3] PCIE_CTX_GRX_P15 PCIE_CTX_C_GRX_P15
TYCO_2013620-2_IVY BRIDGE
CONN@
CONN@
A A
Security Classification Compal Secret Data

Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
5 4 3 2 1
5 4 3 2 1
<27> SYSTEM_PWROK
0.1U_0402_16V4Z
+3VALW
+3VALW +3VS
+1.5V_CPU_VDDQ
C85
1
R104 @ RC13
R289 10K_0402_5% R81
200_0402_1% 0_0402_5% 200_0402_1%
short@
2
U5
5
74AHC1G08DCKR_SC70-5
1
P
B 4
2 O VDDPWRGOOD
RC21 0_0402_5% A
G
D <27> PM_DRAM_PWRGD short@ D_PWG D
3
R110
39_0402_1%
@
RC17 1 @ 2
1
D @
<10,45> RUN_ON_CPU1.5VS3#
2 Q5
0_0402_5%
G 2N7002_SOT23-3
RC16 1 @ 2 S
3
<11,40,43,45> SUSP
0_0402_5%
+3VS +1.05VS_VCCP
0.1U_0402_16V4Z
1
R64
C84
75_0402_5%
2
5
U3
1 R72
P
C NC 4 C
2 Y BUFO_CPU_RST# BUF_CPU_RST#
43_0402_1%
A
G
<28,34,35,36,37,39,41,42,44> PLT_RST#
1
SN74LVC1G07DCKR_SC70-5 @
R73
3
0_0402_5%
2
JCPU1B
PROC_SELECT#:
Sandy Bridge---output high;
Ivy Bridge---output low.
A28 short@
Processor Pullups +1.05VS_VCCP C26 BCLK A27 R138 1 2 0_0402_5%
PROC_SELECT#
MISC
CLK_CPU_DMI_R
CLOCKS
BCLK# R139 1 2 0_0402_5% CLK_CPU_DMI <26>
<29> H_SNB_IVB# CLK_CPU_DMI#_R short@ CLK_CPU_DMI# <26>
1 2
R47 +1.05VS_VCCP
H_PROCHOT# 62_0402_5% AN34
SKTOCC#
PU/PD for JTAG signals
A16
DPLL_REF_CLK R126 1 2 1K_0402_5%
@ CC62 A15
DPLL_REF_CLK# CLK_CPU_DPLL_R R115 1 2 1K_0402_5% 51_0402_5% RC46
CLK_CPU_DPLL#_R +1.05VS_VCCP XDP_TMS_R 51_0402_5% RC47
220P_0402_25V8J
T0501 AL33
CATERR# XDP_TDI_R
H_CATERR# 51_0402_5% @ RC48
XDP_PREQ#_R
RC441 2 AN33
THERMAL R8
51_0402_5% RC49
PECI XDP_TDO_R
43_0402_1% H_PECI_R
SM_DRAMRST#
H_DRAMRST#
DDR3 Compensation
140_0402_1% 1
Signals
2 RC42
<29,41> H_PECI H_DRAMRST# <7>
SM_RCOMP0
DDR3
MISC
25.5_0402_1% 1 2 RC43 51_0402_5% RC57
R58 AL32 AK1
PROCHOT# SM_RCOMP[0] SM_RCOMP1 XDP_TCK_R
H_PROCHOT# 1 2 A5 51_0402_5% RC55
SM_RCOMP0 200_0402_1% 1 2 RC45
<41,47> H_PROCHOT# 56_0402_5% H_PROCHOT#_R SM_RCOMP[1] A4
SM_RCOMP[2] SM_RCOMP1 SM_RCOMP2 XDP_TRST#_R
B Place R58 close to CPU. AN32 SM_RCOMP2 B
1 2 THERMTRIP#
R14 H_THERMTRIP#_R
0_0402_5%
<29> H_THERMTRIP#
short@
AP29
PRDY# AP27
PREQ# XDP_PRDY#_R
XDP_PREQ#_R +5VS1A
R15
TCK
TMS
AR26
AR27
XDP_TCK_R
FAN Control Circuit
PWR MANAGEMENT
AM34 AP30
JTAG & BPM
1 2 PM_SYNC TRST# XDP_TMS_R

<27> H_PM_SYNC H_PM_SYNC_R
0_0402_5% short@ XDP_TRST#_R
AR28 2
TDI AP26 JFAN
R16 TDO XDP_TDI_R
AP33 C863 1
1 2 UNCOREPWRGOOD XDP_TDO_R
10U_0805_10V4Z +FAN1 2 1
<29> H_CPUPWRGD H_CPUPWRGD_R
0_0402_5% short@ 1 2
3
R79 AL35 2 3
V8 DBR# U58
1 2 XDP_DBRESET# @ C864 4
SM_DRAMPWROK 1 8 GND
VDDPWRGOOD 130_0402_1% VDDPWRGOOD_R EN GND 1000P_0402_50V7K 5
AT28 2 7 GND
BPM#[0] VIN GND 1
AR29 +FAN1 3 6
BPM#[1] VOUT GND ACES_85205-03001
AR30 4 5
BPM#[2] <41> EN_DFAN1 VSET GND CONN@
AR33 AT30 1
RESET# BPM#[3] AP32 G996P11U SOP 8P
BUF_CPU_RST# BPM#[4] 10mil C1
AR31
BPM#[5] AT31 10U_0805_10V4Z R3 10K_0402_5%
10K_0402_5% R50 BPM#[6] 2
AR32 2 1
H_CPUPWRGD_R BPM#[7] +3VS
@ C379 FAN_SPEED <41>

1
220P_0402_25V8J
A C865@ A
0.01U_0402_25V7K
CONN@ 2

Issued Date 2011/09/23 2012/12/31 Title
Compal Electronics, Inc.
Deciphered Date
5 4 3 2 1
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ JCPU1C
JCPU1D
AB6
SA_CLK[0] AA6
C5 SA_CLK#[0] V9
<11> DDR_A_D[0..63] D5 SA_DQ[0] SA_CKE[0] DDRA_CLK0 <11>
D3 SA_DQ[1] DDRA_CLK0# <11> AE2
SA_DQ[2] <12> DDR_B_D[0..63] SB_CLK[0] AD2 DDRB_CLK0 <12>
D2 DDRA_CKE0 <11>
SA_DQ[3] C9 SB_CLK#[0] R9 DDRB_CLK0# <12>
DDR_A_D0 D6 A7 SB_DQ[0] SB_CKE[0]
D SA_DQ[4] AA5 DDRB_CKE0 <12> D
DDR_A_D1 C6 SA_CLK[1] DDR_B_D0 D10 SB_DQ[1]
SA_DQ[5] AB5 DDR_B_D1
DDR_A_D2 C2 SA_CLK#[1] C8 SB_DQ[2]
SA_DQ[6] V10 DDRA_CLK1 <11>
DDR_A_D3 C3 SA_CKE[1] DDR_B_D2 A9 SB_DQ[3]
F10 SA_DQ[7] DDRA_CLK1# <11> SB_DQ[4] AE1
DDR_A_D4 SA_DQ[8] DDR_B_D3 A8 SB_CLK[1] DDRB_CLK1 <12>
F8 DDRA_CKE1 <11> SB_DQ[5] AD1
DDR_A_D5 SA_DQ[9] AB4 DDR_B_D4 D9 SB_CLK#[1] R10 DDRB_CLK1# <12>
DDR_A_D6 G10 RSVD_TP[1] DDR_B_D5 SB_DQ[6]
SA_DQ[10] AA4 D8 SB_CKE[1] DDRB_CKE1 <12>
DDR_A_D7 G9 RSVD_TP[2] DDR_B_D6 G4 SB_DQ[7]
SA_DQ[11] W9
DDR_A_D8 F9 RSVD_TP[3] DDR_B_D7 F4 SB_DQ[8]
DDR_A_D9 F7 SA_DQ[12] DDR_B_D8 SB_DQ[9] AB2
SA_DQ[13] F1 RSVD_TP[11]
DDR_A_D10 G8 DDR_B_D9 SB_DQ[10] AA2
SA_DQ[14] G1 RSVD_TP[12]
DDR_A_D11 G7 SB_DQ[11] T9
SA_DQ[15] AB3 DDR_B_D10 G5 RSVD_TP[13]
DDR_A_D12 K4 RSVD_TP[4] DDR_B_D11 SB_DQ[12]
SA_DQ[16] AA3 F5
DDR_A_D13 K5 RSVD_TP[5] DDR_B_D12 SB_DQ[13]
SA_DQ[17] W10 F2
DDR_A_D14 K1 RSVD_TP[6] DDR_B_D13 G2 SB_DQ[14]
DDR_A_D15 J1 SA_DQ[18] SB_DQ[15] AA1
SA_DQ[19] DDR_B_D14 J7 RSVD_TP[14]
DDR_A_D16 J5 DDR_B_D15 SB_DQ[16] AB1
SA_DQ[20] J8 RSVD_TP[15]
DDR_A_D17 J4 DDR_B_D16 SB_DQ[17] T10
DDR_A_D18 SA_DQ[21] K10 RSVD_TP[16]
J2 DDR_B_D17 K9 SB_DQ[18]
DDR_A_D19 SA_DQ[22] AK3 SB_DQ[19]
K2 SA_CS#[0] DDR_B_D18 J9
DDR_A_D20 SA_DQ[23] AL3
AG1 SB_DQ[20]
M8 SA_CS#[1]
RSVD_TP[7] DDR_B_D19 J10
DDR_A_D21 N10 SA_DQ[24] AH1 DDRA_SCS0# <11> DDR_B_D20 SB_DQ[21] AD3
DDR_A_D22 SA_DQ[25] RSVD_TP[8] K8 SB_CS#[0]
N8 DDRA_SCS1# <11> DDR_B_D21 K7 SB_DQ[22] AE3
DDR_A_D23 SA_DQ[26] SB_DQ[23] SB_CS#[1] AD6 DDRB_SCS0# <12>
N7 DDR_B_D22 M5
DDR_A_D24 SA_DQ[27] SB_DQ[24] RSVD_TP[17] AE6 DDRB_SCS1# <12>
M10 DDR_B_D23 N4 RSVD_TP[18]
DDR_A_D25 M9 SA_DQ[28] SB_DQ[25]
AH3 DDR_B_D24 N2
DDR_A_D26 N9 SA_DQ[29] DDR_B_D25 SB_DQ[26]
SA_ODT[0] AG3 N1
DDR_A_D27 M7 SA_DQ[30] AG2 SB_DQ[27]
SA_ODT[1]
RSVD_TP[9] DDR_B_D26 M4
DDR_A_D28 AG6 SA_DQ[31] AH2 DDRA_ODT0 <11> DDR_B_D27 SB_DQ[28]
N5
DDR SYSTEM MEMORY A
DDR_A_D29 SA_DQ[32] RSVD_TP[10] AE4
AG5 DDRA_ODT1 <11> DDR_B_D28 M2 SB_DQ[29]
DDR_A_D30 SA_DQ[33] SB_DQ[30] SB_ODT[0] AD4
AD5 DDRB_ODT0 <12>
AK6 DDR_B_D29 M1 SB_ODT[1]
RSVD_TP[19]
DDR_A_D31 SA_DQ[34] SB_DQ[31] AE5 DDRB_ODT1 <12>
DDR SYSTEM MEMORY B

AK5 DDR_B_D30 AM5 RSVD_TP[20]
DDR_A_D32 AH5 SA_DQ[35] DDR_B_D31 SB_DQ[32]
AM6
DDR_A_D33 AH6 SA_DQ[36] DDR_B_D32 SB_DQ[33]
AR3
DDR_A_D34 AJ5 SA_DQ[37] C4 SB_DQ[34]
SA_DQS#[0] G6 DDR_B_D33 AP3
C DDR_A_D35 AJ6 SA_DQ[38] DDR_A_DQS#[0..7] <11> SB_DQ[35] C
SA_DQS#[1] J3 DDR_B_D34 AN3
DDR_A_D36 AJ8 SA_DQ[39] DDR_B_D35 SB_DQ[36]
SA_DQS#[2] M6 DDR_A_DQS#0 AN2
DDR_A_D37 AK8 SA_DQ[40] DDR_B_D36 SB_DQ[37] D7 DDR_B_DQS#[0..7] <12>
SA_DQS#[3] AL6 DDR_A_DQS#1 AN1 SB_DQS#[0]
DDR_A_D38 AJ9 SA_DQ[41] DDR_B_D37 SB_DQ[38] F3 DDR_B_DQS#0
SA_DQS#[4] AM8 DDR_A_DQS#2 AP2 SB_DQS#[1]
DDR_A_D39 AK9 SA_DQ[42] DDR_B_D38 SB_DQ[39] K6 DDR_B_DQS#1
SA_DQS#[5] AR12 DDR_A_DQS#3 AP5 SB_DQS#[2]
DDR_A_D40 AH8 SA_DQ[43] DDR_B_D39 SB_DQ[40] N3 DDR_B_DQS#2
SA_DQS#[6] AM15 DDR_A_DQS#4 AN9 SB_DQS#[3]
DDR_A_D41 AH9 SA_DQ[44] DDR_B_D40 SB_DQ[41] AN5 DDR_B_DQS#3
SA_DQS#[7] DDR_A_DQS#5 AT5 SB_DQS#[4]
DDR_A_D42 AL9 SA_DQ[45] DDR_B_D41 SB_DQ[42] AP9 DDR_B_DQS#4
DDR_A_DQS#6 AT6 SB_DQS#[5]
DDR_A_D43 AL8 SA_DQ[46] SB_DQ[43] AK12 DDR_B_DQS#5
DDR_A_DQS#7 DDR_B_D42 AP6 SB_DQS#[6]
DDR_A_D44 AP11 SA_DQ[47] SB_DQ[44] AP15 DDR_B_DQS#6
DDR_B_D43 AN8 SB_DQS#[7]
DDR_A_D45 AN11 SA_DQ[48] DDR_B_D44 SB_DQ[45] DDR_B_DQS#7
AR6
DDR_A_D46 AL12 SA_DQ[49] D4 DDR_B_D45 AR5 SB_DQ[46]
SA_DQ[50] SA_DQS[0] F6 DDR_A_DQS[0..7] <11> SB_DQ[47]
DDR_A_D47 AM12 DDR_B_D46 AR9
DDR_A_D48 SA_DQ[51] SA_DQS[1] K3 SB_DQ[48]
AM11 SA_DQS[2] DDR_B_D47 AJ11
DDR_A_D49 SA_DQ[52] N6 DDR_A_DQS0 SB_DQ[49] C7 DDR_B_DQS[0..7] <12>
AL11 SA_DQS[3] DDR_B_D48 AT8 SB_DQS[0]
DDR_A_D50 SA_DQ[53] AL5 DDR_A_DQS1 SB_DQ[50] G3 DDR_B_DQS0
AP12 SA_DQS[4] DDR_B_D49 AT9 SB_DQS[1]
DDR_A_D51 SA_DQ[54] AM9 DDR_A_DQS2 SB_DQ[51] J6 DDR_B_DQS1
AN12 DDR_B_D50 AH11
DDR_A_D52 SA_DQ[55] SA_DQS[5] AR11 DDR_A_DQS3 SB_DQ[52] SB_DQS[2] M3 DDR_B_DQS2
AJ14 DDR_B_D51 AR8
DDR_A_D53 SA_DQ[56] SA_DQS[6] AM14 DDR_A_DQS4 SB_DQS[3] DDR_B_DQS3
AH14 DDR_B_D52 AJ12 SB_DQ[53] AN6
DDR_A_D54 SA_DQ[57] SA_DQS[7] DDR_A_DQS5 SB_DQ[54] SB_DQS[4] DDR_B_DQS4
AL15 DDR_B_D53 AH12 AP8
DDR_A_D55 SA_DQ[58] DDR_A_DQS6 DDR_B_D54 SB_DQ[55] SB_DQS[5] AK11 DDR_B_DQS5
AK15 DDR_A_DQS7 AT11 SB_DQS[6] DDR_B_DQS6
DDR_A_D56 AL14 SA_DQ[59] DDR_B_D55 AN14 SB_DQ[56] AP14
DDR_A_D57 SA_DQ[60] DDR_B_D56 SB_DQ[57] SB_DQS[7] DDR_B_DQS7
AK14 AR14
DDR_A_D58 AJ15 SA_DQ[61] AD10 DDR_B_D57 AT14 SB_DQ[58]
SA_DQ[62] SA_MA[0] W1 DDR_A_MA[0..15] <11> DDR_B_D58 SB_DQ[59]
DDR_A_D59 AH15 AT12
DDR_A_D60 SA_DQ[63] SA_MA[1] W2 SB_DQ[60]
SA_MA[2] DDR_A_MA0 DDR_B_D59 AN15
DDR_A_D61 W7 DDR_B_D60 SB_DQ[61] AA8 DDR_B_MA[0..15] <12>
SA_MA[3] DDR_A_MA1 AR15 SB_MA[0] DDR_B_MA0
DDR_A_D62 V3 DDR_B_D61 AT15 SB_DQ[62] T7
SA_MA[4] DDR_A_MA2 SB_MA[1] DDR_B_MA1
DDR_A_D63 V2 DDR_B_D62 SB_DQ[63] R7
W3 DDR_B_D63 T6
AE10 W6 T2
SA_BS[0] SA_MA[7] DDR_A_MA5 SB_MA[4] DDR_B_MA4
AF10 V1 T4
<11> DDR_A_BS0 V6 SA_BS[1] W5 T3
<11> DDR_A_BS1 SA_BS[2] AD8 AA9 R2
SA_MA[10] DDR_A_MA8 SB_BS[0] SB_MA[7] DDR_B_MA7
B <11> DDR_A_BS2 V4 <12> DDR_B_BS0 AA7 T5 B
W4 <12> DDR_B_BS1 R6 R3
AE8 AF8 <12> DDR_B_BS2 AB7
AD9 SA_CAS# V5 R1
<11> DDR_A_CAS# AF9 SA_RAS# V7 T1
<11> DDR_A_RAS# SA_WE# AA10 AB10
DDR_A_MA14 SB_CAS# SB_MA[13] DDR_B_MA13
<11> DDR_A_WE# <12> DDR_B_CAS# AB8 R5
DDR_A_MA15 <12> DDR_B_RAS# SB_RAS# SB_MA[14] R4 DDR_B_MA14
AB9 SB_MA[15]
<12> DDR_B_WE# SB_WE# DDR_B_MA15
CONN@ TYCO_2013620-2_IVY BRIDGE
CONN@
+1.5V
@
R124 0_0402_5%
R123
QC3 1K_0402_5%
BSS138_SOT23
3
S
1
<6> H_DRAMRST# H_DRAMRST# DDR3_DRAMRST#_R SM_DRAMRST# <11,12>
R129 1K_0402_5%
A A
G
2
R119
4.99K_0402_1% DRAMRST_CNTRL short@
R118 0_0402_5% DRAMRST_CNTRL_PCH <10,26>

C86 Security Classification Compal Secret Data
0.047U_0402_16V4Z
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor
D D
CFG2
RC51
JCPU1E 1K_0402_1%
CFG[1:0]: reserved configuration lane. AH27

T266 PAD VCC_DIE_SENSE AH26
CFG0 AK28 VSS_DIE_SENSE
T251 AK29 CFG[0]
T252 PAD
PAD CFG1 CFG[1]
T253 PAD CFG2 AL26
CFG[3]: reserved AL27 CFG[2]
T254 PAD CFG3 CFG[3] L7
T255 PAD CFG4 AK26 RSVD28 AG7
AL29 CFG[4] RSVD29
CFG[17:7]: reserved configuration lanes. T256 PAD CFG5 CFG[5] AE7 PEG Static Lane Reversal - CFG2 is for the 16x
T257 PAD CFG6 AL30 RSVD30 AK2
AM31 CFG[6] RSVD31
T258 PAD CFG7 CFG[7]
T259 PAD CFG8 AM32
AM30 CFG[8] W8 1:(Default) Normal Operation; Lane #
T260 PAD CFG9 RSVD32
CFG
T261 PAD AM28 CFG[9] CFG2 definition matches socket pin map definition
CFG10 CFG[10]
T267 PAD AM26
CFG11 CFG[11] AT26 0:Lane Reversed
T268 PAD CFG12 AN28 RSVD33
CFG[17:0]: T269 PAD AN31 CFG[12] AM33
Processor internal pull up 5~15Kohm to VCCIO CFG13 CFG[13] RSVD34
T270 PAD AN26 AJ27
CFG14 CFG[14] RSVD35
T262 PAD AM27
CFG15 CFG[15] CFG4
T263 PAD AK31
CFG16 CFG[16]
AN29
CFG17 CFG[17]
@ RC52
1K_0402_1%
T8
RSVD37
T245 PAD J16
AJ31 RSVD38 H16
T246 PAD AH31 VAXG_VAL_SENSE RSVD39
VSSAXG_VAL_SENSE G16
T247 PAD AJ33 RSVD40
T248 PAD AH33 VCC_VAL_SENSE
VSS_VAL_SENSE
C C
AJ26 AR35
RSVD5 RSVD_NCTF1 Display Port Presence Strap
AT34
RSVD_NCTF2 AT33
RESERVED
RSVD_NCTF3 AP35
RSVD_NCTF4
AR34 1 : Disabled; No Physical Display Port
RSVD_NCTF5 CFG4 attached to Embedded Display Port
F25
F24 RSVD8 0 : Enabled; An external Display Port device is
F23 RSVD9
D24 RSVD10 connected to the Embedded Display Port
B34
G25 RSVD11 RSVD_NCTF6 A33
G24 RSVD12 RSVD_NCTF7 A34
E23 RSVD13 RSVD_NCTF8 B35
RSVD14 RSVD_NCTF9 CFG6
D23 C35
C30 RSVD15 RSVD_NCTF10
A31 RSVD16 CFG5
B30 RSVD17
B29 RSVD18 @ RC54 @ RC53
D30 RSVD19 1K_0402_1% 1K_0402_1%
AJ32
B31 RSVD20 RSVD51 AK32
A30 RSVD21 RSVD52
C29 RSVD22
RSVD23
AN35
J20 BCLK_ITP AM35 CLK_RES_ITP <26>
B18 RSVD24 BCLK_ITP# CLK_RES_ITP# <26>
RSVD25
J15 AT2
RSVD27 RSVD_NCTF11 AT1 PCIE Port Bifurcation Straps
RSVD_NCTF12 AR1
B RSVD_NCTF13 B
11: (Default) x16 - Device 1 functions 1 and 2 disabled
KEY
B1 CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
TYCO_2013620-2_IVY BRIDGE 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CONN@
CFG7
@ RC56
1K_0402_1%
PEG DEFER TRAINING
1: (Default) PEG Train immediately

CFG7 following RESETB de assertion
0: PEG Wait for BIOS for training
A A

5 4 3 2 1
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ JCPU1F POWER

JCPU1H
AJ22
AT35 VSS81 AJ19
AT32 VSS1 VSS82 AJ16
AT29 VSS2 VSS83 AJ13
AT27 VSS3 VSS84 AJ10 +1.05VS_VCCP
AT25 VSS4 VSS85
VSS5 AJ7 +VCC_CORE
AT22 VSS86 AJ4 AG35 AH13
VSS6
D AT19
VSS7
VSS87 AJ3 AG34 VCC1 VCCIO1 8.5A
AH10 D
AT16
VSS8
VSS88
VSS89
AJ2 97A AG33 VCC2 VCCIO2
VCCIO3
AG10
AT13
VSS9 AJ1 AG32 VCC3 AC10
AT10 VSS90 AH35 AG31 VCC4 VCCIO4 Y10
VSS10 VSS91 VCCIO5
AT7
VSS11 AH34 AG30 VCC5 U10
VSS92 VCCIO6
AT4
VSS12 AH32 AG29 VCC6 P10
VSS93 VCCIO7
AT3
VSS13 AH30 AG28 VCC7 L10
VSS94 VCCIO8
AR25
VSS14 AH29 AG27 VCC8 J14
VSS95 VCCIO9
AR22
VSS15 AH28 AG26 VCC9 J13
VSS96 VCCIO10
AR19
VSS16 AH25 AF35 VCC10 J12
VSS98 VCCIO11
AR16
VSS17 AH22 AF34 VCC11 J11
VSS99
AR13
VSS18 AH19 AF33 VCC12 VCCIO12 H14
VSS100 VCCIO13
AR10
VSS19 AH16 AF32 VCC13 H12
VSS101 VCCIO14
AR7
VSS20 AH7 AF31 VCC14 H11
VSS102
AR4
VSS21 AH4 AF30 VCC15 VCCIO15 G14
AR2 VSS103
VSS22 AG9 AF29 VCC16 VCCIO16 G13
AP34 VSS104
VSS23 AG8 AF28 VCC17 VCCIO17
G12
AP31 VSS105
VSS24 AG4 AF27 VCC18 VCCIO18 F14
AP28 VSS106
AF26 VCC19 VCCIO19
PEG AND DDR

VSS25 AF6 F13
AP25 VSS107
VSS26 AF5 AD35 VCC20 VCCIO20 F12
AP22 VSS108
VSS27 AF3 AD34 VCC21 VCCIO21 F11
AP19 VSS109
VSS28 AF2 AD33 VCC22 VCCIO22 E14
AP16 VSS110
VSS29 AE35 AD32 VCC23 VCCIO23 E12
AP13 VSS111
VSS30 AE34 AD31 VCC24 VCCIO24
Package Sensing Recommendations--PDDG P30
AP10 VSS112
VSS31 AE33 AD30 VCC25 E11
AP7 VSS113
VSS32 AE32 AD29 VCC26 VCCIO25 D14 Sense Trace Impedance Trace Length Match
AP4 VSS114
VSS33 AE31 AD28 VCC27 VCCIO26 D13
AP1 VSS115
VSS34 AE30 AD27 VCC28 VCCIO27 D12 VCC_SENSE / 25.5-34.5ohm
AN30 VSS116
VSS35 AE29 AD26 VCC29 VCCIO28 D11
AN27 VSS117 VSS_SENSE
VSS36 AE28 AC35 VCC30 VCCIO29 C14
AN25 VSS118 AE27 AC34 VCC31 VCCIO30 C13
AN22
AN19
AN16
VSS37
VSS38
VSS39
VSS VSS119
VSS120
VSS121
AE26
AE9
AC33 VCC32
AC32 VCC33
VCCIO31
VCCIO32
C12
C11
VCCAXG_SENSE /
VSSAXG_SENSE <25 mils
VSS40 VSS122
AD7 AC31 VCC34 VCCIO33 B14 VCCIO_SENSE / 55ohm
AN13
VSS41 VSS123
AC9 AC30 VCC35 VCCIO34 B12
AN10
VSS42 AC8 AC29 VCC36 VCCIO35 VSS_SENSE_VCCIO
AN7 VSS124 A14
C
VSS43 VSS125
AC6 AC28 VCC37 VCCIO36 A13 VCCSA
C
AN4
VSS44 VSS126
AC5 AC27 VCC38 VCCIO37 A12
AM29
VSS45 VSS127
AC3 AC26 VCC39 VCCIO38 A11
AM25
VSS46 VSS128
AC2 AA35 VCC40 VCCIO39
AM22
AM19 VSS47 VSS129
AB35 AA34 VCC41 J23
AM16 VSS48 VSS130
AB34 AA33 VCC42 VCCIO40
AM13 VSS49 VSS131
AB33 AA32 VCC43
AM10 VSS50 VSS132
AB32 AA31 VCC44
AM7 VSS51 VSS133
AB31 AA30 VCC45
AM4 VSS52 VSS134
AB30 AA29 VCC46
AM3 VSS53 VSS135
AB29 AA28 VCC47
AM2 VSS54 VSS136
AB28 AA27 VCC48 +1.05VS_VCCP
AM1 VSS55 VSS137
AB27 AA26 VCC49
short@
VSS56 AB26 Y35 VCC50
0.1U_0402_16V4Z
AL34 VSS138
VSS57 Y9 Y34 VCC51
CORE SUPPLY
AL31 VSS139 RC59 0_0402_5%
AL28 VSS58 VSS140
Y8 Y33 VCC52 H_CPU_SVIDCLK VR_SVID_CLK <54>
AL25 VSS59 VSS141
Y6 Y32 VCC53
CC49
AL22 VSS60 VSS142
Y5 Y31 VCC54
VSS61 Y3 Y30 VCC55
1
AL19 VSS143
AL16 VSS62 VSS144
Y2 Y29 VCC56
RC60
AL13 VSS63 VSS145
W35 Y28 VCC57 Place the PU resistors
AL10 VSS64 VSS146
W34 Y27 VCC58 75_0402_5%
AL7 VSS65 VSS147
W33 Y26 VCC59 RC60, RC137 close to CPU.
VSS66 W32 V35 VCC60
2
AL4 VSS148
AL2 VSS67 VSS149
W31 V34 VCC61
AJ29
W30 V33 VCC62
SVID
AK33 VSS68 VSS150 VIDALERT# AJ30
VSS69 W29 V32 VCC63 RC61
AK30 VSS151 VIDSCLK AJ28 H_CPU_SVIDALRT# VR_SVID_ALRT# <54>
AK27 VSS70 VSS152
W28 V31 VCC64 VIDSOUT H_CPU_SVIDCLK 43_0402_1%
AK25 VSS71 VSS153
W27 V30 VCC65 H_CPU_SVIDDAT
AK22 VSS72 VSS154
W26 V29 VCC66 +1.05VS_VCCP
AK19 VSS73 VSS155
U9 V28 VCC67
U8 V27 VCC68
0.1U_0402_16V4Z
AK16 VSS74 VSS156
AK13 VSS75 VSS157
U6 V26 VCC69
RC137
AK10 VSS76 VSS158
U5 U35 VCC70
U3 U34 VCC71 130_0402_1%
CC50
AK7 VSS77 VSS159
B AK4 VSS78 VSS160
U2 U33 VCC72 B
AJ25 VSS79 U32 VCC73
VSS80 U31 VCC74
U30 VCC75
U29 VCC76 H_CPU_SVIDDAT RC65 0_0402_5%
VR_SVID_DAT <54>
U28 VCC77 short@
U27 VCC78
TYCO_2013620-2_IVY BRIDGE U26 VCC79
R35 VCC80
CONN@ R34 VCC81
R33 VCC82 +VCC_CORE
1
R32 VCC83
R31 VCC84 R53
R30 VCC85 Place the PU resistors 100_0402_1%
R29 VCC86
R28 VCC87 R53, R54 close to CPU
2
R27 VCC88
SENSE LINES
R26 VCC89 AJ35 short@

VCC_SENSE AJ34VCCSENSE_R
P35 VCC90 VSS_SENSE VCCSENSE <54>
P34 VCC91 VSSSENSE_R R52
R51 short@ 0_0402_5%
0_0402_5%
VSSSENSE <54>
P33 VCC92
P32 VCC93 VCCIO_SENSE
B10
R168
P31 VCC94
1
P30 VCC95 A10 1 2 R54
VSS_SENSE_VCCIO
P29 VCC96 +1.05VS_VCCP 100_0402_1%
P28 VCC97 10_0402_1%
P27 VCC98
2
P26 VCC99
VCC100
VCCIO_SENSE <51>
1
R158
10_0402_1%
A A
2
CONN@

5 4 3 2 1
5 4 3 2 1
+1.5V_CPU_VDDQ
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ +1.5V +1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ
Q7
AO4728L_SO8 R131
1 220_0402_5%
8
1
+3VALW +VSB 7 2
0.1U_0402_10V6K
6 3
5
1
1
R135 @ D
10U_0805_10V4Z
100K_0402_5% @ 2
C107
G
4
2
2
R134 S Q8 RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3# <6,45>
CC38
3
100K_0402_5% 2N7002E-T1-GE3_SOT23-3
D D
3
RUN_ON_CPU1.5VS3
C196
330K_0402_1%
R1361
Q208B
5 2N7002DW-T/R7_SOT363-6 0.1U_0603_50V7K
RUN_ON_CPU1.5VS3#
4
6
2
@ R132
+1.5V_CPU_VDDQ +1.5V +1.5V_CPU_VDDQ
0_0402_5% Q208A
C199 0.1U_0402_10V7K
2 2N7002DW-T/R7_SOT363-6
<39,41,45,50,51,52,57> SUSP#
R133 J3
C201 0.1U_0402_10V7K
1
0_0402_5% 2 1
<41> CPU1.5V_S3_GATE 2 1 +1.5VS
J2
@ JUMP_43X118
2 1
2 1
CC47 0.1U_0402_10V7K
@ JUMP_43X118 +1.5V
CC48 0.1U_0402_10V7K
R89 CPU
Close to +GFX_CORE
100_0402_1%
1 2
JCPU1G
POWER VCC_AXG_SENSE
VSS_AXG_SENSE 1
R86
2
100_0402_1%
Intel future processor compatibility design. --DG1.5 P113
+V_SM_VREF should
have 20 mil trace width
AT24 AK35
33A RC77 0_0402_5%
SENSE
LINES
AT23 VAXG1 VAXG_SENSE AK34 VCC_AXG_SENSE
+GFX_CORE VCC_AXG_SENSE <54> +1.5V_CPU_VDDQ @
AT21 VAXG2 VSSAXG_SENSE VSS_AXG_SENSE
VAXG3 VSS_AXG_SENSE <54> +V_DDR_REFA +VREF_CA
AT20
AT18 VAXG4 @ RC83 C
C
AT17 VAXG5 RC118
VAXG6 RC76 0_0402_5% 2 3 RC79
AR24 1K_0402_1%
AR23 VAXG7 VREFDQ_DIMMA_CPU 0_0402_5%
VAXG8 0_0402_5% short@
AR21
AR20 VAXG9
VAXG10 QC6
AR18 AL1 2 3 1 AP2302GN-HF_SOT23-3
AR17 VAXG11 SM_VREF @ RC121
+V_SM_VREF_CNT +V_SM_VREF
AP24 VAXG12 RC119 1K_0402_1%
R120
VREF
0.1U_0402_16V4Z
AP23 VAXG13 1K_0402_1%
VAXG14 1 @
AP21 CC178 QC5 0_0402_5%
VAXG15 B4
AP20 SA_DIMM_VREFDQ 1 AP2302GN-HF_SOT23-3 DRAMRST_CNT short@ DRAMRST_CNTRL_PCH <7,26>
VAXG16 D1
AP18 SB_DIMM_VREFDQ VREFDQ_DIMMA_CPU
AP17 VAXG17 VREFDQ_DIMMB_CPU 2
AN24 VAXG18
AN23 VAXG19 RUN_ON_CPU1.5VS3
AN21 VAXG20
AN20 VAXG21
VAXG22 +1.5V_CPU_VDDQ RC78 0_0402_5%
AN18 @
VAXG23 +V_DDR_REFB +VREF_CB
DDR3 -1.5V RAILS
AN17
AM24 VAXG24 AF7 RC80
VAXG25 VDDQ1 10A @ RC84
GRAPHICS
AM23 AF4
VAXG26 VDDQ2 AF1
AM21 0_0402_5% short@
10U_0805_6.3V6M
10U_0805_6.3V6M
VAXG27 VDDQ3 AC7 1 2 3
AM20 VREFDQ_DIMMB_CPU
10U_0805_6.3V6M
10U_0805_6.3V6M
VDDQ4 0_0402_5%
10U_0805_6.3V6M
10U_0805_6.3V6M
AM18 VAXG28 AC4
VAXG29 VDDQ5 AC1 + RC122
AM17
CC56
CC55
CC54
VAXG30 VDDQ6 Y7 CC57 @ 1K_0402_1%
AL24
CC51
VDDQ7 330U_X_2VM_R6M QC7
CC52
CC53
AL23 VAXG31 Y4
VDDQ8 2 1 AP2302GN-HF_SOT23-3
AL21 VAXG32 Y1
VAXG33 VDDQ9 U7
AL20 VDDQ10
AL18 VAXG34 U4
VAXG35 VDDQ11 U1
AL17 DRAMRST_CNT
VAXG36 VDDQ12 P7
AK24
VAXG37 VDDQ13 P4
AK23
VAXG38 VDDQ14 P1
AK21
VAXG39 VDDQ15
AK20 check Confirm QC6, QC7 is low Rdson or not--Joyce 0929
AK18 VAXG40
AK17 VAXG41
AJ24 VAXG42
AJ23 VAXG43
AJ21 VAXG44
B AJ20 VAXG45 B
AJ18 VAXG46
AJ17 VAXG47 M27
AH24 VAXG48 VCCSA1 M26 6A +VCCSA
10U_0805_6.3V6M
VCCSA2
SA RAIL
AH23 VAXG49 L26

VCCSA: 0.675V (Min) ~ 0.9V (Max)
10U_0805_6.3V6M
VCCSA3
10U_0805_6.3V6M
10U_0603_6.3V6M
AH21 VAXG50 J26 @ 1

VAXG51 VCCSA4 J25
AH20 + CC44
VCCSA5
CC40
CC43
AH18 VAXG52 J24 330U_X_2VM_R6M SA: System Agent

CC42
VCCSA6
CC41
AH17 VAXG53 H26

VAXG54 VCCSA7 H25 (Memory controller, DMI, PCIE controllers, and display engine)
VCCSA8 2
+1.8VS +1.8VS_VCCPLL @ R92

H23
1.8V RAIL
RC120 VCCSA_SENSE 1 2
+VCCSA_SENSE +VCCSA
0_0805_5% +VCCSA_SENSE <53>
1.5A B6
100_0402_1%
A6 VCCPLL1 C22
1U_0402_6.3V6K
VCCPLL2 VCCSA_VID[0]
1U_0402_6.3V6K
@ RC111
MISC
1 1 A2 C24
330U_X_2VM_R6M
H_VCCSA_VID0 <53>
10U_0805_6.3V6M
1 VCCPLL3 VCCSA_VID[1] 0_0402_5%

H_VCCSA_VID1 <53>
CC60
CC59
VCCSA_VID Configuration --CPU EDS Page99.

CC61
+
CC58
2 2
A19
VCCIO_SEL
2 VCCSA_VID[0] output default logic state is low for Sandy Bridge processors
TYCO_2013620-2_IVY BRIDGE +3VS
2
CONN@
RC112 @
10K_0402_5%
RC113
1
@ 0_0402_5%
A A

5 4 3 2 1
5 4 3 2 1
1K_0402_1%
+1.5V
R55 +1.5V +1.5V <7> DDR_A_D[0..63]
3A@1.5V <7> DDR_A_DQS[0..7]
2
DDR3 SO-DIMM A JDDRL
<7> DDR_A_DQS#[0..7]
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
1 2
0.1U_0402_10V6K
1
<7> DDR_A_MA[0..15]
1K_0402_1%
+V_DDR_REFA 1 1 3 VREF_DQ VSS1 4
1 VSS2 DQ4
5 6
DQ0 DQ5
R57
7 8 DDR_A_D4
DDR_A_D5
C133
VSS3
C134
DDR_A_D0 9 DQ1 10
CD1
2 2 VSS4 DQS#0
2 DDR_A_D1 11 12 DDR_A_DQS#0
2
13 DM0 DQS0 14
15 VSS5 VSS6 16 DDR_A_DQS0
DDR_A_DM0
17 DQ2 DQ6 18
D DDR_A_D2 D
19 DQ3 DQ7 20 DDR_A_D6 Layout Note:
DDR_A_D3 21 VSS7 VSS8 22 DDR_A_D7
DQ8 DQ12 Place near JDDRL
10U_0603_6.3V6M
10U_0603_6.3V6M
23 24
10U_0603_6.3V6M
10U_0603_6.3V6M
DDR_A_D8 DQ9 DQ13
25 26 DDR_A_D12
DDR_A_D9 VSS9 VSS10 DDR_A_D13
C147
27 28
C148
C146
C143
10U_0603_6.3V6M
+1.5V 1
10U_0603_6.3V6M
10U_0603_6.3V6M
DQS#1 DM1 1 1 1
330U 2V Y D2 LESR9M
29 30
C153
47P_0402_50V8J
CD15
DDR_A_DQS#1 31 DQS1 RESET# 32 1
DDR_A_DM1
C144
C145
DDR_A_DQS1 VSS11 VSS12 SM_DRAMRST# <7,12> 1 1
33 34 1
1
DQ10 DQ14 SM_DRAMRST# +
35 36 2 2 2 2
DDR_A_D14
DDR_A_D10 37 DQ11 DQ15 38
DDR_A_D11
C140
39 VSS13 VSS14 40 DDR_A_D15 +V_DDR_REFA +V_DDR_REFB @
2
2 2 2 2
41 DQ16 DQ20 42
DDR_A_D16 43 DQ17 DQ21 44 DDR_A_D20 RC81 0_0402_5%
DDR_A_D17 VSS15 VSS16 DDR_A_D21 @
45 46
47 DQS#2 DM2 48
DDR_A_DQS#2 49 DQS2 VSS17 50
VSS18 DQ22 DDR_A_DM2
DDR_A_DQS2 51 52 DDR_A_D22
53 DQ18 DQ23 54
DDR_A_D18 55 DQ19 VSS19 56 DDR_A_D23
57 VSS20 DQ28 58
DDR_A_D19
59 DQ24 DQ29 60
DQ25 VSS21 DDR_A_D28
DDR_A_D24 61 62 DDR_A_D29 +VREF_CA +VREF_CB
DDR_A_D25 VSS22 DQS#3
63 64
65 DM3 DQS3 66 DDR_A_DQS#3 RC82 0_0402_5%
DDR_A_DM3 67 VSS23 VSS24 68 DDR_A_DQS3 @
69 DQ26 DQ30 70 Layout Note: Place these 4 Caps near
DDR_A_D26 DQ27 DQ31 Command and Control signals of JDDRL
71 72 DDR_A_D30
VSS25 VSS26 +1.5V
DDR_A_D27 DDR_A_D31
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
C152
C149
C150
73 74 1 1 1
0.1U_0402_10V6K
75 CKE0 CKE1 76
C VDD2 DDRA_CKE1 C
C151
<7> DDRA_CKE0 77 VDD1 78 DDRA_CKE1 <7> 1
DDRA_CKE0 NC1 A15
79 80
BA2 A14 2 2 2
81 82
<7> DDR_A_BS2 VDD3 VDD4 DDR_A_MA15
DDR_A_BS2 83 84 DDR_A_MA14
A12/BC# A11 2
DDR_A_MA12 85 86
87 A9 A7 88 DDR_A_MA11
DDR_A_MA9 89 VDD5 VDD6 90 DDR_A_MA7
91 A8 A6 92
93 A5 A4 94
DDR_A_MA8 DDR_A_MA6
DDR_A_MA5 95 VDD7 VDD8 96 DDR_A_MA4
97 A3 A2 98
99 A1 A0 100 DDR_A_MA2
DDR_A_MA3 VDD9 VDD10
DDR_A_MA1 101 102 DDR_A_MA0
103 CK0 CK1 104
<7> DDRA_CLK0 DDRA_CLK0 105 CK0# CK1# 106 DDRA_CLK1 DDRA_CLK1 <7>
<7> DDRA_CLK0# DDRA_CLK0# 107 VDD11 VDD12 108 DDRA_CLK1# DDRA_CLK1# <7> +1.5V
1
109 A10/AP BA1 110
DDR_A_MA10 111 BA0 RAS# 112 DDR_A_BS1 DDR_A_BS1 <7> R56 Layout Note:
<7> DDR_A_BS0 DDR_A_BS0 113 VDD13 VDD14 114 DDR_A_RAS# <7> 1K_0402_1% Place near JDDRL.203,204
WE# S0# DDR_A_RAS#
115 116
<7> DDR_A_WE# 117 CAS# ODT0 118 DDRA_SCS0# <7>
DDR_A_WE# DDRA_SCS0#
2
<7> DDR_A_CAS# DDR_A_CAS# 119 VDD15 VDD16 120 DDRA_ODT0 DDRA_ODT0 <7>
A13 ODT1 +0.75VS
121 122
DDR_A_MA13 123 S1# NC2 124 DDRA_ODT1 DDRA_ODT1 <7>
<7> DDRA_SCS1# VDD17 VDD18
1U_0402_6.3V6K
C362
125 126
1U_0402_6.3V6K
C361
1U_0402_6.3V6K
C360
1U_0402_6.3V6K
C359
DDRA_SCS1# NCTEST VREF_CA
127 128
0.1U_0402_10V6K
VSS27 VSS28 +VREF_CA 1 1 1 1
129 130
22U_0805_6.3V6M
C369
2.2U_0603_6.3V4Z
DQ32 DQ36 1
131 132
DQ37 1
1
DDR_A_D32 133 DQ33 134 DDR_A_D36
VSS29 VSS30 1 2
135 136 DDR_A_D37 2 2
C138
DDR_A_D33 2
137 DQS#4 DM4 138 2 R60
DDR_A_DQS#4 139 DQS4 VSS31 140 1K_0402_1% 2
C139
B DDR_A_DQS4 VSS32 DQ38 DDR_A_DM4 B
141 142 2
2
143 DQ34 DQ39 144 DDR_A_D38
DDR_A_D34 145 DQ35 VSS33 146 DDR_A_D39 +3VALW
DDR_A_D35 147 VSS34 DQ44 148
149 DQ40 DQ45 150
DQ41 VSS35 DDR_A_D44
DDR_A_D40 151 152 DDR_A_D45 R5536
DDR_A_D41 153 VSS36 DQS#5 154
DM5 DQS5 100K_0402_5%
155 156 DDR_A_DQS#5
157 VSS37 VSS38 158 DDR_A_DQS5
DDR_A_DM5 DQ42 DQ46
159 160
DDR_A_D42 161 DQ43 DQ47 162
VSS39 VSS40 DDR_A_D46
DDR_A_D43 163 164 DDR_A_D47
165 DQ48 DQ52 166 0.75VR_EN#
DDR_A_D48 167 DQ49 DQ53 168 DDR_A_D52
3
DDR_A_D49 169 VSS41 VSS42 170 DDR_A_D53
171 DQS#6 DM6 172 <52> 0.75VR_EN Q5520B
173 DQS6 VSS43 174 DDR_A_DM6
DDR_A_DQS#6 5
DDR_A_DQS6 175 VSS44 DQ54 176 2N7002DW-T/R7_SOT363-6
177 DQ50 DQ55 178 DDR_A_D54
DDR_A_D50 179 DQ51 VSS45 180 DDR_A_D55 <51,53> +1.05VSP_PWRGOOD R5535 0.75VR_EN
4
181 VSS46 DQ60 182 100K_0402_5%
DDR_A_D51 DQ61
183 DQ56 184 DDR_A_D60
6
DDR_A_D56 185 DQ57 VSS47 186 DDR_A_D61 Q5520A
187 VSS48 DQS#7 188 2N7002DW-T/R7_SOT363-6
DDR_A_D57 DM7 DQS7
189 190 DDR_A_DQS#7
DDR_A_DM7 191 VSS49 VSS50 192 2 refer to QAL51, need confirm. --Joyce 0929/2011
DQ58 DQ62 DDR_A_DQS7
193 194
195 DQ59 DQ63 196 DDR_A_D62 <6,40,43,45> SUSP SUSP
DDR_A_D58
1
197 VSS51 VSS52 198 DDR_A_D63
DDR_A_D59 SA0 EVENT#
199 200
VDDSPD SDA
2.2U_0603_6.3V4Z
201 202
+3VS 1 203 SA1 SCL 204 PM_SMBDATA PM_SMBDATA <12,26,36,39>
0.1U_0402_10V6K
A A
1
VTT2
10K_0402_5%
VTT1 PM_SMBCLK <12,26,36,39>

1 PM_SMBCLK
R67
205 206 +0.75VS

10K_0402_5%
C160
G1 G2
R68
2
0.65A@0.75V
C161
2 LCN_DAN06-K4526-0101
2
Compal Secret Data Compal Electronics, Inc.

2
Security Classification
CONN@
Custom B
5 4 3 2 1
5 4 3 2 1
1K_0402_1%
+1.5V
RD10 +1.5V +1.5V +1.5V Layout Note:
10U_0603_6.3V6M
Place near JDDRH
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
<7> DDR_B_D[0..63]
2
C176
330U 2V Y D2 LESR9M
C174
CD49
C175
CD48
3A@1.5V 1 1 1 1 1
C173
10U_0603_6.3V6M
10U_0603_6.3V6M
+V_DDR_REFB <7> DDR_B_DQS[0..7] 1 1
JDDRH
2.2U_0603_6.3V4Z
0.1U_0402_10V6K
+
0.1U_0402_10V6K
C171
1 2
C172
<7> DDR_B_DQS#[0..7] 1 1 @ @
1
1 VREF_DQ VSS1
1K_0402_1%
1 1 3 4 2 2 2 2 2
VSS2 DQ4 2
C141
5 6 <7> DDR_B_MA[0..15]
DQ0 DQ5 DDR_B_D4 2
7 8
RD11
CD28
DDR_B_D0 DQ1 VSS3
CD27
9 10 DDR_B_D5 2 2
CD51
2 2 DDR_B_D1 VSS4 DQS#0

2 11 12
2
13 DM0 DQS0 14 DDR_B_DQS#0

DDR_B_DM0 VSS5 VSS6 DDR_B_DQS0
D 15 16 D
17 DQ2 DQ6 18
DDR_B_D2 19 DQ3 DQ7 20 DDR_B_D6
DDR_B_D3 VSS7 VSS8 DDR_B_D7
21 22
DDR_B_D8 23 DQ8 DQ12 24
25 DQ9 DQ13 26 DDR_B_D12
27 28
29 DQS#1 DM1 30
DDR_B_DQS#1
DDR_B_DQS1 31 DQS1 RESET# 32 DDR_B_DM1
VSS11 VSS12 SM_DRAMRST# <7,11>
33 34 SM_DRAMRST#
35 DQ10 DQ14 36
DDR_B_D10 DQ11 DQ15 Layout Note: Place these 4 Caps near
DDR_B_D11 37 38 DDR_B_D14
DDR_B_D15
39 VSS13 VSS14 40
Command and Control signals of JDDRH
DQ16 DQ20 +1.5V
41 42 DDR_B_D20
DDR_B_D16 DQ17 DQ21
DDR_B_D17 43 44 DDR_B_D21
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
45 VSS15 VSS16 46
C179
C180
C177
47 DQS#2 DM2 48 1 1 1
DDR_B_DQS#2
0.1U_0402_10V6K
49 DQS2 VSS17 50 DDR_B_DM2
C178
DDR_B_DQS2 51 VSS18 DQ22 52 1
53 DQ18 DQ23 54 DDR_B_D22
DDR_B_D18 DDR_B_D23 2 2 2
55 DQ19 VSS19 56
DDR_B_D19 57 VSS20 DQ28 58
DQ24 DQ29 2
59 60 DDR_B_D28
DDR_B_D24 DQ25 VSS21 DDR_B_D29
61 62
DDR_B_D25 63 VSS22 DQS#3 64 DDR_B_DQS#3
65 DM3 DQS3 66
DDR_B_DM3 67 VSS23 VSS24 68 DDR_B_DQS3
69 DQ26 DQ30 70
71 DQ27 DQ31 72 DDR_B_D30
DDR_B_D26
C 73 74 C
75 CKE0 CKE1 76
<7> DDRB_CKE0
77 VDD1 VDD2 78 DDRB_CKE1 <7> Layout Note:
DDRB_CKE0 DDRB_CKE1
79 NC1 A15 80 Place near JDDRH.203 and 204
81 BA2 A14 82 +0.75VS
<7> DDR_B_BS2 DDR_B_MA15
DDR_B_MA14
DDR_B_BS2 VDD3 VDD4
83 84
85 A12/BC# A11 86 DDR_B_MA11
1U_0603_10V4Z
1U_0603_10V4Z
1U_0603_10V4Z
A7
1U_0603_10V4Z
A9
22U_0805_6.3V6M
C370
DDR_B_MA12 87 88
C184
C182
DDR_B_MA9
C183
C181
89 VDD5 VDD6 90 DDR_B_MA7 1 1 1 1 1
91 A8 A6 92
DDR_B_MA8 93 A5 A4 94 DDR_B_MA6
DDR_B_MA5 VDD7 VDD8 DDR_B_MA4
95 96
A3 A2 2 2 2 2 2
97 98 DDR_B_MA2
DDR_B_MA3 99 A1 A0 100
DDR_B_MA1 101 VDD9 VDD10 102 DDR_B_MA0
103 CK0 CK1 104
<7> DDRB_CLK0 DDRB_CLK0 CK0# CK1# DDRB_CLK1 DDRB_CLK1 <7>
DDRB_CLK0# 105 106
<7> DDRB_CLK0# VDD11 VDD12 DDRB_CLK1# DDRB_CLK1# <7>
107 108
109 A10/AP BA1 110 +1.5V
BA0 RAS#
1
DDR_B_MA10 111 112 DDR_B_BS1 DDR_B_BS1 <7>
<7> DDR_B_BS0 DDR_B_BS0 113 VDD13 VDD14 114 DDR_B_RAS# DDR_B_RAS# <7> RD12
115 WE# S0# 116 1K_0402_1%
<7> DDR_B_WE# DDR_B_WE# 117 CAS# ODT0 118 DDRB_SCS0# DDRB_SCS0# <7>
<7> DDR_B_CAS# DDR_B_CAS# 119 VDD15 VDD16 120 DDRB_ODT0 DDRB_ODT0 <7>
A13 ODT1
2
DDR_B_MA13 121 122
S1# NC2 DDRB_ODT1 DDRB_ODT1 <7>
123 124
<7> DDRB_SCS1# VDD17 VDD18
2.2U_0603_6.3V4Z
DDRB_SCS1# 125 126
0.1U_0402_10V6K
127 NCTEST VREF_CA 128

VSS27 VSS28 +VREF_CB +VREF_CB
1
129 130 1
131 DQ32 DQ36 132 1
DDR_B_D32 DQ33 DQ37
133 134 DDR_B_D36 RD13
VSS29 VSS30 DDR_B_D37
C168
DDR_B_D33 135 136

C167
DQS#4 DM4 1K_0402_1%

B 137 138 2 2 B
DDR_B_DQS#4 DQS4 VSS31
2
139 140 DDR_B_DM4
141 VSS32 DQ38 142
DDR_B_DQS4 DDR_B_D38
143 DQ34 DQ39 144
DDR_B_D34 145 DQ35 VSS33 146 DDR_B_D39
147 VSS34 DQ44 148
DDR_B_D35
149 DQ40 DQ45 150 DDR_B_D44
DDR_B_D40 151 DQ41 VSS35 152 DDR_B_D45
DDR_B_D41 VSS36 DQS#5
153 154
159 DQ42 DQ46 160
161 DQ43 DQ47 162 DDR_B_D46
DDR_B_D42
DDR_B_D43 163 VSS39 VSS40 164 DDR_B_D47
165 DQ48 DQ52 166
DDR_B_D48 167 DQ49 DQ53 168 DDR_B_D52
DDR_B_D49 169 VSS41 VSS42 170 DDR_B_D53
171 DQS#6 DM6 172
DDR_B_DQS#6 173 DQS6 VSS43 174 DDR_B_DM6
175 VSS44 DQ54 176
DDR_B_DQS6
177 DQ50 DQ55 178 DDR_B_D54
179 180
DDR_B_D51 181 VSS46 DQ60 182
183 DQ56 DQ61 184 DDR_B_D60
185 186
DDR_B_D57 187 VSS48 DQS#7 188
193 DQ58 DQ62 194
DDR_B_D58 195 DQ59 DQ63 196 DDR_B_D62
197 VSS51 VSS52 198
1DDR_B_D59
R76 2 DDR_B_D63
199 SA0 EVENT# 200
10K_0402_5%
0.1U_0402_10V6K
2.2U_0603_6.3V4Z
A 201 VDDSPD SDA 202 A

+3VS 1 1 203 SA1 SCL 204 PM_SMBDATA <11,26,36,39>
PM_SMBDATA
VTT1 VTT2 PM_SMBCLK <11,26,36,39>
1 2 PM_SMBCLK
205 206 +0.75VS
R77 10K_0402_5%
C186
C185
G1 G2
2 2
0.65A@0.75V
LCN_DAN06-K4926-0101
CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
B
5 4 3 2 1
A UV1A
B C D E
AN12 Part 1 of 7 P6
AM12 PEX_RX0 GPIO0
PEX_RX0_N M3
<5> PCIE_GTX_C_CRX_P[0..15]
AN14
PEX_RX1
GPIO1 L6 GPIO I/O USAGE
PCIE_GTX_C_CRX_P[0..15] PCIE_CTX_C_GRX_P15 AM14 GPIO2 P5
PCIE_CTX_C_GRX_N15 AP14 PEX_RX1_N GPIO3
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ PEX_RX2 P7 VID_4

<5> PCIE_GTX_C_CRX_N[0..15]
PCIE_CTX_C_GRX_P14 AP15
PEX_RX2_N
GPIO4 L7 VID_3 GPIO0 O GPU Core VID4
PCIE_GTX_C_CRX_N[0..15] PCIE_CTX_C_GRX_N14 AN15 GPIO5 M7
PCIE_CTX_C_GRX_P13 AM15 PEX_RX3 GPIO6
PEX_RX3_N N8
<5> PCIE_CTX_C_GRX_P[0..15]
PCIE_CTX_C_GRX_N13 AN17
PEX_RX4
GPIO7 M1 GPIO1 O GPU Core VID3
PCIE_CTX_C_GRX_P[0..15] PCIE_CTX_C_GRX_P12 AM17 GPIO8 M2 VID_1
PCIE_CTX_C_GRX_N12 AP17 PEX_RX4_N GPIO9
PEX_RX5 L1 VID_2 RV30
RV29 OPT@10K_0402_5%
OPT@ 10K_0402_5%
<5> PCIE_CTX_C_GRX_N[0..15]
PCIE_CTX_C_GRX_P11 AP18
PEX_RX5_N
GPIO10 M5 +3VS_DGPU GPIO2 O LCD_BL_PWM
PCIE_CTX_C_GRX_N[0..15] PCIE_CTX_C_GRX_N11 AN18 GPIO11 N3
PEX_RX6
GPIO
PCIE_CTX_C_GRX_P10 AM18 GPIO12 M4
AN20 PEX_RX6_N GPIO13 RH168 OPT@ 330K_0402_5% GPIO3 O LCD_VCC or PSI
PCIE_CTX_C_GRX_N10 N4
1
AM20 PEX_RX7 GPIO14 1
PCIE_CTX_C_GRX_P9 P2 VID_0 +3VS_DGPU
AP20 PEX_RX7_N GPIO15
PCIE_CTX_C_GRX_N9 R8 GPS_DOWN# @
PCIE_CTX_C_GRX_P8 AP21 PEX_RX8 GPIO16 GPIO4 O LCD_BLEN
PEX_RX8_N M6 VID_5 0_0402_5% 2 R266 1
PCIE_CTX_C_GRX_N8 AN21 GPIO17 R1 +3VS_DGPU PSI: Phase shedding
PCIE:80ohm+_10% PCIE_CTX_C_GRX_P7 AM21 PEX_RX9 GPIO18
5
PEX_RX9_N P3 UV2 0_0402_5% 2 R267 1
45~50ohm+_10% PCIE_CTX_C_GRX_N7 AN23
PEX_RX10
GPIO19 P4 1 @ GPIO5 O GPU Core VID1
PCIE_CTX_C_GRX_P6 AM23 GPIO20
P
PEX_RX10_N P1 4 IN1 PWR_GPS_DOWN# <41,57>
PCIE_CTX_C_GRX_N6 AP23 GPIO21 O
PCIE_CTX_C_GRX_P5 AP24 PEX_RX11 2 GPIO6 O GPU Core VID2
IN2
G
PEX_RX11_N GPS_DOWN# ACIN <27,41,48>
PCIE_CTX_C_GRX_N5 AN24
PCIE_CTX_C_GRX_P4 AM24 PEX_RX12 @ TC7SH08FU(TE85L,F)
@ DV6
3
PCIE_CTX_C_GRX_N4 AN26 PEX_RX12_N 2 1 GPIO7 O 3D Vision
PCIE_CTX_C_GRX_P3 AM26 PEX_RX13
PCIE_CTX_C_GRX_N3 AP26 PEX_RX13_N CH751H-40PT_SOD323-2
PCIE_CTX_C_GRX_P2 AP27 PEX_RX14 GPIO8 I/O OVERT
PEX_RX14_N AK9
PCIE_CTX_C_GRX_N2 AN27 DACA_RED AL10
PEX_RX15 DACA_GREEN @ R270
PCIE_CTX_C_GRX_P1 AM27 AL9
PEX_RX15_N 2 1
PCIE_CTX_C_GRX_N1 DACA_BLUE
0_0402_5%
GPIO9 I/O ALERT
PCIE_CTX_C_GRX_P0
DACs
PCIE_CTX_C_GRX_N0 AK14 AM9
OPT@ C16 1 2 0.1U_0402_16V7K
AJ14 PEX_TX0 DACA_HSYNC AN9 2 1 GPIO10 O MEM_VREF_CTL
AH14 PEX_TX0_N DACA_VSYNC +3VS_DGPU
PCIE_GTX_C_CRX_P15 OPT@ 11 22 PCIE_GTX_CRX_P15 R268 OPT@ 0_0402_5%
OPT@ C17
C20 0.1U_0402_16V7K
0.1U_0402_16V7K AG14 PEX_TX1 EC_GPS_DOWN# <41>
PCIE_GTX_C_CRX_N15 OPT@ C18 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N15
PCIE_GTX_C_CRX_P14 OPT@ C19 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P14 AK15 PEX_TX1_N
AG10
RV39 OPT@ 2.2K_0402_5% GPIO11 O GPU Core VID0
AJ15 PEX_TX2 DACA_VDD
PCIE_GTX_C_CRX_N14 PCIE_GTX_CRX_N14 PEX_TX2_N AP9 RH172 OPT@ RV38 OPT@ 2.2K_0402_5%
PCIE_GTX_C_CRX_P13 OPT@ C21 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P13 AL16 DACA_VREF AP8 2 1
PCI EXPRESS
PCIE_GTX_C_CRX_N13 OPT@ C22 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N13 AK16 PEX_TX3 DACA_RSET VGA_CRT_CLK GPIO12 I PWR_LEVEL
AK17 PEX_TX3_N
PCIE_GTX_C_CRX_P12 10K_0402_5% VGA_CRT_DATA
OPT@ C23
C24 11 22 0.1U_0402_16V7K PCIE_GTX_CRX_P12
0.1U_0402_16V7K AJ17 PEX_TX4 RV41 OPT@ 2.2K_0402_5%
PCIE_GTX_C_CRX_N12 OPT@ C25 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N12 PEX_TX4_N RV42
RV44 OPT@ 2.2K_0402_5% GPIO13 O GPU Core VID5
PCIE_GTX_C_CRX_P11 PCIE_GTX_CRX_P11 AH17 I2CB_SCL OPT@ 2.2K_0402_5%
OPT@
OPT@ C26
C28 11 22 0.1U_0402_16V7K
0.1U_0402_16V7K PCIE_GTX_CRX_N11 AG17 PEX_TX5 I2CB_SDA RV43 OPT@ 2.2K_0402_5%
PCIE_GTX_C_CRX_N11
OPT@ C29 1 2 0.1U_0402_16V7K AK18 PEX_TX5_N
2 PCIE_GTX_C_CRX_P10 OPT@ C27 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P10 PEX_TX6 GPIO14 I HPD_AB 2
PCIE_GTX_C_CRX_N10 PCIE_GTX_CRX_N10 AJ18 VGA_LCD_CLK
AL19 PEX_TX6_N VGA_LCD_DATA
PCIE_GTX_C_CRX_P9 PCIE_GTX_CRX_P9 PEX_TX7 R4 RV46 OPT@ 2.2K_0402_5%
OPT@ C30
OPT@ C32 11 22 0.1U_0402_16V7K
0.1U_0402_16V7K AK19 I2CA_SCL RV47 OPT@ 2.2K_0402_5%
PCIE_GTX_C_CRX_N9 PCIE_GTX_CRX_N9 PEX_TX7_N R5 GPIO15 I HPD_C
OPT@ C31 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P8 AK20 I2CA_SDA I2CS_SCL
PCIE_GTX_C_CRX_P8 PEX_TX8
AJ20 I2CS_SDA
PCIE_GTX_C_CRX_N8 OPT@ C33 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N8 PEX_TX8_N R7
PCIE_GTX_C_CRX_P7 OPT@ C35 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P7 AH20 I2CB_SCL VGA_CRT_CLK
OPT@ C34 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N7 AG20 PEX_TX9
I2CB_SDA
R6
VGA_CRT_DATA GPIO16 O MEM_VDD_CTL or PSI
PCIE_GTX_C_CRX_N7 PEX_TX9_N
OPT@ C37 1 2 0.1U_0402_16V7K AK21
PCIE_GTX_C_CRX_P6 OPT@ C36 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P6 PEX_TX10 R2
I2C
AJ21 I2CC_SCL I2CB_SCL
PCIE_GTX_C_CRX_N6 PCIE_GTX_CRX_N6
AL22 PEX_TX10_N R3 I2CA/B/C: Master GPIO17 I HPD_D
I2CC_SDA I2CB_SDA
PCIE_GTX_C_CRX_P5 OPT@ C38
OPT@ C39 11
1 22
2
0.1U_0402_16V7K PCIE_GTX_CRX_P5
0.1U_0402_16V7K AK22 PEX_TX11 I2CS: Slaver (for Internal Thermal Sensor)
PCIE_GTX_C_CRX_N5 OPT@ C40 0.1U_0402_16V7K PCIE_GTX_CRX_N5 PEX_TX11_N
AK23 T4
2 I2CS_SCL VGA_LCD_CLK
PCIE_GTX_C_CRX_P4 OPT@ C45 1 0.1U_0402_16V7K PCIE_GTX_CRX_P4
AJ23 PEX_TX12
I2CS_SDA
T3
VGA_LCD_DATA
GPIO18 I HPD_E
PCIE_GTX_C_CRX_N4 PCIE_GTX_CRX_N4 PEX_TX12_N
PCIE_GTX_C_CRX_P3 AH23
OPT@ C46 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P3 PEX_TX13 SM010018510---
PCIE_GTX_C_CRX_N3 OPT@ C116 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N3 AG23 I2CS_SCL SM01000FE00--
OPT@ C48 1 2 0.1U_0402_16V7K AK24 PEX_TX13_N
I2CS_SDA SM010007W00-- GPIO19 I HPD_F
猁ㄩ30ohm,
PCIE_GTX_C_CRX_P2 PCIE_GTX_CRX_P2 AJ24 PEX_TX14
PCIE_GTX_C_CRX_N2 OPT@ C213 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_N2 AL25 PEX_TX14_N +1.05VS_DGPU
LV10 ESR=0.05 OPT@ LV10
30R@100MHz(ESR=0.5) GPIO20 Reserved
0.1U_0402_16V4Z
4.7U_0402_6.3V6M
PCIE_GTX_C_CRX_P1 PCIE_GTX_CRX_P1 PEX_TX15
OPT@ C226 1 2 0.1U_0402_16V7K AK25
CV41
CV42
PCIE_GTX_C_CRX_N1 PCIE_GTX_CRX_N1 PEX_TX15_N 1 2
22U_0805_6.3V6M
PCIE_GTX_C_CRX_P0 OPT@ C47 1 2 0.1U_0402_16V7K PCIE_GTX_CRX_P0 AD8 +PLLVDD BLM18PG330SN1D_0603
22U_0805_6.3V6M
CV44
PCIE_GTX_C_CRX_N0 PCIE_GTX_CRX_N0 PLLVDD GPIO21 Reserved
CV43
AJ11
@
OPT@
PEX_WAKE_N AE8
1 OPT@ 2 SP_PLLVDD +PLLVDD 60mA
OPT@
AL13 +PLLVDD
OPT@
RV48 10K_0402_5% AK13 PEX_REFCLK AD7
+3VS_DGPU PEX_REFCLK_N VID_PLLVDD +GPU_PLLVDD
<26> CLK_PCIE_VGA AK12
PEX_CLKREQ_N CV42, CV43,
CLK
<26> CLK_PCIE_VGA# CV44

AJ26 H3
<26> PEG_CLKREQ# PEX_TSTCLK_OUT XTAL_IN H2 CV41 under GPU LV10
RV36 @ 200_0402_1% AK26 XTAL_OUT
PEX_TSTCLK_OUT_N close to ball : AD8 Near GPU
PEX_TSTCLK_OUT+ AJ12 J4
termination XTAL_OUTBUFF XTALIN
拸CV42ㄛCV44
PEX_TSTCLK_OUT- AP29 PEX_RST_N H1
3
RV36 default unmount XTAL_SSIN XTALOUT 3
PEX_TERMP
<28> PLTRST_VGA# DG
XTAL_OUTBUFF
猁ㄩ180ohm,
RV37 OPT@ 2.49K_0402_1% LV18 OPT@
PEX_TREMP XTAL_SSIN
1 2
LV18 ESR=0.2
BLM18PG181SN1D_2P
N13P-GLP-A1 FCBGA 908P GPU +GPU_PLLVDD +1.05VS_DGPU
22U_0805_6.3V6M
+GPU_PLLVDD
PEX_TERMP: used for internal calibration.
CV310
OPT@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0402_6.3V6M
90mA
CV38
CV40
+3VS_DGPU
CV311
VID Default setup is
10K_0402_5%
OPT@
10K_0402_5%
10K_0402_5%
10K_0402_5%
@
for boot voltage 0.9V
10K_0402_5%
RV55 1M_0402_5%
10K_0402_5%
OPT@
OPT@
OPT@
XTALOUT YV1 XTALIN CV38,CV40 under CV311,
@ 1
2 OPT@ 1
Crystal GPU CV310,

@ 1
@ 1
10P_0402_50V8J
4 3 close to ball : LV18

2 OPT@ 1
OPT@
@ 1
GND OUT
OPT@
AE8,AD7 Near GPU

CV46 1 2
IN GND
CV47
RV160
RV163
RV159
RV161
2
2
RV164
27MHZ_10PF_7V27000050
RV162
10P_0402_50V8J
2
OPT@
RV165
RV166 1 22 0_0402_5%
OPT@
OPT@ 0_0402_5% RV45 1 2 10K_0402_5%
OPT@
VID_0 RV167 1 OPT@2 0_0402_5% GPU_VID0 <57>
VID_1 RV168 1 OPT@2 0_0402_5% GPU_VID1 <57>
GPU_VID2 <57> +3VS_DGPU XTAL_OUTBUFF RV52 1 2 10K_0402_5%
OPT@ PFH: Pixel-Clock Frequency Hopping Interface.
VID_2
RV169 1 2
OPT@ GPU_VID3 <57> PFH can be implemented in system software with
VID_3 RV170 1 2 0_0402_5%
OPT@ 0_0402_5% GPU_VID4 <57>
XTAL_SSIN
NVAPI to reduce interference between graphic
VID_4
RV171
2
RV173
RV176
RV175
2 OPT@ 1
GPU_VID5 <57>
2 OPT@ 1
and wireless networking modems.

@ 1
@ 1
VID_5 OPT@
RV172
RV174
2 OPT@ 1
Refer to SP-04941-001
2 OPT@ 1
1 6
4 4
EC_SMB_CK2 <26,41>
I2CS_SCL
DMN66D0LDW-7_SOT363-6
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
QV6A
2
2
10K_0402_5%
@ RV35 0_0402_5%
10K_0402_5%
I2CS_SCL
+3VS_DGPU
@ RV40
5
0_0402_5% Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title

I2CS_SDA
OPT@
4 3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
I2CS_SDA EC_SMB_DA2 <26,41> Custom B
QV6B
A B C D E
A
<18> MDA[15..0] <20> MDC[15..0] MDC[15..0]
VRAM Interface <18> MDA[31..16] MDA[15..0] <20> MDC[31..16] MDC[31..16]
<19> MDA[47..32] MDA[31..16] <21> MDC[47..32] MDC[47..32]
<19> MDA[63..48] MDA[47..32] <21> MDC[63..48] MDC[63..48]
UV1C
MDA[63..48]
Part 3 of 7 D13
UV1B G9 FBB_CMD0 E14 CMDC[30..0] <20,21>
E9 FBB_D0 FBB_CMD1 F14
Part 2 of 7 U30 CMDA[30..0] <18,19> G8 FBB_D1 FBB_CMD2
FBA_CMD0 A12
L28 T31 F9 FBB_D2 FBB_CMD3 CMDC0
FBA_D0 FBA_CMD1 B12
M29 U29 MDC0 F11 FBB_D3 FBB_CMD4 CMDC1
FBA_D1 C14
L29 FBA_CMD2 R34 CMDA0 MDC1 G11 FBB_D4 FBB_CMD5 CMDC2
MDA0 FBA_D2 B14
M28 FBA_CMD3 R33 CMDA1 MDC2 F12 FBB_D5 FBB_CMD6 CMDC3
MDA1 FBA_D3 FBA_CMD4 MDC3 G15
N31 U32 CMDA2 G12 FBB_D6 FBB_CMD7 CMDC4
MDA2 FBA_D4 FBA_CMD5 MDC4 F15
P29 U33 CMDA3 G6 FBB_D7 FBB_CMD8 CMDC5
MDA3 FBA_D5 FBA_CMD6 MDC5 E15
R29 U28 CMDA4 F5 FBB_D8 FBB_CMD9 CMDC6
MDA4 FBA_D6 MDC6 D15
P28 FBA_CMD7 V28 CMDA5 E6 FBB_D9 FBB_CMD10 CMDC7
MDA5
J28 FBA_D7 MDC7 A14
FBA_CMD8 V29 CMDA6 F6 FBB_D10 FBB_CMD11 CMDC8
MDA6 FBA_D8 FBA_CMD9 MDC8 D14
H29 V30 CMDA7 F4 FBB_D11 FBB_CMD12 CMDC9
MDA7 FBA_D9 FBA_CMD10 MDC9 A15
J29 U34 G4 FBB_D12 FBB_CMD13 CMDC10
MDA8 H28 FBA_D10 FBA_CMD11 MDC10 B15
U31 CMDA8
CMDA9 E2 FBB_D13 FBB_CMD14 CMDC11
MDA9 G29 FBA_D11 FBA_CMD12 MDC11 C17
V34 CMDA10 F3 FBB_D14 FBB_CMD15 CMDC12
MDA10 E31 FBA_D12 MDC12 D18
FBA_CMD13 V33 CMDA11 C2 FBB_D15 FBB_CMD16 CMDC13
MDA11 E32 FBA_D13 FBA_CMD14 MDC13 E18
Y32 CMDA12 D4 FBB_D16 FBB_CMD17 CMDC14
MDA12 F30 FBA_D14 MDC14 F18
FBA_CMD15 AA31 CMDA13 D3 FBB_D17 FBB_CMD18 CMDC15
MDA13 C34 FBA_D15 FBA_CMD16 MDC15 A20
MDA14 AA29 CMDA14 C1 FBB_D18 FBB_CMD19 CMDC16
D32 FBA_D16 FBA_CMD17 MDC16 B20
AA28 CMDA15 B3 FBB_D19 FBB_CMD20 CMDC17
MDA15 B33 FBA_D17 MDC17 C18
FBA_CMD18 AC34 CMDA16 C4 FBB_D20 FBB_CMD21 CMDC18
MDA16 C33 FBA_D18 MDC18 B18
MDA17 FBA_CMD19 AC33 CMDA17 B5 FBB_D21 FBB_CMD22 CMDC19
F33 FBA_D19 FBA_CMD20 MDC19 G18
AA32 CMDA18 C5 FBB_D22 FBB_CMD23 CMDC20
MDA18 F32 FBA_D20 MDC20 G17
MDA19 FBA_CMD21 AA33 CMDA19 A11 FBB_D23 FBB_CMD24 CMDC21
H33 FBA_D21 MDC21 F17
FBA_CMD22 CMDA20 C11 FBB_D24 FBB_CMD25 CMDC22
MDA20 H32 FBA_D22 Y28 MDC22 D16
FBA_CMD23 D11 FBB_D25 FBB_CMD26 CMDC23
MEMORY INTERFACE B
MDA21 P34 FBA_D23 Y29 CMDA21 MDC23 A18
FBA_CMD24 FBB_D26
MEMORY INTERFACE
MDA22 FBA_D24 W31 CMDA22 MDC24 B11 FBB_CMD27 D17 CMDC24
P32 FBA_CMD25 CMDA23 FBB_D27 FBB_CMD28 CMDC25
MDA23 FBA_D25 Y30 MDC25 D8 A17
P31 FBA_CMD26 CMDA24 FBB_D28 FBB_CMD29 CMDC26
MDA24 FBA_D26 AA34 MDC26 A8 B17
P33 FBA_CMD27 CMDA25 FBB_D29 FBB_CMD30
MDA25 FBA_D27 Y31 MDC27 C8 E17 CMDC27
L31 FBA_CMD28 CMDA26 FBB_D30 FBB_CMD31 CMDC28
MDA26 L34 FBA_D28 Y34 MDC28 B8
MDA27 FBA_D29 FBA_CMD29 Y33 F24 FBB_D31 CMDC29
L32 FBA_CMD30 V31 CMDA27 MDC29 FBB_D32
FBA_D30 CMDA28 G23 CMDC30
MDA28 L33 FBA_CMD31 MDC30 FBB_D33
MDA29 FBA_D31 CMDA29 E24
AG28 CMDA30 MDC31 FBB_D34 C12
MDA30 FBA_D32 MDC32 G24 FBB_CMD_RFU0 C20
AF29 FBB_D35
MDA31 FBA_D33 D21 FBB_CMD_RFU1
AG29 R32 MDC33 FBB_D36
MDA32 AF28 FBA_D34 FBA_CMD_RFU0 MDC34 E21
AC32 FBB_D37
MDA33 AD30 FBA_D35 FBA_CMD_RFU1 MDC35 G21
MDA34 FBA_D36
RV57, RV58, RV59, RV60 change BS from F21 FBB_D38 2RV58 @ 1 60.4_0402_1%
AD29 MDC36 G14
MDA35 FBA_D37 "OPT@"
2
RV57 @ to 160.4_0402_1%
"@".--Design Guide. Joyce 1018 MDC37 G27 FBB_D39 FBB_DEBUG0 G20 +1.5VSDGPU
AC29 FBB_D40
MDA36 FBA_D38 +1.5VSDGPU MDC38 D27 FBB_DEBUG1
AD28 R28 FBB_D41 2 1
MDA37 AJ29 FBA_D39 FBA_DEBUG0 MDC39 G26 FBB_DEBUG0 RV60 @ 60.4_0402_1%
AC28 FBB_D42
A
MDA38 AK29 FBA_D40 FBA_DEBUG1 FBA_DEBUG0 MDC40 E27 FBB_DEBUG1

MDA39 FBA_D41 2 1 E29 FBB_D43
AJ30 FBA_DEBUG1 MDC41 FBB_D44 D12
MDA40 FBA_D42 RV59 @ 60.4_0402_1% F29 FBB_CLK0
AK28 MDC42 FBB_D45 E12
MDA41 AM29 FBA_D43 MDC43 E30 FBB_CLK0_N E20
MDA42 FBA_D44 R30 D30 FBB_D46 FBB_CLK1
AM31 FBA_CLK0 R31 MDC44 FBB_D47 F20 CLKC0 <20>
MDA43 AN29 FBA_D45 FBA_CLK0_N MDC45 A32 FBB_CLK1_N
AB31 CLKA0 <18> FBB_D48 CLKC0# <20>
MDA44 AM30 FBA_D46 FBA_CLK1 MDC46 C31
AC31 CLKA0# <18> FBB_D49 CLKC1 <21>
MDA45 AN31 FBA_D47 FBA_CLK1_N MDC47 C32
CLKA1 <19> FBB_D50 CLKC1# <21>
MDA46 AN32 FBA_D48 MDC48 B32
1
CLKA1# <19> FBB_D51 F8 1
MDA47 AP30 FBA_D49 MDC49 D29 FBB_WCK01

MDA48 FBB_D52 E8
AP32 FBA_D50 MDC50 A29 FBB_WCK01_N
MDA49 K31 FBB_D53 A5
AM33 FBA_D51 MDC51 C29 FBB_WCK23
MDA50 FBA_WCK01 L30 FBB_D54 A6
AL31 FBA_D52 MDC52 B29 FBB_WCK23_N
MDA51 FBA_WCK01_N H34 FBB_D55 D24
AK33 FBA_D53 MDC53 B21 FBB_WCK45
MDA52 FBA_WCK23 J34 FBB_D56 D25
AK32 FBA_D54 FBA_WCK23_N MDC54 C23 FBB_WCK45_N
MDA53 AG30 FBB_D57 B27 +FB_PLLAVDD LV11 OPT@ +1.05VS_DGPU
AD34 FBA_D55 MDC55 A21 FBB_WCK67
FBA_WCK45 C27 1 2
1U_0402_6.3V6K
MDA54 FBA_D56 AG31 C21 FBB_D58
AD32 FB_CLAMP: MDC56 FBB_WCK67_N
CV53
MDA55 FBA_WCK45_N AJ34 FBB_D59 MPZ1608S300AT 0603
1U_0402_6.3V6K
FBA_D57
22U_0805_6.3V6M
AC30 FBA_WCK67 MDC57 B24 300mA
Leave as NC for N13P-PES/-GL/-GLP/-NS1 FBB_D60
OPT@ CV52
OPT@ CV51
MDA56 FBA_D58 AK34 C24 1
AD33 FBA_WCK67_N MDC58 FBB_D61 +FB_PLLAVDD
MDA57 AF31 FBA_D59 and N13M-GE1/NS1; MDC59 B26
OPT@
FBA_D60 FBB_D62 D6
MDA58 AG34 Pull down with a 10K on N13P-GV, N13M-GS, MDC60 C26 FBB_WCKB01
FBA_D61 FBB_D63 D7
MDA59 AG32 MDC61 FBB_WCKB01_N 2
MDA60 FBA_D62 J30 N13E-GE,N13P-GT/-GS/-LP and N14-Q1/-Q3. E11 FBB_WCKB23
C6
AG33 FBA_WCKB01 MDC62 FBB_DQM0 B6
MDA61 FBA_D63 J31 E3 FBB_WCKB23_N
FBA_WCKB01_N <20> DQMC[3..0] MDC63 FBB_DQM1 F26
MDA62 P30 J32 A3 FBB_WCKB45
<18> DQMA[3..0] FBA_DQM0 FBA_WCKB23 J33 DQMC0 FBB_DQM2 E26
MDA63 F31 FBA_WCKB23_N DQMC1 C9 FBB_WCKB45_N
DQMA0 FBA_DQM1 AH31 FBB_DQM3 A26
F34 FBA_WCKB45 DQMC2 F23 FBB_WCKB67
DQMA1 FBA_DQM2 AJ31 FBB_DQM4 A27
M32 FBA_WCKB45_N <21> DQMC[7..4] DQMC3 F27 FBB_WCKB67_N
DQMA2 FBA_DQM3 AJ32 FBB_DQM5
AD31 FBA_WCKB67 DQMC4 C30
<19> DQMA[7..4] DQMA3 FBA_DQM4 AJ33 FBB_DQM6
AL29 FBA_WCKB67_N DQMC5 A24
DQMA4 FBA_DQM5 FBB_DQM7
AM32 DQMC6
DQMA5 FBA_DQM6 30ohm@100M // ESR=0.01
DQMA6 AF34 DQMC7 D10
FBA_DQM7 D5 FBB_DQS_WP0 SM01000EQ00--
DQMA7 E1 @ RV152 <20> DQSC[3..0] FBB_DQS_WP1 SM010031100--
M31 FB_CLAMP DQSC0 C3
<18> DQSA[3..0] FBA_DQS_WP0 10K_0402_5% FBB_DQS_WP2
G31 DQSC1 B9
DQSA0 FBA_DQS_WP1 FBB_DQS_WP3 H17
E33 DQSC2 E23 FBB_PLL_AVDD
DQSA1 FBA_DQS_WP2 FBB_DQS_WP4
M33 <21> DQSC[7..4] DQSC3 E28
DQSA2 FBA_DQS_WP3 K27 FBB_DQS_WP5
AE31
0.1U_0402_16V4Z
<19> DQSA[7..4] DQSA3 FB_DLL_AVDD DQSC4 B30 +FB_PLLAVDD +FB_PLLAVDD
FBA_DQS_WP4
CV48
AK30 DQSC5 A23 FBB_DQS_WP6
DQSA4 FBA_DQS_WP5 +FB_PLLAVDD
AN33 DQSC6 FBB_DQS_WP7
DQSA5 FBA_DQS_WP6
DQSA6 AF33 35mA DQSC7 D9 66mA
FBA_DQS_WP7
OPT@
U27 E4 FBB_DQS_RN0
DQSA7 FBA_PLL_AVDD <20> DQSC#[3..0] FBB_DQS_RN1
M30
0.1U_0402_16V4Z
<18> DQSA#[3..0] +FB_PLLAVDD DQSC#0 B2

FBA_DQS_RN0 FBB_DQS_RN2
CV50
DQSA#0 H30 66mA DQSC#1 A9

E34 FBA_DQS_RN1 D22 FBB_DQS_RN3 CV48 Under GPU
DQSA#1 FBA_DQS_RN2 DQSC#2
M34 H26 FBB_DQS_RN4
DQSA#2 FBA_DQS_RN3 FB_VREF CV49 <21> DQSC#[7..4] DQSC#3 D28 close to ball : H17
OPT@
AF30 A30 FBB_DQS_RN5

<19> DQSA#[7..4] DQSA#3 FBA_DQS_RN4 DQSC#4
OPT@
AK31 0.1U_0402_16V4Z B23 FBB_DQS_RN6

AM34 FBB_DQS_RN7
DQSA#6 AF32 DQSC#7
FBA_DQS_RN7
DQSA#7
N13P-GLP-A1 FCBGA 908P GPU

CV50 Under GPU OPT@ FBB_PLL_AVDD Design Guide:
close to ball : K27
OPT@ CV49 Under GPU 100nF X7R 0402 1pcs per pin under GPU
close to ball : U27
22uF X5R 0805 1pcs per pin Near GPU
bead--30ohm@100MHz (ESR=0.01ohm) 0603 1pcs Near GPU

A
5 4 3 2 1
UV1D
Part 4 of 7 MULTI LEVEL STRAPS +3VS_DGPU

AM6 +3VS_DGPU
AN6 IFPA_TXC P8
PAD @
AP3 IFPA_TXC_N NC AC6 TV5
1
1
1
IFPA_TXD0
1
NC RV71
1
AN3 AJ28 @ RV68
34.8K_0402_1%
IFPA_TXD0_N NC
1
RV69
1
AN5 AJ4 RV65 RV66
AM5 IFPA_TXD1 NC @ @
AJ5 RV64 RV70
IFPA_TXD1_N NC
@
AL6
@
AL11
AK6 IFPA_TXD2 NC 4.99K_0402_1% 30K_0402_1% 4.99K_0402_1% 4.99K_0402_1%
C15 4.99K_0402_1%
RV67
2
2
2
IFPA_TXD2_N
2
NC
2
AJ6 D19
NC
IFPA_TXD3 45.3K_0402_1% 4.99K_0402_1%
NC
2
AH6
IFPA_TXD3_N NC
D20 Straps
D23
NC D26 STRAP0 ROM_SI
D AJ9 NC H31 STRAP1 STRAP3 ROM_SO D
AH9 IFPB_TXC NC STRAP2 STRAP4 ROM_SCLK
T8
1
1
1
1
IFPB_TXC_N
1
NC V32 RV74
1
RV79
1
AP6 RV73
4.99K_0402_1%
20K_0402_1%
NC RV77 RV78
AP5 IFPB_TXD4
1
IFPB_TXD4_N
@
AM7 RV72 @
IFPB_TXD5
@ RV75
AL7
@ RV76
AN8 IFPB_TXD5_N 45.3K_0402_1% 10K_0402_1% 15K_0402_1%
10K_0402_1%
@
45.3K_0402_1%
2
2
2
2
IFPB_TXD6
2
2
AM8 4.99K_0402_1%
IFPB_TXD6_N
2
AK8
AL8 IFPB_TXD7 RV177 1 2 0_0402_5%
OPT@
IFPB_TXD7_N L4
VDD_SENSE
VCCSENSE_VGA <57>
AK1
AJ1 IFPC_L0
IFPC_L0_N L5 RV178 1 2 0_0402_5%
OPT@ X76-
AJ3 GND_SENSE
AJ2 IFPC_L1
IFPC_L1_N VSSSENSE_VGA <57>
AH3
AH4 IFPC_L2 @ RV88 10K_0402_5%
AG5 IFPC_L2_N
AG4 IFPC_L3 +3VS_DGPU
啎啎RV88 for XOR tree testing. --Joyce 1026

IFPC_L3_N
AM1
TEST AK11 DG: Physical
strapping pin
Logical
Strapping Bit3
Logical
Strapping Bit2
Logical
Strapping Bit1
Logical
Strapping Bit0
Resistor
Values
Pull up
to 3V
Pull down
to GND
IFPD_L0 TESTMODE RV82 OPT@ 10K_0402_5%
AM2 RV83 OPT@ 10K_0402_5%
AM3 IFPD_L0_N AM10 5K 1000 0000
IFPD_L1 JTAG_TCK AM11 @
AM4 JTAG_TCK PAD TV1 @ ROM_SCLK PCI_DEVID[4] SUB_VENDOR SLOT_CLK_CFG PEX_PLL_EN_TERM
IFPD_L1_N JTAG_TDI AP12 PAD TV2
AL3 JTAG_TDO JTAG_TDI 10K 1001 0001
IFPD_L2 AP11 JTAG_TDO PAD TV3 @
AL4 JTAG_TMS @ ROM_SI RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
AK4 IFPD_L2_N AN11 JTAG_TMS PAD TV4 15K 1010 0010
IFPD_L3 JTAG_TRST_N
AK5 JTAG_TRST ROM_SO FB [1] FB [0] SMB_ALT_ADDR VGA_DEVICE
IFPD_L3_N OPT@
20K 1011 0011
LVDS/TMDS
RV84 10K_0402_5%
STRAP0 USER [3] USER [2] USER [1] USER [0]
C AD2 25K 1100 0100 C
AD3 IFPE_L0 STRAP1 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] 3GIO_PAD_CFG_ADR[0]
AD1 IFPE_L0_N 30K 1101 0101
AC1 IFPE_L1
IFPE_L1_N
SERIAL RV85 10K_0402_5%
STRAP2 PCI-DEVID [3] PCI-DEVID [2] PCI-DEVID [1] PCI-DEVID [0]
AC2 H6 35K 1110 0110
IFPE_L2 ROM_CS_N H4 OPT@
AC3 ROM_CS# +3VS_DGPU STRAP3 SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
IFPE_L2_N ROM_SCLK H5
AC4 ROM_SCLK 45K 1111 0111
IFPE_L3 ROM_SI H7
AC5 ROM_SI STRAP4 RESERVED PCIE_SPEED_ PCIE_MAX_SPEED DP_PLL_VDD33V
IFPE_L3_N ROM_SO CHANGE_GEN3
ROM_SO
AE3 ROM support: 512Kbit or greater, up to 50MHz.

AE4 IFPF_L0
AF4 IFPF_L0_N
IFPF_L1 CEC: Place a 10K pull up resistor to 3.3V on
AF5 N13P-PES/-GL/-GLP/-NS1 and N13M-NS1 SUB_VENDOR PEX_PLL_EN_TERM: PCIE_MAX_SPEED
IFPF_L1_N
AD4
IFPF_L2
GENERAL L2 @ RV153 10K_0402_5%
PLL termination setting
AD5 0 No VBIOS ROM 0 Limited to PCIE GEN 1
IFPF_L2_N BUFRST_N
AG1 0 Disable (Default)
AF1 IFPF_L3 L3 OPT@ RV86 10K_0402_5% 1 BIOS ROM is present (Default) 1 Enable 1 PCIE GEN 2/3 capable
IFPF_L3_N CEC
+3VS_DGPU
J1
MULTI_STRAP_REF0_GND MULTI_STRAP_REF0_GND 1 2 FB [1:0]: N13x FB Aperture Size
AG3 OPT@ RV87 40.2K_0402_1%
AG2 IFPC_AUX_I2CW_SCL
0 RESERVED
IFPC_AUX_I2CW_SDA_N
J2
STRAP0 J7 STRAP0 1 RESERVED
AK3 STRAP1 J6 STRAP1
AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP2 2 256 MB (Default)
IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP3
STRAP4 STRAP4 3 RESERVED
AB3
AB4 IFPE_AUX_I2CY_SCL USER Straps
IFPE_AUX_I2CY_SDA_N K3
B THERMDP K4 1111 EDID is used B
AF3 THERMDN
AF2 IFPF_AUX_I2CZ_SCL others: DG-05587 Page195
IFPF_AUX_I2CZ_SDA_N
3GIO_PAD_CFG
0000--0101 RESERVED
N13P-GLP-A1 FCBGA 908P GPU 0110 Notebook (default)
OPT@
0111--1111 RESERVED
For N13P-GLP strap table
For N13P-PES :
Strap 0 : PU45 GPU Frenq. Memory Size Memory Config strap0 strap1 strap2 strap3 strap4 ROM_SI ROM_SO ROM_SCLK
Strap 1 : PD35 64M* 16* 8 Hynix RV64 RV73 RV74 RV77 RV70 RV71
Strap 2 : PU35 900 MHz 1GB SA000041S20 PU 45K PD 45K PU 5K NC NC PD 15K PD 30K PD 15K
ROM_SCLK : PU15 64M* 16* 8 Samsung RV64 RV73 RV74 RV77 RV70 RV71
900 MHz 1GB SA00004GS00 PU 45K PD 45K PU 5K NC NC PD 20K PD 30K PD 15K
ROM_SI : PD35 N13P-GLP
ROM_SO : PD10 128M* 16* 8 Hynix RV64 RV73 RV74 RV77 RV70 RV71
A 900 MHz 2GB SA00003YO00 PU 45K PD 45K PU 5K NC NC PD 35K PD 30K PD 15K A
128M* 16* 8 Samsung RV64 RV73 RV74 RV77 RV70 RV71

900 MHz 2GB SA000047Q00 PU 45K PD 45K PU 5K NC NC PD 45K PD 30K PD 15K

5 4 3 2 1
5 4 3 2 1
Under GPU +1.05VS_DGPU
4.7U_0603_6.3V6K
10U_0603_6.3V6M
1U_0402_6.3V6K
22U_0805_6.3V6M
Near GPU
CV56
1U_0402_6.3V6K
CV57
22U_0805_6.3V6M
1
CV55
CV59
CV54
CV60
10U_0603_6.3V6M
CV58
1
OPT@
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍDesign guide no define
OPT@
OPT@
OPT@
2
OPT@
OPT@
UV1E
OPT@
2
Part 5 of 7
+1.5VSDGPU Under GPU
1U_0402_6.3V6K
4.7U_0603_6.3V6K
AA27
0.1U_0402_16V4Z
7200mA AG19
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV62
FBVDDQ_0
CV61
CV65
0.1U_0402_16V4Z
AA30 PEX_IOVDD_0 +1.05VS_DGPU
CV63
AG21
CV64
CV66
FBVDDQ_1 PEX_IOVDD_1
4.7U_0603_6.3V6K
AB27 AG22 Under GPU Near GPU
10U_0603_6.3V6M
1U_0402_6.3V6K
22U_0805_6.3V6M
1U_0402_6.3V6K
CV76
FBVDDQ_2
22U_0805_6.3V6M
AB33 PEX_IOVDD_2
CV67
CV74
AG24
CV78
1
CV75
CV68
OPT@
OPT@
FBVDDQ_3
OPT@
10U_0603_6.3V6M
PEX_IOVDD_3
OPT@
AC27
OPT@
FBVDDQ Decouping Design Guide: AH21
3300 mA
OPT@
CV77
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25 1
D 0.1uF X7R 0402 8pcs under GPU PEX_IOVDD_5 D
OPT@
FBVDDQ_5
OPT@
AE27
OPT@
OPT@
OPT@
OPT@
1uF X7R 0603 2pcs under GPU FBVDDQ_6 2
AF27
OPT@
4.7uF X6S 0603 2pcs under GPU AG27 FBVDDQ_7 2
10uF X5R 0805 4pcs Near GPU FBVDDQ_8 AG13
B13 PEX_IOVDDQ_0 AG15
B16 FBVDDQ_9 PEX_IOVDDQ_1
FBVDDQ_10 AG16
Under GPU B19 PEX_IOVDDQ_2 AG18
E13 FBVDDQ_11 PEX_IOVDDQ_3
0.1U_0402_16V4Z
FBVDDQ_12 AG25
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
CV72
E16 PEX_IOVDDQ_4
CV69
AH15
CV73
FBVDDQ_13
0.1U_0402_16V4Z
1U_0402_6.3V6K
0.1U_0402_16V4Z
E19 PEX_IOVDDQ_5 AH18
CV79
CV71
CV70
H10 FBVDDQ_14 PEX_IOVDDQ_6 +3VS_DGPU
FBVDDQ_15 AH26
OPT@
H11 PEX_IOVDDQ_7
OPT@
AH27 Near GPU
OPT@
FBVDDQ_16
4.7U_0603_6.3V6K
H12 PEX_IOVDDQ_8
CV81
AJ27 PEX_PLL_HVDD:
OPT@
OPT@
OPT@
FBVDDQ_17
4.7U_0603_6.3V6K
H13 PEX_IOVDDQ_9 AK27 420mA
CV82
H14 FBVDDQ_18 PEX_IOVDDQ_10 AL27
N13P-GLP/PES :NC
FBVDDQ_19
H15 PEX_IOVDDQ_11 N13P-LP : power.
POWER
OPT@
FBVDDQ_20 AM28
H16 PEX_IOVDDQ_12 AN28 CV80,CV198 Under GPU
OPT@
H18 FBVDDQ_21 PEX_IOVDDQ_13
H19 FBVDDQ_22 close to ball
Near GPU FBVDDQ_23 @
H20
FBVDDQ_24 210mA
10U_0603_6.3V6M
CV80 0.1U_0402_16V4Z
10U_0603_6.3V6M
H21 AH12
CV83
CV85
1 1 H22 FBVDDQ_25 PEX_PLL_HVDD
10U_0603_6.3V6M
10U_0603_6.3V6M
FBVDDQ_26
CV86
CV84
1 1 H23
H24 FBVDDQ_27
OPT@
OPT@
2 H8 FBVDDQ_28
2 FBVDDQ_29 AG12 210mA
OPT@
LV12
OPT@
H9 PEX_SVDD_3V3
1U_0402_6.3V6K
2 Under GPU Near GPU
4.7U_0603_6.3V6K
2 L27 FBVDDQ_30 OPT@ 2 1
CV89
CV88
FBVDDQ_31 CV198 0.1U_0402_16V4Z BLM18PG121SN1D_0603 +1.05VS_DGPU
M27
0.1U_0402_16V4Z
FBVDDQ_32
CV87
N27 AG26 OPT@
150mA
猁:120ohm@100MHz, ESR=0.18ohm 0603
FBVDDQ_33 PEX_PLLVDD
P27
OPT@
OPT@
FBVDDQ_34 +PEX_PLLVDD
R27
FBVDDQ_35 LV12
OPT@
T27
T30 FBVDDQ_36
C J8 LV12 stuff a 0ohm resistor instead for C
T33 FBVDDQ_37 VDD33_0 +VDD33
120mA
FBVDDQ_38 K8 N13E-GE, N13P-GT/-GS/-LP/-GV, N13M-GS,
V27 VDD33_1 L8
W27 FBVDDQ_39 VDD33_2 N14P-Q1/-Q3
FBVDDQ_40 M8 Design guide no define
W30 VDD33_3
W33 FBVDDQ_41
Y27 FBVDDQ_42
FBVDDQ_43 2 10K_0402_5%
1OPT@ RV102 OPT@
AH8 @ RV90 1K_0402_5% Under GPU
0.1U_0402_16V4Z
IFPAB_PLLVDD
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
AJ8 RV89
CV91
+IFPAB_PLLVDD
CV97
CV90
CV92
IFPAB_RSET +3VS_DGPU
1U_0402_6.3V6K
1U_0402_6.3V6K
2 10K_0402_5%
1OPT@ RV104 0_0603_5%
CV96
AG8
CV95
IFPA_IOVDD AG9
OPT@
2 OPT@ 1
OPT@
+IFPAB_IOVDD
OPT@
OPT@
F1 IFPB_IOVDD
RV91 10_0402_5% FB_VDDQ_SENSE
OPT@
OPT@
+1.5VSDGPU FB_VDDQ_SENSE 1OPT@ RV922 10K_0402_5%
2 OPT@ 1 AF7
F2 IFPC_PLLVDD AF8
RV93 10_0402_5% FB_GND_SENSE IFPC_RSET +IFPC_PLLVDD
@ RV94 1K_0402_5%
FB_GND_SENSE
AF6
J27 IFPC_IOVDD 1OPT@ RV952 10K_0402_5%
FB_CAL_PD_VDDQ +IFPC_IOVDD
2 OPT@ 1
+1.5VSDGPU RV96 FB_CAL_PD_VDDQ
40.2_0402_1% 1OPT@ RV972 10K_0402_5%
AG7
2 OPT@ 1 H27 IFPD_PLLVDD AN2 @ RV99 1K_0402_5%
FB_CAL_PU_GND IFPD_RSET +IFPD_PLLVDD
RV98 42.2_0402_1%
FB_CAL_PU_GND
2 OPT@ 1 AG6
Calibration Pin DDR3 GDDR5 H25 IFPD_IOVDD 2 10K_0402_5%
1OPT@ RV100
RV101 51.1_0402_1% FB_CAL_TERM_GND +IFPD_IOVDD
FB_CAL_PD_VDDQ 40.2ohm 40.2ohm FB_CAL_TERM_GND 2 10K_0402_5%
1OPT@ RV114
AB8
IFPEF_PLVDD AD6 @
FB_CAL_PU_GND 42.2ohm 40.2ohm IFPEF_RSET +IFPEF_PLLVDD
RV103 1K_0402_5%
AC7
FB_CAL_TERM_GND 51.1ohm 60.4ohm IFPE_IOVDD AC8
IFPF_IOVDD 2 10K_0402_5%
1OPT@ RV126
+IFPEF_IOVDD
B B
PEX_IOVVD/Q
OPT@ Capacitor Type Footprint Population Location
1.0uF X6S 0402 4 Under GPU
Near GPU
+3VS_DGPU LV7 Under GPU 4.7uF X6S 0603 2 Near GPU
2 1 0.1U_0402_16V4Z
BLM18PG181SN1D_0603 1U_0402_6.3V4Z 110mA 10uF X5R 0805 4 Midway between GPU and Power Supply
+IFPC_PLLVDD
@
22uF X5R 0805 4 Midway between GPU and Power Supply
1 1 1
1 CV215
300ohm 100MHz, ESR=0.25ohm 1
CV203 CV202 0.1U_0402_16V4Z
@ CV199 CV200 @ @ PEX_PLLVDD
2 @ 2 2
@
2 2 Capacitor Type Footprint Population Location
4.7U_0603_6.3V6K 100nF X6S 0402 1 Under GPU

0.1U_0402_16V4Z
1.0uF X5R 0603 1 Near GPU
4.7uF X5R 0805 1 Near GPU
LV13
+1.05VS_DGPU Under GPU(below 150mils)
2 1 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 50mA PEX_SVDD/PLL_HVDD
BLM18PG181SN1D_0603 +IFPC_IOVDD
@ 1
Capacitor Type Footprint Population Location
A 1 1 A
CV205 1 0.1uF X5R 0402 1 Near GPU

CV201 CV204 CV206
220ohm 100MHz, ESR=0.05ohm @ @ 0.1U_0402_16V4Z
2 @ 4.7uF X5R 0603 2 Near GPU
2 2 @
2
1U_0402_6.3V4Z
5 4 3 2 1
5 4 3 2 1
UV1F
+VGA_CORE UV1G +VGA_CORE
Part 6 of 7 D2
A2 GND_100 D31
GND_0 GND_101 V17
AA17 D33 Part 7 of 7 VDD_56
D AA18 GND_1 GND_102 E10 60A AA12 VDD_57
V18
D
GND_2 GND_103 V20
AA20 E22 AA14 VDD_0 VDD_58 V22
GND_3 GND_104
AA22 E25 AA16 VDD_1 VDD_59 W12
GND_4 GND_105
AB12 E5 AA19 VDD_2 VDD_60 W14
GND_5 GND_106
AB14 E7 AA21 VDD_3 VDD_61
GND_6 GND_107 W16
AB16 F28 AA23 VDD_4 VDD_62
GND_7 GND_108 W19
AB19 F7 AB13 VDD_5 VDD_63
GND_8 GND_109 W21
AB2 G10 AB15 VDD_6 VDD_64
GND_9 GND_110 W23
GND_10 GND_111 Y13
A33 G16 AB18 VDD_8 VDD_66
GND_11 GND_112 Y15
GND_12 GND_113 Y17
GND_13 GND_114 Y18
AB30 G22 AC12 VDD_11 VDD_69
GND_14 GND_115 Y20
GND_15 GND_116 Y22
AB7 GND_16 GND_117 G3 AC19 VDD_14
AC13 GND_17 GND_118 G30 AC21 VDD_15
GND_18 GND_119 U1
AC15 G32 AC23 VDD_16 XVDD_1
GND_19 GND_120 U2
AC17 G33 M12 VDD_17 XVDD_2
GND_20 U3
AC18 GND_121 G5 M14 VDD_18 XVDD_3
GND_21 U4
AA13 GND_122 G7 M16 VDD_19
POWER
XVDD_4 U5
AC20 GND_22 GND_123 K2 M19 VDD_20 XVDD_5 U6
AC22 GND_23 GND_124 K28 M21 VDD_21 XVDD_6 U7
AE2 GND_24 GND_125 M23 VDD_22
K30 XVDD_7 U8
AE28 GND_25 GND_126 N13 VDD_23
K32 XVDD_8
K33
K5 V1
K7 XVDD_9 V2
M13 XVDD_10 V3
M15 XVDD_11 V4
AH10 GND_31 GND_132 P12 VDD_29
M17 XVDD_12 V5
AA15 GND_32 GND_133 M18 P14 VDD_30 XVDD_13 V6
C AH13 GND_33 GND_134 M20 P16 VDD_31 XVDD_14 C
V7
AH16 GND_34 GND_135 M22 P19 VDD_32 XVDD_15 V8
AH19 GND_35 GND_136 N12 P21 VDD_33 XVDD_16
AH2 GND_36 GND_137 N14 P23 VDD_34
AH22 GND_37 GND_138 N16 R13 VDD_35
GND_38 GND_139 R15 VDD_36 W2
AH24 N19 XVDD_17
GND_39 GND_140 R17 VDD_37 W3
AH28 N2 XVDD_18
GND_40 GND_141 R18 VDD_38 W4
AH29 N21 XVDD_19
GND_41 GND_142 R20 VDD_39 W5
AH30 N23 XVDD_20
GND_42 GND_143 R22 VDD_40 W7
AH32 N28 XVDD_21 W8
GND
AH33 GND_43 GND_144 N30 T12 VDD_41 XVDD_22

AH5 GND_44 GND_145 N32 T14 VDD_42
AH7 GND_45 GND_146 N33 T16 VDD_43
GND_46 GND_147 T19 VDD_44 Y1
AJ7 N5 XVDD_23
GND_47 GND_148 T21 VDD_45 Y2
AK10 N7 XVDD_24
GND_48 GND_149 T23 VDD_46 Y3
AK7 P13 XVDD_25
GND_49 GND_150 U13 VDD_47 Y4
AL12 P15 XVDD_26
GND_50 GND_151 U15 VDD_48 Y5
AL14 P17 XVDD_27
GND_51 GND_152 U17 VDD_49 Y6
AL15 P18 XVDD_28
GND_52 GND_153 U18 VDD_50 Y7
AL17 P20 XVDD_29
GND_53 GND_154 U20 VDD_51 Y8
AL18 P22 XVDD_30
AL2 GND_54 GND_155 R12 U22 VDD_52
AL20 GND_55 GND_156 R14 V13 VDD_53
GND_56 GND_157 V15 VDD_54 AA1
AL21 R16 XVDD_31
GND_57 GND_158 VDD_55 AA2
AL23 R19 XVDD_32
GND_58 GND_159 AA3
AL24 R21 XVDD_33
GND_59 GND_160 AA4
AL26 R23 XVDD_34
GND_60 GND_161 AA5
AL28 T13 XVDD_35
GND_61 GND_162 AA6
AL30 T15 XVDD_36
GND_62 GND_163 AA7
AL32 T17 XVDD_37
GND_63 GND_164 AA8
AL33 T18 XVDD_38
AL5 GND_64 GND_165
GND_65 T2
AM13 GND_166 T20 B
B GND_66
AM16 GND_167 T22
AM19 GND_67 GND_168
GND_68 AG11
AM22 GND_169 T28 N13P-GLP-A1 FCBGA 908P GPU
AM25 GND_69 GND_170
GND_70 T32 OPT@
AN1 GND_171 T5
AN10 GND_71 GND_172
GND_72 T7
AN13 GND_173 U12
AN16 GND_73 GND_174
GND_74 U14
AN19 GND_175 U16
AN22 GND_75 GND_176
GND_76 U19
AN25 GND_177 U21
AN30 GND_77 GND_178
GND_78 U23
AN34 GND_179 V12
AN4 GND_79 GND_180
GND_80 V14
AN7 GND_181 V16
AP2 GND_81 GND_182
GND_82 V19
AP33 GND_183 V21
B1 GND_83 GND_184
GND_84 V23
B10 GND_185 W13
B22 GND_85 GND_186
GND_86 W15
B25 GND_187 W17
B28 GND_87 GND_188
GND_88 W18
B31 GND_189 W20
B34 GND_89 GND_190
GND_90 W22
B4 GND_191 W28
B7 GND_91 GND_192
GND_92 Y12
C10 GND_193 Y14
C13 GND_93 GND_194
GND_94 Y16
C19 GND_195 Y19
C22 GND_95 GND_196
GND_96 Y21
C25 GND_197 Y23
C28 GND_97 GND_198
A AH11 A
C7 GND_98 GND_199
GND_99 C16
GND_OPT W32
GND_OPT

OPT@ Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title
5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D
Address 0..31 32..63
CMD0 CS0_L#
D 64Mx16 DDR3 *8==>1GB CMD1 D
128Mx16 DDR3 *8==>2GB CMD2 ODT_L

CMD3 CKE
UV4 X76@ CMD4 A14 A14
<14,19> DQSA[7..0] UV3 X76@ M8
DQSA[7..0] H1 VREFCA E3 CMD5 RST RST
M8 VREFDQ DQL0 F7
<14,19> DQSA#[7..0] H1 VREFCA E3
DQSA#[7..0] DQL0 MDA12 swap 0329 DQL1 F2
VREFDQ F7 MDA3 CMD6 A9 A9
+MEM_VREF0 DQL1 MDA14 +MEM_VREF1 N3 DQL2 F8
<14,19> DQMA[7..0] F2 A0 MDA4
DQMA[7..0] N3 DQL2 MDA8 P7 DQL3 H3
A0 F8 A1 MDA2 CMD7 A7 A7
P7 DQL3 MDA15 DQL4 H8
<14,19> MDA[63..0] A1 H3 CMDA9 P3 MDA7
CMDA9 DQL4 DQL5
MDA[63..0] P3 H8 MDA9
CMDA11 N2 A2 G2 MDA0 CMD8 A2 A2
DQL5 DQL6
<14,19> CMDA[30..0]
CMDA11 N2 A2 G2 MDA13 Group1
CMDA8 P8 A3 H7 MDA5 Group0
DQL6 DQL7
CMDA[30..0] CMDA8
P8 A3 H7 MDA10
CMDA25 P2 A4 MDA1 CMD9 A0 A0
CMDA25 A4 DQL7 MDA11 R8 A5
P2 CMDA10 D7 MDA6
CMDA10
R8 A5
CMDA24 R2 A6 DQU0 CMD10 A4 A4
CMDA24 D7 C3
R2 A6 DQU0 CMDA22 T8 A7 DQU1
CMDA22 C3 C8
+1.5VSDGPU T8 A7
DQU1 MDA17 CMDA7 R3 A8 DQU2 MDA27 CMD11 A1 A1
C8 C2
CMDA7 R3 A8
DQU2 MDA21 CMDA21 L7 A9 DQU3 MDA29
CMDA21 C2 A7
L7 A9
DQU3 MDA18 R7 A10/AP DQU4 MDA25 CMD12 BA0 BA0
OPT@
RV105 CMDA6 A7 CMDA6 N7 A11 A2

R7 A10/AP MDA23 DQU5 MDA30
1.33K_0402_1% CMDA29 N7 DQU4 A2 CMDA29 T3 A12 B8
A11
CMDA23 T3 A12 DQU5 B8
MDA19 CMDA23 T7 A13 DQU6 A3
MDA24 CMD13 WE* WE*
MDA22 Group2 MDA28 Group3
CMDA28 T7 A13 DQU6 A3 CMDA28 M7 A14 DQU7
CMDA20 M7 A14 DQU7 MDA16 CMDA20 A15/BA3 MDA26 CMD14 A15 A15
A15/BA3 MDA20 CMDA4 MDA31
CMDA4
CMDA14 +1.5VSDGPU CMDA14 +1.5VSDGPU CMD15 CAS* CAS*
M2 B2
+MEM_VREF0 BA0 VDD
M2 VDD
B2 N8
M3 BA1 VDD
D9
G7
CMD16 CS0_H#
1 BA0
0.1U_0402_16V4Z
N8 D9 CMDA12 BA2 VDD

C CMDA12 M3 BA1 VDD G7 K2 C
CMDA27 BA2 VDD CMDA27 VDD CMD17
OPT@
RV106 K2 K8
1.33K_0402_1% CMDA26 VDD CMDA26 VDD
OPT@
K8 N1
2 VDD N1 VDD N9 CMD18 ODT_H
CV109
VDD N9 J7 VDD R1
J7 VDD K7 CK VDD CMD19 CKE_H
CK R1 CK R9
K7 VDD R9 K9 VDD
CLKA0 CK VDD CLKA0 CKE/CKE0 CMD20 A13 A13
K9 CLKA0#
CLKA0# CKE/CKE0
CMDA3 +1.5VSDGPU CMDA3 K1 +1.5VSDGPU
ODT/ODT0 VDDQ
A1 CMD21 A8 A8
K1 A1 A8
+1.5VSDGPU ODT/ODT0 VDDQ L2 VDDQ
CMDA2 L2 VDDQ
A8 CMDA2 J3 CS/CS0
VDDQ
C1 CMD22 A6 A6
J3 CS/CS0 C1 CMDA0 K3 RAS C9
CMDA0 VDDQ VDDQ D2
RAS C9 CMDA30 CAS VDDQ CMD23 A11 A11
OPT@
RV107 CMDA30 K3 VDDQ D2 L3

1.33K_0402_1% L3 CAS VDDQ CMDA15 WE E9
CMDA15 VDDQ
CMDA13 WE
VDDQ
E9 CMDA13 VDDQ
F1 CMD24 A5 A5
F1 F3 H2
VDDQ H2 DQSL VDDQ
F3
DQSL 310mA VDDQ
C7
DQSU VDDQ
H9 CMD25 A3 A3
DQSA1 C7 H9 310mA
DQSU VDDQ DQSA0
DQSA2
DQSA3
CMD26 BA2 BA2
E7 A9
+MEM_VREF1 E7 DML VSS CMD27 BA1 BA1
A9 D3 B3
1 DML VSS DMU VSS
0.1U_0402_16V4Z
DQMA1 D3 B3 E1
OPT@
RV108 DMU VSS DQMA0 VSS

1.33K_0402_1%
DQMA2 E1
DQMA3 VSS
G8 CMD28 A12 A12
VSS G8 G3 J2
OPT@
VSS J2 DQSL VSS J8

2 G3
DQSL VSS B7 VSS CMD29 A10 A10
CV110
DQSA#1 J8 DQSU M1
B7 VSS M1 DQSA#0 VSS
DQSA#2 DQSU M9 CMD30 RAS* RAS*
VSS M9 DQSA#3 VSS P1
VSS P1 VSS
T2 P9 Not Available
VSS P9 VSS
T2 RESET T1
RESET VSS T1 VSS
L8 T9 LOW HIGH
CMDA5 VSS T9 CMDA5 VSS
L8 ZQ/ZQ0
B ZQ/ZQ0 VSS B
1 2
1
ZQ0 ZQ1 RV112 1 OPT@ 2 10K_0402_5%

RV109 B1
1
J1
OPT@ 1
OPT@
CLKA0 @ J1 B1 NC/ODT1 VSSQ B9

<14> CLKA0 L1 RV115 1 OPT@ 2 10K_0402_5%
OPT@
80.6_0402_1% RV110 L1 NC/ODT1 VSSQ B9 NC/CS1 VSSQ
243_0402_1% VSSQ RV111 J9 D1 CMDA2 RV113 1 OPT@2 10K_0402_5%
1 OPT@ 2 10K_0402_5%
RV15 J9 NC/CS1 L9 NC/CE1 VSSQ RV116
D1 243_0402_1% NCZQ1 D8 Command Bit Default Pull-down
160_0402_1% L9 NC/CE1 VSSQ D8 VSSQ CMDA3
E2
2
NCZQ1 VSSQ VSSQ CMDA5 RV117 1 OPT@ 2 10K_0402_5% ODTx 10k

E2
2
E8
2
VSSQ E8 VSSQ CMDA18

F9 CMDA19 CKEx 10k
1 2 VSSQ F9 VSSQ DDR3
G1
RV118 VSSQ G1 VSSQ RST 10k
<14> CLKA0# CLKA0# G9
@ VSSQ G9 VSSQ
80.6_0402_1% VSSQ CS* No Termination
1
@ 96-BALL
CV111 96-BALL SDRAM DDR3
0.01U_0402_16V7K SDRAM DDR3 K4B1G1646E-HC12_FBGA96
2 K4B1G1646E-HC12_FBGA96
NV recommand 0720
+1.5VSDGPU
+1.5VSDGPU
close to UV3 close to UV4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
OPT@ CV125
OPT@ CV124
OPT@ CV130
1U_0402_6.3V6K
1
OPT@ CV134
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
1
0.1U_0402_16V4Z
CV138
OPT@ CV119
OPT@ CV112
CV137
OPT@ CV118
1U_0402_6.3V6K
1U_0402_6.3V6K
CV136
CV135
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
1U_0402_6.3V6K
1
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
CV114
CV121
CV129
CV120
1U_0402_6.3V6K
CV115
CV116
OPT@ CV113
CV128
CV127
CV126
1
1U_0402_6.3V6K
1U_0402_6.3V6K
OPT@
1U_0402_6.3V6K
OPT@
OPT@
OPT@
2 2
CV123
CV117
CV122
2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2
OPT@
2 2
OPT@
OPT@
OPT@
2
A A

5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB) Mode D
Address 0..31 32..63
64Mx16 DDR3 *8==>1GB CMD0 CS0_L#
UV5 X76@ CMD1
D
128Mx16 DDR3 *8==>2GB M8 E3
UV6 X76@
D
H1 VREFCA DQL0 M8
CMD2 ODT_L
VREFDQ F7 VREFCA E3
DQL1 H1 DQL0 MDA45
F2 MDA39 VREFDQ F7 CMD3 CKE
+MEM_VREF2 N3 DQL2 F8 +MEM_VREF3 DQL1 MDA40
P7 A0 MDA35 F2
DQL3 H3 N3 DQL2 MDA46
<14,18> DQMA[7..0]
DQMA[7..0]
A1 DQL4 MDA37
P7 A0 DQL3
F8
MDA41
CMD4 A14 A14
P3 H8 MDA33 A1 H3
CMDA9 A2 DQL5 CMDA9 DQL4
<14,18> CMDA[30..0] N2 G2 MDA38 P3 H8 MDA47 CMD5 RST RST
CMDA[30..0] CMDA11 A3 DQL6 H7 Group4 CMDA11 A2 DQL5 MDA43 Group5
P8 MDA32 CMDA8 N2 G2
CMDA8 A4 DQL7 A3 DQL6 MDA44
<14,18> DQSA#[7..0]
DQSA#[7..0] CMDA25
P2
A5
MDA36 CMDA25 P8
DQL7
H7 CMD6 A9 A9
R8 MDA34 P2 A4 MDA42
CMDA10 A6 D7 CMDA10 A5
<14,18> DQSA[7..0]
DQSA[7..0] CMDA24
R2
A7
DQU0 C3 CMDA24 R8 D7 CMD7 A7 A7
T8 DQU1 R2 A6 DQU0
CMDA22 A8 C8 CMDA22 A7 C3
<14,18> MDA[63..0] R3 DQU2 MDA61 CMDA7 T8 DQU1 MDA53 CMD8 A2 A2
MDA[63..0] CMDA7 A9 C2 MDA59 A8 C8
L7 DQU3 CMDA21 R3 DQU2 MDA49
CMDA21 A10/AP A7 A9 C2
CMDA6
R7
N7 A11
DQU4 A2
MDA60
CMDA6 L7
A10/AP
DQU3 A7
MDA55 CMD9 A0 A0
A12 DQU5 MDA57 R7 DQU4 MDA50
CMDA29 T3 B8 CMDA29 N7 A11 A2
A13 DQU6 MDA63 CMDA23 A12 DQU5 MDA52 CMD10 A4 A4
CMDA23 T7 A3 MDA56 Group7 T3 B8 Group6
M7 A14 DQU7 CMDA28 A13 DQU6 MDA48
+1.5VSDGPU CMDA28 T7 A3
CMDA20
A15/BA3 MDA62 CMDA20 M7 A14 DQU7 MDA54 CMD11 A1 A1
MDA58 CMDA4 A15/BA3 MDA51
CMDA4
CMD12 BA0 BA0
OPT@
RV119 +1.5VSDGPU CMDA14 +1.5VSDGPU

CMDA14 B2
1.33K_0402_1% M2 VDD
N8 BA0 D9 M2 B2 CMD13 WE* WE*
M3 BA1 VDD G7 BA0 VDD
BA2 VDD CMDA12 N8 D9
CMDA12 K2 M3 BA1 VDD G7
CMDA27 VDD K8 CMDA27 BA2 VDD K2
CMD14 A15 A15
CMDA26 VDD N1 CMDA26 VDD K8
VDD N9 VDD N1
CMD15 CAS* CAS*
+MEM_VREF2 J7 VDD R1 VDD N9
K7 CK VDD J7 VDD CMD16 CS0_H#
OPT@
RV120 1 R9 R1
0.1U_0402_16V4Z
K9 CK VDD K7 CK VDD
1.33K_0402_1% CLKA1 CLKA1 R9
CKE/CKE0
CLKA1# K9 CK VDD CMD17
CLKA1# CKE/CKE0
OPT@
C CMDA19 K1 +1.5VSDGPU CMDA19 +1.5VSDGPU C

2 ODT/ODT0 A1 CMD18 ODT_H
CV131
VDDQ A8 K1 A1
L2 VDDQ ODT/ODT0 VDDQ
CMDA18 J3 CS/CS0
VDDQ
C1 CMDA18 L2 VDDQ
A8 CMD19 CKE_H
CMDA16 K3 RAS C9 CMDA16 J3 CS/CS0 C1
VDDQ D2 VDDQ
CMDA30 L3 CAS VDDQ CMDA30 K3 RAS
VDDQ
C9
D2
CMD20 A13 A13
CMDA15 WE E9 CMDA15 L3 CAS VDDQ
VDDQ F1 WE E9 CMD21 A8 A8
CMDA13 VDDQ CMDA13 VDDQ
F3 H2 F1
+1.5VSDGPU C7 DQSL
DQSU
310mA VDDQ
VDDQ
H9 F3
DQSL
310mA VDDQ
VDDQ
H2 CMD22 A6 A6
DQSA4 DQSA5 C7 H9
DQSU VDDQ
DQSA7 DQSA6 CMD23 A11 A11
E7 A9
D3 DML VSS E7 CMD24 A5 A5
B3 A9
OPT@
RV121 DMU VSS DQMA5 DML VSS B3

DQMA4 E1 D3
1.33K_0402_1% DQMA7 VSS G8 DMU VSS E1 CMD25 A3 A3
VSS DQMA6
G3 J2 VSS G8
DQSL VSS J8 VSS J2
B7 VSS G3
DQSL VSS J8
CMD26 BA2 BA2
1 DQSU M1 DQSA#5
0.1U_0402_16V4Z
+MEM_VREF3 DQSA#4 VSS B7 VSS M1

DQSA#7 M9 DQSA#6 DQSU CMD27 BA1 BA1
VSS VSS M9
OPT@
RV122 P1
1.33K_0402_1% VSS VSS P1
OPT@
T2 P9 CMD28 A12 A12

2 VSS T1 VSS P9
RESET
CV132
VSS T2 VSS T1
T9 RESET CMD29 A10 A10
CMDA5 L8 VSS CMDA5 VSS T9
ZQ/ZQ0 L8 VSS
1
ZQ/ZQ0 CMD30 RAS* RAS*

ZQ2 ZQ3
B1
1
J1
OPT@
RV123 NC/ODT1 VSSQ B9 B1 Not Available

L1 J1
OPT@
243_0402_1% NC/CS1 VSSQ RV124 NC/ODT1 VSSQ
J9 D1 L1 B9
243_0402_1% VSSQ
L9 NC/CE1 VSSQ D8 J9 NC/CS1
D1 LOW HIGH
2
1 2 NCZQ1 VSSQ L9 NC/CE1 VSSQ

E2 D8
OPT@ 1
RV125 VSSQ NCZQ1 VSSQ E2
2
<14> CLKA1 CLKA1 E8
@ VSSQ VSSQ E8
F9 B
B RV16 80.6_0402_1% VSSQ VSSQ F9
G1
160_0402_1% VSSQ VSSQ G1
G9
VSSQ VSSQ G9
2
1 2 VSSQ
RV127 96-BALL
@ SDRAM DDR3 96-BALL
<14> CLKA1# CLKA1# SDRAM DDR3
80.6_0402_1% 1 K4B1G1646E-HC12_FBGA96
@ K4B1G1646E-HC12_FBGA96
CV133
0.01U_0402_16V7K
2
NV recommand 0720
+1.5VSDGPU
+1.5VSDGPU
close to UV6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
close to UV5 OPT@ CV160
OPT@ CV159
OPT@ CV165
1 1
OPT@ CV151
1U_0402_6.3V6K
1
0.1U_0402_16V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1U_0402_6.3V6K
0.1U_0402_16V4Z
OPT@ CV139
CV158
CV157
CV156
CV152
1U_0402_6.3V6K
OPT@ CV145
1U_0402_6.3V6K
CV164
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
OPT@ CV144
CV163
CV140
0.1U_0402_16V4Z
CV162
CV149
CV148
CV147
1
CV146
1U_0402_6.3V6K
OPT@ CV150
1 CV161
1U_0402_6.3V6K
1U_0402_6.3V6K
OPT@
CV143
OPT@
OPT@
OPT@
OPT@
2 2
CV142
2
CV141
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2
OPT@
2
OPT@
OPT@
A A

5 4 3 2 1
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ Mode D
Address 0..31 32..63
VRAM DDR3 chips (1GB) CMD0 CS0_L#
CMD1
64Mx16 DDR3 *8==>1GB CMD2 ODT_L
D CMD3 CKE D
128Mx16 DDR3 *8==>2GB
CMD4 A14 A14
<14,21> DQSC[7..0] UV8 X76@ CMD5 RST RST
DQSC[7..0] UV7 X76@ M8
H1 VREFCA E3
<14,21> DQSC#[7..0]
DQSC#[7..0] M8 VREFDQ DQL0 F7 CMD6 A9 A9
H1 VREFCA E3 DQL1
VREFDQ DQL0 F7 MDC8 swap 0329 F2
<14,21> DQMC[7..0]
DQMC[7..0] +MEM_VREF4 DQL1 MDC12 +MEM_VREF5
N3
A0
DQL2 F8
MDC3 CMD7 A7 A7
F2 P7 DQL3 MDC7
N3 DQL2 F8 MDC11 A1 H3
<14,21> MDC[63..0]
MDC[63..0] P7 A0 DQL3 MDC13 P3
DQL4 H8
MDC1 CMD8 A2 A2
A1 H3 CMDC9 DQL5 MDC4
CMDC9 DQL4 MDC9 N2 A2 G2
<14,21> CMDC[30..0] P3 H8 CMDC11 DQL6 MDC2 CMD9 A0 A0
CMDC[30..0] CMDC11 A2 DQL5 P8 A3 H7
N2 G2 MDC14 Group1 CMDC8 DQL7 MDC6 Group0
CMDC8 A3 DQL6 P2 A4
P8 H7 MDC10 MDC0 CMD10 A4 A4
CMDC25 A4 DQL7 CMDC25 A5
P2 MDC15 R8 D7 MDC5
CMDC10 A5 CMDC10 A6
R8 R2 DQU0 CMD11 A1 A1
D7 CMDC24 A7 C3
CMDC24 R2 A6 DQU0 T8 DQU1
C3 CMDC22 A8 C8
+1.5VSDGPU CMDC22 A7 MDC18 R3 DQU2
CMDC7
T8
A8
DQU1 C8 CMDC7 L7 A9 C2 MDC26 CMD12 BA0 BA0
R3 DQU2 MDC20 DQU3 A7 MDC31
CMDC21 A9 C2 CMDC21 R7 A10/AP
L7 DQU3 MDC17 CMDC6 N7 DQU4 A2 MDC25 CMD13 WE* WE*
CMDC6 A10/AP A7 A11
R7 MDC22 A12 DQU5 B8 MDC30
OPT@
RV128 DQU4 A2 CMDC29 T3

CMDC29 N7 A11 MDC16 A13 DQU6
1.33K_0402_1%
CMDC23 T3 A12 DQU5 B8 CMDC23 T7 A3 MDC27 CMD14 A15 A15
A13 DQU6 MDC23 Group2 M7 A14 DQU7 MDC28 Group3
CMDC28 T7 A3 CMDC28
A14 DQU7 MDC19 A15/BA3 MDC24 CMD15 CAS* CAS*
CMDC20 M7 CMDC20
A15/BA3 MDC21 CMDC4 MDC29
CMDC4
1 CMDC14 CMD16 CS0_H#
0.1U_0402_16V4Z
CMDC14 +1.5VSDGPU M2 B2 +1.5VSDGPU

BA0 VDD D9
+MEM_VREF4 M2 B2 N8 CMD17
VDD M3 BA1 VDD G7
BA0 D9 BA2
OPT@
VDD
OPT@
RV129 CMDC12 N8
M3 CMDC12 K2
2 BA1 VDD G7
1.33K_0402_1% BA2 VDD CMD18 ODT_H
CV153
CMDC27 VDD K2 CMDC27 K8

VDD CMDC26 VDD N1
C CMDC26 K8 C
VDD N1
VDD N9 CMD19 CKE_H
VDD J7 VDD R1
N9 CK
J7 VDD R1
K7
CK
VDD R9 CMD20 A13 A13
K7 CK VDD K9 VDD
CLKC0 CK R9 CLKC0 CKE/CKE0
K9 VDD
CLKC0#
CMD21 A8 A8
CLKC0# CKE/CKE0
CMDC3 +1.5VSDGPU CMDC3 K1 A1 +1.5VSDGPU
K1
ODT/ODT0 VDDQ CMD22 A6 A6
A1 L2 A8
ODT/ODT0 VDDQ CS/CS0 VDDQ
L2 A8 CMDC2 J3 C1 CMD23 A11 A11
CMDC2
CS/CS0 VDDQ RAS VDDQ C9
J3 C1 CMDC0 K3 D2
CMDC0 VDDQ CAS VDDQ
CMDC30 K3 RAS
VDDQ
C9
D2 CMDC30 L3 VDDQ CMD24 A5 A5
CAS VDDQ CMDC15 WE E9
+1.5VSDGPU CMDC15 L3 VDDQ F1
CMDC13
WE
VDDQ
E9 CMDC13 VDDQ H2
CMD25 A3 A3
F1 F3
VDDQ C7 DQSL VDDQ H9
F3 310mA H2 CMD26 BA2 BA2
OPT@
RV130 DQSL VDDQ DQSU VDDQ

DQSC1 C7 H9 310mA
1.33K_0402_1% DQSU VDDQ DQSC0
DQSC2
DQSC3
CMD27 BA1 BA1
E7 A9
D3 DML VSS
E7
DML
A9 DMU VSS
B3 CMD28 A12 A12
DQMC1 D3 VSS B3 E1
DMU VSS DQMC0 VSS G8
DQMC2 E1
DQMC3 VSS CMD29 A10 A10
VSS G8 G3 J2
+MEM_VREF5 VSS J2 DQSL VSS J8
G3 B7 VSS CMD30 RAS* RAS*
OPT@
RV131 DQSL VSS J8 M1

1 DQSU
0.1U_0402_16V4Z
1.33K_0402_1% DQSC#1 B7 VSS VSS

DQSU M1 DQSC#0 M9
DQSC#2 VSS VSS Not Available
M9 DQSC#3 P1
VSS VSS
OPT@
P1 P9
2 VSS P9
T2
RESET VSS T1
LOW HIGH
CV154
T2 VSS VSS
RESET T1 L8 T9
CMDC5 VSS T9 CMDC5 ZQ/ZQ0 VSS
L8
1
ZQ/ZQ0 VSS
ZQ4 ZQ5
J1 B1
1
OPT@
B RV151 B1 NC/ODT1 VSSQ B9 RV134 1 OPT@ 2 10K_0402_5% B

J1 L1
243_0402_1% NC/ODT1 VSSQ B9 NC/CS1 VSSQ RV135 1 OPT@ 2 10K_0402_5%
L1 J9 D1
OPT@
NC/CS1 VSSQ RV133 L9 NC/CE1 VSSQ
J9 D8
2
D1 243_0402_1% NCZQ1 CMDC2 RV136 1 OPT@ 2 10K_0402_5% Command Bit Default Pull-down
L9 NC/CE1 VSSQ D8 VSSQ E2
NCZQ1 VSSQ VSSQ CMDC3
E2 E8 ODTx 10k
2
VSSQ VSSQ CMDC5 RV137 OPT@ 2 2 10K_0402_5%
RV1381 1OPT@ 10K_0402_5%
E8 F9 CMDC18
VSSQ VSSQ DDR3 CKEx 10k
F9 G1 CMDC19
VSSQ G1 VSSQ G9 RST 10k
1 2 VSSQ G9 VSSQ
RV139 VSSQ CS* No Termination
1
<14> CLKC0 CLKC0 @ 96-BALL

80.6_0402_1% 96-BALL SDRAM DDR3
SDRAM DDR3 K4B1G1646E-HC12_FBGA96
2OPT@
RV17
160_0402_1% K4B1G1646E-HC12_FBGA96
1 2
RV141
@
<14> CLKC0# CLKC0# +1.5VSDGPU +1.5VSDGPU
80.6_0402_1%
1
@ close to UV7 close to UV8
0.1U_0402_16V4Z
0.1U_0402_16V4Z
CV155
OPT@ CV172
OPT@ CV171
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
0.1U_0402_16V4Z
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
0.01U_0402_16V7K 1U_0402_6.3V6K
OPT@ CV180
OPT@ CV187
OPT@ CV186
OPT@ CV166
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
CV190
1
1U_0402_6.3V6K
CV189
1
CV170
1U_0402_6.3V6K
1
1U_0402_6.3V6K
0.1U_0402_16V4Z
1U_0402_6.3V6K
2
OPT@ CV192
CV188
CV169
CV168
OPT@ CV181
1U_0402_6.3V6K
1U_0402_6.3V6K
CV167
1U_0402_6.3V6K
CV179
1U_0402_6.3V6K
1U_0402_6.3V6K
CV185
1U_0402_6.3V6K
1U_0402_6.3V6K
1
CV184
CV178
CV183
CV174
CV182
CV173
CV191
OPT@
OPT@
OPT@
2 2
OPT@
OPT@
NV recommand 0720
OPT@
OPT@
OPT@
OPT@
2 2 2 2
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2
A A

5 4 3 2 1
5 4 3 2 1
VRAM DDR3 chips (1GB)
64Mx16 DDR3 *8==>1GB
D 128Mx16 DDR3 *8==>2GB D
<14,20> DQMC[7..0]
DQMC[7..0]
<14,20> CMDC[30..0]
UV10 X76@
CMDC[30..0] M8 Mode D
H1 VREFCA E3 UV9 X76@
<14,20> DQSC#[7..0]
DQSC#[7..0] VREFDQ DQL0 F7 M8
Address 0..31 32..63
DQL1 F2 H1 VREFCA E3
N3 DQL2 MDC39 VREFDQ DQL0 F7 MDC63 CMD0 CS0_L#
<14,20> DQSC[7..0] F8
DQSC[7..0] +MEM_VREF6 P7 A0 DQL3 MDC33 +MEM_VREF7 DQL1 MDC58
H3 F2
A1 DQL4 MDC38 N3 DQL2 F8 MDC62 CMD1
<14,20> MDC[63..0] P3 H8 A0
MDC[63..0] DQL5 MDC32 P7 DQL3 MDC59
CMDC9 A2 G2 CMDC9 A1 H3
N2 MDC36 DQL4 MDC60 CMD2 ODT_L
CMDC11 A3 DQL6 H7 CMDC11 P3 H8
P8 MDC34 Group4 A2 DQL5 MDC61 Group7
CMDC8 A4 DQL7 CMDC8 N2 G2
P2 MDC37 A3 DQL6 MDC57 CMD3 CKE
CMDC25 A5 CMDC25 P8 H7
R8 D7 MDC35 A4 DQL7 MDC56
CMDC10 R2 A6 DQU0 CMDC10 P2
CMDC24 T8 A7 C3 CMDC24 R8 A5
D7
CMD4 A14 A14
DQU1 C8 A6
+1.5VSDGPU CMDC22 R3 A8 CMDC22 R2 DQU0
DQU2 C2 MDC44 A7 C3 MDC54 CMD5 RST RST
CMDC7 L7 A9 CMDC7 T8 DQU1
DQU3 A7 MDC43 A8 C8 MDC48
CMDC21 R7 A10/AP CMDC21 R3 DQU2
DQU4 A2 MDC47 A9 C2 MDC52 CMD6 A9 A9
CMDC6 N7 A11 CMDC6 L7 DQU3
T3 A12 DQU5 B8 MDC40 A10/AP A7 MDC50
CMDC29 R7 DQU4
OPT@
RV142 CMDC29 A13 DQU6 N7 A2 MDC53

1.33K_0402_1% CMDC23
T7 A3 MDC45 CMDC23 T3
A11
A12 DQU5 CMD7 A7 A7
M7 A14 DQU7 MDC42 Group5 B8 MDC51 Group6
CMDC28 CMDC28 T7 A13 DQU6
A15/BA3 MDC46 A3 MDC55 CMD8 A2 A2
CMDC20 CMDC20 M7 A14 DQU7
MDC41 A15/BA3 MDC49
CMDC4 CMDC4
CMDC14 B2 +1.5VSDGPU CMDC14 +1.5VSDGPU CMD9 A0 A0
M2 VDD
1 BA0
0.1U_0402_16V4Z
+MEM_VREF6 N8 D9 CMD10 A4 A4
M3 BA1 VDD G7 M2 B2
BA2 VDD BA0 VDD D9
K2 CMDC12 N8
OPT@
RV143 CMDC12 M3 BA1 VDD

VDD G7 CMD11 A1 A1
OPT@
1.33K_0402_1% CMDC27 K8 CMDC27 BA2 VDD

2 VDD N1 K2
CV175
C CMDC26 CMDC26 VDD C

VDD N9 K8 CMD12 BA0 BA0
VDD VDD N1
J7 R1 VDD
CK N9
K7
CK
VDD R9 J7 VDD CMD13 WE* WE*
K9 VDD CK R1
CLKC1 CKE/CKE0 CLKC1 K7 VDD R9
CLKC1# K9 CK VDD CMD14 A15 A15
CLKC1# CKE/CKE0
CMDC19 K1 A1 +1.5VSDGPU CMDC19 +1.5VSDGPU
ODT/ODT0 VDDQ CMD15 CAS* CAS*
L2 A8 K1 A1
CS/CS0 VDDQ C1 ODT/ODT0 VDDQ
CMDC18 J3 VDDQ CMDC18 L2 A8 CMD16 CS0_H#
+1.5VSDGPU K3 RAS C9 CS/CS0 VDDQ
CMDC16 VDDQ D2 CMDC16 J3 C1
L3 CAS VDDQ RAS VDDQ CMD17
CMDC30 CMDC30 K3 C9
WE E9 CAS VDDQ D2
CMDC15 VDDQ F1 CMDC15 L3 VDDQ
CMDC13 VDDQ CMDC13 WE E9 CMD18 ODT_H
OPT@
RV144 F3 H2 VDDQ
DQSL VDDQ F1
1.33K_0402_1% C7 H9 VDDQ CMD19 CKE_H
DQSU310mA VDDQ F3
DQSL
310mA VDDQ
H2
DQSC4 DQSC7 C7 H9
DQSU VDDQ CMD20 A13 A13
DQSC5 DQSC6
E7 A9
D3 DML VSS
DMU VSS
B3 E7 A9 CMD21 A8 A8
+MEM_VREF7
1 DML
0.1U_0402_16V4Z
DQMC4 E1 DQMC7 D3 VSS B3

VSS G8 DMU VSS E1 CMD22 A6 A6
DQMC5 VSS DQMC6
OPT@
RV145 G3 J2 VSS G8
DQSL VSS J8
OPT@
1.33K_0402_1% VSS J2 CMD23 A11 A11

2 B7 VSS M1 G3
VSS J8
CV176
DQSC#4 DQSU VSS DQSC#7 DQSL

M9 B7 VSS M1
DQSC#5 VSS P1 DQSC#6 DQSU VSS M9
CMD24 A5 A5
VSS P9 VSS P1
T2
RESET VSS T1 VSS P9
CMD25 A3 A3
VSS T9 T2 VSS T1
CMDC5
L8
ZQ/ZQ0 VSS CMDC5
RESET
VSS T9
CMD26 BA2 BA2
L8 VSS
ZQ/ZQ0 CMD27 BA1 BA1
1
ZQ6 ZQ7
J1 B1
1
B
L1 NC/ODT1 VSSQ B9 CMD28 A12 A12 B
J1 B1
OPT@
NC/CS1 VSSQ RV147 VSSQ
J9 D1 L1 NC/ODT1 B9
L9 NC/CE1 VSSQ 243_0402_1% VSSQ CMD29 A10 A10
OPT@
RV146 D8 J9 NC/CS1
1 2 NCZQ1 VSSQ D1
243_0402_1% E2 L9 NC/CE1 VSSQ
2
VSSQ NCZQ1 D8
RV148 E8 VSSQ E2 CMD30 RAS* RAS*
1
<14> CLKC1 CLKC1

2
@ VSSQ F9 VSSQ
VSSQ E8
80.6_0402_1% G1 VSSQ F9 Not Available
VSSQ
2OPT@
RV18 G9 VSSQ
VSSQ G1
160_0402_1% VSSQ LOW HIGH
G9
VSSQ
1 2 96-BALL
RV150 SDRAM DDR3 96-BALL
<14> CLKC1# CLKC1# @ K4B1G1646E-HC12_FBGA96 SDRAM DDR3
1
80.6_0402_1% @ K4B1G1646E-HC12_FBGA96
CV177
0.01U_0402_16V7K
2
NV recommand 0720
+1.5VSDGPU +1.5VSDGPU
close to UV10 close to UV9
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
OPT@ CV227
OPT@ CV209
OPT@ CV216
OPT@ CV208
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
OPT@ CV214
1U_0402_6.3V6K
1
OPT@ CV222
CV212
CV220
1
1U_0402_6.3V6K
1
OPT@ CV193
OPT@ CV221
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1
CV211
CV219
CV218
CV210
CV217
CV226
CV225
CV207
CV224
CV196
CV223
CV195
CV194
CV213
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
OPT@
2 2 2 2 2 2 2 2
A A

5 4 3 2 1
5 4 3 2 1
+5VS
1
1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ @ @ 2
D58
+CRT_VCC_R
1 F3
+CRT_VCC
D29 D30 3 1
RB491D_SOT23-3 2 40mil
1
PESD5V0U2BT_SOT23-3 PESD5V0U2BT_SOT23-3 1.1A_6V_MINISMDC110F-2
C679
0.1U_0402_16V4Z
2
3
2
2
If=1A
D D
L18
1 2
PCH_CRT_R NBQ100505T-800Y_0402 CRT_R_L
<27> PCH_CRT_R
L19
<27> PCH_CRT_G PCH_CRT_G

1 2
NBQ100505T-800Y_0402 CRT_G_L CRT CONNECTOR
L20
2
2.2P_0402_50V8C
1
2.2P_0402_50V8C
JCRT
2.2P_0402_50V8C
2.2P_0402_50V8C
PCH_CRT_B NBQ100505T-800Y_0402 CRT_B_L 6
2.2P_0402_50V8C
<27> PCH_CRT_B RGND
2.2P_0402_50V8C
1 1 11
1 C683 1 T264 PAD ID0
1 1 CRT11 1
150_0402_1%
150_0402_1%
150_0402_1%
Red
1
C680
1
7
1
C682 C684 CRT_R_L
C681 C685 12 GGND
R672 R671 R670 2 2 2 2 SDA
2 2 2 CRT_DDC_DAT
8 Green
CRT_G_L
13 BGND
Hsync
2
2
2
HSYNC 3
CRT_B_L 9 Blue
40mil +5V
+CRT_VCC 14
VSYNC 4 Vsync
T265 PAD CRT12 10 res
15 SGND
5 SCL
CRT_DDC_CK
GND
16
+3VS +CRT_VCC 17 GND
C C
GND
SUYIN_070546FR015S293ZR
2
R678 CONN@
R677
4.7K_0402_5%
4.7K_0402_5%
1
1
2
Q157A
1 6
<27> PCH_CRT_DATA PCH_CRT_DATA CRT_DDC_DAT
2N7002DW-T/R7_SOT363-6
5
4 3 Q157B
<27> PCH_CRT_CLK PCH_CRT_CLK CRT_DDC_CK
1 1 1
1 2N7002DW-T/R7_SOT363-6
@ C850 @ C689 @ C690
33P_0402_50V8K @ C849 470P_0402_50V8J 470P_0402_50V8J
2 33P_0402_50V8K 2 2
2
B B
+CRT_VCC R1436 10K_0402_5%
1 2 2 1
C686
5
1
0.1U_0402_16V4Z
P
OE#
2 4 1 2
PCH_CRT_HSYNC A Y D_CRT_HSYNC L21 10_0402_5% HSYNC
<27> PCH_CRT_HSYNC
G
U38
SN74AHCT1G125GW_SOT353-5
3
1 2
+CRT_VCC
C851
0.1U_0402_16V4Z
5
1 P
OE#
PCH_CRT_VSYNC 2 4 D_CRT_VSYNC 1 2 VSYNC

<27> PCH_CRT_VSYNC A Y
L22 10_0402_5%
G
U39
10P_0402_50V8J
SN74AHCT1G125GW_SOT353-5
10P_0402_50V8J
3
1 1
@ C687
@ C688
2 2
A A

Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
B
5 4 3 2 1
5 4 3 2 1
+LCD_VDD +3VS +3VS
1
R1440
0_0402_5% R621
1 2 300_0603_5%
<27> PCH_BL_PWM LCD_BL_PWM
1 2
62
1
<41> INVT_PWM 0_0402_5% @ R1441
1
Vds=-20V
Q17A R627
C958
2N7002DW-T/R7_SOT363-6 2 100K_0402_5%
Id=-3A
2
D
2
180P_0402_50V8J C908 Rds=130m ohm D
3
Vgs=-4.5
S
0.1U_0402_16V7K
1
G
1 2 2 Vth=-1
Q18
1
3
R623 47K_0402_5% AO3413_SOT23
D
1
R103 short@ 2
Q17B C671
33_0402_5% 2 1 5
1 2 0.01U_0402_25V7K
R1379 +LCD_VDD
<41> BKOFF# BKOFF# BKOFF#_R <27> PCH_ENVDD 0_0402_5% 2N7002DW-T/R7_SOT363-6 1
4
1
W=60mils 1 L24 2
1
1 0_0805_5% +LCDVDD_R
R1421 @ C672 1 1
10K_0402_5% 4.7U_0805_10V4Z C673 C693 C678
2 0.1U_0402_16V4Z
2 4.7U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2
Close to JLVDS1
C C
LCD/PANEL BD. Conn. +LCD_INV

L23
B+
2 1
Must close JLVDS pin 28、30

+5VS 1.5A FBMA-L11-201209-221LMA30T_0805
PCH_EDID_CLK
+5VS PCH_EDID_DATA
W=30mils 1 1 1
R1428 0_0603_5% 1
1
2 1 DMIC_CLK 1 @ C319 @ C400

@ C692
100P_0402_50V8J
C760
TF@ 2 030@ 680P_0402_50V7K
68P_0402_50V8J 0.1U_0402_25V4K
100P_0402_50V8J
C758
R628 C909 2 2
DMIC_DATA 2
0.1U_0402_16V7K
100K_0402_5% 2
1 1 2
TF@ 3
S
C327 @ @ C328
2
1 G
TF@ 2 Q20
1 2CAMPWR_EN# AO3413_SOT23 220P_0402_25V8J
220P_0402_25V8J Rated Current MAX:3000mA
R624 47K_0402_5% D TF@ 2 2
1
2 @ 1
1
2 1 D Q61 R1401 DMIC_CLK

0_0402_5% DMIC_CLK <38>
R1403 TF@ 0_0402_5% 2 TF@ W=30mils
CAMPWR_EN 2N7002_SOT23-3 2 @ 1
<41> CAMPWR_EN G
1
S +LVDS_CAM C911 R1402 0_0402_5%

DMIC_DATA DMIC_DATA <38>
3
R1422 1 47P_0402_50V8J
C699
0.1U_0402_16V4Z
10K_0402_5% @ 1 2
DMIC_DATA_R
TF@ W=30mils +LVDS_CAM
2
2 DMIC_CLK_R
R1427 0_0603_5%
@ 2 1
JP4
B +3VS 1 2 B
3 1 2
4
5 3 4 6
USB20_P10_R 5 6 PCH_TXCLK+ PCH_TXCLK+ <27>
USB20_N10_R 7 8
7 8 PCH_TXCLK-
Add on 7/27 for fn+f5 turn off camera. PCH_TXOUT0+
9
11 9 10
10
12
PCH_EDID_CLK
PCH_TXCLK- <27>
<27> PCH_TXOUT0+ 13 11 12 14 PCH_EDID_CLK <27>

<27> PCH_TXOUT0- PCH_TXOUT0- 13 14 PCH_EDID_DATA1 2PCH_EDID_DATA <27>
15 16 R183
<27> PCH_TXOUT1+ PCH_TXOUT1+ 15 16 1K_0402_5%
17 18 CE_EN_R CE_EN
<27> PCH_TXOUT1- PCH_TXOUT1- 19 17 18 CE_EN <29>
20 LCD_BL_PWM
<27> PCH_TXOUT2+ PCH_TXOUT2+ 19 20 22
R6 0_0402_5% 21 BKOFF#_R
1 2 <27> PCH_TXOUT2- PCH_TXOUT2- 21 22 CE_EN: reserve for special panel,
23 24
L4 25 23 24 26 controlled by PCH--Joyce 0921-2011
DMIC_DATA_R 25 26 +LCDVDD_R
1 2 27 28
1 2 +LCD_INV 27 28 30
USB20_P10_R 29 1
<28> USB20_P10 +LCD_INV 29 30 +3VS
C691
0.1U_0402_16V4Z
1
@ 1
R1191
100K_0402_5%
+LCD_INV DMIC_CLK_R
C399
0.1U_0402_16V4Z
4 3 USB20_P10_R 31
4 3 32 GND1
<28> USB20_N10 USB20_N10_R USB20_N10_R GND2 2
WCM-2012-900T_0805 @
2
ACES_88242-3001
1 2
2
CONN@
2
R7 0_0402_5% @ D14
PJDLC05_SOT23-3
A A
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF Size
R&D Document Number Rev
B
5 4 3 2 1
5 4 3 2 1
HDMI Source Select 1 @ 2 R164

0_0402_5%
HOT PLUG1
HDMI_CK+ HDMI_R_CK+
WCM-2012-121T_0805
1
4 3 +3VS
4 3
R1568
1M_0402_5%
1 2
1 2
2
2N7002_SOT23-3
2
L91 2 R166 short@
@ Q16
0_0402_5% 1 3 1 2
VGA Video Chanel HDMI_CK- HDMI_R_CK- R438 0_0402_5%
S
HDMI_HPD
PCH_HDMI_HPD <27>
1 @ 2 R167
D DISO and OPT Channel D
2
0_0402_5% R573 2
100K_0402_5% C729
HDMI_D0+ HDMI_R_D0+
WCM-2012-121T_0805
4 3 0.1U_0402_16V4Z
2
4 3 1 C730
@
1
1 2 0.1U_0402_16V4Z
1 2 1
2 1
1
L10
0.1U_0402_16V7K C433 1 @ 2 R172
2 1 HDMI_CK+
<27> PCH_HDMI_TXC+ 0_0402_5%
0.1U_0402_16V7K C401 HDMI_D0- HDMI_R_D0-
HDMI_CK- BAV99_SOT23-3
<27> PCH_HDMI_TXC- D34
2 1
0.1U_0402_16V7K 2 HDMI_D0+
<27> PCH_HDMI_TX0+ 1C458
2
1 @ 2 R173
0.1U_0402_16V7K C392 HDMI_D0- 0_0402_5%
<27> PCH_HDMI_TX0- Internal Graphic Video Chanel HDMI_D1+ WCM-2012-121T_0805 HDMI_R_D1+
2 1 4 3
0.1U_0402_16V7K C402 HDMI_D1+ 4 3
<27> PCH_HDMI_TX1+ UMAO Channel
2 1 +HDMI_5V_OUT
HDMI_D1- 1 2
<27> PCH_HDMI_TX1- 0.1U_0402_16V7K 2 1C435 1 2
0.1U_0402_16V7K C457 HDMI_D2+ L11
<27> PCH_HDMI_TX2+ 2 1
0.1U_0402_16V7K C436 HDMI_D2-
<27> PCH_HDMI_TX2- 1 @ 2 R176
HDMI_D1- 0_0402_5% HDMI_R_D1-
@
1 2 R177
0_0402_5%
C HDMI_D2+ HDMI_R_D2+ C
WCM-2012-121T_0805
4 3
4 3
1 2
1 2
L12
1 @ 2 R178
HDMI_D2- 0_0402_5% HDMI_R_D2-
EVT mount chock, DVT mount resistor
HDMI Connector EDID SELECT +HDMI_5V_OUT

+3VS
if use VGA_HDMI,
1 2
1
R690~R697 should be 499ohm+/-1%.
1
B +5VS_HDMI B
R434 short@ 0_0402_5% R1328
1 2 R1329
40mil HDMI_R_CK+ 2.2K_0402_5% 2.2K_0402_5%
2
R690 680 +-5% 0402
1.1A_6V_MINISMDC110F-2
G
F2 HDMI_R_CK-
1 2
2
RB161M-20_SOD123-2 D53
2
2 1 R691 680 +-5% 0402
2 1 1 2 3 1
+5VS 1 +HDMI_5V_OUT HDMI_R_D1- R692 680 +-5% 0402 HDMI_R_CLK HDMI_SCLK
1 2
2
C250 BSH111_SOT23-3
SG
D
R693 680 +-5% 0402 Q182
HDMI_R_D1+ Q183 BSH111_SOT23-3
0.1U_0402_16V4Z
2 HDMI_R_D0- 1 2 3 1
R694 1 680
2 +-5% 0402 HDMI_SDATA
HDMI_R_DATA
HDMI_R_D0+ R695 680 +-5% 0402
D
JHDMI
1 2
HDMI_R_D2+ R696 680 +-5% 0402
19
HDMI_HPD 18 HP_DET 1 2
+HDMI_5V_OUT +5V HDMI_R_D2- R697 680 +-5% 0402
17
1
D
16 DDC/CEC_GND
HDMI_SDATA SDA 2 Q2
15 short@
HDMI_SCLK SCL +5VS G 2N7002_SOT23-3
14 1 2
13 Reserved S
3
CEC 1 2 HDMI_R_CLK R433 0_0402_5%

12 20 PCH_HDMI_CLK <27>
HDMI_R_CK- CK- GND R698 100K_0402_5% 1 2
11 21 HDMI_R_DATA R436 short@ 0_0402_5%
10 CK_shield GND 22 PCH_HDMI_DATA <27>
HDMI_R_CK+ CK+ GND
9 23 1
HDMI_R_D0- D0- GND
8
7 D0_shield
HDMI_R_D0+ D0+ C266
6 2 0.1U_0402_16V4Z
HDMI_R_D1- D1-
A 5 A
4 D1_shield
HDMI_R_D1+ D1+
HDMI_R_D2-
3
2 D2-
1 D2_shield
HDMI_R_D2+ D2+
LOTES_ABA-HDM-029-P01 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@
B
5 4 3 2 1
5 4 3 2 1
2 1 1 2
C204 18P_0402_50V8J R1300 1K_0402_5%
1
Integrated SUS 1.05V VRM Enable
PCH_RTCX1 W=20mils +RTCBATT
1
Y6 High - Enable Internal VRs Place near PCH D2
32.768KHZ_12.5PF +RTCVCC
PCH_INTVRMEN (must be always pulled high)
1
2 1 Y2 BAS40-04_SOT23-3
10M_0402_5%
NC OSC
3 4
R94
NC OSC +RTCVCC
2
2 1
R95 1 2
32.768KHZ_12.5PF_Q13MC14610002C205 15P_0402_50V8J
1M_0402_5% 1
2
@ R96 1 2 SM_INTRUDER#
PCH_RTCX2 330K_0402_5% W=20mils +CHGRTC
C363
PCH_INTVRMEN 0.1U_0402_16V4Z
RH37INTVRMEN:
@ 330K_0402_5%
check list Rev1.5 P63, P64 error 2
far away hot spot
PCH_INTVRMEN
D D
MP BOM: Y2-SJ100001K00, C204-18pF, C205-15pF.
another solution: Y2-SJ100004Z00, C204-15pF, C205-15pF. UPCH1A

this is tested OK by DQA, but not add into BOM. JCMOS & JME1 place near DIMM
2
@ A20 C38
+RTCVCC C206 RTCX1 FWH0 / LAD0 A38
CMOS
JCOMS FWH1 / LAD1
1U_0603_10V4Z PCH_RTCX1 C20 B37 LPC_AD0 LPC_AD0 <34,41,44>
LPC
SHORT PADS RTCX2 FWH2 / LAD2 LPC_AD1 LPC_AD1 <34,41,44>
1
1 2 C37
PCH_RTCX2 D20 FWH3 / LAD3 LPC_AD2 LPC_AD2 <34,41,44>
R97 20K_0402_5% RTCRST# D36 LPC_AD3 LPC_AD3 <34,41,44>
PCH_RTCRST# G22 FWH4 / LFRAME#
R98 20K_0402_5% SRTCRST# E36 LPC_FRAME# LPC_FRAME# <34,41,44>
PCH_SRTCRST# LDRQ0# K36
K22
RTC
2
@ INTRUDER# LDRQ1# / GPIO23 2 1
C207 JME1 V5 R99 10K_0402_5% +3VS
SM_INTRUDER# C17 SERIRQ
1U_0603_10V4Z SHORT PADS INTVRMEN
1
PCH_INTVRMEN SERIRQ <34,41,44>
ME CMOS AM3
SATA0RXN AM1
N34 SATA0RXP
HDA_BCLK AP7 SATA_PRX_C_DTX_N0 SATA_PRX_C_DTX_N0 <34>
SATA 6G
HDA_BIT_CLK SATA0TXN AP5 SATA_PRX_C_DTX_P0 SATA_PRX_C_DTX_P0 <34>
L34
HDA_SYNC SATA0TXP SATA_PTX_DRX_N0 SATA_PTX_DRX_N0 <34>
HDD
ME_EN from EC. R180 0_0402_5%
Please place close to RH29 aviod the branch. HDA_SYNC T10 AM10 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 <34>
SPKR SATA1RXN
<41> HDA_SDO HDA_SDOUT AM8
<38> PCH_SPKR SATA1RXP AP11
1 2 PCH_SPKR K34
HDA_RST# SATA1TXN AP10
<38> AZ_BITCLK_HD R101 33_0402_5%
HDA_BIT_CLK SATA1TXP
HDA_RST#
E34 AD7
HDA_SDIN0 SATA2RXN AD5
1 2 <38> AZ_SDIN0_HD SATA2RXP SATA_PRX_C_DTX_N2 SATA_PRX_C_DTX_N2 <34>
AZ_SDIN0_HD G34 AH5
<38> AZ_RST_HD# R106 33_0402_5%
HDA_RST# HDA_SDIN1 SATA2TXN AH4 SATA_PRX_C_DTX_P2 SATA_PRX_C_DTX_P2 <34>
1 2 SATA2TXP SATA_PTX_DRX_N2 SATA_PTX_DRX_N2 <34>
C34 ODD
<38> AZ_SDOUT_HD R108 33_0402_5%
HDA_SDOUT HDA_SDIN2 AB8 SATA_PTX_DRX_P2 SATA_PTX_DRX_P2 <34>
IHDA
SATA3RXN AB10
A34
HDA_SDIN3 SATA3RXP AF3
C SATA3TXN C
AF1
+3VS SATA3TXP
A36
HDA_SDO Y7
SATA
HDA_SDOUT SATA4RXN Y5
R1299 @ 1K_0402_5% SATA4RXP SATA_PRX_C_DTX_N4 SATA_PRX_C_DTX_N4 <43>
C36 AD3
PCH_SPKR HDA_DOCK_EN# / GPIO33 SATA4TXN SATA_PRX_C_DTX_P4 SATA_PRX_C_DTX_P4 <43>
AD1
SATA4TXP SATA_PTX_DRX_N4 SATA_PTX_DRX_N4 <43> E-Sata
N32 SATA_PTX_DRX_P4
HDA_DOCK_RST# / GPIO13 Y3 SATA_PTX_DRX_P4 <43>
LOW=Default SATA5RXN Y1
*HIGH=No Reboot
T1512 PAD
SATA5RXP
SATA5TXN
AB3
J3 AB1
JTAG_TCK SATA5TXP
T1513 PAD PCH_JTAG_TCK H7 Y11
JTAG_TMS SATAICOMPO
+1.05VS_VCC_SATA
HDA_SDO
JTAG
T1514 PAD PCH_JTAG_TMS K5 Y10
JTAG_TDI SATAICOMPI
T1515 PAD
ME debug mode , this signal has a weak internal PD PCH_JTAG_TDI H1 SATA_COMP R1202 37.4_0402_1%
JTAG_TDO AB12
PCH_JTAG_TDO SATA3RCOMPO
+1.05VS_SATA3
L=>security measures defined in the Flash AB13
SATA3COMPI 1 2
Descriptor will be in effect (default) SATA3_COMP RH42 49.9_0402_1%
H=>Flash Descriptor Security will be overridden T3 AH1
SPI_CLK SATA3RBIAS RH46 750_0402_1%
+3VALW_PCH <33> PCH_SPI_CLK PCH_SPI_CLK Y14 RBIAS_SATA3
SPI_CS0# +3VS
R182 @ 1K_0402_5% <33> PCH_SPI_CS# PCH_SPI_CS# T1
SPI_CS1#
P3
SPI
HDA_SDOUT <33> PCH_SPI_CS1# PCH_SPI_CS1# SATALED# R113 10K_0402_5%

V4 V14 SATA_LED# SATA_LED# <43>
SPI_MOSI SATA0GP / GPIO21 SATA_LED# R208 2 @ 1 4.7K_0402_5%
*Low = Disabled
High = Enabled <33> PCH_SPI_MOSI PCH_SPI_MOSI U3
SPI_MISO SATA1GP / GPIO19
P1 PCH_GPIO21
BBS_BIT0_R
<33> PCH_SPI_MISO PCH_SPI_MISO BBS_BIT0_R R205 10K_0402_5%
PANTHER-POINT_FCBGA989 PCH_GPIO21 @
@ 2 1
B B
+5VS +3VS SATA1GP/GPIO19: Integrated 20K pull up.
R207
2
10K_0402_5%
2
R189
0_0402_5% R190
@ 0_0402_5%
1
SATA0GP / GPIO21: Serial ATA 0 General Purpose. SATA1GP/GPIO19: Boot BIOS Strap bit 0 (BBS0)
This is an input pin which can be configured as an
2
G
Q10 GNT1#/GPIO51: Boot BIOS Strap bit 1 (BBS1)

BSS138_NL_SOT23-3 interlock switch corresponding to SATA Port 0.
＆＊
1 2 +3VALW +3VALW +3VALW
R145 33_0402_5% 3 1 When used as an interlock switch status indication,
HDA_SYNC
1
AZ_SYNC_HD_R this signal should be drive to 0 to indicate

1
<38> AZ_SYNC_HD
S
RH38 RH40
＆＊
1
RH39 XDP@ that

XDP@
XDP@ 200_0402_5% the switch is closed and to 1 to indicate that
GPIO19 => BBS_BIT0
200_0402_5%
200_0402_5%
the switch is open. GPIO51 => BBS_BIT1
If interlock switches are not required,
2
2
1 @ 2 Boot BIOS Strap

1 2
0_0402_5% R188 this pin can be configured as

1
1
PCH_JTAG_TDO
RH44 PCH_JTAG_TMS PCH_JTAG_TDI GPIO21.
RH45 Bit 11 Bit 10 Boot BIOS
1
R418 XDP@ XDP@ RH47

1M_0402_5% 100_0402_1% XDP@ (BBS1) (BBS0) Destination
100_0402_1%
100_0402_1% 0 1 Reserved
2
Intel recommend 1 0 PCI

2
1 1 SPI *
RH50 2 XDP@ 1 0 0 LPC
51_0402_5%
PCH_JTAG_TCK
HDA_SYNC
Intel DPDG Rev1.2 requirement. PCH EDS Rev1.5 P99, P98
This signal has a weak internal pull-down
A On Die PLL VR is supplied by A
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Chief River platfrom
+3VALW_PCH
R181 1K_0402_5%
HDA_SYNC
Custom B
5 4 3 2 1
5 4 3 2 R1207
1 1 2 10K_0402_5%
+3VALW_PCH
1 2
R1319 1K_0402_5%
R1320 1 2 10K_0402_5%
PCH_GPIO11
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ DRAMRST_CNTRL_PCH
PCH_HOT#
R1322 2 1 2.2K_0402_5%
UPCH1B R1222 2 1 2.2K_0402_5%
C385 1 2 0.1U_0402_16V7K BG34 E12 PCH_SMBCLK

BJ34 PERN1 SMBALERT# / GPIO11
C384 1 2 0.1U_0402_16V7K PERP1
<36> PCIE_PRX_C_WWANTX_N1 AV32 H14
PETN1 PCH_SMBDATA +3VALW_PCH
AU32 SMBCLK
D <36> PCIE_PRX_C_WWANTX_P1 PETP1 D
<36> PCIE_PTX_C_WWANRX_N1 PCIE_PTX_WWANRX_N1 C9 PCH_GPIO11
WWAN <36> PCIE_PTX_C_WWANRX_P1 PCIE_PTX_WWANRX_P1 BE34 SMBDATA
R1224 2 1 2.2K_0402_5%
BF34 PERN2
BB32 PERP2 PCH_SMBCLK
<36> PCIE_PRX_WLANTX_N2 PETN2 R1229 2 1 2.2K_0402_5%
C215 1 2 0.1U_0402_16V7K AY32 A12 PCH_SMBDATA
<36> PCIE_PRX_WLANTX_P2 PETP2 PCH_SMLCLK0
SML0ALERT# / GPIO60
SMBUS
C216 1 2 0.1U_0402_16V7K
WLAN <36> PCIE_PTX_C_WLANRX_N2
C391 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2 BG36 C8 PCH_SMLDATA0
<36> PCIE_PTX_C_WLANRX_P2 PERN3 SML0CLK RH92 1 2 10K_0402_5%
PCIE_PTX_WLANRX_P2 BJ36
C386 1 2 0.1U_0402_16V7K AV34 PERP3 DRAMRST_CNTRL_PCH <7,10>
<39> PCIE_PRX_C_EXPTX_N3 PETN3 G12
DRAMRST_CNTRL_PCH RH90 1 2 10K_0402_5%
AU34 SML0DATA
<39> PCIE_PRX_C_EXPTX_P3 PETP3 PCH_CLK_DMI#
PCH_SMLCLK0 <42> RH91 1 2 10K_0402_5%
<39> PCIE_PTX_C_EXPRX_N3 PCH_SMLCLK0 PCH_CLK_DMI
Express Card PCIE_PTX_EXPRX_N3 BF36 RH76
RH89RH771 11 2 2210K_0402_5%
10K_0402_5%
10K_0402_5%
<39> PCIE_PTX_C_EXPRX_P3 PCIE_PTX_EXPRX_P3 PERN4 PCH_SMLDATA0 <42>
BE36 C13PCH_SMLDATA0 CLKIN_DMI2#
AY34 PERP4 SML1ALERT# / PCHHOT# / GPIO74
PETN4 CLKIN_DMI2
BB34 E14 RH79
RH78 11 22 10K_0402_5%
10K_0402_5%
PETP4 SML1CLK / GPIO58 CLK_DOT#
BG37 M16PCH_HOT# PCH_HOT# <41> CLK_DOT
PCI-E*
PERN5 add port to EC--Joyce RH183 1 2 10K_0402_5%
BH37 SML1DATA / GPIO75
<37> PCIE_PRX_C_CARDTX_N5 AY36 PERP5
PETN5 PCH_SMLCLK1 CLK_SATA#
<37> PCIE_PRX_C_CARDTX_P5 2 0.1U_0402_16V7K BB36 CLK_SATA
C404 1 PETP5 To EC SM BUS 2
<37> PCIE_PTX_C_CARDRX_N5 C403 1 2 0.1U_0402_16V7K PCIE_PTX_CARDRX_N5 PCH_SMLDATA1
Card Reader <37> PCIE_PTX_C_CARDRX_P5 C217 1 2 0.1U_0402_16V7K PCIE_PTX_CARDRX_P5 BJ38 CLK_14M_PCH
BG38 PERN6
M7 +5VALW_PCH
AU36 PERP6 CL_CLK1
<35,42> PCIE_PRX_C_LANTX_N6
Controller
AV36 PETN6
1 2
If use extenal CLK gen, please place close to
<35,42> PCIE_PRX_C_LANTX_P6 R219 2.2K_0402_5%
PETP6
@
CLK gen, else, please place close to PCH
<35,42> PCIE_PTX_C_LANRX_N6 C218 1 2 0.1U_0402_16V7K PCIE_PTX_LANRX_N6 T11
LAN BG40 CL_DATA1 CL_CLK_DMC
Link
<35,42> PCIE_PTX_C_LANRX_P6 PCIE_PTX_LANRX_P6 PERN7 1 2 CL_CLK_DMC <36> @ C368
BJ40 R222 2.2K_0402_5% @ R265
PERP7 22P_0402_50V8J
AY40 @ 33_0402_5%
PETN7 P10 1 2
BB40 CL_RST1# CL_DATA_DMC 2 1
PETP7 R223 1 2 10K_0402_5%
CL_DATA_DMC <36>
@
C BE38 CLK_14M_PCH @ R269 @ C367 C
BC38 PERN8 CL_RST#_DMC 22P_0402_50V8J
PERP8 CL_RST#_DMC <36> 33_0402_5%
AW38 2 1 1 2
AY38 PETN8
PETP8 CLK_PCILOOP
+3VALW_PCH M10
PEG_A_CLKRQ# / GPIO47 R253 short@
1 @ 2 short@ Y40
R1213 1 2 0_0402_5% CLKOUT_PCIE0N 0_0402_5% 2 1 Reserve for EMI please close to UPCH1
R1523 10K_0402_5% Y39
1 2 R1214 1 2 0_0402_5% CLKOUT_PCIE0P AB37PEG_CLKREQ#_R 0_0402_5% 2 1 Q4A
R1521 10K_0402_5% <35,42> CLK_LAN# short@ CLK_R_LAN# J2 CLKOUT_PEG_A_N AB38 R254 short@ 2N7002DW T/R7_SOT-363-6
1 2 CLK_REQ_CARD# <35,42> CLK_LAN CLK_R_LAN PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P VGA +3VALW_PCH
CLOCKS
short@ CLK_PCIE_VGA# <13> 6 1
R1527 10K_0402_5% LAN R140 1 2 0_0402_5%
CLK_VGA#
PCH_GPIO46 <35,42> CLKREQ_LAN# CLKREQ_LAN# AV22CLK_VGA CLK_PCIE_VGA <13> R130
AB49 CLKOUT_DMI_N 2 1
AB47 CLKOUT_PCIE1N AU22
1 2 CLKOUT_DMI_P
2
CLKREQ_LAN# CLKOUT_PCIE1P PCH_SMLCLK1 EC_SMB_CK2 EC_SMB_CK2 <13,41>
1
R1531 2
10K_0402_5% <36> CLK_WLAN# R1212 1 2 0_0402_5% 2.2K_0402_5%
CLK_R_WLAN# M1 CLK_CPU_DMI# CLK_CPU_DMI# <6>
5
R1530 10K_0402_5% PEG_CLKREQ#_R <36> CLK_WLAN short@ CLK_R_WLAN PCIECLKRQ1# / GPIO18 AM12
CLK_CPU_DMI CLK_CPU_DMI
T13 PAD <6>
WLAN short@ CLKOUT_DP_N AM13 @ R1206 +3VS
1 2 CLKREQ_R_WWAN# <36> CLKREQ_WLAN# R1227 1 2 0_0402_5% CLKREQ_WLAN# CLKOUT_DP_P 2 3 4
R1228 1 2 0_0402_5% AA48 T14 PAD 1
R1522 10K_0402_5% CLKOUT_PCIE2N CLK_DP# @
PCH_GPIO44 short@ AA47 2N7002DW T/R7_SOT-363-6
CLKOUT_PCIE2P BF18CLK_DP 2.2K_0402_5%
1 2 Express
<39> Card
CLK_PCIE_EXPCARD# CLK_R_CARD# V10 CLKIN_DMI_N BE18
Q4B
R1529
2 10K_0402_5%
1 PCH_GPIO45 <39> CLK_PCIE_EXPCARD CLK_R_CARD PCIECLKRQ2# / GPIO20 CLKIN_DMI_P PCH_SMLDATA1 EC_SMB_DA2 EC_SMB_DA2 <13,41>
R1217 10K_0402_5% PCH_CLK_DMI#
PCH_GPIO56 <39> CLKREQ_EXPCARD# R260 1 2 0_0402_5% CLKREQ_EXPCARD#
short@ Y37 BJ30PCH_CLK_DMI
short@ CLKOUT_PCIE3N CLKIN_GND1_N
R264 1 2 0_0402_5% Y36 BG30
CLKOUT_PCIE3P CLKIN_GND1_P Q3A 1 2
<37> CLK_PCIE_READER# CLK_CARD# 2N7002DW T/R7_SOT-363-6
A8 CLKIN_DMI2# R1225 short@ 0_0402_5%
<37> CLK_PCIE_READER CLK_CARD PCIECLKRQ3# / GPIO25 1 6
1 2 G24 CLKIN_DMI2
Card Reader R144
R255 2 0_0402_5%
1 short@10K_0402_5% CLKIN_DOT_96N E24
CLK_REQ_CARD# CLKIN_DOT_96P <11,12,36,39> PM_SMBCLK PM_SMBCLK PCH_SMBCLK
Y43
Y45 CLKOUT_PCIE4N CLK_DOT# 2 1
2
B CLKOUT_PCIE4P AK7 CLK_DOT +3VS 4.7K_0402_5% R1208 B
R1220 1 2 0_0402_5%
5
+3VS <36> CLK_WWAN# CLK_R_WWAN# CLKIN_SATA_N
L12 AK5 +3VS
<36> CLK_WWAN R1226 1 short@ 2 0_0402_5% CLK_R_WWAN PCIECLKRQ4# / GPIO26 CLKIN_SATA_P 2 1
1 2 WWAN short@ CLK_SATA# 4.7K_0402_5% R1209 4 3 1 2
R1520 10K_0402_5%CLKREQ_WLAN# <36> CLKREQ_WWAN# CLKREQ_R_WWAN# R1223 short@ 0_0402_5%
V45 K45 CLK_SATA
V46 CLKOUT_PCIE5N REFCLK14IN 2N7002DW T/R7_SOT-363-6
CLKOUT_PCIE5P <11,12,36,39> PM_SMBDATA PM_SMBDATA Q3B PCH_SMBDATA
1 2 L14 H45 CLK_14M_PCH
R1532 10K_0402_5% PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK
CLKREQ_EXPCARD# PCH_GPIO44 CLK_PCILOOP <28>
AB42 V47 CLK_PCILOOP
AB40 CLKOUT_PEG_B_N XTAL25_IN V49
CLKOUT_PEG_B_P XTAL25_OUT
PCH_X1 PCH_X1
E6
PEG_B_CLKRQ# / GPIO56 PCH_X2 1 2 1M_0402_5%
Y3 R1216 PCH_X2
PCH_GPIO56 Y47
V40 XCLK_RCOMP R1221 90.9_0402_1%
V42 CLKOUT_PCIE6N 1 3
XCLK_RCOMP +1.05VS_VCCDIFFCLKN 1 3
CLKOUT_PCIE6P
+3VS GND GND
T13
10P_0402_50V8J
PCIECLKRQ6# / GPIO45
2 4 1
10P_0402_50V8J
RH108 @ 0_0402_5% PCH_GPIO45 V38 K43 C225
V37 CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 @
2
CLKOUT_PCIE7P T15 PAD 1 25MHZ_10PF_7V25000014
RH109 @ 0_0402_5%
FLEX CLOCKS
F47 R2571 2 0_0402_5% @ C869

CLKOUTFLEX1 / GPIO65 R1533 2
K12 UMA@
<8> CLK_RES_ITP# PCIECLKRQ7# / GPIO46 R2581 2 0_0402_5% 10K_0402_5%
H47
CLK_FLEX1
<8> CLK_RES_ITP AK14 CLKOUTFLEX2 / GPIO66 short@ 2
PCH_GPIO46 CLKOUT_ITPXDP_N
1
AK13 K49
22 0_0402_5% CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67 CLK_FLEX2 CLK_SIO_48M <44>
RN19311 OPT@
RN192 0_0402_5% CLK_BCLK_ITP#
@ DGPU_PWR_EN <28,45,57> CLK_BCLK_ITP DGPU_PRSNT#
2
PANTHER-POINT_FCBGA989
VGA_PWROK <29,45,57> OPT@ R1534
A @ A
10K_0402_5%
QN4
2
OPT@ Add RN192,RN193 5/12 T15, T16 reserve 27M_CLK and 27M_SSC for VGA.
G
1
SSM3K7002F_SC59-3 we have crystal at VGA side.
1 3 1 2
RN71 OPT@ 0_0402_5% FROM CLK GEN FOR: 133/100/96/14.318 MHZ
D
PEG_CLKREQ#_R Pull PEG_CLKREQ#

high @ VGA <13>
side Security Classification Compal Secret Data
1
1 2
RN72
RN188 @ 0_0402_5% RN73 Issued Date 2011/09/23 Deciphered Date 2012/12/31 Title Compal Electronics, Inc.
@
@
2.2K_0402_5% THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
for safe 2.2K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
2
Custom B
2
5 4 3 2 1
5 4 3 2 1
UPCH1C UPCH1D AP43

J47 SDVO_TVCLKINN AP45 +3VS
BC24 BJ14 M45 L_BKLTEN SDVO_TVCLKINP
DMI0RXN FDI_RXN0 AY14 L_VDD_EN
BE20 FDI_RXN1 Pull high at LVDS conn side. AM42
BG18 DMI1RXN BE14 P45 SDVO_STALLN
FDI_RXN2 AM40
1
DMI2RXN
1
<5> DMI_CTX_PRX_N0 BG20 BH13 FDI_CTX_PRX_N0 <5> PCH_ENBKL L_BKLTCTL SDVO_STALLP
DMI_CTX_PRX_N0 DMI3RXN FDI_RXN3 BC12 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 <5> <23> PCH_ENVDD
<5> DMI_CTX_PRX_N1 T40 AP39 R1334 R1335
DMI_CTX_PRX_N1 FDI_RXN4 BJ12 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 <5> L_DDC_CLK
<5> DMI_CTX_PRX_N2 BE24 K47 SDVO_INTN AP40 2.2K_0402_5% 2.2K_0402_5%
DMI_CTX_PRX_N2 DMI0RXP FDI_RXN5 BG10 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 <5> <23> PCH_BL_PWM L_DDC_DATA
<5> DMI_CTX_PRX_N3 BC20 FDI_CTX_PRX_N3 SDVO_INTP
DMI_CTX_PRX_N3 DMI1RXP FDI_RXN6 BG9 FDI_CTX_PRX_N4 <5>
BJ18 FDI_CTX_PRX_N4 <23> PCH_EDID_CLK T45
2
FDI_RXN7
2
<5> DMI_CTX_PRX_P0 BJ20 DMI2RXP FDI_CTX_PRX_N5 <5> PCH_EDID_CLK L_CTRL_CLK
FDI_CTX_PRX_N5 <23> PCH_EDID_DATA P39
<5> DMI_CTX_PRX_P1 DMI_CTX_PRX_P0 DMI3RXP BG14 FDI_CTX_PRX_N6 <5> PCH_EDID_DATA L_CTRL_DATA
DMI_CTX_PRX_P1 FDI_RXP0 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 <5> AF37 P38
<5> DMI_CTX_PRX_P2 AW24 BB14 SDVO_CTRLCLK
DMI0TXN FDI_RXP1 FDI_CTX_PRX_N7 AF36 LVD_IBG M39
D <5> DMI_CTX_PRX_P3 DMI_CTX_PRX_P2 AW20 BF14 CTRL_CLK SDVO_CTRLDATA D
DMI_CTX_PRX_P3 DMI1TXN FDI_RXP2 BG13 FDI_CTX_PRX_P0 <5> LVD_VBG
BB18 FDI_CTX_PRX_P0 2 1 CTRL_DATA
<5> DMI_CRX_PTX_N0 DMI2TXN FDI_RXP3 BE12 FDI_CTX_PRX_P1 <5>
AV18 FDI_CTX_PRX_P1 RH244 short@
2.37K_0402_1% AE48 PCH_HDMI_CLK <24>
DMI_CRX_PTX_N0 DMI3TXN FDI_RXP4 BG12 FDI_CTX_PRX_P2 <5> LVD_VREFH AT49
<5> DMI_CRX_PTX_N1 LVDS_IBG AE47
FDI
DMI
FDI_RXP5 FDI_CTX_PRX_P2 2 1 DDPB_AUXN AT47 PCH_HDMI_DATA <24>
<5> DMI_CRX_PTX_N2 DMI_CRX_PTX_N1 AY24 BJ10 FDI_CTX_PRX_P3 <5> LVD_VREFL 2 @ 1RH142
FDI_RXP6 FDI_CTX_PRX_P3 RH290 0_0402_5% DDPB_AUXP AT40
<5> DMI_CRX_PTX_N3 DMI_CRX_PTX_N2 AY20 DMI0TXP BH9 FDI_CTX_PRX_P4 <5> 100K_0402_5%
FDI_RXP7 FDI_CTX_PRX_P4 DDPB_HPD
DMI_CRX_PTX_N3 AY18 DMI1TXP FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 <5> AK39
<5> DMI_CRX_PTX_P0 AU18 DMI2TXP LVDSA_CLK# AV42
FDI_CTX_PRX_P6 AK40
LVDS
<5> DMI_CRX_PTX_P1 DMI_CRX_PTX_P0 DMI3TXP AW16 FDI_CTX_PRX_P7 <5> LVDSA_CLK DDPB_0N AV40
FDI_INT FDI_CTX_PRX_P7 DDPB_0P PCH_HDMI_HPD <24>
<5> DMI_CRX_PTX_P2 DMI_CRX_PTX_P1 PCH_HDMI_HPD
AV45
DMI_CRX_PTX_P2 <23> PCH_TXCLK- AN48
<5> DMI_CRX_PTX_P3 BJ24 AV12 PCH_TXCLK- LVDSA_DATA#0 DDPB_1N AV46
DMI_ZCOMP FDI_FSYNC0 FDI_INT <5> <23> PCH_TXCLK+ AM47 DDPB_1P PCH_HDMI_TX2- <24>
DMI_CRX_PTX_P3 FDI_INT PCH_TXCLK+ LVDSA_DATA#1 AU48 PCH_HDMI_TX2-
AK47 PCH_HDMI_TX2+ <24>
Digital Display Interface

+1.05VS_PCH BC10 LVDSA_DATA#2 DDPB_2N AU47 PCH_HDMI_TX2+
BG25 AJ48 PCH_HDMI_TX1- <24>
R1236 49.9_0402_1% DMI_IRCOMP FDI_FSYNC1 FDI_FSYNC0 <5> <23> PCH_TXOUT0- DDPB_2P
FDI_FSYNC0 <23> PCH_TXOUT1-
PCH_TXOUT0- LVDSA_DATA#3 AV47 PCH_HDMI_TX1- PCH_HDMI_TX1+ <24>
BH21 AV14 PCH_TXOUT1- DDPB_3N AV49 PCH_HDMI_TX1+
DMI2RBIAS FDI_LSYNC0 FDI_FSYNC1 <5> <23> PCH_TXOUT2- AN47 DDPB_3P PCH_HDMI_TX0- <24>
FDI_FSYNC1 PCH_TXOUT2- AM49 LVDSA_DATA0 PCH_HDMI_TX0-
RH112 750_0402_1% PCH_HDMI_TX0+ <24>
DMI_IRCOMP BB10 LVDSA_DATA1 PCH_HDMI_TX0+
FDI_LSYNC1 FDI_LSYNC0 <5> AK49 PCH_HDMI_TXC- <24>
FDI_LSYNC0 LVDSA_DATA2 P46 PCH_HDMI_TXC-
RBIAS_CPY <23> PCH_TXOUT0+ AJ47 DDPC_CTRLCLK P42 PCH_HDMI_TXC+ PCH_HDMI_TXC+ <24>
PCH_TXOUT0+ LVDSA_DATA3
FDI_LSYNC1 <5> <23> PCH_TXOUT1+ DDPC_CTRLDATA
FDI_LSYNC1 PCH_TXOUT1+
A18 <23> PCH_TXOUT2+
DSWVRMEN PCH_TXOUT2+ AF40
4mil width and place LVDSB_CLK# AP47
AF39 DDPC_AUXN
DSWVRMEN: must be always pulled-up to VCCRTC. --PCH EDS LVDSB_CLK AP49
within 500mil of the PCH C12 E22 +RTCVCC DDPC_AUXP AT38
System Power Management

+3VS SUSACK# DPWROK DSWODVREN RH127 330K_0402_5% AH45 DDPC_HPD
AH47 LVDSB_DATA#0 R1235 100K_0402_5%
non Deep S4/S5: tied "DPWROK"to
RH113 0_0402_5%
RSMRST#. AF49 LVDSB_DATA#1 AY47 1 2
K3 B9 RH129 @ 330K_0402_5% LVDSB_DATA#2 DDPC_0N AY49
R35 10K_0402_5% SUSACK# SYS_RESET# WAKE# PCH_DPWROK PCH_RSMRST#_R DSWODVREN AF45 DDPC_0P @
LVDSB_DATA#3 AY43
EC_SWI# <35,36,39> DDPC_1N AY45
SYS_RST# EC_SWI# AH43 DDPC_1P
P12 N3 AH49 LVDSB_DATA0 BA47
SYS_PWROK CLKRUN# / GPIO32 LVDSB_DATA1 DDPC_2N
AF47 BA48
AF43 LVDSB_DATA2 DDPC_2P
PM_CLKRUN# <34,44> BB47
L22 G8 PM_CLKRUN# LVDSB_DATA3 DDPC_3N
*：
BB49
8111E@SYSTEM_PWROK PWROK SUS_STAT# / GPIO61 DSWODVREN - On Die DSW VR Enable DDPC_3P
C
1
VPRO@
2
RH120 0_0402_5%
PM_PWROK L10
APWROK SUSCLK / GPIO62
N14 SUS_STAT#
2
short@
1
SUS_STAT# <34>
：H Enable
L Disable N48
P49 CRT_BLUE DDPD_CTRLCLK
M43
M36
C
RH118 0_0402_5% RH119 0_0402_5% T49 CRT_GREEN DDPD_CTRLDATA

<41> PCH_APWROK SUSCLK_R <41>
B13 D10 SUSCLK T18 CRT_RED
DRAMPWROK SLP_S5# / GPIO63 <22> PCH_CRT_B
PCH_CRT_B AT45
short@ <22> PCH_CRT_G PCH_CRT_G DDPD_AUXN
T19 T39 AT43
<22> PCH_CRT_R DDPD_AUXP
CRT
<6> PM_DRAM_PWRGD R2 C21 H4 PM_SLP_S5# <41> PCH_CRT_R M40 CRT_DDC_CLK BH41 100K_0402_5%
PM_DRAM_PWRGD RSMRST# SLP_S4# PM_SLP_S5# DDPD_HPD 2 1
0_0402_5% CRT_DDC_DATA R1475
@
<41> PCH_RSMRST# PM_SLP_S4# <41> <22> PCH_CRT_CLK BB43
PCH_RSMRST# PCH_RSMRST#_R K16 F4 PM_SLP_S4# T20 PCH_CRT_CLK M47 DDPD_0N BB45
SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# <22> PCH_CRT_DATA PCH_CRT_DATA CRT_HSYNC DDPD_0P
1 2 M49 BF44
<41> SUSWARN# CRT_VSYNC DDPD_1N BE44
R291 short@ 0_0402_5%
SUSWARN#_R G10 PM_SLP_S3# <41> DDPD_1P
E20 PM_SLP_S3# <22> PCH_CRT_HSYNC
PWRBTN# SLP_A# 1 VPRO@ 2 PCH_CRT_HSYNC BF42
short@ RH116 0_0402_5% <22> PCH_CRT_VSYNC T43 DDPD_2N BE42
SLP_A# <41> PCH_CRT_VSYNC T42 DAC_IREF DDPD_2P
<41> PBTN_OUT# RH137
D12 0_0402_5% CRT_IRTN BJ42
PBTN_OUT#_R H20 G16 SLP_R_A# DDPD_3N BG42
1 2 ACPRESENT / GPIO31 SLP_SUS# PAD T21 DDPD_3P
Can be left NC when IAMT is
PAD T22 CRT_IREF
<13,41,48> ACIN CH751H-40PT_SOD323-2 E10 not support on the platfrom PANTHER-POINT_FCBGA989
AC_PRESENT_R AP14
BATLOW# / GPIO72 PMSYNCH @
R1250
A10 K14 H_PM_SYNC H_PM_SYNC <6> 1K_0402_0.5%
PCH_GPIO72 SLP_LAN# / GPIO29
RI#
1 VPRO@ 2
SLP_R_LAN# RH117 0_0402_5% SLP_LAN# <41>
RI# PANTHER-POINT_FCBGA989
@
2 1 @
RH135 0_0402_5%
SUSACK# SUSWARN#
Check EC for S3 S4 LED
+3VS +3VS
+3VS
B +3VS B
R284 1 2 2.2K_0402_5% RH291 1 2 2.2K_0402_5%
R301
1 2 8.2K_0402_5% R302 1 2 2.2K_0402_5% CTRL_CLK PCH_CRT_CLK
1 2 2.2K_0402_5%
5
U12 PM_CLKRUN# RH292

short@ 1 2 10K_0402_5% CTRL_DATA PCH_CRT_DATA
1 R304 1 2 2.2K_0402_5%
P
0_0402_5% R1314 IN1 @ R283

4
<54> VGATE 2 O PCH_EDID_CLK
R305 1 2 2.2K_0402_5% 1 2 150_0402_1%
IN2 RH131
G
SYSTEM_PWROK SYSTEM_PWROK <6>

<41> PM_PWROK PCH_EDID_DATA PCH_CRT_B
1
PM_PWROK TC7SH08FU(TE85L,F) R1438 1 2 4.7K_0402_5% RH132 1 2 150_0402_1%

3
R1255 PCH_BL_PWM PCH_CRT_G

10K_0402_5% R1620 1 2 100K_0402_5% RH133 1 2 150_0402_1%
PCH_ENVDD PCH_CRT_R
2
2 1
C953 @ 180P_0402_50V8J
VGATE
<41> PCH_ENBKL PCH_ENBKL
2
R300
+3VALW_PCH
祥"SUSWARN#'妗妗妗妗妗"SUSPWRDNACK"
support deep S4/S5:
100K_0402_5%
1
R1251 10K_0402_5%
SUSWARN# /SUSPWRDNACK/ GPIO30 (Mobile Only):
PCH_GPIO72 R1252 10K_0402_5% Used by Intel@ME as either SUSWARN#
RI# in Deep S4/S5 state supported platforms
R279 10K_0402_5% or as SUSPWRDNACK in non Deep S4/S5
EC_SWI# R1244 330K_0402_5% state supported platforms.
AC_PRESENT_R R1243 10K_0402_5%
A SUSWARN#_R R282 10K_0402_5% A
@
SLP_R_LAN#
R1257 10K_0402_5%
PCH_RSMRST#_R R1256 10K_0402_5%

PM_PWROK Security Classification Compal Secret Data
Custom B
5 4 3 2 1
5 4 3 2 1
AY7
BG26 RSVD1 AV7
BJ26 TP1 RSVD2 AU3
BH25 TP2 RSVD3 BG4
BJ16 TP3 RSVD4 SATA1GP/GPIO19: Boot BIOS Strap bit 0 (BBS0)
BG16 TP4
TP5 AT10
AH38 RSVD5 BC8 GNT1#/GPIO51: Boot BIOS Strap bit 1 (BBS1)
AH37 TP6 RSVD6
+3VS AK43 TP7 AU2
AK45 TP8 RSVD7 AT4
1 2 C18
N30
TP9
TP10
RSVD8
RSVD9
AT3 GPIO19 => BBS_BIT0
R320 8.2K_0402_5% TP11 AT1
H3 RSVD10 AY3 GPIO51 => BBS_BIT1
AH12 TP12 RSVD11 AT5
1 2 AM4 TP13 RSVD12 Boot BIOS Strap
PCH_GPIO55 AV3
2 8.2K_0402_5% PCH_GPIO51 TP14 RSVD13
R321 1 AM5 AV1
R322 1 2 8.2K_0402_5% PCH_GPIO52 TP15 RSVD14 Bit 11 Bit 10 Boot BIOS
Y13 BB1 D
D R323 8.2K_0402_5% PCI_PIRQA# RSVD15
K24 TP16 BA3 (BBS1) (BBS0) Destination
TP17 RSVD16
1 2 L24 BB5
2 8.2K_0402_5% AB46 TP18 RSVD17 BB3 0 1 Reserved
R324 1 TP19 RSVD18
R327 8.2K_0402_5% AB45 BB7
TP20 RSVD19 BE8 1 0 PCI
PCH_GPIO2 RSVD20 BD4
RSVD
1 2 PCH_GPIO4 RSVD21 BF6 1 1 SPI *
R329 1 2 8.2K_0402_5% PCH_GPIO53 B21 RSVD22
R330 8.2K_0402_5% PCI_PIRQC# M20 TP21 AV5
0 0 LPC
1 @ 2 TP22 RSVD23
AY16 AV10
R319 8.2K_0402_5% BG46 TP23 RSVD24
TP24 NV_ALE
AT8
DGPU_HOLD_RST#_R RSVD25 PCH EDS Rev1.5 P99, P98
1 2 AY5 Intel Anti-Theft Techonlogy
R3161 PCI_PIRQB# RSVD26
2 8.2K_0402_5% BE28 RSVD27
BA2
High=Endabled
BC30 USB3Rn1
R317 8.2K_0402_5% ODD_DA# NV_ALE
BE32 USB3Rn2 AT12
1 2 Low=Disable(floating)
R318 8.2K_0402_5% DGPU_PWR_EN_R <40> USB3_RX0_N BJ32
BC28
USB3Rn3
USB3Rn4
RSVD28
RSVD29
BF3 * +1.8VS
1 2 USB3Rp1
BE30
R310 8.2K_0402_5% PCH_GPIO5 USB3.0 Port0 BF32 USB3Rp2 @ RH164 1K_0402_5%
1 2 USB3Rp3
<40> USB3_RX0_P BG32 NV_ALE
R311 8.2K_0402_5% PCI_PIRQD# USB3Rp4 C24
AV26 USBP0N
BB26 USB3Tn1 A24
USB3Tn2 USBP0P C25
AU28 USB20_N0 USB20_N0 <40>
USB3Tn3 USBP1N B25
<40> USB3_TX0_N AY30 USB20_P0 USB20_P0 <40>
USB3Tn4 USBP1P C26 USB20_N1 USB20_N1 <43> USB30
2 @ 1 AU26 USBP2N
USB3Tp1 A26 USB20_P1 USB20_P1 <43>
DEL RP5, ADD R316,R317,R318 FOR REMOVE AY26 USBP2P
10K_0402_5% R1277
AV28 USB3Tp2 K28 L-CONN
GPIO53 PU---0609 USB3Tp3 USBP3N H28
<40> USB3_TX0_P AW30 USBP3P
DGPU_PWR_EN USB3Tp4 E28 USB20_N3 USB20_N3 <44>
USBP4N D28 USB20_P3 USB20_P3 <44>
C USBP4P C
C28 USB20_N4 USB20_N4 <44> R-CONN
USBP5N A28 USB20_P4 USB20_P4 <44>
USBP5P C29 USB20_N5 USB20_N5 <39> R-CONN
USBP6N B29 USB20_P5 USB20_P5 <39>
USBP6P N28 Smart Card
K40 USBP7N
K38 PIRQA# M28
PIRQB# USBP7P L30
PCI_PIRQA# H38
PCI
PCI_PIRQB# G38 PIRQC# USBP8N K30 USB port 6,7 are disabled on HM76 and HM75.
2 OPT@ 1 PIRQD# USBP8P G30 USB20_N8 USB20_N8 <39>
PCI_PIRQC#
R262 0_0402_5% USBP9N E30 USB20_P8 USB20_P8 <39>
PCI_PIRQD# C46
1 OPT@ 2 C44 REQ1# / GPIO50 USBP9P C30
USB20_N9 USB20_N9 <43> New Card
USB
REQ2# / GPIO52 USBP10N A30
DGPU_HOLD_RST# R161 0_0402_5% DGPU_HOLD_RST#_R E40 USB20_P9 USB20_P9 <43>
PCH_GPIO52 REQ3# / GPIO54 USBP10P L32 USB20_N10 USB20_N10 <23> USB port with Esata
<26,45,57> DGPU_PWR_EN USBP11N K32
DGPU_PWR_EN_R D47 USB20_P10 USB20_P10 <23>
<40> Int. Camera
GNT1# / GPIO51 USBP11P G32
E42 USB20_N11 USB20_N11
GNT2# / GPIO53 USBP12N E32
PCH_GPIO51 F46 USB20_P11 USB20_P11 <40>
<36>Finger Printer
GNT3# / GPIO55 USBP12P C32
PCH_GPIO53 USBP13N USB20_N12 USB20_N12
PCH_GPIO55 A32 USB20_P12 <36>
USBP13P USB20_P12
G42 USB20_N13 USB20_N13 <36> WWAN
G40 PIRQE# / GPIO2 USB20_P13 <36>
USB20_P13
PCH_GPIO2 C42 PIRQF# / GPIO3 C33
RH165
BT
22.6_0402_1%
PIRQG# / GPIO4 USBRBIAS#
<34> ODD_DA# ODD_DA# D44
PCH_GPIO4 PIRQH# / GPIO5
USBRBIAS
Within 500 mils
PCH_GPIO5 B33
K10 USBRBIAS
PME#
C6 A14
2 @ 1 PLTRST# OC0# / GPIO59 K20
R259 0_0402_5% BUF_PLT_RST# OC1# / GPIO40 B17
<6,34,35,36,37,39,41,42,44> PLT_RST# PLT_RST# USB_OC0# USB_OC0# <40>
H49 OC2# / GPIO41 C16 USB_OC1# USB_OC1# <44> For USB3.0, Left USB.
H43 CLKOUT_PCI0 OC3# / GPIO42 L16 For Right power USB port
22_0402_5% 22 R280
22_0402_5% R285 11
CLKOUT_PCI1 OC4# / GPIO43 USB_OC2#
USB_OC3#
B <41> CLK_PCI_EC 22_0402_5% 2 R281 1 CLK_PCI_EC_R J48 A16 B
CLK_PCI K42 CLKOUT_PCI2 OC5# / GPIO9 D14 USB_OC4# USB_OC4# <40,43>
<26> CLK_PCILOOP +3VALW_PCH
<44> CLK_PCI_SIO 22_0402_5% 2 R286 1 CLK_SIO H40 CLKOUT_PCI3 OC6# / GPIO10 C14 PCH_GPIO9
For USB port with eSATA.
<34> CLK_PCI_TPM CLK_TPM CLKOUT_PCI4 OC7# / GPIO14
PCH_GPIO10
CP_PE# CP_PE# <39>
1 2
USB_OC3# R1270 2
1 10K_0402_5%
PANTHER-POINT_FCBGA989 R1271 10K_0402_5%
@ USB_OC4#
1 2
+3VS R1268 10K_0402_5%
1 2
USB_OC2#
5
U8 R1267 10K_0402_5%
1 1 2
P
IN1 4 USB_OC0# R1269 10K_0402_5%

2 O 1 @ 2
BUF_PLT_RST# IN2 USB_OC1#
G
R1306 10K_0402_5%
PLT_RST#
TC7SH08FU(TE85L,F) 1 2
CP_PE#
3
R1307 10K_0402_5%
1 2
2
PCH_GPIO9
2
R151 R1308 10K_0402_5%

R157 +3VS_DGPU PCH_GPIO10
100K_0402_5% +3VS_DGPU 100K_0402_5%
1
2
1
C477 RV49
U20 0.1U_0402_16V4Z 10K_0402_5%
5
OPT@ 1 OPT@
1 @
P
IN1 2 1
2
4
2 O R261 OPT@ 0_0402_5%
A A
IN2
G
PLTRST_VGA# <13>
DGPU_HOLD_RST# TC7SH08FU(TE85L,F)
3
R165
2
100K_0402_5%
R413 OPT@
1K_0402_5% Security Classification Compal Secret Data
1
OPT@
1
Custom B
5 4 3 2 1
PLT_RST#
5 4 3 2 1
+3VALW_PCH
@ 2 1
2 1 UPCH1F
QAL50/51, PBL22: GPIO24 NC 10K_0402_5% R1287 +3VS
10K_0402_5% R1332 C40
PCH_GPIO24 T7
2 1 BMBUSY# / GPIO0 TACH4 / GPIO68
10K_0402_5% R1330 LID_SW#_R A42 B41 ODD_EN# <34>
KEEP LOW XXMS ACTIVE, PCH_GPIO0 TACH1 / GPIO1 TACH5 / GPIO69 ODD_EN#
NOT TAKE ACTIVE ON H36 C41 PROJECT_ID0 DMI Termination Voltage
2 1 PCH_GPIO1 TACH2 / GPIO6 TACH6 / GPIO70
2 1 RISE/FALL EDGE
10K_0402_5% R61 A40 Set to Vcc when HIGH
10K_0402_5% R1284 EC_SMI# PCH_GPIO6 E38 PROJECT_ID1
TACH3 / GPIO7 TACH7 / GPIO71 NV_CLE
PM_LANPHY_ENABLE <41> EC_SCI# C10 PROJECT_ID2 Set to Vss when LOW
EC_SCI# GPIO8
D 1 2 Weak internal +1.8VS D
1
10K_0402_5% R337 PCH_GPIO28 <41> EC_SMI# EC_SMI# C4 1 R1259 2
1 2 LAN_PHY_PWR_CTRL / GPIO12 PU,Do not pull low
PCH_GPIO57 2 1 10K_0402_5%
10K_0402_5% R338 <42> PM_LANPHY_ENABLE PM_LANPHY_ENABLE G2 P4 +3VS RH187
R147 0_0402_5% GPIO15 A20GATE
short@ 2.2K_0402_5%
<41> LID_SW_OUT# LID_SW#_R AU16 GATEA20 GATEA20 <41>
PECI 1 2
2
U2
SATA4GP / GPIO16 0_0402_5% @ RH159
P5 PCH_PECI_R H_PECI <6,41>
RCIN# 2 1
+3VS <37> CR_PE# CR_PE#
D40 AY11 KB_RST# <41> 1K_0402_5% RH189 H_SNB_IVB# <6>
GPIO
2 1 TACH0 / GPIO17 PROCPWRGD NV_CLE
1 2
CPU/MISC
10K_0402_5% R1325
PCH_GPIO0 <26,45,57> VGA_PWROK RH170 short@ 0_0402_5%VGA_PWROK_R T5 AY10 H_CPUPWRGD <6>
SCLOCK / GPIO22 THRMTRIP# 1 2
22 11 CLOSE TO THE BRANCHING POINT
PCH_GPIO1 T14
10K_0402_5%
10K_0402_5% R1323
R1274 PCH_GPIO22 E8 INIT3_3V# PCH_THRMTRIP# R1261 390_0402_5% H_THERMTRIP# H_THERMTRIP# <6>
1 2 GPIO24
KB_RST# AY1
RH171 0_0402_5% PCH_GPIO24 E16 DF_TVS
2 1 GPIO27
10K_0402_5% R1278 VGA_PWROK_R <35,41> GPIO27_WAKE# GPIO27_WAKE#_R P8 NV_CLE
1 2 GPIO28 AH8 1 2
TS_VSS1 INIT3_3V R1279 10K_0402_5%
10K_0402_5% R339 PCH_GPIO22 K1 PROJECT_ID2
PCH_GPIO28 STP_PCI# / GPIO34 AK11
12 21 TS_VSS2 This signal has weak internal
10K_0402_5% R352 CR_WAKE# <37> CR_WAKE# CR_WAKE# K4
10K_0402_5% R1280 GPIO35 AH10 PU, can't pull low
1 2 TS_VSS3
CR_PE# PCH_GPIO35 V8
R34 200K_0402_5% SATA2GP / GPIO36 AK10
2 1 TS_VSS4 +3VS
10K_0402_5% R1286 ODD_DETECT# <34> ODD_DETECT# ODD_DETECT# M5
1 2 1 2 SATA3GP / GPIO37
PCH_GPIO6 <36,41> WWAN_OFF# P37 1 2
R36 200K_0402_5% RH167 @ 0_0402_5% WWAN_R_OFF# N2 NC_1
SLOAD / GPIO38 PROJECT_ID2 R1276 @ 10K_0402_5%
1 OPT@ 2
WWAN_R_OFF# <23> CE_EN CE_EN M3
SDATAOUT0 / GPIO39 10K_0402_5% R333
2 1
V13 BG2 PROJECT_ID0
10K_0402_5% R1324 PCH_GPIO39 VSS_NCTF_15 1 UMA@ 2
C
SDATAOUT1 / GPIO48 C
2 1 1 2 BG48 10K_0402_5% R370
CE_EN V3
10K_0402_5% R1296 RH166 @ 0_0402_5% PCH_GPIO48 SATA5GP / GPIO49 / TEMP_ALERT#
VSS_NCTF_16 1 030@ 2
2 1 EC_SCI# <36,41> WL_OFF# BH3 10K_0402_5% R409
WL_R_OFF# D6 VSS_NCTF_17
10K_0402_5% R1326 GPIO57 PROJECT_ID1
PCH_GPIO39 PCH_GPIO57 BH47 1 TF@ 2
1 2 VSS_NCTF_18 10K_0402_5% R408
10K_0402_5% R356 PCH_GPIO48 BJ4
A4 VSS_NCTF_19 @ T1908 PAD
1 2 VSS_NCTF_1
10K_0402_5% R355 WL_R_OFF# BJ44
A44 VSS_NCTF_20 PROJECT_ID2 PROJECT_ID1 PROJECT_ID0
VSS_NCTF_2
PAD T1911 @ BJ45 @ T1912 PAD
A45 VSS_NCTF_21
VSS_NCTF_3
BJ46
QAQ10 (UMA) 0 0 0
A46
NCTF
VSS_NCTF_4 VSS_NCTF_22 @ T1914 PAD
PAD T1913 @
BJ5
QAQ11 (Optimus) 0 0 1
1 @ 2 A5
WWAN_R_OFF# VSS_NCTF_5 VSS_NCTF_23 @ T1916 PAD
10K_0402_5%
2 @ R365
1 QAQ12 (UMA) 0 1 0
A6 BJ6
10K_0402_5% R1275 PCH_GPIO35 VSS_NCTF_6 VSS_NCTF_24
C2
QAQ13 (Optimus) 0 1 1
B3 VSS_NCTF_25
VSS_NCTF_7
C48
QAT10 (UMA) 1 0 0
B47 VSS_NCTF_26
VSS_NCTF_8
D1
QAT11 (Optimus) 1 0 1
BD1 VSS_NCTF_27
VSS_NCTF_9 QAQ12 (vPro) 1 1 0
D49 @ T1926 PAD
BD49 VSS_NCTF_28
VSS_NCTF_10 QAQ13 (vPro) 1 1 1
PAD T1927 @ E1
BE1 VSS_NCTF_29
VSS_NCTF_11
BE49 E49
PAD T1929 @ VSS_NCTF_12 VSS_NCTF_30 @ T1930 PAD
PCH_GPIO27 (Have internal Pull-High) BF1 F1 For TongFang: QAQ10 (UMA) / QAQ11 (Optimus)
B High: VCCVRM VR Enable PAD T1931 @
VSS_NCTF_13 VSS_NCTF_31 For 030: QAQ12 (UMA) / QAQ13 (Optimus) B
Low: VCCVRM VR Disable BF49 F49
* PAD T1933 @
VSS_NCTF_14 VSS_NCTF_32
Can be configured as wake input to allow wakes from
Deep Sleep. PANTHER-POINT_FCBGA989
If not used then use 8.2-kΩ to 10-kΩ pull-down to @
GND.
R328 1 2 10K_0402_5%
@ GPIO27_WAKE#_R
PCH_GPIO28 needs to be connected to XDP_FN8
R331 1 2 10K_0402_5%
@ +3VALW PCH_GPIO35 needs to be connected to XDP_FN9
PCH_GPIO15 needs to be connected to XDP_FN16
Please refer to Huron River Debug Board DG 1.2

GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
* H
L
：：On-Die voltage regulator enable
On-Die PLL Voltage Regulator disable
R325 1 @ 2 1K_0402_5% PCH_GPIO28
A A

Custom B
5 4 3 2 1
5 4 3 2 1
L5
MBK1608221YZF_2P
2 1 +3VS
PCH Power Rail Table
0.1U_0402_10V7K
+VCCADAC
10U_0603_6.3V6M
10U_0603_6.3V6M
+1.05VS_PCH Refer to PCH EDS R1.5
0.01U_0402_16V7K
1
UPCH1G POWER C271
1
C309
1
C308
1 C249
S0 Iccmax
Voltage Rail Voltage Current (A)
1300mA U48 2 2
AA23 VCCADAC 2 2
1U_0402_6.3V6K
C247
1U_0402_6.3V6K
C244
VCCCORE[1]
10U_0603_6.3V6M
C245
1
1U_0402_6.3V6K
C246
1 1 1 AC23 1mA
AD21 VCCCORE[2] V_PROC_IO 1.05/1.0 0.002
CRT
AD23 VCCCORE[3] U47
VCCCORE[4] VSSADAC
2 AF21
2
VCC CORE
2 2 AF23 VCCCORE[5] V5REF 5 0.001
AG21 VCCCORE[6]
D VCCCORE[7] +3VS D
AG23 1 2
AG24 VCCCORE[8] AK36 V5REF_Sus 5 0.001
VCCALVDS R423 0_0805_5%
AG26 VCCCORE[9] +VCCALVDS
VCCCORE[10] 1mA AK37
AG27 VSSALVDS L6 +1.8VS
AG29 VCCCORE[11] 0.1UH_MLF1608DR10KT_10%_1608 Vcc3_3 3.3 0.178
AJ23 VCCCORE[12] 2 1
AJ26 VCCCORE[13] AM37 1
LVDS
VCCTX_LVDS[1] 1 1
AJ27 VCCCORE[14] +VCCTX_LVDS VccADAC 3.3 0.063
AJ29 VCCCORE[15] AM38 C310 C366 C311
+1.05VS_PCH AJ31 VCCCORE[16] VCCTX_LVDS[2] 0.01U_0402_16V7K
VCCCORE[17] 0.01U_0402_16V7K 2
0.1uH inductor, 200mA
22U_0805_6.3V6M
AP36 2 2 VccADPLLA 1.05 0.075
40mA VCCTX_LVDS[3]
R357 2 1 0_0603_5% AP37
AN19 VCCTX_LVDS[4] VccADPLLB 1.05 0.075
+1.05VS_VCCDPLLEXP VCCIO[28]
+1.05VS_PCH @ LH3
@ 1 2
RH210 0_0603_5% 1UH_LB2012T1R0M_20% BJ22 R363 VccCore 1.05 1.73
+VCCAPLLEXP_R +VCCAPLLEXP VCCAPLLEXP
10U_0805_6.3V6M
1 2
1 V33
@ VCC3_3[6] +3VS_VCC3_3_6 VccDMI 1.1 0.047
AN16 +3VS
HVCMOS
1 0_0805_5%
VCCIO[15]
CH41
2 AN17 C254
VCCIO[16] V34 VccIO 1.05 3.799
VCC3_3[7] 0.1U_0402_10V7K
2
AN21
VCCIO[17] R366 VccASW 1.05 0.803
+1.05VS_PCH +VCCAFDI_VRM 0_0603_5%
AN26
VCCIO[18] 1 2
AN27 AT16 VccSPI 3.3 0.01
VCCIO[19] 3709mA VCCVRM[3] +VCCAFDI_VRM +1.5VS
PJPH1 AP21
@ +VCCP_VCCDMI R361 +1.05VS_PCH
VCCIO[20] VccDSW 3.3 0.001
2 1 0_0805_5%
C AP23 AT20 C
VCCIO[21] VCCDMI[1] 1 2
10U_0603_6.3V6M
C256
1 +1.05VS_VCC_EXP +VCCP_VCCDMI 1
PAD-OPEN 3x3m
1U_0402_6.3V6K
C269
1U_0402_6.3V6K
C267
R359
1U_0402_6.3V6K
C264
1 1 1 AP24 VccDFTERM 1.8 0.002
DMI
1U_0402_6.3V6K
C258
1 VCCIO[22] 0_0805_5% C255
VCCIO
AB36 1 2 1U_0402_6.3V6K
AP26 VCCCLKDMI 1 2
2 VCCIO[23] 75mA +1.05VS_VCC_DMI_CCI +1.05VS_PCH VccRTC 3.3 N/A
2 2 2
2 AT24 C262
VCCIO[24] 1U_0402_6.3V6K
2 VccSus3_3 3.3 0.065
AN33
VCCIO[25]
R369 AN34 AG16 R360 VccSusHDA 3.3 0.01
VCCIO[26] VCCDFTERM[1]
+3VS 0_0805_5% +VCCPNAND 0_0805_5% +1.8VS
1 2 1 2
1
BH29 AG17 VccVRM 1.5 0.147
VCC3_3[3] VCCDFTERM[2]
C270 +3VS_VCCA3GBG
DFT / SPI
2mA
0.1U_0402_10V7K 1
AJ16 C263 VccCLKDMI 1.05 0.075
2 VCCDFTERM[3] 0.1U_0402_10V7K
AP16
@ R367 +VCCAFDI_VRM VCCVRM[2] 2 VccSSC 1.05 0.095
+1.05VS_PCH 0_0603_5% AJ17
VCCDFTERM[4]
2 1 Place C265 Near BG6 pin BG6
+1.05VS_VCCAPLL_FDI VccAFDIPLL VccDIFFCLKN 1.05 0.050
R364 R362
1 0_0805_5%
1 2 AP17
0_0805_5% +1.05VS_VCCDPLL_FDI VCCIO[27] 1 2
@ C265 +1.05VS_PCH V1 VccALVDS 3.3 0.001
1U_0402_6.3V6K VCCSPI VPRO@
FDI
10mA +3V_VCCPSPI +3V_M

2 1
AU20 C268
VCCDMI[2] 1 8111E@ 2 VccTX_LVDS 1.8 0.04
+VCCP_VCCDMI 1U_0402_6.3V6K R414 +3VS
2 0_0805_5%
B
PANTHER-POINT_FCBGA989 B
@
Intel recommand
VCCVRM==>1.5V FOR MOBILE
A A

5 4 3 2 1
5 4 3 2 1
@ R386 R392
+5VALW
0_0805_5% 0_0603_5%
1 2 @ R374 R3732 1
+3VS +1.05VS_PCH 0_0603_5% 0_0603_5%
L7
2 1 UPCH1J POWER 2
@
1 Q14
+VCCACLK R371 AO3413_SOT23-3
10UH_LB2012T100MR_20% R382 AD49 N26 +5VALW_PCH
0_0603_5%
0.1U_0402_10V7K
C272
0_0603_5% VCCACLK VCCIO[29] 1 +1.05VS_PCH
1 2 +3VALW 2 1 3 1
D
1 1 2 P26 1
T16 VCCIO[30] C295 @
1U_0402_6.3V6K
C278
1 2 1
20K_0402_5%
R388
1 VCCDSW3_3 1U_0402_6.3V6K
+1.05VS_VCCUSBCORE
10U_0603_6.3V6M
C273
+3VS_VCC_CLKF33 +VCCPDSW
C293
1
1 2 C277 P28 2 R1382
0.1U_0402_10V7K VCCIO[31]
G
0_0402_5%
2
2 @ R415 2 1 1 2
2 0_0603_5% T27 <45> PCH_PWR_EN# @
2 @ 0.1U_0402_10V7K V12 VCCIO[32] @
+3VALW_PCH DCPSUSBYP
3mA C677
D T29 D
T38 VCCIO[33] 0.1U_0402_16V4Z
2
VCC3_3[5] 2@
Stuff C277 will make +PCH_VCCDSW
@ L8
voltage 10UH_LB2012T100MR_20%
leakage BH23
T23
VCCSUS3_3[7] 2 1
1 2 +3VS_VCC_CLKF33 VCCAPLLDMI2 R383 0_0603_5%
@ R372 T24
AL29 VCCSUS3_3[8] 1
1 2 VCCIO[14] +3V_VCCPUSB
C287 +3VALW_PCH
1 1 2 V23 R376
+1.05VS_PCH +VCCAPLL_CPY R375 +VCCAPLL_CPY_PCH
0_0603_5%
119mA VCCSUS3_3[9]
0_0805_5% 2 1
USB
@ C274 AL24 0.1U_0402_10V7K +5VALW_PCH +3VALW_PCH
+1.05VS_PCH +VCCDPLL_CPY DCPSUS[3] V24 2 0_0603_5%
10U_0603_6.3V6M VCCSUS3_3[10] +3VALW_PCH
1
+3V_VCCAUBG
2
2 1
1 P24 C298 R377 D5
VCCSUS3_3[6]
+VCCSUS1
@ C276 0.1U_0402_10V7K 100_0402_5% CH751H-40PT_SOD323-2
1U_0402_6.3V6K AA19
2 VCCASW[1] T26 2
DcpSus and DcpSusByp do not require Decoupling. VCCIO[34]
1
Stuffing Decoupling Caps may cause voltage AA21 2 1
VCCASW[2] R378 0_0603_5%
oscillations, when Internal 1.05 Voltage R379 1
0_0805_5% AA24 M26 +1.05VS_VCCAUPLL +1.05VS_PCH +PCH_V5REF_SUS
Regulator is used. By CPET VCCASW[3] V5REF_SUS C294
1 2 903mA
AA26 0.1U_0603_25V7K
Clock and Miscellaneous

+1.05VM_PCH VCCASW[4] AN23 @ 2
DCPSUS[4] +PCH_V5REF_SUS
AA27 1mA 1 2
VCCASW[5] AN24 C314 1U_0402_6.3V6K
1 +1.05VM_VCCASW
1 VCCSUS3_3[1] CH66 0.1U_0402_10V7K
22U_0805_6.3V6M
C280
22U_0805_6.3V6M
C279
Short J6J6When No VPRO AA29 +VCCA_USBSUS
VCCASW[6]
+1.05VM_PCH +1.05VS_PCH
1 2 AA31 +3V_VCCPSUS
2 2 VCCASW[7]
@ AC26 P34 +5VS +3VS
PAD-OPEN 2x2m VCCASW[8] V5REF
2
1
AC27 R380 D4
VCCASW[9] N20 +PCH_V5REF_RUN R381
1 1mA VCCSUS3_3[2] 0_0603_5%+3VALW_PCH 100_0402_5% CH751H-40PT_SOD323-2
AC29
PCI/GPIO/LPC
C C
1U_0402_6.3V6K
C281
VCCASW[10] N22 2 1
L16 1 1 VCCSUS3_3[3]
1U_0402_6.3V6K
C292
+3V_VCCPSUS
1
1U_0402_6.3V6K
C282
AC31 1
2
10UH_LB2012T100MR_20% VCCASW[11] P20 C283 1
+1.05VS_PCH 1 2 2 VCCSUS3_3[4] R390
AD29 1U_0402_6.3V4Z 0_0805_5% +3VS
2 2 VCCASW[12] P22 C284
+PCH_V5REF_RUN
VCCSUS3_3[5] 2 2 1 1U_0603_10V6K
AD31 2
VCCASW[13] 1
+1.05VS_VCCA_A_DPL C285
1 2 W21 AA16 0.1U_0402_10V7K
220U_B2_2.5VM_R35
C312
L14 1 VCCASW[14] VCC3_3[1]

1U_0402_6.3V6K
C289
10UH_LB2012T100MR_20% W23
220U_B2_2.5VM_R35
C286
1 +1.05VS_VCCA_B_DPL W16 2
1U_0402_6.3V6K
C288
+ 1 VCCASW[15] VCC3_3[8] +3VS_VCCPCORE

R384
+ 1 W24 T34 +3VS
VCCASW[16] 0_0603_5%
VCC3_3[4]
2 2 1
2 W26 1
2 VCCASW[17] +3VS_VCCPPCI C290
2 0.1U_0402_10V7K
W29 R385
VCCASW[18] 0_0603_5%
2 2
W31 AJ2 1
+3VS
VCCASW[19] VCC3_3[2] R387
W33 0_0805_5%
VCCASW[20] +VCC3_3_2 1 2 1
AF13 +1.05VS_SATA3 +1.05VS_PCH
VCCIO[5] C291
N16 0.1U_0402_10V7K
DCPRTC AH13 2
R399 VCCIO[12] 1
+1.05VS_PCH 1
0_0603_5% C306 +VCCRTCEXT AH14 C297
Y49 VCCIO[13]
2 1 0.1U_0402_10V7K VCCVRM[4] 1U_0402_6.3V6K
+VCCDIFFCLK 2
1 2 +VCCAFDI_VRM AF14 +1.05VS_SATA3
C315 VCCIO[6] @ R389
1U_0402_6.3V6K BD47 @ L13
VCCADPLLA AK1 0_0805_5%
+1.05VS_PCH
SATA
B R417 VCCAPLLSATA 10UH_LB2012T100MR_20% 2 1 B
0_0603_5% 2 BF47 1 2
+1.05VS_PCH +1.05VS_VCCDIFFCLKN +1.05VS_VCCA_A_DPL VCCADPLLB
2 1 75mA AF11 +VCCSATAPLL +VCCSATAPLL_R
VCCVRM[1] +VCCAFDI_VRM
1 +1.05VS_VCCA_B_DPL AF17 1
+1.05VS_VCCDIFFCLKN VCCIO[7] 75mA @ C296
AF33 +VCCAFDI_VRM 10U_0603_6.3V6M
C318 AF34 VCCDIFFCLKN[1] +1.05VS_VCC_SATA +1.05VS_PCH
+VCCDIFFCLK AC16
1U_0402_6.3V6K AG34 VCCDIFFCLKN[2] VCCIO[2]
2 VCCDIFFCLKN[3] 2 1 2
AC17 +1.05VS_VCC_SATA R391 0_0805_5%
Place C296 Near AK1 pin
55mA VCCIO[3]
R416 +1.05VS_VCCDIFFCLKN
+1.05VS_PCH 0_0603_5% AG33 AD17 1
VCCSSC VCCIO[4] C300
2 1 1U_0402_6.3V6K
1 +1.05VS_SSCVCC +1.05VS_SSCVCC
V16 95mA 2
DCPSST
C317
1U_0402_6.3V6K +1.05VM_PCH
2 +VCCSST
1 T17 T21
V19 DCPSUS[1] VCCASW[22] R393 2 1 0_0603_5%
@ R398 C299 DCPSUS[2]
+1.05VM_PCH +VCCME_22
MISC
0_0603_5% 0.1U_0402_10V7K +1.05VM_VCCSUS

2 V21
2 1 VCCASW[23] R394 2 1 0_0603_5%
+1.05VM_VCCSUS R395
+1.05VS_PCH BJ8
CPU
0_0603_5% V_PROC_IO +VCCME_23

1 T19 R396 2 1 0_0603_5%
1 2 2mA VCCASW[21]
C316 +V_CPU_IO
1 1 +VCCME_21
1U_0402_6.3V6K 1
4.7U_0603_6.3V6K
C301
0.1U_0402_10V7K
C302
2
0.1U_0402_10V7K
C303
+RTCVCC A22 +3VALW_PCH

P32
RTC
VCCRTC VCCSUSHDA R397 2 1 0_0603_5%

HDA
2 2 2 +VCCSUSHDA
0.1U_0402_10V7K
C313
10mA
0.1U_0402_10V7K
C305
1U_0402_6.3V6K
C304
1 1 1 PANTHER-POINT_FCBGA989 1
@ C307
0.1U_0402_16V4Z
A 2 A
2 2 2

5 4 3 2 1
5 4 3 2 1
UPCH1I
H46
VSS[259] K18
AY4 VSS[260] K26
H5 UPCH1H AY42 VSS[159] VSS[261]
VSS[0] VSS[160] K39
AY46 VSS[262] K46
AY8 VSS[161] VSS[263]
AK38 VSS[162]
D AA17 VSS[80] AK4 B11 K7 D
VSS[1] VSS[81] B15 VSS[163] VSS[264]
AA2 AK42 L18
AA33 VSS[2] B19 VSS[164] VSS[265]
AA3 VSS[4] VSS[82] AK46 L2
VSS[3] B23 VSS[165] VSS[266]
VSS[83] AK8 L20
B27 VSS[166] VSS[267]
AA34 VSS[84] AL16 L26
VSS[5] B31 VSS[167] VSS[268]
AB11 VSS[85] AL17 L28
VSS[6] B35 VSS[168] VSS[269]
AB14 VSS[86] AL19 L36
VSS[7] B39 VSS[169] VSS[270]
AB39 VSS[87] AL2 F45 L48
VSS[8] B7 VSS[170]
VSS[172] VSS[271]
AB4 VSS[88] AL21 M12
VSS[9] VSS[171] VSS[272]
AB43 VSS[89] AL23 P16
AB5 VSS[10] VSS[90] BB12 VSS[273] M18
VSS[11] AL26 VSS[173] VSS[274]
AB7 VSS[91] BB16 M22
VSS[12] AL27 BB20 VSS[174] VSS[275]
AC19 VSS[92] AL31 VSS[175] M24
AC2 VSS[13] VSS[93] AL33 BB22 VSS[276] M30
VSS[14] VSS[94] AL34 VSS[176] VSS[277]
AC21 BB24 M32
VSS[15] VSS[95] VSS[177] VSS[278]
AC24 BB28 M34
VSS[16] AL48 BB30 VSS[178] VSS[279]
AC33 VSS[96] AM11 VSS[179] M38
AC34 VSS[17] VSS[97] BB38 VSS[280] M4
VSS[18] AM14 BB4 VSS[180] VSS[281]
AC48 VSS[98] AM36 VSS[181] M42
AD10 VSS[19] VSS[99] BB46 VSS[282] M46
VSS[20] AM39
AM43 BC14 VSS[182] VSS[283]
AD11 VSS[100]
VSS[101] VSS[183] M8
AD12 VSS[21] BC18 VSS[284] N18
VSS[22] AM45 BC2 VSS[184] VSS[285]
AD13 VSS[102] AM46 VSS[185] P30
VSS[23] BC22 VSS[286] N47
AD19 VSS[103] AM7 VSS[186] VSS[287]
AD24 VSS[24] VSS[104] BC26 P11
VSS[25] AN2 BC32 VSS[187] VSS[288]
AD26 VSS[105] AN29 VSS[188] P18
AD27 VSS[26] VSS[106] BC34 VSS[289] T33
VSS[27] AN3 BC36 VSS[189] VSS[290]
AD33 VSS[107] AN31 VSS[190] P40
AD34 VSS[28] VSS[108] BC40 VSS[291] P43
VSS[29] AP12 BC42 VSS[191] VSS[292]
AD36 VSS[109] AP19 VSS[192] P47
AD38
AD37 VSS[30] VSS[110] BC48 VSS[293] P7
VSS[32]
VSS[31] AP28 BD46 VSS[193] VSS[294]
VSS[111] AP30 VSS[194] R2
C AD39 VSS[112] BD5 VSS[295] R48 C
VSS[33] AP32 BE22 VSS[195] VSS[296]
AD4 VSS[113] AP38 VSS[196] T12
AD40 VSS[34] AP4 BE26 VSS[297] T31
VSS[114] VSS[197]
AD42 VSS[35] VSS[115] BE40 VSS[298] T37
VSS[36] AP42 BF10 VSS[198] VSS[299]
AD43 VSS[116] VSS[199] T4
VSS[37] AP46 BF12 VSS[300]
AD45 VSS[117] VSS[200] W34
VSS[38] AP8 BF16 VSS[301]
AD46
AD8 VSS[118] VSS[201] T46
VSS[39]
VSS[40] AR2 BF20 VSS[302]
AE2 VSS[119] VSS[202] T47
VSS[41] AR48 BF22 VSS[303]
AE3 VSS[120] VSS[203] T8
VSS[42] AT11 BF24 VSS[304]
VSS[121] VSS[204] V11
AT13 BF26 VSS[305]
AF10 VSS[122] VSS[205] V17
VSS[43] AT18 BF28 VSS[306]
AF12
AD14 VSS[123] VSS[206] V26
VSS[44]
VSS[45] AT22 BD3 VSS[307]
VSS[124] VSS[207] V27
AT26 BF30 VSS[308]
AD16 VSS[125] VSS[208] V29
VSS[46] AT28 BF38 VSS[309]
AF16 VSS[126] VSS[209] V31
VSS[47] AT30 BF40 VSS[310] V36
AF19 VSS[127] AT32 BF8 VSS[210]
VSS[48] VSS[311] V39
AF24 VSS[128] AT34 BG17 VSS[211]
VSS[49] VSS[129] VSS[312] V43
AF26 AT39 BG21 VSS[212]
VSS[50] VSS[130] VSS[313] V7
AF27 AT42 BG33 VSS[213]
VSS[51] VSS[314] W17
AF29 VSS[131] AT46 BG44 VSS[214]
VSS[52] VSS[315] W19
AF31 VSS[132] BG8 VSS[215]
VSS[53] AT7 VSS[316] W2
AF38 VSS[133] BH11 VSS[216] VSS[317]
VSS[54] AU24 W27
AF4 VSS[134] BH15 VSS[217] VSS[318]
VSS[55] AU30 W48
AF42 VSS[135] BH17 VSS[218] VSS[319]
VSS[56] AV16 Y12
AF46
AF5 VSS[136] BH19 VSS[219] VSS[320]
VSS[57]
VSS[58] AV20 H10 Y38
VSS[137] VSS[220]
VSS[221] VSS[321]
AV24 Y4
AF7 VSS[138] BH27 VSS[322]
VSS[59] AV30 Y42
AF8 VSS[139] BH31 VSS[222] VSS[323]
VSS[60] AV38 Y46
AG19 VSS[140] BH33 VSS[223] VSS[324]
VSS[61] AV4 Y8
AG2 VSS[141] BH35 VSS[224] VSS[325]
VSS[62] AV43 BG29
AG31 VSS[142] BH39 VSS[225] VSS[328]
VSS[63] AV8 N24
AG48 VSS[143] BH43 VSS[226] VSS[329]
VSS[64] AW14 AJ3
B AH11 VSS[144] BH7 VSS[227] VSS[330]
B
VSS[65] AW18 AD47
AH3 VSS[145] D3 VSS[228] VSS[331]
VSS[66] AW2 B43
AH36 VSS[146] D12 VSS[229] VSS[333]
VSS[67] AW22 VSS[230] BE10
AH39 VSS[147] D16 VSS[334]
VSS[68] AW26 VSS[231] BG41
AH40 VSS[148] D18 VSS[335]
VSS[69] AW28 VSS[232] G14
AH42 VSS[149] D22 VSS[337]
VSS[70] AW32 VSS[233] H16
AH46 VSS[150] D24 VSS[338]
VSS[71] AW34 VSS[234] T36
AH7 VSS[151] D26 VSS[340]
VSS[72] AW36 VSS[235] BG22
AJ19
AJ21 VSS[152] D30 VSS[342]
VSS[73] AW40 VSS[236] BG24
AJ24 VSS[74] VSS[153] D32 VSS[343]
AW48 D34 VSS[237] C22
VSS[75] VSS[154] VSS[344]
AV11 D38 VSS[238] AP13
AJ33 VSS[155] VSS[345]
VSS[76] AY12 D42 VSS[239] M14
AJ34 VSS[156] VSS[346]
VSS[77] AY22 D8 VSS[240] AP3
AK12 VSS[157] VSS[347]
VSS[78] AY28 E18 VSS[241] AP1
AK3 VSS[158] VSS[348]
VSS[79] E26 VSS[242] BE16
VSS[243] VSS[349] BC16
G18 VSS[350]
PANTHER-POINT_FCBGA989 G20 VSS[244] BG28
@ VSS[245] VSS[351] BJ28
G26 VSS[352]
G28 VSS[246]
G36 VSS[247]
G48 VSS[248]
H12 VSS[249]
H18 VSS[250]
H22 VSS[251]
H24 VSS[252]
H26 VSS[253]
H30 VSS[254]
H32 VSS[255]
H34 VSS[256]
F3 VSS[257]
VSS[258]
A A
PANTHER-POINT_FCBGA989
@

5 4 3 2 1
5 4 3 2 1
SBIOS SPI Flash
U59
2 1 5 2 2 1
PCH_SPI_MOSI R401 SBIOS_SI SI SO PCH_SPI_MISO_R R403 PCH_SPI_MISO
33_0402_5% PCH_SPI_MISO <25>
<25> PCH_SPI_MOSI 33_0402_5%
2 1 6
PCH_SPI_CLK R402 SBIOS_CLK
33_0402_5% SCLK
<25> PCH_SPI_CLK
D 1 D
PCH_SPI_CS# CS
<25> PCH_SPI_CS#
1 2 R4927 7
HOLD
4.7K_0402_5%
R405 1 2 R4928 3
0_0603_5% WP
4.7K_0402_5%
2 1 8 4
+3VS 8111E@ VCC GND
2 1
32M W25Q32BVSSIG
+3V_M 8111E@
0_0603_5%
R411 C405
VPRO@ 0.1U_0402_16V4Z
U59
64M W25Q64FVSSIG SOIC 8P SPI ROM
VPRO@
For EMI resuest.

C409 @ 2 @ 1
R419
10_0402_5%
SBIOS_CLK
U59:
6P_0402_25V
Vpro--SA000039A20 8MB
C413
12P_0402_50V8J
non-Vpro--SA00003K800 4MB
C C
BIOS SPI Flash (2MByte*1) For Win8

U60 WIN8@
2 WIN8@ 1R404 5 2 2 WIN8@ 1
PCH_SPI_MOSI SBIOS_SI1 SI SO SBIOS_SO1 PCH_SPI_MISO
33_0402_5% R407 33_0402_5%
PCH_SPI_CLK 2 WIN8@ 1R406 SBIOS_CLK1 6
33_0402_5% SCLK
PCH_SPI_CS1# 1
<25> PCH_SPI_CS1# CS
R4932 1 WIN8@ 2 7
4.7K_0402_5% HOLD
B R421 R4933 1 WIN8@ 2 3 B
0_0603_5% 4.7K_0402_5% WP
2 1 8 4
+3VS 8111E@ VCC GND
2 1 16M MX25L1606EM2I-12G SOP 8P ROM
+3V_M
C406
0_0603_5%
0.1U_0402_16V4Z
R422
WIN8@
VPRO@
P/N: SA000041N00
For EMI resuest.

@ C420 @ R420
2 1 SBIOS_CLK1
6P_0402_25V 10_0402_5%
@
C421 12P_0402_50V8J
A A

B
5 4 3 2 1
5 4 3 2 1
SATA HDD Conn. TPM 1.2 R664

1WB_TPM@2
4.7K_0402_5%
PM_CLKRUN#_R +3VS_TPM
@
+5VS
Place closely JP25 SATA CONN.
1.2A 1
C390
2 @ 1
2
C768
1
15P_0402_50V8J
1 1 1 R669
CLK_PCI_TPM 10_0402_5%
C387 C388 C389 0.1U_0402_16V4Z +3VS TPM@ +3VS_TPM
10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 2
2 R30 0_0603_5% EMI
2 2 2 1 1 1
C764 C765 C419
TPM@ TPM@ TPM@ 1 IN_TPM@2
10U_0805_10V4Z BADD R659 1 @ 4.7K_0402_5% +3VS_TPM
D 0.1U_0402_16V4Z 1U_0402_6.3V4Z 2 D
2 2 2
R663 4.7K_0402_5%
BADD: IN_TPM PD, WB_TPM NC

JHDD
Base I/O Address:
IN_TPM:
1 0 = 02Eh * 1 = 04Eh
GND 2
RX+ C513 1 2 0.01U_0402_25V7K WB_TPM:
3 C512 1 2 0.01U_0402_25V7K +3VALW_TPM Default:7EH-7FH
RX- +3VALW
4 SATA_PTX_C_DRX_P0 SATA_PTX_DRX_P0 <25> 4.7K PD:EEH-EFH
GND C410 1 2 0.01U_0402_25V7K TPM@
5 SATA_PTX_C_DRX_N0 SATA_PTX_DRX_N0 <25>
TX- 6 1 2 1 @ 2
1 1
TX+ 7 C412 1 2 0.01U_0402_25V7K R49 0_0603_5% C778 R660 1 IN_TPM@ 2
4.7K_0402_5%
SATA_PRX_DTX_N0 SATA_PRX_C_DTX_N0 <25> C777 +3VS_TPM
GND SATA_PRX_DTX_P0 TPM@ R661 0_0402_5%
SATA_PRX_C_DTX_P0 <25> TPM@
0.1U_0402_16V4Z TPM_TEST1
2 1U_0402_6.3V4Z 2
8 TEST:
3.3V 9
3.3V Default: Normal Mode, IN_TPM PD,
10
3.3V 11 WB_TPM NC
GND 12
GND 4.7K PU: Test Mode
13
GND 14
5V +3VS_TPM +3VALW_TPM
15
5V 16 +5VS
5V 17
GND 18
C Reserved 19 C
23 GND 20 1 2
10
19
24
GND 12V
5
24 21 U37 R727 4.7K_0402_5%
GND 12V 22 +3VS_TPM
VSB
VDD
VDD
VDD
12V
1@ 2
26 28 R726 0_0402_5%
CONN@ <25,41,44> LPC_AD0 LPC_AD0 LAD0 LPCPD# 9 SUS_STAT#_R SUS_STAT# <27>
23
<25,41,44> LPC_AD1 LPC_AD1 20 LAD1 TESTB1/BADD 8 BADD
LAD2 TEST1 TPM_TEST1 IN_TPM@
<25,41,44> LPC_AD2 LPC_AD2 17
LAD3 11 22
<25,41,44> LPC_AD3 LPC_AD3 14
SATA ODD Conn TPM
XTALO
XTALI
13 TPM_XTALO_R
TPM_XTALI_R
R728
R729 IN_TPM@ 0_0402_5%
0_0402_5%TPM_XTALO
TPM_XTALI
+5VS_ODD
21 SLB 9635 TT 1.1 C766 IN_TPM@
<28> CLK_PCI_TPM CLK_PCI_TPM 22 LCLK 2
LPC_FRAME# LFRAME# GPIO2 18P_0402_50V8J
10U_0805_10V4Z 1 <25,41,44> LPC_FRAME# 16 6
1 <6,28,35,36,37,39,41,42,44> PLT_RST# PLT_RST# 27 LRESET# GPIO
1 1 C415 1 1 SERIRQ TPM_XTALI
C952 C414 C416 C418 <25,41,44> SERIRQ 1 2 2
@ 1SERIRQ 15
10M_0402_5%
C417 0.1U_0402_16V4Z <27,44> PM_CLKRUN# PM_CLKRUN#_R 7 CLKRUN# 1
R773 4.7K_0402_5%
0_0402_5%
1
10U_0805_10V4Z @ R665
1
10U_0805_10V4Z 2 0.1U_0402_16V4Z 2 +3VS_TPM PP PP NC 3
@ 1U_0402_6.3V4Z IN_TPM@
IN_TPM@
2 2 2 NC 32.768KHZ_12.5PF_Q13FC1350000400
2 12
GND
GND
GND
GND
NC X3
R668
2
IN_TPM:
2
if support physically access R772 IN_TPM@
2
SLB 9635 TT 1.2 TSSOP28P FW REV3.19
25
18
11
4
the platform, connect the pin @ 0_0402_5% IN_TPM@ C767 IN_TPM@
JODD to 3.3V.
TPM_XTALO
If this feature is not used,
1
the pin can be left open (it 18P_0402_50V8J
13
B
GND 12 Place component's closely ODD CONN. has an internal pull-down). B
A+ C518 1 2 0.01U_0402_25V7K
11 SATA_PTX_C_DRX_P2 C519 1 2 0.01U_0402_25V7K
A- 10 SATA_PTX_DRX_P2 <25>
GND SATA_PTX_C_DRX_N2 SATA_PTX_DRX_N2 <25>
9 WB_TPM:
B- 8 C424 1 2 0.01U_0402_25V7K
B+ SATA_PRX_DTX_N2 2 0.01U_0402_25V7K SATA_PRX_C_DTX_N2 <25> SERIRQ PU At Page29
7 C425 1
GND SATA_PRX_DTX_P2 SATA_PRX_C_DTX_P2 <25>
short@ GPIO_IF, GPX and PP are optional.
6 0_0402_5% 2 1 R762 Leave them open if not used.
DP 5
V5 ODD_DETECT#_R ODD_DETECT# <29>
4 +5VS_ODD U37
V5 3 0_0402_5% 2+5VS_ODD1 R763
MD 2 short@
GND ODD_DA#_R ODD_DA# <28>
1
GND
SUYIN_127382FR013G109ZR_RV S IC WPCT200AA0WG TSSOP 28P TPM

WB_TPM@
CONN@ +5VS +5VS_ODD
R107
0_0805_5%
+VSB
1 2 BOM
IN_TPM:IN_TPM@&TPM@
WB_TPM:WB_TPM@&TPM@
D
6
2
1 5 4 For NON_TPM SKU Reserve

1U_0402_6.3V6K
CS27
R760 2
470K_0402_5% 1 Q55
@ SI3456BDV-T1-E3 1N TSOP6
2
G
@ @
1
A A
3
ODD_EN
0.1U_0402_16V4Z
C818
2
1
D 1
1.5M_0402_5%
R764
<29> ODD_EN#
2
G
Q59
SSM3K7002FU_SC70-3
@ 2011/09/23 2011/12/30 Title
S @ @ 2 Issued Date Deciphered Date
3
1
B
5 4 3 2 1
A B 22 31 C D E
8111E@ HSOP LED3/EEDO 37
IC function Part <26,42>

CL1 8111E@
CL2 1
1 2 0.1U_0402_16V7K
2 0.1U_0402_16V7K
23
HSON
LED1/EESK
LED0
40 PWR +3VALW TO +3V_LAN
PCIE_PRX_C_LANTX_P6 PCIE_PRX_RTLANTX_P6 30
17
HSIP EECS/SCL 32 10/100_LINK_LED J35
18 EEDI/SDA RL1 2 1 10K_0402_5% LL1 8111E@ Vgs=-4.5V,Id=3A,Rds<97mohm
<26,42> PCIE_PRX_C_LANTX_N6 RL20 8111E@0_0402_5% PCIE_PRX_RTLANTX_N6 HSIN RL2 LAN_ACTIVITY#
2 8111E@ 1 10K_0402_5% LL1,CL13
1 will be 2changed to +LAN_VDD10 2 1
2 1
RL24 0_0402_5% 8111E@
8111E@ 2.2uH&4.7uF after EVT test
2.2UH_1008HC-472EJFS-A_5%_1008 +3VALW +3V_LAN
<26,42> PCIE_PTX_C_LANRX_P6 PCIE_PTX_C_C_RTLANRX_P6 16 1
+3V_LAN <26,42> PCIE_PTX_C_LANRX_N6 CLKREQB MDIP0 1 JUMP_43X79
PCIE_PTX_C_C_RTLANRX_N6 2
@ MDIN0 2 @ 1
2 1 25 4 +LAN_REGOUT CL13 1
PERSTB MDIP1 5
10K_0402_5% RL25 <26,42> CLKREQ_LAN# 4.7U_0603_6.3V6K CL9 8111E@ C840 C841
CLKREQ_LAN# MDIN1 LAN_MDI0+ 2
CLKREQ_LAN# 19 7 8111E@ 0.1U_0402_16V4Z 4.7U_0805_10V4Z 1U_0402_6.3V4Z
20 REFCLK_P NC/MDIP2 8 LAN_MDI0- Layout Note: LL1 must be 1 @ 2 8111E@
<6,28,34,36,37,39,41,42,44> PLT_RST# PLT_RST# REFCLK_N NC/MDIN2 10 LAN_MDI1+ within 200mil to Pin36, 2
1 <26,42> CLK_LAN
NC/MDIP3 11 LAN_MDI1- CL13,CL9 must be within
1
@ CLK_LAN 43 NC/MDIN3 LAN_MDI2+ 200mil to LL1
+3V_LAN 1 2 <26,42> CLK_LAN# CLK_LAN# CKXTAL1 LAN_MDI2-
RL3 10K_0402_5% 44 13 LAN_MDI3+
CKXTAL2 DVDD10 29 LAN_MDI3-
LAN_WAKE# @ RL10 0_0402_5% LAN_X1 DVDD10 41
<29,41> GPIO27_WAKE# DVDD10
@ RL9 0_0402_5% 28 +LAN_VDD10
LAN_X2 LANWAKEB
<36,39,41,42> EC_PME#
26 27
8111E@ RL8 0_0402_5% ISOLATEB DVDD33 39 +LAN_VDD10 2 8111E@ 1 +LAN_EVDD10 +3V_LAN
RTL8105E RTL8111E 1 RL6 2 LAN_WAKE#
<27,36,39> EC_SWI# DVDD33 0_0603_5% LL2
1K_0402_1% 1 2 Close to Pin 27,39,12,47,48
Pin14 NC NC +3VS 14 12 +3V_LAN
8111E@ ISOLATEB 15 NC/SMBCLK AVDD33 1 1 2 2 8111E@
8111E@
42 CL18 CL17
38 NC/SMBDATA AVDD33 0.1U_0402_16V4Z
0.1U_0402_16V4Z CL10
CL12
Pin15 NC 10K ohm PD 47 1U_0402_6.3V4Z 0.1U_0402_16V4Z
RL7 RL22 21 8111E@ 12 10K_0402_5%
RL21 1K_0402_5% GPO/SMBALERT AVDD33 2 1 8111E@
48 +3V_LAN 8111E@
15K_0402_5% 8111E@ AVDD33 1 2
Pin38 1K ohm Pull-high
8111E@ 0.1U_0402_16V4Z CL4
+3V_LAN 33 1 2 8111E@
ENSWREG 21 0.1U_0402_16V4Z CL5 8111E@
+3V_LAN EVDD10
34
35 VDDREG 1 2
ENSWREG VDDREG AVDD10
3 Close to Pin 21 0.1U_0402_16V4Z CL6 8111E@
RL4 6 +LAN_EVDD10
AVDD10 9
0_0402_5% +LAN_VDDREG AVDD10 1 2
46 45 +LAN_VDD10
RSET AVDD10 0.1U_0402_16V4Z CL7 8111E@
8111E@ 1 2
LanWake O/D PU at Page31. Used 24 36
RL5 2.49K_0402_1% GND REGOUT
to reactivate PCIE slot's main 49
PGND +3V_LAN +LAN_VDDREG CL7 close to pin12
ENSWREG PWR rail and REF CLK 2 1
0_0603_5% LL3
ISOLATEB used to isolate 8111E +LAN_REGOUT 2
RL23 RTL8111E-VL-CGT QFN 48P 8111E@ 1
2
0_0402_5%
from PCIE 60 mils CL29
2
CL28 0.1U_0402_16V4Z Close to Pin 3,6,9,13,29,41,45
+LAN_VDD10
@ CLKREQ O/D PU at PCH side 4.7U_0603_6.3V6K 1 8111E@ 1 2
8111E@ 2
0.1U_0402_16V4Z 1 CL19
2 8111E@
SMBDATA and GPO using EFuse
only without ASF function. 0.1U_0402_16V4Z CL20 8111E@
1 2
0.1U_0402_16V4Z CL21 8111E@
25MHZ_10PF_7V25000014 LAN Conn. 1 2
Crystal YL1 2 8111E@ 1

R1713 510_0402_5%
2 8111E@ 1
LAN_ACTIVITY# R1709 LAN_R_ACTIVITY#
510_0402_5%
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
1
CL22 8111E@
2
CL23 8111E@
10/100_LINK_LED LAN_LINK# 2 1 2
1 3 C2002 220P_0402_50V7K 0.1U_0402_16V4Z CL24 8111E@
1 3
GND GND DL2 1 2
LAN_X1 LAN_X2 0.1U_0402_16V4Z CL25 8111E@
1 2 2 VPRO@ 1 JLAN1 CONN@
1 2 4 +3V_LAN 1
8111E@ +3V_M R1711 510_0402_5%
CL27 3 VPRO@ 12
CL26 12P_0402_50V8J <42> LAN_1000_LED# Yellow LED-
CL11 close to pin42
12P_0402_50V8J 8111E@ 2 11 CL23,CL24,CL25 close to pin6,9,41, respectively
8111E@ 2 1 <42> LAN_10/100_ LED# S DIO BAW56W SOT-323 Yellow LED+
+3V_LAN
CL11 8
VPRO@ PR4-
0.1U_0402_16V4Z RJ45_MIDI3-
2 8111E@ RL36 0_0402_5% 7
PR4+
<42> LAN_ACT_LED# LAN_R_ACTIVITY# RJ45_MIDI3+
6
PR2-
RJ45_MIDI1-
3
5 3
PR3-
RJ45_MIDI2-
4
PR3+
RJ45_MIDI2+
3
PR2+
RJ45_MIDI1+
2
PR1-
Transformer UL5 CL39
2
1000P_0402_50V7K
1
RJ45_MIDI0-
1
PR1+
SHLD2
14
24 1 2 13
1 RJ45_MIDI0+ SHLD1
2 TCT1 MCT1 23 RL11 75_0402_1% 10
TD1+ MX1+ Green LED-
LAN_MDI3- 3 22 RJ45_MIDI3- LAN_LINK#
TD1- MX1- 1 2 9
LAN_MDI3+ CL40 1000P_0402_50V7K RJ45_MIDI3+ 2 1 Green LED+
4 21 2 1 RL12 75_0402_1% C2003 220P_0402_50V7K
5 TCT2 MCT2 20
6 TD2+ MX2+ 19 CL41 1000P_0402_50V7K LIYO_101002-00803-3
LAN_MDI2- 2 RJ45_MIDI2-
LAN_MDI2+ TD2- MX2- 2 1 1 RJ45_MIDI2+
7 18 RL13 75_0402_1% 2 VPRO@ 1
8 TCT3 MCT3 17 +3V_M R1712 510_0402_5%
9 TD3+ MX3+ 16
LAN_MDI1- RJ45_MIDI1-
TD3- MX3- CL42 1000P_0402_50V7K
LAN_MDI1+ 2
10 15 2 1 1 RJ45_MIDI1+
+3V_LAN
MCT4 RL15 75_0402_1% 1 2 1000P_1808_3KV7K
11 TCT4 14
TD4+ MX4+ RJ45_GND CL36 LAN_GND
LAN_MDI0- 12 13 RJ45_MIDI0-
TD4- MX4-
4.7U_0603_6.3V6K
LAN_MDI0+ RJ45_MIDI0+
0.1U_0402_16V4Z
1
1 RL38 RL37 2
RJ45_GND 0_0402_5% CL30 0_0402_5%
CL34 NS892407 1G CL31
4
0.1U_0402_25V4K 2 4
Place CL34 colse 2 8111E@ 1
RL28VPRO@0_0402_5%
to LAN chip RL29VPRO@0_0402_5%
<42> LAN_TX0+ LAN_TX0+ LAN_MDI0+
RL30VPRO@0_0402_5% LAN_MDI0-
CL34 <42> LAN_TX0- LAN_TX0- RL31VPRO@0_0402_5%
<42> LAN_TX1+ LAN_TX1+ RL32VPRO@0_0402_5% LAN_MDI1+
1U_0402_6.3V4Z
<42>
<42>
LAN_TX1-
LAN_TX2+
LAN_TX1-
LAN_TX2+
RL33VPRO@0_0402_5%
RL35VPRO@0_0402_5%
LAN_MDI1-
LAN_MDI2+
LAN_TX2- RL34VPRO@0_0402_5% LAN_MDI2- Issued Date 2011/09/23 Deciphered Date 2011/12/30 Title
VPRO@ <42> LAN_TX2-
<42> LAN_TX3+ LAN_TX3+
LAN_TX3-
LAN_MDI3+
LAN_MDI3- THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
<42> LAN_TX3- Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
Intel check:Better to put 4x 0.1uF bypass cap
near 4 central tap pin of Transformer. Date: Friday, August 24, 2012 Sheet 35 of 60
A B C D E
5 4 3 2 1
Slot 1 Half PCIe Mini Card-WLAN

RH122
& BT3.0 +3V_M +3VS +3VS_WLAN
1 8111E@ 2
short@
@ 0_0402_5% 0_0603_5% R87 0.1U_0402_16V4Z 2 1
1 R1380
2 JMINI1
1
<35,39,41,42> EC_PME# 1 1 VPRO@ 2 <41> BT_PWRON BT_PWRON_R
1 WLAN/ WiFi2 2 +1.5VS +3VS_WLAN 1 0_0402_5%
RH121 0_0402_5% 0_0603_5% R83
CM17 CM18 1
3 1 4
4
5 3 6 CM19
2
2
WLAN_WAKE
WLAN_WAKE 6 C675
<27,35,39> EC_SWI# 7 5 8
8
2 0.1U_0402_16V4Z
9 7 10 47P_0402_50V8J
BT_PWRON_R 10 2@
11 9 12 4.7U_0805_10V4Z
<26> CLKREQ_WLAN# 11 12 14
13 14
15 13 16
16
D <26> CLK_WLAN# 17 15 18
18 D
<26> CLK_WLAN 19 17 20
20
21 19 22
22 +1.5VS
23 21 24
24 0.1U_0402_16V4Z
25 23 26 WL_OFF# <29,41> 1 1
1
26 PLT_RST#
27 25 28
28 PLT_RST# <6,28,34,35,37,39,41,42,44>
CM20 CM22
<26> PCIE_PRX_WLANTX_N2 29 27 30
30 CM21
<26> PCIE_PRX_WLANTX_P2 29 32
2
31 32 2 2
33 31 34
33 34 36 PM_SMBCLK <11,12,26,39> 47P_0402_50V8J 4.7U_0805_10V4Z
35 36
<26> PCIE_PTX_C_WLANRX_N2 35 38 PM_SMBDATA <11,12,26,39>
37 38
<26> PCIE_PTX_C_WLANRX_P2 39 37 40 R1435
40 0_0402_5% USB20_N13 <28>Bluetooth 3.0
41 39 42
42
43 41 44 1 @ 2 USB20_P13 <28> +3VS_WLAN
+3VS_WLAN 1 44 1 2
0_0402_5% VPRO@ 2R1434 45 43 46
46 R44 @ 10K_0402_5% 0.1U_0402_16V4Z
47 45 48
48 0.1U_0402_16V4Z
LED_WLAN# <43> EMI 0.1U_0402_16V4Z
49 47 50
<26> CL_CLK_DMC 0_0402_5% 1 VPRO@ 2R1431 50 1 2
<26> CL_DATA_DMC 51 49 52
52
0_0402_5% 1 VPRO@ 2R1430 51 R42 @ 10K_0402_5% 1 1 1 1
<26> CL_RST#_DMC 1
53 54 1 1
GND1 GND2 +3VS
2 1 C374 C380 C381 C382
BT_PWRON C373 2 2 2 0.1U_0402_16V4Z
2 2 C371 C372
1K_0402_5% R1437 ACES_88910-5204 2 2 @ @ @
@ @
@ @
CONN@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
0.1U_0402_16V4Z
C C
Vpro SKU: please delete E51_TXD_R /RXD connection on JMINI1.
Slot 2 Half PCIe Mini Card-G/GPS (FULL Card)
D19 @
+3VS_FULL +1.5VS +3VS_FULL CM1293-04SO_SOT23-6
1 4
1 UIM_DATA CH1 CH4 UIM_VPP
C634 1
1
0.1U_0402_16V4Z
1 1 Peak: 2.75A
2
+ C667
C637 1 C615 C612 Normal: 1.1A10_1206_5%
C666
+3VS
R662 1050mA 60mil+3VS_FULL
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 5
150U_B2_6.3VM_R35M 2 2 Vn Vp +UIM_PWR
2 2 2
2
4.7U_0805_10V4Z
3 6
UIM_CLK CH2 CH3 UIM_RST
JSIM
4 1
5 GND VCC 2 40mil
B VPP RST +UIM_PWR B
R702 6 3
UIM_VPP I/O CLK UIM_RST
C1325
EC_PME# UIM_DATA UIM_CLK
@ 0_0402_5% 8 7
C1324
JMINI2 GND GND 1
C428
C664
C665
1 2 1
C426
C427
1 2 1 1 1 1 1
EC_SWI# R701 0_0402_5% 1 2 @
3 4 +3VS_FULL @
3 4 @ @ @
56P_0402_50V8
5 6 CONN@
22P_0402_50V8J
2
56P_0402_50V8
56P_0402_50V8
5 6
0.1U_0402_16V4Z
1U_0402_6.3V4Z
22P_0402_50V8J
1 2 7 8 +1.5VS 2 2 2 2 2
7 8 +UIM_PWR 2
<26> CLKREQ_WWAN# R638 short@ 0_0402_5% 9 10 +UIM_PWR
9 10 UIM_DATA UIM_DATA @
11 12 2 1
13 11 12 14 UIM_CLK
<26> CLK_WWAN# C429 22P_0402_50V8J
15 13 14 16 UIM_RST
<26> CLK_WWAN
15 16 UIM_VPP
17 18
19 17 18 20
21 19 20 22 WWAN_OFF#
1 2 WWAN_OFF# <29,41>
23 21 22 24 PLT_RST#
23 24 R1375 short@ 0_0402_5%
<26> PCIE_PRX_C_WWANTX_N1 25 26 +3VS_FULL
27 25 26 28
<26> PCIE_PRX_C_WWANTX_P1 short@
27 28
29
29 30
30 11 22
31 32 MINI_SMBCLK R1433
R1432 0_0402_5% PM_SMBCLK
short@ 0_0402_5%
33 31 32 34 MINI_SMBDATA PM_SMBDATA
<26> PCIE_PTX_C_WWANRX_N1 33 34
<26> PCIE_PTX_C_WWANRX_P1 35 36
37 35 36 38 USB20_N12
37 38 USB20_N12 <28>
39 40 USB20_P12
1 2 USB20_P12 <28>
+3VS_FULL 41 39 40 42 R45 @ 10K_0402_5%
43 41 42 44
43 44
+3VS Up to 150MA, Default 8-10MA
A
45 46 A
47 45 46 48
short@ 47 48
R682 1 2 0_0402_5% 49 50
49 50
<41> E51_TXD R1333 1 2 0_0402_5% E51_TXD_R 51
51 52
52
1
<41> E51_RXD E51_RXD_R

short@
G3
G3
G2
G1
R683
100K_0402_5% ACES_88910-5204
56
55
54
53

CONN@
2
B
5 4 3 2 1
5 4 3
JMB388-QGAZ0A QFN 48P CARD READER 2 1
IC PWR +3VS
R11
1 2 +3VS_READER 0.1U_0402_16V4Z
IC Function Part 1 2
U4388@
Strap Pin Definition +3V_MCVCC
0_0805_5% C73 0.1U_0402_16V4Z 1 5

2 XRSTN APVDD 10 1 2
0.1U_0402_16V4Z
<BOM Structure> 1
40mil C83 1
C44
XTEST APV18 R12 10K_0402_5%
1 2
1 <6,28,34,35,36,39,41,42,44> PLT_RST# R141 100_0402_1% 19 +1.8VS_APVDD
C50 XRSTN# 3 SDCMD_MSBS_XDWE#
2 4 APCLKN DV33 20 1 2
2
APCLKP DV33 44 +3VS_READER R22 1K_0402_5%
DV33
C41,C43,C97 close U4 Pin5. 2 0.1U_0402_16V4Z 18 XDWP_SDWP
<26> CLK_PCIE_READER# 7 DV18 37
Pin5 -> 1000pF -> 0.1uF -> 10uF. <26> CLK_PCIE_READER APREXT DV18 1 2
C42 close U4 Pin10. 48 R17 1K_0402_5%
MDIO0 XD_RB
C77 close U4 Pin37. 47 +1.8VS_APVDD 2 385@ 1
APREXT: PCIE reference resistor 9
D
APREXT
15mil 8 APRXN MDIO1 46 R40 1K_0402_5%+3VS_READER D
C52close U4 Pin18. 8.2Kused in JMB385C; APRXP MDIO2 45
12Kused in JMB388A
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<26> PCIE_PTX_C_CARDRX_N5
JMB389 C MDIO3
MDIO4
43
42
XD_SD_MS_D0
XD_CD#
2 385@ 1
+1.8VS_APVDD 0.1U_0402_16V4Z XD_SD_MS_D1 R20
<26> PCIE_PTX_C_CARDRX_P5 MDIO5 41 2 385@ 1K_0402_5%
1
MDIO6 XD_SD_MS_D2 XD_CLE R18 1K_0402_5%
1 1 1 11 40XD_SD_MS_D3
40mil C42 C43 C97 12 APTXN MDIO7 29
SLE3
C41 1 1 APTXP MDIO8 2 385@ 1
C52 C77 1 2 28XDCE_SDCLK_MSCLK_R SDCD#
C53 MDIO9 SEL2 R31 1K_0402_5%
1
C80 2
0.1U_0402_16V7K 27
2 2 2 <26> PCIE_PRX_C_CARDTX_N5 MDIO10 1 2
C51 PCIE_PRX_CARDTX_N5
0.1U_0402_16V7K 26XD_CLE
10U_0805_10V4Z 2 MDIO11 25XD_D4 MSCD# R21 @ 200K_0402_5%
2 1000P_0402_50V7K <26> PCIE_PRX_C_CARDTX_P5 MDIO12
PCIE_PRX_CARDTX_P5 13 23XD_D5
10U_0805_10V4Z CPPE_N MDIO13 22XD_D6 XD_RE
0.1U_0402_16V4Z MDIO14 1 385@ 2
1 @ 2 6 XD_D7
APGND 24XD_RE R23 200K_0402_5%
<29> CR_PE# R24 0_0402_5%
CR_PE#_R GND 49XD_RB
D1 XD_ALE
GND 1 385@ 2
CH751H-40PT_SOD323-2 15 30XD_ALE
16 CR1_CD1N/WAKEN NC 31SEL1 R71 0_0402_5%
1 2 NC
CR1_CD0N 32
@ NC SLE3 SDCMD_MSBS_XDWE#
33TAV33 389@ R66 1 2 1 2
MSCD# NC 34TPB- C101 2.2U_0603_6.3V4Z
External Crystal XIN
<29> CR_WAKE#
R26
1 @ 2 SDCD#
17
NC
NC
35TPB+
36TPA-
389@ R65 11
385@ R63
2 0_0402_5%
2
0_0402_5%
0_0402_5%
0_0402_5% 21 CR1_PCTLN NC 38
R13 NC
1 2 40 mil CR1_LEDN 39TPA+ 1 388@ 2
TPBIAS C101 should be close to ChipSet for power
XOUT
NC source for SDA3.0 3.3/1.8v signaling
388@ 1M_0402_5% 14 R25 12K_0402_1%
MC_PWREN# NC APWR 1 2
X1 <43> 5IN1_LED# SEL2
C82 XIN 385@ 20_0402_5%
R74 1 385@ SDCMD_MSBS_XDWE#
1 3 JMB389-QGAZ0C QFN 48P R75 0_0402_5%
C XOUT
XD_CD#_R 2 1 C
7mil
IN OUT 1 XDWP_SDWP
2
22_0402_5% R37
7mil
2 4 389@ R78 0_0402_5%

C54 GND GND 0_0402_5%
389@ XDCE_SDCLK_MSCLK_R XDCE_SDCLK_MSCLK SEL1 2
1 385@ XDWP_SDWP
24.576MHZ_12PF_X3G024576FC1H 2 1 2
388@ 0_0402_5% R82 R80 0_0402_5%
0_0402_5% C82
2 2 388@ 1
389@ 15P_0402_50V8J R410 0_0603_5%
C54 1 1 2
388@
1
15P_0402_50V8J Note: TAV33 C76 +3VS_READER
0.1U_0402_16V4Z
2 389@ 1
388@ Colay With JMB385; W/1394, mount JMB388;WO/1394, mount JMB385. APWR
R412 0_0603_5% 2 385@ 1
R19 1 2
9.1K_0402_5%
CR_PE# and CR_WAKE reserve for D3 mode APREXT
R39 12K_0402_1%
JREAD
24.576MHz--main: SJ10000EV00 13 35
22 SD_VCC XD_D0 36
Memory Card Power 1394 Conn 7 IN 1 Conn
+3V_MCVCC
43 MS_VCC
XD_VCC
XD_D1
XD_D2
XD_D3
37
38
XD_SD_MS_D0
XD_SD_MS_D1
39 XD_SD_MS_D2
10 XD_D4 40 XD_SD_MS_D3
19 SD_CLK XD_D5 XD_D4
+3VS +3V_MCVCC SD_CMD 41
XDCE_SDCLK_MSCLK 1 XD_D6 42 XD_D5
2 SD_CD XD_D7 XD_D6
U49 @ SDCMD_MSBS_XDWE#
1 8 SDCD# 4 SD_WP XD_D7
26
2 GND OUT 7 40mil R29 XDWP_SDWP 3 SD/MMC_DAT0 XD_CD 27
IN OUT 56_0402_5% @ D20 25 SD/MMC_DAT1 XD_R/B XD_CD#
3 6 XD_SD_MS_D0 28
IN OUT 388@ 2 SD/MMC_DAT2 XD_RE XD_RB
4 5 XD_SD_MS_D1 23 29
EN# FLG 10mil 1 SD/MMC_DAT3 XD_CE XD_RE
B MC_PWREN# XD_SD_MS_D2 21 30 B
1
1
1 3 MMC_DATA4 XD_CLE XDCE_SDCLK_MSCLK

TPS2061DRG4_SO8 C95 XD_SD_MS_D3 17 31
1
R1676 @ MMC_DATA5 XD_ALE XD_CLE

1
R27 R28 XD_D4 8 32

2
300_0603_5% 220P_0402_50V7K
388@ 4.99K_0402_1%
388@
56_0402_5% CloseR411to@ Chip
0_0402_5% PJDLC05C_SOT23-3 XD_D5
XD_D6
5 MMC_DATA6
MMC_DATA7
XD_WE
XD_WP
33 XD_ALE
SDCMD_MSBS_XDWE#
2 388@
2WCM-2012-900T_4P 1 XD_D7 7 XDWP_SDWP
2
2
2 1 SD_GND
12 15
2
L2 388@ MS_DATA0 SD_GND

2
1
D TPB- JP6 11 6
3 4 1 XD_SD_MS_D0 14 MS_DATA1 MS_GND 24
2 Q116 @ 3 4 MS_DATA2
MC_PWREN# 2 1 XD_SD_MS_D1 18 MS_GND 34
G 2N7002_SOT23 MS_DATA3 XD_GND
TPB+ 3 2 XD_SD_MS_D2 20 44
S 3 MS_SCLK XD_GND
3
1 @ 2 4 XD_SD_MS_D3 16 45
4 XDCE_SDCLK_MSCLK 9 MS_INS GND 46
R48 0_0402_5%
5 MSCD# MS_BS GND
1 @ 2 GND1 SDCMD_MSBS_XDWE#
6 TAITW_R013-P12-HM_NR
R43 0_0402_5% GND2
CONN@
2 388@ 1 2 1 FOX_UV31413-WR50D-7F~N
1 2 +3V_MCVCC 10mil
R32 2 388@ 1
56_0402_5% TPA-
2 1
D7@
1
MC_PWREN#
C1962
R1677 0_0805_5%
C1959 1 C1960 1
C1961 1 R38 56_0402_5%
3
3
L1
4
388@
4 CONN@ 2 Card Detect
1
1 2
TPBIAS TPA+ WCM-2012-900T_4P 2 SDCD# R33 0_0402_5%
4.7U_0805_10V4Z 10U_0805_10V4Z @ D21 3 XD_CD#_R
2 1 XD_CD# 2
2 2 0.1U_0402_16V4Z C100
1 @ 2 2 C49 MSCD#
2 R46 0_0402_5% DAN202UT106_SC70-3
0.1U_0402_16V4Z 0.33U_0603_10V7K 1 22P_0402_50V8J 2 C96
3 1 @ 2
388@ 0.1U_0402_16V4Z
2 C99 C98 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z
PJDLC05C_SOT23-3 1 1
A A
Note:
if use external PWR and change
+3V_MCPWR as control signal, Need BIOS
to change the Setting. SCHEMATICS, MB A8581
B
5 4 3 2 1
5 4 3 2 1
0.1U_0402_16V4Z
1 RA2
0_0603_5% RA1 CA57 2 1 1
1 2 1BLM18PG181SN1D_0603CA44
RA32 0_0603_5% +PVDD1 1 +5VS
2 1
600 mA
+3VS_DVDD 2 CA56
2
2 CA43
1 2
+3VS +3VS JA1
2
1 135 mA +DVDD_IO 2
1 CA2 JUMP_43X39 10U_0805_10V4Z
CA7 10U_0805_10V4Z
CA8 CA1 10U_0805_10V4Z
1
RA34 2 @
@ 0_0402_5% 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 0.1U_0402_16V4Z
2
1
place close to chip
RA12
DVT NOT POP RA12, USE0.1U_0402_16V4Z
JA1
place close to chip 2 1
Ext. Mic/LINE IN 1 2 place close to chip 1 +5VS
RA3 +PVDD2 1 1BLM18PG181SN1D_0603 1
D MIC1_LINE1_R_R CA9 4.7U_0603_6.3V6K +AVDD 0.1U_0402_16V4Z CA60 CA59 CA58 D
MIC1_LINE1_R 0.1U_0402_16V4Z 2 1
10U_0805_10V4Z CA61 @ @ @
0_0603_1%
MIC1_LINE1_R_L U143 68 mA +5VS 2 2 2
@ 1 2 2
CA10 4.7U_0603_6.3V6K 1 1 10U_0805_10V4Z 10U_0805_10V4Z
MIC1_LINE1_L 22 1 1 1 CA6
RA25 RA39 CA26 MIC1_R DVDD 9
21 CA3 CA4 CA5
1K_0402_5%
0_0402_5% 1U_0402_6.3V4Z MIC1_L DVDD_IO
1 2 1 2 25
17 2
MIC2_R AVDD1 38 2 2 2
16 AVDD2
MIC 1 2 MIC2_L
1 2 MIC2R_R MIC2_R 10U_0805_10V4Z 0.1U_0402_16V4Z
MIC2R_L MIC2_L 31 39
CA28 MIC1_VREFO_L PVDD1 46
RA26 30
1U_0402_6.3V4Z +MIC1_VREFO_L 29 MIC1_VREFO_R PVDD2
1K_0402_5% +PVDD1 place close to chip placement
+MIC1_VREFO_R
MIC2_VREFO
+PVDD2 RA13near Audio Codec
+MIC2_VREFO 15 45 2 1
SPK_OUT_R+
14 LINE2_R
LINE2_L SPK_OUT_R-
44
SPKR+
SPKL- 0_0603_1%
short@
1 SPK_L-
Speaker Connector
DA8
2
SPKR- CA19 10U_0805_10V4Z
1U_0603_10V6K
40 @
1
20
CA42
MONO_OUT SPK_OUT_L+ 41 2 1 3
SPK_OUT_L- 30MIL/30MIL @
1 2 12 SPKL+ 1
PCBEEP_IN PESD5V0U2BT_SOT23-3
CA12 100P_0402_50V8J RA4 75_0402_1%
SPKL- RA14 JSPK
MONO_IN 10 33 CA46 10U_0805_10V4Z 2
SYNC HPOUT_R 2 1 1
32 @ 2 1
11 HPOUT_L 0_0603_1% short@
2 2
<25> AZ_SYNC_HD AZ_SYNC_HD RA5 75_0402_1% HP_R 3
RESET# SPKL+ SPK_L+ SPK_R- 3
HP_L 4
<25> AZ_RST_HD# 5 RA15 SPK_R+ 4
SDATA_OUT 2 1 2 1
20K_0402_1% 1 RA10 2 8 1 SPK_L-
SDATA_IN RA6 33_0402_5% 0_0603_1% SPK_R-
C 19 AZ_SDOUT_HD AZ_SDOUT_HD <25> SPKR- SPK_L+
DA9 C
JDREF short@ CA51 10U_0805_10V4Z ACES_85204-0400N
CA35 2 110U_0805_10V4Z 28 LDO_CAP
6 AZ_SDIN0_HD_R AZ_SDIN0_HD <25> 2
1U_0603_10V6K
AC_JDREF 27 BITCLK @
2 1
CA45
34 VREF 1 CONN@
CPVEE @ AZ_BITCLK_HD
@ <25> 3
AC_VREF 35 RA7 CA23 1 @
2.2U_0603_6.3V4Z 2 1CA14 24
1 1 2 CPVEE 36 CBN NC 23
2 CBP NC CA39 10U_0805_10V4Z PESD5V0U2BT_SOT23-3
CA16 48
CA17 CA18 NC RA44 @ 2
2.2U_0603_6.3V4Z 2.2U_0603_6.3V4Z 10_0402_5% 10P_0402_50V8J 2 1 2
2 2 0_0603_1%
1 3 GPIO0/DMIC_DATA 26
0.1U_0402_16V4Z DMIC_DATA GPIO1/DMIC_CLK AVSS1 SPKR+ short@ SPK_R+
<23> DMIC_DATA 37
<23> DMIC_CLK1 2 DMIC_CLK AVSS2
PVSS1
42 AGND
RA18 20K_0402_1% 13 43
MIC_SENSE 1 2 SENSE_A PVSS2 7 Close to Audio Chip
18
place close to chip NBA_PLUG
RA16 39.2K_0402_1% SENSE_A
47
SENSE_B DVSS
Head Phone JACK
EAPD JHP
4 49 1
EAPD PD# THERMAL_PAD
<41> EAPD LA3 2
<41> EC_MUTE# EC_MUTE# 6
ALC259-VB5-GR_QFN48_7X7
DGND FBMA-L11-160808-121LMT_0603
1
LA4
2 3
HP_L FBMA-L11-160808-121LMT_0603 HP_L_L AGND
1 2 1 1
MIC+MIC2_VREFO
CONN RA51
CA47 1 2 0.1U_0603_50V7K HP_R
CA11
HP_R_R
CA13
4
4.7K_0402_5% CA48 1 2 0.1U_0603_50V7K 100P_0402_50V8J NBA_PLUG 5

100P_0402_50V8J
2 1 2 2@
@
SINGA_2SJ-S351-013
CONN@ CA49 1 2 0.1U_0603_50V7K
JMIC CA50 1 2 0.1U_0603_50V7K
D9 CONN@
B DA10 1 B
MIC 2 1 1 2 3
2 2
1 RA43 0_0603_5% 1
3 2
3 GND
4 @
GND
PESD5V0U2BT_SOT23-3 PACDN042Y3R_SOT23-3
ACES_88231-02001
2 RA48 1
RA47 4.7K_0402_5%
1K_0402_5% +MIC1_VREFO_R
2 1
Beep sound
MIC1_LINE1_R_R
MIC1_LINE1_R_L
2 1 MIC1_R
MIC1_L
Ex.MIC JACK
1 RA8 2 1K_0402_5%
EC Beep 47K_0402_5% LA2
RA45 2 RA46 1
4.7K_0402_5% +MIC1_VREFO_L JEMIC
Sense Pin Impedance Codec Signals Function <41> EC_BEEP# FBMA-L11-160808-121LMT_0603
1 2
1
2
MIC1_L MIC1_L_L AGND 6
39.2K PORT-A (PIN 39, 41) Headphone out 1 2 3
1 RA9 2 MIC1_R
1 1MIC1_R_R
PCI Beep 47K_0402_5%
CA15
1 2 MONO_IN
LA8
FBMA-L11-160808-121LMT_0603
CA22 MIC_SENSE 4
20K PORT-B (PIN 21, 22) CA21
Ext. MIC <25> PCH_SPKR
100P_0402_50V8J 100P_0402_50V8J
SENSE A 0.1U_0402_16V4Z
@ 2 2@ 5
1
10K PORT-C (PIN 23, 24) 1 SINGA_2SJ-S351-012

CONN@
RA11 CA20 D10
5.1K PORT-D (PIN 35, 36) 10K_0402_5% 3
0.1U_0402_16V4Z
2 1
2
A A
2
39.2K PORT-E (PIN 14, 15) @
PACDN042Y3R_SOT23-3
20K PORT-F (PIN 16, 17)
SENSE B Security Classification Compal Secret Data Compal Electronics, Inc.
10K PORT-H (PIN 37)
5.1K PORT-I (PIN 32, 33) B
5 4 3 2 1
5 4 3 2 1
Express Card U52

12 PWR Switch
1.5Vin 1.5Vout
11 +3VALW_CARD +3VS_CARD +1.5VS_CARD New Card Socket (Left/TOP)
0.1U_0402_16V4Z
14 13 +1.5VS JEXP1
1.5Vin 1.5Vout 1 +3VS +3VALW_PCH
10U_0805_10V4Z
1 1
40mil Imax = 0.275A Imax =C2030
1.35A Imax = 0.75A
0.1U_0402_16V4Z
1
10U_0805_10V4Z
+1.5VS +1.5VS_CARD 1 C2029 GND
0.1U_0402_16V4Z
10U_0805_10V4Z
C2027 C2028 1 2
2 3 C2031 1 1 1 1 3 USB_D-
3.3Vin 3.3Vout C2032 C2034 C2035 C2036 USB20_R_N8 USB_D+
4 5 2 4
3.3Vin 3.3Vout 2 2 CPUSB#
2 USB20_R_P8 5
+3VS 17 15
60mils +3VS_CARD 2 10U_0805_10V4Z 10U_0805_10V4Z10U_0805_10V4Z CP_USB# RSV
2 2 2 2 6
AUX_IN AUX_OUT RSV
7
6 19 8 SMB_CLK
+3VALW_PCH SYSRST# OC# 40mil +3VALW_CARD R102 <11,12,26,36> PM_SMBCLK SMB_DATA
1 2 9
20 8 <11,12,26,36> PM_SMBDATA 10 +1.5V
PLT_RST# SHDN# PERST# 0_0402_5% +1.5VS_CARD +1.5V
<6,28,34,35,36,37,41,42,44> PLT_RST# 11
D 1 16 12 WAKE# D
STBY# NC R100
<41,45,52> SYSON SYSON PERST1# <27,35,36> EC_SWI# 13 +3.3VAUX
1 2 +3VALW_CARD
10 7 +3VS 14 PERST#
CPPE# GND @ 0_0402_5%
<10,41,45,50,51,52,57> SUSP# SUSP# PERST1# 15 +3.3V
9 21 +3VS 1 <35,36,41,42> EC_PME# +3VS_CARD 16 +3.3V
CPUSB# Thermal_Pad C2033 CLKREQ#
CP_PE# +3VS 17
1
(Internal Pull High to AUXIN) 18 CLKREQ1# 18 CPPE#
RCLKEN 0.1U_0402_16V4Z REFCLK-
CP_USB# R1727 2 <28> CP_PE# CP_PE# 19
1
(Internal Pull High to AUXIN) 10K_0402_5% <26> CLK_PCIE_EXPCARD# 20 REFCLK+
5
RCLKEN1 G577NSR91U_TQFN20_4x4 R1726 U53 <26> CLK_PCIE_EXPCARD GND
21
10K_0402_5% 2 22 PERn0
G Vcc
B
2
4 <26> PCIE_PRX_C_EXPTX_N3 23 PERp0
CLKREQ1# 1 Y <26> PCIE_PRX_C_EXPTX_P3 GND
24
1 2
A PETn0
D CLKREQ_EXPCARD# <26> 25
NC7SZ32P5X_NL_SC70-5 <26> PCIE_PTX_C_EXPRX_N3 26 PETp0
3
2 Q118 R59 0_0402_5%
<26> PCIE_PTX_C_EXPRX_P3 GND
G 2N7002_SOT23 1 2 27
RCLKEN1 S 28 GND
3
WCM-2012-900T_0805 29 GND
4 3 30 GND
4 3 GND
1 2
1 2 USB20_R_N8 CONN@
<28> USB20_N8
L26
@ USB20_R_P8
<28> USB20_P8
1 2
R84 0_0402_5%
C C
This pin1 define need check JSMART

1
+SC_PWR 2 1
3 2
3
0.1U_0402_10V6K
4
1 5 4
Smart Card SC_RST
CS32
6 5
1 2 SM@ SCard0C6 6
SC_CLK 7
RS14 0_0402_5% 8 7 +3V_SC +3V_SC +5VS +5VS
Layout note: Close to PIN14
CS18to PIN18
Close to PIN13

2 SC_DATA 8 +SC_PWR +1.8V_SC
SM@ 9 +3V_SC
Close to PIN15

SCard0Fcb
1U_0402_6.3V4K
9
1U_0402_6.3V4K
0.1U_0402_10V6K
1U_0402_6.3V4K
10
0.1U_0402_10V6K
0.1U_0402_10V6K
0.1U_0402_10V6K
1 2 SCard0C8 10 1
0.1U_0402_10V6K
1 1
0.1U_0402_10V6K
ICCInsertN 11 1 1 1 1
CS31
CS30
CS21
GND
1U_0402_6.3V4K
RS20 0_0402_5% 1
CS22
12
CS25
SM@
SM@ 1
SM@
CS24
SM@
CS26
GND SM@
CS28
1
Layout note: Close

SM@ SM@ SM@
CS17
SM@ SM@ SM@
ACES_88514-104N 2 2 2 2
@ 2 2 2
CONN@ 2 2
3 4
Layout note:
3 4 2
Layout note:
<28> USB20_N5 USB20_N5
USB20_N5_R
2 1
2 1 USB20_P5_R
<28> USB20_P5 USB20_P5
LS2
WCM2012F2S-900T04_0805
B B
+3V_SC
1
RS22
10K_0402_5% +3V_SC SC_XTAL_In 1 SM@ 2
US4 SM@ RS15 1M_0402_5%
1
SC_XTAL_Out YS2
2
1 28 RS16 12MHZ_16PF_X5H012000FG1H-X
SCard0C8 SCard0C8 XO 27 SC_XTAL_Out
2 100K_0402_5%
1
XI
0.1U_0402_10V6K
1
SCard0C6 SCard0C6 26
47K_0402_5%
3 SC_XTAL_In
47K_0402_5%
SM@ 1 2
1
PWRSV_SEL 2 1
47K_0402_5%
SCard0Fcb 4 SCard0Fcb 25 1 1 2
RS21 @
CS20
SMIO_5VPWR LEDCRD
2
24
2 RS17
+5VS
2 RS19
5 10K_0402_5%
1U_0402_6.3V4K
LEDPWR
2 RS11
SC_RST 2 RS18 1 0_0402_5% 6 SCard0Rst 23
SCard0Clk RESET 1 @ SM@
SC_CLK 2 7 22
18P_0402_50V8J
RS13 1470_0402_5%
18P_0402_50V8J
EEPDATA 2 SM@
SC_DATA SM@ 8 SCard0Data 21 SC_SDA
1 CS16 1 CS23
CS29
USB20_N5_R 9 DM EEPCLK 20 SC_SCL @

RS12 SM@ DP P1(6) SM@ US3 @
2 1 USB20_P5_R 10 19 EEPWP 2
AV33 ICCInsertN 1 8 SM@
+3V_SC 11 18 ICCInsertN A0 VCC SM@
+SC_PWR SC_DATA_R +SC_PWR 12 SCPWR0 VDDH 17 +3V_SC 2 7 2
4.7K_0402_5% A1 WP 2
13 5VGND VDDP 16 +1.8V_SC 3 EEPWP 6
SM@ 5VInput VDD 4 A2 SCL 5
+5VS 14 15 SC_SCL SDA
V33OUT V18OUT GND
+3V_SC SC_SDA
@ AT24C02BN-SH-T_SO8
AU9540B55-GBS-GR
SM@ PWRSV_SEL: (Default high)
High: Normal mode,
Low: Power Saving Mode
A A
MP: to solve issue of "Smart Card also show in Device Manager

after plug out it", change US4 from SA000042I00 to SA000042I10.
B
5 4 3 2 1
5 4 3 2 1
UU1
+5VALW 1 8 +USB_VCCB
2 GND VOUT 7
KEYBOARD CONN. 2.5A VIN VOUT
1000P_0402_50V7K
4.7U_0805_10V4Z
0.1U_0402_16V4Z
3 6
2
1For EMC VIN VOUT RU7 @ 0_0402_5%
JKB 4 5 W=100mils <28> USB3_RX0_P U3RXDP0_L
4.7U_0805_10V4Z
CU4
CU2
C803 100P_0402_50V8J EN FLG
CU3
KSO10 1 LU2 WCM-2012-121T_0805
11 @ 22 1 G547E2P11U
CU1
2 4 3
0.1U_0402_16V4Z
C805
C804 100P_0402_50V8J
100P_0402_50V8J 3 2 4 3
CU6
KSO11 3
KSO0 4
0.1U_0402_16V4Z
@
@ 4
KSO12 KSO1 5 @ 1 2
1 2 KSO2 6 5 1 2
1
1000P_0402_50V7K
C807 100P_0402_50V8J 7 6 @
KSO15 KSO3 RU6 @ 0_0402_5%
1 @ 2 KSO4 8 7
C8081 2
100P_0402_50V8J 8 @ RU27 U3RXDN0_L
KSI7 KSO5 9 2 1 C13 <28> USB3_RX0_N
C3606
D C810 @ 100P_0402_50V8J KSO6 10 9 2 D
10 0_0402_5%
1 2 @
KSI2 KSO7 11
1 @ 2 12 11 <6,11,43,45> SUSP R90 0_0402_5% USB_OC0# USB_OC0# <28>
KSO8
C8111 100P_0402_50V8J
2 KSO9 13 12
KSI3 1 2
C812 @ 100P_0402_50V8J KSO10 14 13 <43,45> SYSON#
15 14 R91 @ 0_0402_5% USB_OC4# <28,43>
KSI4 KSO11
1 @ 2 KSO12 16 15
C813 100P_0402_50V8J KSO13 17 16
KSI0
KSO14 18 17 CU11
1 @ 2 1 2
KSO15 19 18
KSI5 C8141 2
100P_0402_50V8J +USB_VCCB
KSI7 20 19 RU5 @ 0_0402_5%
2
C8151 @ 100P_0402_50V8J 20 JUSB31 CONN@
KSI6 KSI6 21 9 <28> USB3_TX0_P 0.1U_0402_16V7K
USB3_TX0_P_C U3TXDP0_L
C816 @ 100P_0402_50V8J
150U_B2_6.3VM_R35M
KSI5 22 21 U3TXDP0_L 1 SSTX+ LU1 WCM-2012-121T_0805
KSI1 1 @ 2 KSI4 23 22 8 VBUS 4 3
C793 100P_0402_50V8J KSI3 24 23 1 U3TXDN0_L SSTX- 4 3
3
CU5
1 @ 2 KSI2 24 USB20_P0_L 7 D+
KSO2 + GND
C7901 100P_0402_50V8J
2 KSI1 2 1 2
KSI0 USB20_N0_L D- CU12 1 2
KSO1 C791 @ 100P_0402_50V8J 6 1 2
25 U3RXDP0_L 4 SSRX+
2 10 RU4 @ 0_0402_5%
@ 26 GND1 GND GND USB30_GND
KSO0 1 2 5 11
GND2 U3RXDN0_L SSRX- GND USB30_GND 0.1U_0402_16V7K
USB3_TX0_N_C U3TXDN0_L
C7921 100P_0402_50V8J <28> USB3_TX0_N
2
KSO4 ACES_85208-24071 SANTA_371394-1 RU2
C795 @ 100P_0402_50V8J
0_0603_5%
KSO3 1 @ 2
C796 100P_0402_50V8J CONN@
1 2
KSO5
C797 @ 100P_0402_50V8J DU1
KSO14 @ 2 1 1 109
1
C C
C7981 100P_0402_50V8J
2 U3RXDN0_L 2 2 U3RXDN0_L
98
KSO6 RU9 @ 0_0402_5%
C799 @ 100P_0402_50V8J
U3RXDP0_L 4 4 U3RXDP0_L
77
KSO7 DU2
1 @ 2 USB20_N0 USB20_N0_L
C800 100P_0402_50V8J KSI[0..7] KSI[0..7] <41,43> <28> USB20_N0
2 U3TXDN0_L U3TXDN0_L
KSO13 5 5 66
1 @ 2 KSO[0..15] KSO[0..15] <41,43>
3 4 1
C801 100P_0402_50V8J 3 4 USB20_P0_L 3 U3TXDP0_L U3TXDP0_L
KSO8 3 3
1 @ 2
C802 100P_0402_50V8J 2 1 USB20_N0_L YSDA0502C 3P C/A SOT-23 8
KSO9 2 1
@ LU3 WCM-2012-900T_0805 L15ESDL5V0NA-4 SLP2510P8
RU8 @ 0_0402_5%
<28> USB20_P0 USB20_P0 USB20_P0_L
Lid SW Finger Print Screw Hole H2 H6 H16 H18

+3VS_FP H4 H1 H8 H9 H33
+3VL H3 H7
U34 1 2
APX9132ATI-TRL_SOT23-3 1 1
1
R62 0_0603_5%
1
1
1
C128 C122
1
1
+3VS +3VS_FP
1 2
1
2 3 R69 @ 0_0603_5% @ @ @ @
GND
VDD VOUT 0.1U_0402_16V4Z 1U_0402_6.3V4Z @ @ @ @ @

LID_SW# <41> 2 2
+3VALW H_3P0 @ H_3P0 @ H_3P0 H_3P0 H_3P0 H_3P0 H_3P0X5P0N
1 H_3P0 H_3P0
H_3P0 H_3P0
1
1
B B
C645
0.1U_0402_16V4Z C647
2 0.1U_0402_16V4Z
2
+3VS_FP
R160
1
0_0402_5%
2
Break hole CPU JWLAN VGA H26 H13
H21 H12 H10
H19 H11 H32
WCM-2012-900T_0805 JFP
H31 H30
Kill Switch 4 3 1
1
1
4 3 2
1
1
1
1
<28> USB20_N11 2
1
1
1
USB20_R_N11 3
4 3
1
+3VALW @
1
1 2 USB20_R_P11 @ @
1 2 4 @ @ @ @ @
<28> USB20_P11 H_4P5 H_4P5 H_4P5
L56 @ @ @ H_4P5 H_4P5 H_4P5 H_4P5 H_3P0N
E&T_6905-F04N-00R H_2P3
1 2 H_2P3
CONN@
3
R159 0_0402_5%
D24 +3VALW
2
@ R580
DAN217_SC59 H25 H24
Diode added on Finger Print small board H23 H22
100K_0402_5%
1
USB20_R_N11
PCB Fiducial Mark PAD
1
1
FD3
1
KILL_SW# USB20_R_P11 FD2 FD4
1
KILL_SW# <41> FD1
3
D15 @
@ @ @ @ @
@ @
A H_3P3 H_3P3 H_3P3 A
1
1
1
H_3P3
1
PJDLC05_SOT23-3
3
2
1
3
2
1
SW5
1

1BS003-1211L_3P
B
5 4 3 2 1
5 4 +3VALW_EC +3VL +3VALW_EC 3 +EC_VCCA 2 1
LE1
+3VL R745
R746 0.1U_0402_16V4Z 2 0.1U_0402_16V4Z H_PROCHOT# <6,47>
0_0805_5% 1 1 1 2 <54> VR_HOT#
0_0805_5% @ VR_HOT#
C770 1 C771
1
FBMA-L11-160808-800LMT_0603 D
0.1U_0402_16V4Z C775 ECAGND <47>
+3VALW C772 ECAGND 2
1 2 1000P_0402_50V7K
2 2 1 G
<47> H_PROCHOT#_EC
2 H_PROCHOT#_EC Q38 S
0.1U_0402_16V4Z C773 C774
3
0.1U_0402_16V4Z 2N7002_SOT23
125
R731 1 2 10K_0402_5%
111
2 1000P_0402_50V7K
1
96
67
+3VS
EC_VDD/VCC 33
22
1 2
9
UE1 R725 1 2 10K_0402_5%
EC_VDD/VCC
R733 100K_0402_5%
EC_VDD0
EC_VDD/VCC
EC_VDD/AVCC
WWAN_OFF_EC#
EC_VDD/VCC
EC_VDD/VCC
WL_OFF_EC# PWR_GPS_DOWN_R#
@
@
R732 1 2 10K_0402_5%
1
1 21 R730 1 2 10K_0402_5%
GATEA20/GPIO00 GPIO0F 23 EC_GPS_DOWN#
D R738 2 D
KBRST#/GPIO01 BEEP#/GPIO10 26 WWAN_OFF_EC# R734 0_0402_5%
@ 10_0402_5% <29> GATEA20 3
SERIRQ GPIO12 27 R724 1 2 10K_0402_5%
CLK_PCI_EC <29> KB_RST# GATEA20 4 EC_BEEP# <38>
LPC_FRAME# ACOFF/GPIO13 PM_SLP_A# <42> @
<25,34,44> SERIRQ KB_RST# 5 EC_BEEP#
PM_SLP_A# PCH_HOT#_R
PWR_GPS_DOWN# <13,57>
2
<25,34,44> LPC_FRAME# SERIRQ 7 LPC_AD3 PWR_GPS_DOWN_R#

1 LPC_FRAME# 8 LPC_AD2 PWM Output 63
<25,34,44> LPC_AD3 BATT_TEMP/GPIO38 64 BKOFF#
LPC_AD3 10 LPC_AD1
C787 <25,34,44> LPC_AD2 LPC & MISC GPIO39 65 --Add net "PWR_GPS_DOWN#" for EC pin27
LPC_AD2 LPC_AD0 BATT_TEMPA <47> +5VS
<25,34,44> LPC_AD1 ADP_I/GPIO3A
@ 22P_0402_50V8J
<25,34,44> LPC_AD0 LPC_AD1 12
66 BATT_TEMPA
Project_ID R4934 as power circuit modified --Joyce 0224/2012
0_0402_5% R740 4.7K_0402_5%
2 AD Input GPIO3B 75 1 1 2 2
LPC_AD0 13 CLK_PCI_EC GPIO42 ADP_I <47,48>
37 PCIRST#/GPIO05 76 ADP_I R741 4.7K_0402_5%
<28> CLK_PCI_EC EC_RST# IMON/GPIO43 Board_ID new added pin --Joyce 0922-2011
CLK_PCI_EC 20 PCH_HOT# <26> TP_CLK
<6,28,34,35,36,37,39,42,44> PLT_RST# PCH_HOT#_R
GREEN_PWR4 <48> PCH_HOT#
@ R761 PLT_RST# 38 EC_SCII#/GPIO0E GREEN_PWR4
GPIO1D 68 TP_DATA
1 2 <29> EC_SCI# ECRST#
EC_SCI# DAC_BRIG/GPIO3C 70
<35,36,39,42> EC_PME# +3VL
10K_0402_5% EC_PME# EN_DFAN1/GPIO3D 71
R739 47K_0402_5% EC_GPS_DOWN# EC_GPS_DOWN# <13>
2
+3VALW_EC 1 DA Output IREF/GPIO3E--Delete
72 net "PWRMOS_TEMP", add net "GREEN_PWR4"for EC pin 76 as power circuit modified R1210
--Joyce
1 0302/2012
2 10K_0402_5%
+3VALW @ R768 55 EN_DFAN1 <6>
1 2 EC_PME# 56 KSI0/GPIO30 CHGVADJ/GPIO3F BT_PWRON <36> --Add net "EC_GPS_DOWN#" to EC pin68 1 2
EN_DFAN1
BT_PWRON
2 1 10K_0402_5% 57 KSI1/GPIO31
TP_ON/OFF# TP_ON/OFF# <43> --Joyce 0224/2012 Ra 100K_0402_5%
KSI2/GPIO32 83 1 2 LID_SW# 1 2
C789 0.1U_0402_16V4Z +3VL KSI0 58
KSI3/GPIO33 EC_MUTE#/GPIO4A 84 R1211 10K_0402_5% Rb VPRO@ 100K_0402_5%
ECRST# KSI1 59 EC_MUTE#
KSI4/GPIO34 USB_EN#/GPIO4B 85 Board_ID
2 1 KSI2 60
KSI5/GPIO35 CAP_INT#/GPIO4C 86 EC_MUTE# <38>
KSI3 61 USB_EN# <44>
0_0402_5% @ R767 KSI6/GPIO36 PS2 Interface EAPD/GPIO4D 87 EC_MUTE#
KSI4 62 TP_LED# <43> Rb
<29,35> GPIO27_WAKE# KSI7/GPIO37 TP_CLK/GPIO4E 88 USB_EN#
TP_LED#
EC_PME# KSI5 39 EAPD EAPD <38> 56K_0402_5%
KSI6 KSO0/GPIO20 TP_DATA/GPIO4F Rb Rb
40 TP_CLK <43> Rb Rev10@
KSI7 KSO1/GPIO21 8.2K_0402_5% 18K_0402_5% 33K_0402_5%
41 TP_CLK TP_DATA <43>
KSO0 KSO2/GPIO22 97 2 1 Rev02@ Rev03@ Rev04@
42 CPU1.5V_S3_GATE/GPXIOA00 98 TP_DATA
KSO1 43 KSO3/GPIO23 R765 0_0402_5%
<40,43> KSI[0..7] KSI[0..7] WOL_EN/GPXIOA01 99
KSO2 44 KSO4/GPIO24 CPU1.5V_S3_GATE <10> @
When use EC_PME#, should pull HDA_SDO/GPXIOA02 109CPU1.5V_S3_GATE
KSO3 45 KSO5/GPIO25 Int. K/B VSB_EN_R VSB_EN VSB_EN <47>
<40,43> KSO[0..15] KSO[0..15] up to +3VL: if pull up to +3VALW, VCIN0_PH/GPXIOD00
KSO4 KSO6/GPIO26 Matrix
由 Board_ID去去去去去去去 VPRO的的的；
the system will auto resume when 46 HDA_SDO HDA_SDO <25>
KSO5 47 KSO7/GPIO27 SPI Device Interface VCIN0_PH <47>
由 Project_ID去去去 Tongfang與1030, UMA2與 Op0mus。
C C
plug in AC at DC mode. KSO6 KSO8/GPIO28 119 VCIN0_PH 2 1
48 SPIDI/GPIO5B 120 0_0402_5% R766
KSO7 49 KSO9/GPIO29 SPIDO/GPIO5C +3VL
1 2 KSO10/GPIO2A 126
KSO8 50 SPICLK/GPIO58 VSB_EN PCH_PWR_EN_R Rc 100K_0402_5%
R755 2.2K_0402_5% KSO9 KSO11/GPIO2B SPI Flash ROM 128
51 SPICS#/GPIO5A 1 @ 2
KSO10 52 KSO12/GPIO2C 1 2
+3VL 1 2 Project_ID Rd 100K_0402_5%
KSO11 53 KSO13/GPIO2D R818 @ 100K_0402_5%
VSB_EN_R
R756
1 2.2K_0402_5%
2
EC_SMB_CK1 KSO12 54 KSO14/GPIO2E 73 Rd Rd Rd Rd
R758 2.2K_0402_5% KSO13 81 KSO15/GPIO2F ENBKL/GPIO40 74 33K_0402_5%
0_0402_5% 8.2K_0402_5% 18K_0402_5%
KSO14 82 KSO16/GPIO48 PECI_KB930/GPIO41 89 PCH_ENBKL PCH_ENBKL <27> 13@
EC_SMB_DA1
FSTCHG/GPIO50 10@ 11@ 12@
+3VS KSO15 KSO17/GPIO49 90 KILL_SW# <40>
WL_OFF_EC# BATT_CHG_LED#/GPIO52 KILL_SW#
1 2 EC_SMB_CK2 <27> SLP_A# SLP_A# 91 PWR_USB_EN# <44>
CAPS_LED#/GPIO53 PWR_USB_EN#
R759 2.2K_0402_5% 77 92
EC_SMB_DA2 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 93 BATT_FULL_LED# BATT_FULL_LED# <43>
78 GPIO CAPS_LED# <44> Rd
79 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 95CAPS_LED# PWR_ON_LED <43>
<47,48> EC_SMB_CK1 PWR_ON_LED 56K_0402_5%
EC_SMB_CK1 80 EC_SMB_CK2/GPIO46
SM Bus SYSON/GPIO56 121 BATT_CHG/LOW_LED# <43>
<47,48> EC_SMB_DA1 VR_ON/GPIO57 BATT_CHG/LOW_LED# 12RM@
EC_SMB_DA1 EC_SMB_DA2/GPIO47 127
To battery
@ & charger<13,26> EC_SMB_CK2 EC_SMB_CK2 PM_SLP_S4#/GPIO59 SYSON <39,45,52> Project_ID Rd Vmin Vtype Vmax
1 2 <13,26> EC_SMB_DA2 SYSON VR_ON <54>
EC_SMB_DA2 VR_ON
R819 To PCH & VGA
100K_0402_5% PM_SLP_S4# <27>
100PM_SLP_S4# Rd
+3VALW 1 2 6 EC_RSMRST#/GPXIOA03 101 100K_0402_5%
0 (QAQ10) 0 0V 0V 0.155V
R817 100K_0402_5% 14 PM_SLP_S3#/GPIO04 EC_LID_OUT#/GPXIOA04
<27> PM_SLP_S3# PM_SLP_S5#/GPIO07 102 13RM@ 1 (QAQ11) 8.2K+/-5% 0.168V 0.250V 0.362V
2 1 PM_SLP_S3# 15 PROCHOT_IN/GPXIOA05 PCH_RSMRST# <27>
<27> PM_SLP_S5# EC_SMI#/GPIO08 103 PCH_RSMRST#
0_0402_5% R754 PM_SLP_S5# 16 H_PROCHOT#_EC/GPXIOA06 LID_SW_OUT# <29>
<29> EC_SMI# GPIO0A 104 LID_SW_OUT# VCIN1_PH <47> 2 (QAQ12) 18K+/-5% 0.375V 0.503V 0.621V
EC_SMI# 17 VCOUT0_PH/GPXIOA07 VCIN1_PH
<45> PCH_PWR_EN PCH_PWR_EN_R GPIO0B 105 H_PROCHOT#_EC
18 BKOFF#/GPXIOA08
<43> WL_BT_LED# WL_BT_LED# 19 GPIO0C GPO PBTN_OUT#/GPXIOA09 106 VCOUT0_PH VCOUT0_PH <47,49> 3 (QAQ13) 33K+/-5% 0.634V 0.819V 0.945V
R326 <27> SLP_LAN# SLP_LAN# 25 GPIO0D GPIO PCH_APWROK/GPXIOA10
107 BKOFF# <23>
+3VALW 1 @ 2 <27> SUSWARN# SUSWARN# EC_INVT_PWM/GPIO11 108 BKOFF#
PBTN_OUT# PBTN_OUT# <27> 4 (12-RM) 56K+/-5% 0.958V 1.185V 1.359V
28 SA_PGOOD/GPXIOA11
<23> INVT_PWM 29 FAN_SPEED1/GPIO14 PCH_APWROK PCH_APWROK <27>
1K_0402_5% <6> FAN_SPEED INVT_PWM EC_PME#/GPIO15 SA_PGOOD SA_PGOOD <53> 5 (13-RM) 100K+/-5% 1.372V 1.650V 1.838V
FAN_SPEED 30 110
EC_SMI# <42,50> PM_SLP_LAN# PM_SLP_LAN# 31 EC_TX/GPIO16 AC_IN/GPXIOD01 112
<36> E51_TXD E51_TXD 32 EC_RX/GPIO17
B EC_ON/GPXIOD02 114 B
<36> E51_RXD E51_RXD 34 PCH_PWROK/GPIO18 ON/OFF/GPXIOD03
<27> PM_PWROK PM_PWROK SUSP_LED#/GPIO19 115 EC_ACIN EC_ON <43,49> 1 2 2 1
36 LID_SW#/GPXIOD04 EC_ON
<48> GREEN_PWR GREEN_PWR NUM_LED#/GPIO1A GPI SUSP#/GPXIOD05
116
ON/OFFBTN# ON/OFFBTN# <43> C776 100P_0402_50V8J C820 0.1U_0402_16V4Z
new added pin--Joyce 0928-2011 <44> NUM_LED# NUM_LED# 117 LID_SW# <40>
GPXIOD06 LID_SW# @
118 SUSP# <10,39,45,50,51,52,57> KB_RST#
PECI_KB9012/GPXIOD07 SUSP# 2 1
122 CAMPWR_EN CAMPWR_EN <23> BATT_TEMPA
AGND/AGND
1 short@ 2 XCLKI/GPIO5D 1 2 C794 330P_0402_16V4Z

123 124H_PECI H_PECI <6,29>
113 GND/GND
R753 0_0402_5% XCLKO/GPIO5E V18R

GND/GND
C788 100P_0402_50V8J
35 GND/GND
24 GND/GND
CRY1 EC_ACIN PLT_RST#

GND0
<27> SUSCLK_R CRY2 +EC_V18R C782

R757 100K_0402_5% 4.7U_0805_10V4Z
EMI request
close U43
1 2
94
KB9012QF A3 LQFP 128P

69
11
C783 20P_0402_50V8
20mil LE2 +3VL +3VALW

2 1 @
FBMA-L11-160808-800LMT_0603 2 1
ECAGND
R742 330K_0402_5%
2 1
reserve forR749
ENE_CS board R747 330K_0402_5%
1 2
CRY1 @ 20M_0603_5%
CRY2
D64
2 1
1 EC_ACIN ACIN <13,27,48>

CH751H-40PT_SOD323-2
C785 1 2
1 @
@ C784 R748 0_0402_5%
15P_0402_50V8J
1
2 WL_OFF_EC# 1 2 WL_OFF# <29,36>

15P_0402_50V8J
R752 0_0402_5%
OSC
OSC
A 2 A
WWAN_OFF_EC# WWAN_OFF# <29,36>
NC
NC

2
Y5 @ 2011/09/23 2011/12/30 Title

32.768KHZ_12.5PF_Q13MC14610002 Issued Date Deciphered Date
B
5 4 3 2 1
5 4 3 2 1
+3V_M
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ U31
R1232 1 @ 2 10K_0402_5%
1 2 48 CLKREQ_LAN#
CLK_REQ_N 13
R564 0_0402_5% VPRO@ 36 MDI_PLUS0 14
PE_RST_N R1230 2 @ 1 2.2K_0402_5%
MDI_MINUS0
<26,35> CLKREQ_LAN# CLKREQ_LAN#_R 44 LAN_TX0+ LAN_TX0+ <35> PCH_SMLCLK0
PLT_RST# PE_CLKP 17
<6,28,34,35,36,37,39,41,44> PLT_RST# 1 2 45 MDI_PLUS1 18 LAN_TX0- LAN_TX0- <35> R1231 2 @ 1 2.2K_0402_5%
PE_CLKN MDI_MINUS1
PCIE
1R563 0_0402_5%
1 2
VPRO@
MDI
D <26,35> CLK_LAN 2 CLK_LAN_R LAN_TX1+ LAN_TX1+ <35> PCH_SMLDATA0 D
R560 0_0402_5% VPRO@ 38 20
<26,35> CLK_LAN# C469 0.1U_0402_10V7K VPRO@ CLK_LAN#_R PETp MDI_PLUS2 LAN_TX1- LAN_TX1- <35>
39 21
<26,35> PCIE_PRX_C_LANTX_P6 PETn MDI_MINUS2
2 1 PCIE_PRX_VLANTX_P6 LAN_TX2+ LAN_TX2+ <35> +1.0V_LAN +1.05V_M
41 23
<26,35> PCIE_PRX_C_LANTX_N6 1C482 0.1U_0402_10V7K
2 VPRO@ PCIE_PRX_VLANTX_N6 42 PERp MDI_PLUS3 24 LAN_TX2- LAN_TX2- <35> R548
PERn MDI_MINUS3 L29 @ 0_0805_5%~D
R556 0_0402_5% VPRO@
PCIE_PTX_C_C_VLANRX_P6 LAN_TX3+ 1 2 1 2
22U_0805_6.3V6M~D
<26,35> PCIE_PTX_C_LANRX_P6 1 2 LAN_TX3+ <35>
0.1U_0402_10V7K~D
R558 0_0402_5% VPRO@ LAN_TX3- LAN_TX3- <35> REGCTL_PNP10 1
28 6 4.7UH_CBC2012T4R7M_20%~D VPRO@
PCIE_PTX_C_C_VLANRX_N6
C470
<26,35> PCIE_PTX_C_LANRX_N6 SMB_CLK RSVD_NC
SMBUS
31 1
C468
SMB_DATA VPRO@
1 2 VPRO@ 1 VPRO@
RSVD_VCC3P3_1 Idc max=330mA
<26> PCH_SMLCLK0 PCH_SMLCLK0
RSVD_VCC3P3_2
2 R554 2 VPRO@ 1 4.7K_0402_1%~D 2
11 @ 22 <26> PCH_SMLDATA0 PCH_SMLDATA0 5 +RSVD_VCC3P3_1 R553 4.7K_0402_1%~D +3V_M 2
3 VDD3P3_IN
+3V_M R549 VPRO@10K_0402_5%
R555 0_0402_5% +RSVD_VCC3P3_2
SMBus Device Address 0xC8 LAN_DISABLE_N 4
VDD3P3_OUT
<29> PM_LANPHY_ENABLE 1 R557 2 10K_0402_5% LAN_DISABLE#_R
@ 15 +3.3V_M_OUT
@ R559 0_0402_5% 26 VDD3P3_15 19 1
27 LED0 VDD3P3_19 29
<35,36,39,41> EC_PME# LED1 VDD3P3_29 C490 Place R548, C462, C463 and L29 close to U31
LED
LAN_ACT_LED# 25 1U_0603_10V6K~D
<35> LAN_ACT_LED# LED2
<35> LAN_1000_LED# LAN_1000_LED# 2 VPRO@ VPRO@ VPRO@ VPRO@
47 +1.0V_LAN
<35> LAN_10/100_ LED# LAN_10/100_ LED# VDD1P0_47 VPRO@
46 +3V_M
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
VDD1P0_46
0.1U_0402_16V4Z~D
+3V_M 32 37 +1.0V_LAN
22U_0805_6.3V6M~D
T142 PAD 34 JTAG_TDI VDD1P0_37 VPRO@ 2 2 2
VPRO@
0.1U_0402_10V7K~D
T143 PAD JTAG_TDO 43 VPRO@ 1
JTAG
33 VPRO@
C1178
0.1U_0402_10V7K~D
TP_LAN_JTAG_TDI
C494
C487
0.1U_0402_10V7K~D
VDD1P0_43 VPRO@
C483
11 22 JTAG_TMS 1
22U_0805_6.3V6M~D
TP_LAN_JTAG_TDO 35
0.1U_0402_10V7K~D
@R545
@ R546 10K_0402_5%
10K_0402_5% JTAG_TCK 1 1
TP_LAN_JTAG_TMS 11 1 1 1 1
C472
VDD1P0_11 1
C1177
TP_LAN_JTAG_TCK 2
C488
C486
9 40 2
C471
1 2 XTAL_OUT VDD1P0_40
10 22 2 2
R1144 VPRO@ 0_0402_5% XTAL_IN VDD1P0_22 2
XTALO 16 2
XTALI VDD1P0_16 8
C C
30 VDD1P0_8
25MHZ_20PF_7V25000016 TEST_EN
Y4 LAN_TEST_EN 12 7
RBIAS CTRL_1P0
49 Place C1178 close to pin5
RES_BIAS REGCTL_PNP10
1
VSS_EPAD
1K_0402_5%
1 3
1 3
R561
LAN_X1 LAN_X2
1
82579_QFN48_6X6~D
33P_0402_50V8J
3.01K_0402_1%
GND GND Note:

33P_0402_50V8J
VPRO@ VPRO@
R562
VPRO@ 2 +1.0V_LAN will work at 0.95V to 1.15V

2 VPRO@
2 4
C493
+1.0V_LAN POWER OPTIONS

2
C485
VPRO@
VPRO@
2
1 1 Shared with PCH

1.05V SVR * Internal SRV
R1200 Resistor Value: STUFF: R548 STUFF: L29
3.01 kohm for Hanksville-M LOM NO STUFF: L29 NO STUFF: R548
2.37 kohm for Hanksville-D LOM
Need to verify A3 silicon drive
power before removing C427
KDS crystal vender verify
driving level in A3
B B
+3VALW
+1.05V_M
+1.05VM_PCH
+5VALW +3V_M
+5VALW 2
2
C497
2
R461 0.1U_0402_16V7K
R462
2
R814 470_0603_5% 2 VPRO@

470_0603_5% C495 1
VPRO@
2
100K_0402_5% VPRO@ 0.1U_0402_16V7K

VPRO@ R442 @
3
31
S
Q57
11
47K_0402_5% 1 G
D 2
1
D
Q44B
1
2 Q60 VPRO@ PM_SLP_LAN

2N7002DW-T/R7_SOT363-6
2 Q56
PM_SLP_LAN G PM_SLP_A# AO3413_SOT23
1
D
G +3V_M
1
Q50 5 2 VPRO@
S 2 S VPRO@ +1.05VM_PCH
3
2N7002E-T1-GE3_SOT23-3
6
0.01U_0402_25V7K
3
VPRO@ PM_SLP_A AO3416_SOT23-3 C498
1
VPRO@ D
2N7002DW-T/R7_SOT363-6
Q44A
4
2N7002_SOT23-3 C496 @ 0.01U_0402_25V7K

2 1
G VPRO@ 1
<41,50> PM_SLP_LAN# 2 1 1 1
S 1 C696
3
<41> PM_SLP_A# C694 4.7U_0805_10V4Z C698

1
4.7U_0805_10V4Z C695 @ 2 1U_0402_6.3V4Z

@ 2 1U_0402_6.3V4Z 2 VPRO@
2 VPRO@
<45> PM_SLP_LAN
A A

B
5 4 3 2 1
5 4 3 2 1
Power Button/ PWR/B

2 1
Touch/B Connector
+3VALW +3VL +5VS C755
2
R152 @ 10K_0603_5% R156
2
2 1 1 2
TOP
R153 Side
@ 10K_0603_5% R154 @
100K_0402_5%
100K_0402_5% JTP
D8 8 0.1U_0402_16V4Z
GND
1
2 7
1
1 GND 6
Bottom Side 6 5
3
5 4
ON/OFFBTN# <41> 4 3
CHN202UPT SC-70D
1
ON/OFFBTN#_R 3 1 TP_CLK <41>
51_ON# <44,47> 2 @
2 Q19 2 1 TP_DATA <41>
1 @
100P_0402_50V8J
C757
D
G 2N7002_SOT23-3 1 LEFT_BTN# D
100P_0402_50V8J
C759
@ RIGHT_BTN#
S ACES_85201-0605N 2
3
CONN@ 2
<41,49> EC_ON
2
R155
10K_0402_5%
@
1 SW8 SW7
SW LTL-613NQR1 SW LTL-613NQR1
3 1 3 1
LEFT_BTN# RIGHT_BTN#
JP7 4 2 4 2
1
1 2
6
5
6
5
2 3
3 +5VALW
4
4 PWR_ON_LED#
5
5 ON/OFFBTN#_R
9 6
G1 6 KSO0 KSO0 <40,41>
10 7
G2 7 KSI0 KSI0 <40,41>
8 KSI2
8 KSI2 <40,41> 2 R214 1
KSI6 KSI6 <40,41> TP_CLK LEFT_BTN# 10K_0402_5%
ACES_51524-0080N-001
CONN@
2
TP_DATA RIGHT_BTN# +3VS SW6
PJDLC05C_SOT23-3
3
2
D16 SMT1-05-A_4P
PJDLC05C_SOT23-3
D18 3 1
<41> TP_ON/OFF# TP_ON/OFF# 4 2
6
5
2
C C
WL&BT LED LED_WLAN# <36>
1
2N7002DW-T/R7_SOT363-6
1 2
1
2 R210 1 6 1
+3VS R1442
10K_0402_5% 0_0402_5% WL_BT_LED# <41>
Q229A
5
LED2
1 2 3 4
2 1 +USB_VCCE
R211 220_0402_5%
+5VS
HT-191UYG5 0603 YELLOW GREEN
Q229B 2N7002DW-T/R7_SOT363-6 Left USB R1
1
0_0402_5%
2
+USB_VCCB
W=40mils JUSB1
1 1 L3 1 5
1 VCC GND
+ C2 1 2 2 6
C7 C8 1 2 3 D- GND 7
220U_6.3V_M 1000P_0402_50V7K <28> USB20_N1 USB20_N1_R D+ GND
0.1U_0402_16V4Z @ 4 8
2 2 GND GND
2 4 3
2
2
4 3 @ D11
2N7002DW-T/R7_SOT363-6 <28> USB20_P1 USB20_P1_R
WCM-2012-900T_0805 SANTA_360117-1
MEDIA_LED#
HDD LED 2 R199 1
10K_0402_5%
6 1
1 2 PJDLC05_SOT23-3
CONN@
Q210A R5 0_0402_5%
+3VS
C3 +5VALW +USB_VCCE
2 1
LED4
5
1
2 1 0.1U_0402_16V4Z
U6
1 2 1 8
+5VS R200 220_0402_5%
HT-191USD 0603 RED
3 4
2 GND VOUT 7 W=80mils
3 VIN VOUT 6
Q210B 2N7002DW-T/R7_SOT363-6 VIN VOUT 1 2
B @ 4 5 B
EN FLG R4
1 2
<6,11,40,45> SUSP G547E2P11U SOP 8P 0_0402_5%
R9 1 0_0402_5%
2 USB_OC4# <28,40>
R10 0_0402_5%
1 D13
<40,45> SYSON#
C14
4.7U_0805_10V4Z
@ C12 2
1 1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 3
2 C4
2
PJDLC05_SOT23-3
Vf=2.1V(typ),2.4V(max) for amber
BATT CHARGE/FULL
LED5 LED Vf=2.2V(typ),2.4V(max) for green @
If=25mA(max)
2 1
5
B 1 2 +3VS R163 0_0402_5%

+5VALW
4 3
RED R203
1
220_0402_5%
2
BATT_CHG/LOW_LED# <41> @
4
2N7002DW-T/R7_SOT363-6
3Q230B +USB_VCCB
ESATA 1 2
+USB_VCCE
A L57
R204 220_0402_5% 1 2
YELLOW GREEN BATT_FULL_LED# <41>
<37> 5IN1_LED# 1 2
MEDIA_LED# <28> USB20_N9 USB20_N9_R
HT-297USD/UYG 0603 RED/YELLOW GREE 1 6 W=40mils @
<25> SATA_LED# @ JESATA
4 3 1 USB
Q230A 1 4 3
2N7002DW-T/R7_SOT363-6 1 1 <28> USB20_P9 USB20_P9_R 2 VBUS
WCM-2012-900T_0805 D-
2
+ C9 3
+3VS C10 C11 4 D+
220U_6.3V_M 1 2
0.1U_0402_16V4Z 1000P_0402_50V7K GND
PWR ON LED
LED6 1 2
@
2 2 2 R162
C2055 2
0_0402_5%
1 0.01U_0402_25V7K 5
GND
R85 0_0402_5% C2054 2 1 0.01U_0402_25V7K 6
2 1 @ SATA_PTX_C_DRX_P4 A+
<25> SATA_PTX_DRX_P4 7 ESATA
1 2 1 2 SATA_PTX_C_DRX_N4 A-
<25> SATA_PTX_DRX_N4 8 12
R202 220_0402_5% PWR_ON_LED# R93 0_0402_5% GND SHIELD
+5VALW Q6 C2052 2 1 0.01U_0402_25V7K 9 13
HT-191UYG5 0603 YELLOW GREEN B- SHIELD
<25> SATA_PRX_C_DTX_N4 C2053 2 1 0.01U_0402_25V7K SATA_PRX_DTX_N4 10 14
1
D 2N7002_SOT23-3 B+ SHIELD
A
<25> SATA_PRX_C_DTX_P4 SATA_PRX_DTX_P4 11 15 A
2 GND SHIELD
G PWR_ON_LED <41> FOX_3Q318111-R33C3-7F
S
3
CONN@
R169
LED8
1 2 2 1 100K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2011/09/23 2011/12/30 Title
1
+5VS R215 220_0402_5% TP_LED# Issued Date Deciphered Date

TP_LED# <41>
LED 19-213A/T1D-CP2Q2HY/3T 0603 WHITE
B
5 4 3 2 1
5 4 3 2 1
+3VS
EMI And ESD CR1 1 @ 2 4.7K_0402_5%

LPC_AD0
CR2 1 @ 2 4.7K_0402_5%
Reserve R199,C207,R226,C208 <EMI> 0601 CU13 LPC_AD1
COM@
CR3 1 @ 2 4.7K_0402_5%
21 CR4 1 @ 2 4.7K_0402_5%LPC_AD2
3
LAD0 GPIO00 12
4
LAD1 CTS0/GPIO01 SIO_GPIO00 LPC_AD3
Place closely pin 18 Place closely pin 1 <25,34,41> LPC_AD0 LPC_AD0 5
RTS0/GPIO02
13
CR5 1
COM@ 2 4.7K_0402_5%
<25,34,41> LPC_AD1 LPC_AD1 6 LAD2 14 CTS1#
D <25,34,41> LPC_AD2 LPC_AD2 LAD3 DSR0/GPIO03 RTS1# LPC_FRAME# D
15 2 4.7K_0402_5%
2
CR6 1 @
2
CLK_SIO_48M CLK_PCI_SIO <25,34,41> LPC_AD3 LPC_AD3 DTR0/GPIO04 16 DSR1#
DCD0/GPIO05 17 DTR1# SERIRQ
CR7 CR8 @ RI0/GPIO06 19 DCD1#
2
10_0402_5% 10_0402_5% LFRAME# SIN1/GPIO07 20 RI1#
1
<25,34,41> LPC_FRAME# LPC_FRAME# 18 LCLK SOUT1/GPIO08
1
<28> CLK_PCI_SIO CLK_PCI_SIO 9 CLKIN 11
1 <26> CLK_SIO_48M CLK_SIO_48M CLKRUN# SOUT0 10
1 <27,34> PM_CLKRUN# PM_CLKRUN# SIN0 8 TXD1
CC2 @ SIRQ# RXD1
7 2
CC1 4.7P_0402_50V8C 22 LRST# SERIRQ1 SERIRQ <25,34,41>
4.7P_0402_50V8C 2 DFT_EN PLT_RST#_R CR9 PLT_RST#
PLT_RST# <6,28,34,35,36,37,39,41,42>
2 0_0402_5% COM@
24 23
VSS VCC 1
+3VS
CC3 COM@ Base Address Selection
KC3820_QFN24
0.1U_0402_16V4Z 2 mount : 4E unmount : 2E
Add CR7,CC1 for EMI test fail issue--0929-2011
SIO_GPIO00
Reserve C292 for SIO_RST# <ESD> 0608
2
@ CR10
470_0402_5%
PLT_RST# 1
CC4
1
0.1U_0402_16V7K
2
@
C C
C5 +5VALW +USB_VCCA
PWR USB 2 1
0.1U_0402_16V4Z Max 2.5A
U7 W=80mils +USB_VCCA
1 8
2 GND VOUT 7
3 VIN VOUT 6 JP1
2 1 VIN VOUT 1 2 1
<41> USB_EN# R1381
4
EN FLG
5
USB_OC1# <28>
W=60mils 1
R149 0_0402_5% 2
0_0402_5% 1 R8 2
1 2 1 G547E2P11U 3
0_0402_5% 4 3
C6
C676 5 4
L54 4.7U_0805_10V4Z
0.1U_0402_16V4Z 2 6 5
2 1
2 1 2@ USB20_N4_R 7 6
<28> USB20_N3 USB20_N3_R USB20_P4_R 8 7
B @ 8 B
3 4 9
3 4 USB20_N3_R 10 9
<28> USB20_P3 USB20_P3_R USB20_P3_R 11 10
WCM-2012-900T_0805 11
12
1 2 TXD1 13 12
R148 0_0402_5% RXD1 14 13
R137 0_0402_5% CTS1# 15 14
1 2 RTS1# 16 15
17 16
L53 change from +3VALW to +3VL 18 17
+3VL +3VALW
2 1 DSR1# 19 18
<28> USB20_N4 2 1 USB20_N4_R
since EC power source changed. DTR1# 19
20
1
--Joyce 1110
1
@ DCD1# 21 20
3 4 R582 R581 RI1# 21
4 22
<28> USB20_P4 3 USB20_P4_R 10K_0402_5% @ NUM_LED# 22
<41> NUM_LED# 23
WCM-2012-900T_0805 10K_0402_5% CAPS_LED# 23
<41> CAPS_LED# 24
D26 +3VS 25 24
2
1 2
2
2 PWR_USB_ON# 26 G1
R127 0_0402_5% 1 PWR_USB_EN# PWR_USB_EN# <41> G2
PWR_USB_ON# 3
51_ON# 51_ON# <43,47>
BAV70W_SOT323-3 E&T_6916-Q26N-00R
A A

B
5 4 3 2 1
5 4 3 2 1
+3VALW TO +3VS 0.1U_0402_16V7K

0.1U_0402_16V7K
Vgs=-0V,Id=9A,Rds=18.5mohm +5VALW TO +5VS +1.5V to +1.5VS
2 +5VALW 2 Vgs=10V,Id=14.5A,Rds=6mohm
+3VALW +3VS
1 1 C843 +5VS
2 1 C842 +1.5V
C824 C825 4.7U_0805_10V4Z C827 +1.5VS
C844 1 1 1
C826 4.7U_0805_10V4Z
470_0805_5%
Q32 2 Q34
470_0805_5%
1 C829
2
Q33 1U_0402_6.3V4Z 1 C828
2
8 1 2 2 C845 8 1
D S 1 8 1 2 D S 1U_0402_6.3V4Z 4.7U_0805_10V4Z
470_0805_5%
7 2 R781 D R782 7 2 2
2
D S 7 S 2 2 D S 2
6 3 D S 6 3
5 D S 1U_0402_6.3V4Z 1 R784 2 6 3 1 D S
4 D S 5 4
D G 47K_0402_5% 5 4 D G R783
D G 1 R785 2
1
2
3 1
C847 SI4800BDY_SO8 47K_0402_5% 0.1U_0402_16V7K SI4856ADY_SO8
4.7U_0805_10V4Z
1 SI4800BDY_SO8
6
Q36A 1 R786 2
0.022U_0402_25V7K
D 1 D
3 1
4.7U_0805_10V4Z
1 RUN_ON +VSB
3
Q35A +VSB 1 220K_0402_5%
0.1U_0603_25V7K
C831 0.1U_0402_16V7K 1
1
2 Q37A
1
C832
0.01U_0402_25V7K
4.7U_0805_10V4Z
1
C833
+VSB
1
1 C830 C846 2
R787 2 Q35B R788 C835
330K_0402_5% 5 2 330K_0402_5% Q36B C834 R789 2
2 2 2N7002KDW 2N SOT-363-6
5 FDS6676AS 820K_0402_5% Q37B
2 2
1
2N7002KDW
2N7002KDW 2N2N SOT-363-6
SOT-363-6 1 2 5
2N7002KDW 2N SOT-363-6 2N7002KDW 2N SOT-363-6
1
SUSP SUSP
1
2N7002KDW 2N SOT-363-6
2
4
2
0.1U_0402_16V7K SUSP
2
4
4
0.1U_0402_16V7K
+3VS to +3VS_DGPU +1.5V to +1.5VSDGPU +3VALW TO +3VALW(PCH AUX Power)

+3VS +3VS_DGPU Short J1 for PCH VCCSUS3.3
+1.5V +1.5VSDGPU +3VALW
J1 @
1 1 1 2
2 C478 1 2 +3VALW_PCH
C491 OPT@
Vgs=10V,Id=14.5A,Rds=6mohm
C475OPT@ JUMP_43X79
470_0805_5%
0.1U_0402_16V7K Q43 SI7326DN-T1-E3_PAK1212-8
2
OPT@ 8 1 2 4.7U_0805_10V4Z U25
3
2
S
7 D S 2 R429 OPT@ 1
1
2
G D S 40mil
6 3 2
1 2 D S 1U_0402_6.3V4Z
1U_0402_6.3V4K
Q54 5
1
4 5 3
C AO3413_SOT23 D D G 1 R431 2 1 1 C
R804
1
1
220K_0402_5%
C838
DGPU_PWR_EN# R426 OPT@ FDS6676AS_SO8 C837 1
2
10U_0603_6.3V6M
C839
470_0402_5%
4.7U_0805_10V4Z
1
1
47K_0402_5% OPT@ OPT@
4
OPT@ C492 +VSB 10U_0603_6.3V6M
3
1 R430
6
C473 2 2
2
0.1U_0402_25V6
0.01U_0402_25V7K 1 OPT@ 820K_0402_5% 2
1@ Q13A
C481
2 OPT@ Q13B
3
C697 2 2 5 2N7002KDW 2N SOT-363-6
2
1U_0402_6.3V4Z OPT@
OPT@ 2N7002KDW 2N SOT-363-6
VGA_PWROK#
+1.05VS_DGPU 2 OPT@
OPT@ 2 1
4
1
5
20mil 10mil
820K_0402_5%
+1.05VS_PCH
PCH_PWR_EN#
1
J4 @ R807 200K_0402_5%
+1.05VS_DGPU +5VALW 3V_GATE Q46B
+VSB
4
1 2 R146 R435 2 2N7002KDW 2N SOT-363-6
6
1 2 1 2 C836
Q40 JUMP_43X79 OPT@ @ 0.1U_0402_16V7K
8 1 100K_0402_5%
1
D S 2 D
2
7 2 1
2
6 D S 3 2 Q188 PCH_PWR_EN#
5 D S 4 G 2N7002_SOT23-3 Q46A
1
D G 1 R805 OPT@ 2N7002KDW 2N SOT-363-6
1
10U_0603_6.3V6M
C854
<26,29,57> VGA_PWROK S
3
1U_0603_10V4Z
C853
SI4800BDY_SO8 470_0603_5%
1
C852 OPT@ OPT@
1
2 OPT@ 2
OPT@ +5VALW
10U_0603_6.3V6M
OPT@ 2
3
2
R813
100K_0402_5%
B 5 B
2 OPT@ 1
820K_0402_5%
1
1
+VSB
1
C848 Q227B
DGPU_PWR_EN#
R808 200K_0402_5% R432
4
6
0.1U_0603_25V7K 2N7002KDW 2N SOT-363-6 PCH_PWR_EN#

<31> PCH_PWR_EN# Q49
2 OPT@ OPT@
@ 2N7002E-T1-GE3_SOT23-3 1 +3VS_DGPU +VGA_CORE +5VALW +5VALW +5VALW
D
2
2
2
2 R458
2
2
2
G 470_0603_5% R459
DGPU_PWR_EN# Q227A R796
470_0603_5% R1453
1
S OPT@ R797
3
2N7002KDW 2N SOT-363-6 <41> PCH_PWR_EN OPT@ 100K_0402_5%

100K_0402_5% 100K_0402_5%
OPT@ 1 OPT@
1
1
1
DGPU_PWR_EN# <40,43> SYSON# SYSON# SUSP SUSP <6,11,40,43>
6
3
OPT@ Q201B Q201A
+1.05V_M +1.05VS_VCCP +1.5V Q191 2N7002KDW 2N SOT-363-6 2N7002KDW 2N SOT-363-6
6
1
D
2
2N7002_SOT23-3
3
1
R1447 R1445 2 5 2
2
470_0805_5% 470_0805_5% R1446 <26,28,57> DGPU_PWR_EN G <39,41,52> SYSON SUSP# <10,39,41,50,51,52,57>
+0.75VS 2
VPRO@ 470_0805_5% R441 S 2 R70 1
1
3
4
5
1
4.7K_0402_5% 10K_0402_5% 1 2
DGPU_PWR_EN#
1
R826 Q225A Q225B @ R440

1
2
22_0603_5% 2N7002KDW 2N SOT-363-6 2N7002KDW 2N SOT-363-6 4.7K_0402_5%
4
2N7002KDW 2N SOT-363-6
1
2N7002KDW 2N SOT-363-6
OPT@ OPT@
6 +1.05V_M_R
2N7002KDW 2N SOT-363-6
3 +VCCP_R
2
+1.5V_R
2N7002KDW 2N SOT-363-6
<6,10> RUN_ON_CPU1.5VS3#
+0.75VS_R
6
A A
Q198A
0_0402_5%
R460
3
Q198B
Q197A Q197B 2
@
2 5 5
SUSP SYSON# Security Classification Compal Secret Data Compal Electronics, Inc.
1
<42> PM_SLP_LAN R463

2011/09/23 2011/12/30 Title
1
SUSP Issued Date

4
Deciphered Date
4
0_0402_5%
B
5 4 3 2 1
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ Power block

CPU OTP
Page 47
D Turn Off D
B+
Input +3VALWP: TDC:6A
DC IN Switch Always
Page 48 +5VALWP: TDC:4A
RT8205LZQW(2) WQFN Page 49
CHARGER
CC:0A~3.64A +1.8VP: TDC:3A SUSP#
CV:12.6V(6cell) SY8033BDBC
BQ24725RGRR Page 50
Page 48
C C
+1.05VSP: TDC:12A SUSP#
Battery TPS51212DSCR Page 51
+1.5VP: TDC:13A SYSON

0.75VS: TDC :2A
RT8207MZQW Page 52
SUSP#
+VGA_CORE
DGPU_PWR_EN TDC:23A
B
ADP3211AMNR2G B
Page 57
+VCCSAP: TDC:5A +1.05VSP_PWRGOOD

+VCC_CORE TPS51461RGER
VR_ON TDC: 36A Page 53
NCP6132A
Page 54
+GFX_CORE
VR_ON TDC: 21.5A
A A
NCP6132A
Page 54

Custom B
5 4 3 2 1
Compal
A B C D
PL1
HCB2012KF-121T50_0805 For KB930 --> Keep PU1 circuit
DCIN jack P/N:DC301008L00, 1 2 PH1 under CPU botten side : (Vth = 0.825V)
need doble confirm P/N with ME PL2
VIN CPU thermal protection at 93 +-3 degree C
HCB2012KF-121T50_0805 For KB9012 (Red square) --> Remove PU1 circuit, but keep
1 2 Recovery at 56 +-3 degree C PH1, PR1, PR2,PR4,PR7,PR9,PQ1
PJPDC1
ADPIN VL
1000P_0402_50V7K
1
+EC_VCCA
1000P_0402_50V7K
V+
100P_0402_50V8J
2
1
1
1
GND
1
3
100P_0402_50V8J
38,47 ADP_I
KB930@
PC1
2
1
PC2
GND
13.7K_0402_1%
7.87K_0402_1%
4
PC3
PR3
1
GND
KB9012@
UMA@ PR1
PC4
5
2
GND
PR2
1 1
PR1
1
2
2
SANTA_322121-1
@ PC5 OPT@ 47.5K_0402_1%
+3VS
1
0.1U_0603_16V7K PU1 KB930@
1 8
2
VCC TMSNS1 2
2
1
100K_0402_1%
2 7 PR5
PR4
GND RHYST1 OTP_N_002 10K_0402_1%
3 6 KB930@
OT1 TMSNS2 PR6
5,38 H_PROCHOT# 1 2
1
PQ1 4 5
PH1
2
OT2 RHYST2
1
KB930@ UMA@
100K_0402_1%
D ADP_OCP_2
2
51.1K_0402_1% PR501
PR7
100K_0402_1%_NCP15WF104F03RC
2 G718TM1U_SOT23-8
2
PR500 PR20 KB9012@
G PR6 PR21 0_0402_5%
ADP_OCP_1 KB9012@ @
S 2N7002KW 1N SOT323-3 @ 100K_0402_1%
OTP_N_003
2 1
2
0_0402_5%
100K_0402_1%
1
OPT@ 309K_0402_1% 2 1
1
2 1
@ PR8 0_0402_5% MAINPOWN 48
1
PR9 2 1
1 2
PL3 38 H_PROCHOT#_EC
0_0402_5%
KB9012@
KB930@ PR10 0_0402_5% VCOUT0_PH 38,48 +3VL
HCB2012KF-121T50_0805 38VCIN0_PH 41ECAGND
1 2 38VCIN1_PH
VMB
PL4 3 1
HCB2012KF-121T50_0805
1 2
PJP1 BATT+
B+ +VSB
100K_0402_1%
0.22U_0603_25V7K
11 9
0.1U_0603_25V7K
1
1
10 GND 9 8
1
PR11
PC9
1
GND 8 PC6 PC7
PC8
7
7 6 1000P_0402_50V7K 0.01U_0402_25V7K
2
2 6 5 2
2
5 VL PQ2
2
4
4 3 PR13 TP0610K-T1-E3_SOT23-3
3 2 22K_0402_1%
2
2 1 1 2
1 @ PR14
1
BATT_B/I 100K_0402_1% VSB_N_001

PR12
VSB_N_003
@ SINGA_2BA1514-000111F
EC_SMCA
EC_SMDA
1K_0402_1%
1
PD2 @ PR15 PR23
1
PD1 2 0_0402_5%
2
1K_0402_1%
1
1 1 2 D
1 2
TH
3 2 PQ3
48 SPOK G 2N7002KW 1N SOT323-3
.1U_0402_16V7K
1
PJSOT24CW_SOT323-3 S
PC10
PR22
3
PJSOT24CW_SOT323-3 PR16
3
2
0_0402_5%
2 1
1 2
2
+3VL
6.49K_0402_1% 41 VSB_EN
1
PR17
1K_0402_1%
2
2
PR18
100_0402_1% PR19
100_0402_1% BATT_TEMPA 38
1
VIN
1
2
3 3
EC_SMB_DA1 38,47
PD20 @
EC_SMB_CK1 38,47 RLS4148_LL34-2
1
VS_N_001
2 1
BATT+
1
PD21
PQ100 PR300
@ LL4148_LL34-2 PR301 @
TP0610K-T1-E3_SOT23-3 @ @ 68_1206_5% 68_1206_5%
RTC Battery 3 1
2
N1
VS
PR24
1
- +
1
PBJ1 PR25
560_0603_5%
1
560_0603_5% PC500 PC501
2 1 2 1 2 PR302
1 +RTCBATT1 +RTCBATT2 @0.22U_0603_25V7K 0.1U_0603_25V7K @
2
@ 100K_0402_1%
2
2
+RTCBATT 1 2
MAXEL_ML1220T10 PR303 VS_N_002
47,48,50 51_ON#
@ 22K_0402_1%
Must close PBJ1
SP093MX0000
4
Change RTC For Cost Down 4
For KB9012 --> Remove all 51_ON# circuit

Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
4019IE B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
A B C D
for reverse PQ5

input protection
1
D
2
G 2N7002KW 1N SOT323-3
S
3
BQ24725_PROT
PR27
PR26 1 2 PQ6
1 2 MDS2659URH
1
3M_0402_5% 1
1M_0402_5% 8 1
PQ7
P2 P3 7 2
TPCA8057-H_PPAK56-8 PL5 6 3
1 1UH_VMPI0703AR-1R0M-Z01_11A_20% 5
PR28
2 PQ8 0.02_2512_1%
5 3
@0_0402_5%
MDS2659URH
0.01U_0402_50V7K
VIN P1 1 4
1
1 8
PR29
2 7 1 2
2 3 B+
10U_0805_25V6K
3 6
PC23
1
2200P_0402_50V7K
0.1U_0402_25V6
5
10U_0805_25V6K
@10U_0805_25V6K
1
10U_0805_25V6K
PC16
@820P_0402_25V7
0.1U_0402_25V6
2200P_0402_25V7K
@10U_0805_25V6K
1
@0_0402_5%
PC22
1
PC21
VIN
1
1
2
1
1
1
1
10U_0805_25V6K
1
PC17
PC18
2
PC13
PC15
4
PR30
2
PC24
PC14
1
PC19
1
2
1 2
PC20
2
2
2
2
2
2
2
PR31
2
2
4.12K_0603_1%
2
PD4 BQ24725_BATDRV BQ24725_BATDRV_1
1
BAS40CW_SOT323-3
PQ9
0.1U_0402_25V6
0.1U_0603_25V7K
BQ24725_VCC1
TP0610K-T1-E3_SOT23-3
1
1
PC26
PC25
3 1
PC27
2
2
2
BQ24725_VCC1 BQ24725_VCC2
1 2
2
PR32 0.047U_0402_25V7K
100K_0402_1% 0.1U_0402_25V6
1
BQ24725_VCC2
PC28 PC29
4.12K_0603_1%
0.22U_0603_25V7K 1 2
2
4.12K_0603_1%
@ PR33
1
1
1 2
1
1
10_1206_1%
PR35
1
PR34
0_0603_5%
PR36
BQ24725_BST1
5
BQ24725_VCC_EN
PR37
22K_0402_1%
1
0_0402_5%
PD5 PQ10
BQ24725_VCC_EN1
PR39
2 2
RB751V-40_SOD323-2
2
MDV1528URH 1N PDFN33-8
2
2
2
1 2 4
2
DH_CHG DH_CHG1
BQ24725_REGN
PR38
BQ24725_BST
BQ24725_VCC
PC31 PL6 BATT+
BQ24725_LX
PC30
BQ24725_ACP
1 2 0_0402_5%
1 2
1
D PR40
DH_CHG
4.7UH_ETQP3W4R7WFN_5.5A_20%
3
2
1
2 1U_0603_25V6K 0.02_1206_1%
BQ24725_ACN
PQ11
GREEN_LATCH# 1 4
@4.7_1206_5%
G SSM3K7002FU_SC70-3 @ 1U_0603_25V6K 1 2
BQ24725_LX
5
S CHG_OUT
1
3
20
19
18
17
16
2 3
PQ12
PR41
2200P_0402_50V7K
10U_0805_25V6K
PU3
0.01U_0402_50V7K
CSOP1
@820P_0402_25V7
10U_0805_25V6K
VCC
PHASE
HIDRV
REGN
BTST
AON7406L 1N DFN
0.1U_0402_25V6
21
CSON1
PC34
1
0.1U_0402_25V6
PAD
PC33
1
PC32
PC36
1
4
PC37
15
2
1
1
PC38
ACN LODRV
2
PC35
DL_CHG
2
2 14
2
ACP GND
2
PR42
3
2
1
2
Vin Dectector
BQ24725_SNUB
BQ24725ARGRR_VQFN20_3P5X3P5 10_0603_1%
1
3 13 1 PR43
2
CMSRC SRP SRP 6.8_0603_1%
BQ24725_CMSRC CSOP1
Min. Typ Max. 1 2
@680P_0402_50V7K
2
H-->L 17.23V 4 12
0.1U_0603_16V7K
1
PR44 ACDRV SRN SRN CSON1
PC40
BQ24725_ACDRV
L--> H 17.63V 1 2
PC39
5 11
2
@10K_0402_1%
BQ24725_ACOK ACOK BATDRV
+3VALW BQ24725_BATDRV
ACDET
IOUT
ILIM and external DPM
SDA
ILIM
SCL
PR45
1 2
3.97A +3VL +3VALW
10
9
8
7
6
1M_0402_1% PR47
PR46 1 2
1 2
0.01U_0402_25V7K
BQ24725_ILIM 133K_0402_1%
3
For KB930 --> Keep PR44 14,20,38 ACIN 10K_0402_1%
3
100K_0402_1%
PR48
PC41
1
1
For KB9012 (Red square) --> Remove PR44 VIN 1 2
PR49
Keep PR45
BQ24725_IOUT
154K_0402_1%
BQ24725_ACDET
2
BQ24725_PRECHG
255K_0402_1% 41 GREEN_PWR4
1
PR50
2
+3VL
0.1U_0402_10V6K
VIN
2
2
PU4 @
1
PC42
PR51 @
0.1U_0402_25V6
66.5K_0402_1%
309K_0402_1% MC74VHC1G08DFT2G_SC70-5
2
1
5
1
2
PC43
PR54 @
1
PR52
EC_SMB_CK1 38,46
5
VCC
PR53
5
10K_0402_5% 1 PU5 @ PU6 @ @
2
100_0402_5% 1 2 IN1 4 1 1
P
P
OUT INB INB 4
2 4
GND
GREEN_PWR3 GREEN_PWR4 O O
2
IN2 2
2
EC_SMB_DA1 38,46 PR55 2

1
INA
G
2 1 GREEN_PWR1
0.1U_0402_10V7K
INA
G
GREEN_PWR# GREEN_PWR2 74LVC1G02_04_SOT353
74LVC1G02_04_SOT353
3
47K_0402_1%
PC44 .1U_0402_16V7K
3
3
1
ADP_I 38,46
PC45
1
2
@ @ @ PR56 0_0402_5% GREEN_LATCH1
Please locate the RC
2
+3VL
2
1 2
Near EC chip @ PR57 @
2
PR179 0_0402_5%
10K_0402_5% 41 GREEN_PWR PR58 @
100K_0402_5%
1
@ PR180
1 2
GREEN_PWR5
1
GREEN_LATCH#
GREEN_LATCH#
4 0_0402_5% 4
1
D
@ PQ109 2 @ PR178
SSM3K7002FU_SC70-3 G 1 2
S
3
0_0402_5%

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019IE B
A B C D
A B C D E
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ 2VREF_51125
1
PC46
1U_0603_16V6K
2
1 1
PR60
PR59 30.9K_0402_1%
13.7K_0402_1% 1 2
1 2
PR61
20K_0402_1% PR62
B+ B++ 1 2 20K_0402_1%
PL7 1 2 B++
HCB2012KF-121T50_0805 FB_3V FB_5V
1 2
+3VLP PR64
10U_0805_25V6K
ENTRIP1
ENTRIP2
137K_0402_1%
2200P_0402_50V7K
2200P_0402_50V7K
PR63
1
2
4.7U_0805_25V6-K
1
0.1U_0402_25V6
0.1U_0402_25V6
1
154K_0402_1%
1
1
1
PC48
PC51
1 2
PC52
PC49
PC50
PC47
1
3
2
2
PU8
2
2
5
ENTRIP2
FB2
TONSEL
REF
ENTRIP1
FB1
PQ14
1
PQ13 4 PC53 25
10U_0805_6.3V6M P PAD MDV1528URH 1N PDFN33-8
MDV1528URH 1N PDFN33-8
2
7 24 4
VO2 VO1
3
2
1
8 23 PR66 PC55
PC54 PR65 VREG3 PGOOD
UG_3V_1
0.1U_0402_10V7K 1 2 2.2_0402_5% 0.1U_0402_10V7K
9 22 1 2
UG_5V_1
1 2 PR68
3
2
1
1 2 PR67 2.2_0402_5% BOOT2 BOOT1
BST1_3V BST_3V BST_5V 1
BST1_5V 2
PL8 1 2 10 21
2 UGATE2 0_0402_5% PL9 2
4.7UH_ETQP3W4R7WFN_5.5A_20% 0_0402_5% UGATE1
2 1 UG_3V UG_5V 4.7UH_ETQP3W4R7WFN_5.5A_20%
11 20 1 2
PHASE2 PHASE1
5
LX_3V LX_5V +5VALWP
1
+3VALWP
@4.7_1206_5%
12 19
1
PQ15 LGATE2 LGATE1
PR69
@4.7_1206_5%
LG_3V LG_5V PQ16
SKIPSEL
VREG5
1 PR71
PR70
GND
499K_0402_1% 1
VIN
EN
NC
PC56 +
2
4 1 2
220U_6.3V_M PC57 +
2
4
51125_PWR 220U_6.3V_M
13
15
16
17
18
14
2 RT8205LZQW(2)_WQFN24_4X4 SPOK 46
SNUB_5V
1 SNUB_3V
2
AON7406L_DFN8-5
3
2
1
@680P_0402_50V7K
3
2
1
@680P_0402_50V7K
1
VL AON7702L_DFN8-5
PC60
1
PR72
PC58
95.3K_0402_1% PC59
2
2
1U_0603_10V6K
1
2
2
PC61
4.7U_0805_10V6K
2
1
PC62
51125_PWR
2
0.1U_0603_25V7K
2VREF_51125
3 ENTRIP2
6 ENTRIP1
PJP2
1 2
3 3
D
D +5VALWP +5VALW (6A,200mils ,Via NO.= 12)
PQ17A 2 5 PQ17B PAD-OPEN 4x4m
SSM6N7002FU_US6 G N_3_5V_001 G SSM6N7002FU_US6
PJP3
S 1 2
4
S
1
PR73 +3VALWP +3VALW (4A,120mils ,Via NO.= 8)

0_0603_5%
PR74
B+ 1 2 51125_PWR PAD-OPEN 4x4m
2.2K_0402_1% 2 1
51125_PWR1
1 2
Vin PD7
1
PR75 PD6
1 2 2 1 1SS355_SOD323-2 PD8
38,39,41 EC_ON PR76 100K_0402_5% GLZ27D_LL34-2
N_3_5V_002
1 2 VL +3VLP PJP4 +3VL

1
1SS355_SOD323-2
38,46 VCOUT0_PH PR181 0_0402_5% 2 1
51125_PWR2
2
PQ18
1 2 KB9012@
DRC5115E0L_SOD323-3 PR77
46 MAINPOWN @ 0_0402_5% BATT+ PAD-OPEN 2x2m
42.2K_0402_1%
1 2 PD9 100_0805_5%
1
2 1 2
VS 2 1
PR320
PR319 @
100K_0402_1%
4.7U_0603_10V6K
1SS355_SOD323-2 +3VLP +CHGRTC

1
PJP5
PC63
3
2
2 1
1
@
2
PC64 PAD-OPEN 2x2m

0.1U_0603_25V7K
2
4 4
For KB930 --> Keep PR319, Remove PR74

For KB9012 (Red square) --> Remove PR319
Keep PR74 Security Classification Compal Secret Data Compal Electronics, Inc.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019IE B
A B C D E
A B C D
1 1
PL10 PU9 PL11
4
HCB1608KF-121T30_0603 0.47UH_PCMB042T-R47MN_6A_20%
+5VALW 1 2 10 2 1 2
LX_1.8VSP
PG
VIN_1.8VSP PVIN LX
+1.8VSP
68P_0402_50V8J
9 3
1
1
4.7_1206_5%
PVIN LX
1
PC66
1
PC65 8 PR79
PR78
22U_0805_6.3VAM SVIN
20K_0402_1%
2
6
22U_0805_6.3VAM
FB
22U_0805_6.3VAM
2
1
5
1
EN
NC
NC
TP
PC67
PC68
FB_1.8VSP
2
9,32,38,44,50,51,56 SUSP#
2
1
7
11
1 2 EN_1.8VSP
1
SNUB_1.8VSP
1
PR80 0_0402_5%
@0.1U_0402_10V7K
PR82
SY8033BDBC_DFN10_3X3
PC69
10K_0402_1%
1
PR81
@47K_0402_5%
2
2
680P_0402_50V7K
PC70
2
2 2
PJP7
1 2
+1.8VSP +1.8VS (3A,120mils ,Via NO.= 6)
PAD-OPEN 3x3m
PL12 VPRO@ VPRO@

VPRO@ PU10 PL13
<Vo=1.05V> VFB=0.6V
4
HCB1608KF_0603 0.47UH_PCMB042T-R47MN_6A_20%
+5VALW 1 2 10 2 1 2 Vo=VFB(1+PR401/PR402)=0.6*(1+7.5K/10K)=1.05V
+1.05V_MP_LX
PG
+1.05V_MP_VIN PVIN LX
+1.05V_MP
PC72
68P_0402_50V
9
PR83 VPRO@
3
1
1
PVIN LX
4.7_1206_5%
1
1
3
PC71 VPRO@ 8 VPRO@ 3
22U_0805_6.3VAM SVIN PR84

7.5K_0402_1%
VPRO@
6
2
+1.05V_MP_FB
2
FB
22U_0805_6.3VAM
22U_0805_6.3VAM
5
1
2
1
2
EN
VPRO@ PC73
NC
NC
TP
VPRO@ PC74
SNUB_+1.05V_MP
PR85 VPRO@
45,46 PM_SLP_LAN#
2
2
1
7
11
1 2
EN_+1.05V_MP 1
100K_0402_1%
0.1U_0402_10V7K
2
PC75
SY8033BDBC_DFN10_3X3 VPRO@ PR86

1
PR87 @
10K_0402_1%
300K_0402_5%
2
@
2
1
PC76
680P_0603_50V7K
2
VPRO@
PJP8
1 2
+1.05V_MP +1.05V_M (1.3A, 52mils, Via NO.= 3)
PAD-OPEN 3x3m
4 4

A B C D
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ PL14
HCB1608KF-121T30_0603
2 1
+1.05VSP_B+
B+
10U_0805_25V6K
4.7U_0805_25V6-K
2200P_0402_50V7K
0.1U_0402_25V6
1
1
1
D D
PC78
PC77
PC79
PC80
+3VS
2
2
5
2
PR88 PQ19
10K_0402_5%
PC81
PR90 0.22U_0402_10V6K 4
1
1 2 1 2
BST1_+1.05VSP
PU11 4.7_0402_5%
44,52 +1.05VSP_PWRGOOD 1 10
PGOOD VBST MDV1525URH_PDFN33-8-5
3
2
1
BST_+1.05VSP
PR89 2 9 PR91
1 2 TRIP DRVH 1 2 PL15
TRIP_+1.05VSP UG_+1.05VSP UG_+1.05VSP1
84.5K_0402_1% 3 8 2.2_0402_5% 0.47UH_PCMB063T-R47MS_18A_20%
EN_+1.05VSP EN SW SW_+1.05VSP 1 2 +1.05VSP
4 7
5
6
8
7
PR92 FB_+1.05VSP
VFB V5IN
0_0402_5% 5 +5VALW PQ20
1
6
1 2 TST DRVL 1
RF_+1.05VSP LG_+1.05VSP
220U_6.3VM_R15
9,32,38,44,49,51,56 SUSP#
1
11 PR93 +
PC83
TP
PC82 4.7_1206_5%
1
4
1
TPS51212DSCR_SON10_3X3 1U_0603_10V6K
1 SNUB_+1.05VSP 2
PC84 2
@0.1U_0402_16V7K PR94
2
470K_0402_1%
AO4456_SO8
3
2
1
2
C C
1
PR95
0_0402_5%
PC86 PC85
@1000P_0402_50V7K
2
1 2 PR96 680P_0402_50V7K
1 2
2
+1.05VSP1 +1.05VSP
@1.2K_0402_1%
PR98
100_0402_1%
PR97 4.99K_0402_1% 2 1
2 1 VCCIO_SENSE1 VCCIO_SENSE 8
2
PR99
10K_0402_1%
1
PJP9
1 2
+1.05VS_PCH
PAD-OPEN 4x4m
PJP10
1 2
B +1.05VSP +1.05VS_VCCP (12A,480mils ,Via NO.= 24) B
PAD-OPEN 4x4m
A A

Deciphered Date
5 4 3 2 1
5 4 3 2 1
起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ 0.75Volt +/- 5%

TDC 0.525A
Peak Current 0.75A
PL16
HCB1608KF-121T30_0603 OCP Current 0.9A
1 2
D B+ 1.5V_B+ D
1 PR100 2
BST_1.5V
2.2_0402_5%
BOOT_1.5V +1.5VP
2200P_0402_50V7K
1 PR101 2
10U_0805_25V6K
@4.7U_0805_25V6-K
0.1U_0402_25V6
+0.75VSP
0.22U_0402_10V6K
PC88
DH_1.5V_1 0_0402_5%
1
DH_1.5V
1
1
10U_0805_6.3V6M
10U_0805_6.3V6M
2
PC87
PC90
PC89
PC91
2
2
SW_1.5V
2
2
1
PC92
PC93
5
19
20
17
18
16
DL_1.5V PU12
PQ21
2
UGATE
VLDOIN
VTT
2
PHASE
BOOT
MDV1528URH 1N PDFN33-8 21
PAD
4 15 1
LGATE VTTGND
PL17 PR102 14 2
1UH_VMPI0703AR-1R0M-Z01_11A_20% 18.7K_0402_1% PGND VTTSNS
1 2
3
2
1
2 1 CS_1.5V 13 3
PC94 CS GND
RT8207MZQW_WQFN20_3X3
+1.5VP
5
1U_0603_10V6K
PQ22 1 2 12 4
PR104 VDDP VTTREF VTTREF_1.5V
1
1
5.1_0603_5%
220U_6.3VM_R15
PC95
+
11 5
C
PR103 4 1 2 VDD_1.5V VDD VDDQ +1.5VP C
PGOOD
@4.7_1206_5%
1
2 +5VALW
TON
2
PC96 PC97
S3
FB
S5
1U_0603_10V6K 0.033U_0402_16V7K
2
1 SNUB_+1.5VP
AON7702L_DFN8-5
2
3
2
1
7
10
6
+5VALW
PR105
10.2K_0402_1%
PC98 2 1
FB_1.5V +1.5VP
TON_1.5V
@680P_0402_50V7K
2
1
PR106
Mode Level +0.75VSP VTTREF_1.5V PR107 PC99
887K_0402_1% 10K_0402_1%
S5 L off off PR108
.1U_0402_16V7K
2
1 2
S3 L off on 0_0402_5% 1.5V_B+
1
S0 H on on 1 2
EN_1.5V
32,38,39,44 SYSON
EN_0.75VSP
Note: S3 - sleep ; S5 - power off
1
PR109
2 1
PC100
2 @0.1U_0402_10V7K 44 0.75VR_EN
B @0_0402_5% B
PR110
2 1
9,32,38,44,49,50,56 SUSP#
0_0402_5%
1
PJP11
1 2
PC101
2
@0.1U_0402_10V7K
PAD-OPEN 4x4m
PJP12
1 2
+1.5VP +1.5V (13A,520mils ,Via NO.= 26)
PAD-OPEN 4x4m
PJP13
1 2
+0.75VSP +0.75VS (2A,80mils ,Via NO.= 4)
PAD-OPEN 3x3m
A A

Deciphered Date
5 4 3 2 1
5 4 3 2 1
VID [0] VID[1] VCCSA Vout
0 0 0.9V
D
The 1k PD on the VCCSA VIDs are empty. 0 1 0.8V D
+3VS These should be stuffed to ensure that 1 0 0.725V

VCCSA VID is 00 prior to VCCIO stability.
1 1 0.675V
PR111
100K_0402_5%
1K_0402_5%
output voltage adjustable network
1
2 1
PR112
H_VCCSA_VID1 9
2
H_VCCSA_VID0 9
+VCC_SAP
TDC 4.2A
PR113
38 SA_PGOOD 1K_0402_5% Peak Current 6A
2 1 OCP current 7.2A
1U_0603_10V6K
2
PC102
+5VALW
1
PR115
PR114 0_0402_5%
17 +VCCSA_V5FILT
10_0402_1% 1 2
@0.1U_0402_10V7K
2 1
+VCCSA_EN +1.05VSP_PWRGOOD 44,50
PC103
1
2.2U_0603_10V7K
1 2
PC104
C C
2
15
14
16
13
18
PU13
PR116
V5FILT
VID1
PC105
PGOOD
VID0
EN
V5DRV
2.2_0603_5% 0.22U_0603_10V7K
12 1 2 1 2
19 BST PL18
+VCCSA_BT +VCCSA_BT_1
PGND 0.47UH_PCMB042T-R47MN_6A_20%
11 1 2
20
PGND
SW +VCCSA_PHASE +VCCSAP
22U_0805_6.3V6M
10
22U_0805_6.3V6M
1
22U_0805_6.3V6M
SW
22U_0805_6.3V6M
21
2
2
2
2200P_0402_50V7K
PGND PR117
PC109
PC107
PC106
2
0.1U_0402_25V6
PC108
4.7_1206_5%
10U_0805_10V6M
10U_0805_10V6M
TPS51461RGER_QFN24_4X4 9
22 SW
1
1
1
VIN
PC111
1
2
1
2
2
PC113
PC112
PC110
8
SW
1 SNUB_VCCSA
23
VIN
1
1
2
PL19 7
SW
24
+5VALW 1 2 +VCCSA_PWR_SRC VIN
25
TP
MODE
COMP
SLEW
VOUT
HCB1608KF-121T30_0603 VREF PC114
GND
1000P_0402_25V8J
2
2
1
6
3
5
PR118
2 1
+VCCSA_MODE
@33K_0402_5%
+VCCSA_COMP
+VCCSA_SLEW
PR119
PC115 100_0402_5%
2 1 2 1
+VCCSA_VOUT
+VCCSA_VREF
0.22U_0402_10V6K
B B
PR120
2 1 2 1 0_0402_5%
+VCCSA_COMP1
2 1
0.01U_0402_25V7K
PC116 PR121 +VCCSA_SENSE 9

2
3300P_0402_50V7K 10K_0402_5%
PC117
PJP14
1 2
+VCCSAP +VCCSA (6A,240mils ,Via NO.= 12)
PAD-OPEN 4x4m
A A

Title
Issued Date 2011/10/31 Deciphered Date 2012/12/31
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019IE B
5 4 3 2 1
5 4 3 2 1
1 2
PR122 @0_0402_5%
+5VS CSP1A
DIS only:
CSP1A, CSP2A to +5VS. All AXG components are @.
Except
PR272 and PR273 are 0ohm.
LGA, SWA, HGA, BSTA, DIFFA, TRBSTA#, ILIMA, PWMA are float. PC223, PC226, PR202 are 0ohm.
D VSPA, VSNA to GND (HW side). FBA and COMPA are short. PC220, PC215, PR206 are 0ohm. D
CSREFA, TSNSA, IOUTA to GND. CSCOMPA, CSSUMA, DROOPA are short.
PC119
1 2 PC118 1 2
1200P_0402_50V7K
@680P_0402_50V7K .1U_0402_16V7K
2
1 PR1232 PR126 1 PR124 2
330P_0402_50V7K
1 2
PC120
@10_0402_1% FBA3
75K_0402_1%
1
24.9K_0402_1%
2
PC123
1
1 PR1252 @10.7K_0402_1% PH2 PUT COLSE
PC121
1 2
PR127
TO GT
TRBSTA# PC122
1
FBA1 PR129 220K_0402_5%_ERTJ0EV224J PR128
@1.21K_0402_1% Inductor 1 2 1000P_0402_50V7K
1 2
2
2P: 24K
2
@4700P_0402_25V7K CSCOMPA DROOPA CSREFA
1
10_0402_1% PC124
1 2 PC125
1P: 24.9K PC126 2 PR1301 1K_0402_1%
1 2 1 2 165K_0402_1% NTC_PH203
FBA2 330P_0402_50V7K
1 PR1312 PR132 10P_0402_50V8J
3300P_0402_25V7K
1 2 2P: 1.65K
1K_0402_1%
COMPA1 1P: 1K
5.11K_0402_1% PC127
CSREFA
2
0.047U_0402_16V7K
PR134 6.98K_0402_1%
1 PR1332 TSENSEA
SW1A 1 2
2
63.4K_0603_1%
1
PC128
2
2P: 21.5K
15.8K_0402_1%
1000P_0402_50V7K SW1A
1
CSP1A
1
1P: 15.8K PH3
1PR135
8.25K_0402_1%
9 VCC_AXG_SENSE
PC129 100K_0402_1%_TSM0B104F4251RZ
PR136
1000P_0402_50V7K PC130 CSREFA 43
1
1 2
+5VS
2
9 VSS_AXG_SENSE
.1U_0402_16V7K
CSP1A
52 CSCOMPA
58 TRBSTA#
50 CSREFA
53DROOPA
TSENSEA
51CSSUMA
56 COMPA
PR137
55IMONA
57 FBA
59 DIFFA
54 ILIMA
C C
1 2
26.1K_0402_1%
61
47
60
48
49
1 PR1382
46
2_0603_5% PU14 2P: 36K
1P: 26.1K PUT COLSE
PAD
CSP1A
CSCOMPA
ILIMA
VSNA
CSP2A
CSSUMA
CSREFA
COMPA
FBA
DROOPA
DIFFA
VSPA
TRBSTA#
IOUTA
TSNSA
+5VS TO V_GT
+1.05VS_VCCP PC134
1 45 PR139 HOT SPOT
1 2PR142 VCC PWMA 1 2 PC131
6132_VCC 2 44
.1U_0402_16V7K
1 2 VDDBP BSTA 2.2_0603_5% 1 2

.1U_0402_16V7K
130_0402_1%
43
2
2.2U_0603_10V7K
0_0402_5% 3 0.22U_0402_10V6K
VRDYA HGA 42
4 BSTA1
1
PR140
54.9_0402_1%
SWA BSTA1_1 PC135

1
5 EN 41 HG1A 43 1 PR1432
PC133 PR146 SDIO LGA 1 2
PC132 29 VR_ON VR_ON_CPU 6 40 2.2_0603_5% SW1A 43
PR141
1 2 ALERT# BST2 39 0.22U_0402_10V6K

7
2
VR_SVID_DAT1 LG1A 43
8
2
PR145 SCLK HG2

1
10K_0402_1%
VR_SVID_ALRT# VBOOT 38 BST2 BST2_1
95.3K_0402_1% VR_SVID_CLK 9 SW2 37 HG2 43
0_0402_5% NCP6132AMNR2G_QFN60_7X7
1 2
1
1 PR144 2 VBOOT 10 ROSC LG2 36 PC136

VRMP <BOM Structure> SW2 43
1 2 11 PVCC 35 LG2 43 1 2
0.01U_0402_25V7K
8 VR_SVID_DAT ROSC_CPU
1
VR_SVID_DAT1
8 VR_SVID_ALRT# CPU_B+ VRMP 12 VRHOT# PGND 34 6132P_VCCP PR148 2.2U_0603_10V7K
PC137
PR147 1K_0402_1% 13 VRDY LG1 33 1 2
8 VR_SVID_CLK VR_HOT# VSN SW1
VGATE 14 32 43 1 PR14920_0402_5% PC138 +5VS
2
HG1 LG1
15 VSP 31 2.2_0603_5% SW1 43
+1.05VS_VCCP BST1 1 2
23 CSCOMP
TRBST#
DIFF
22 DROOP
30 DRVEN
24 CSSUM
+3VS HG1 43 0.22U_0402_10V6K
25 CSREF
1
19 COMP
29 TSNS
CSP2
PWM
BST1_1
28 CSP1
20 IOUT
26 CSP3
DIFF_CPU BST1
ILIM
1
PR151
18 FB
PR150 10K_0402_5%
75_0402_1%
16
27
17
21
1 PR1522
2
41.2K_0402_1%
2
29 VR_HOT#
3P: 73.2K
2P: 41.2K
COMP_CPU
14,29 VGATE TRBST#
FB_CPU
DROOP
TSENSE
ILIM_CPU
1
8 VSSSENSE 3P: 22p PC140

PC139
2P: 10p
IMON
1 2
1000P_0402_50V7K
.1U_0402_16V7K
2
2
B 8 VCCSENSE B
PR153 12.4K_0402_1%
PC141
2 1
1
CSP1 1 PR1552 TSENSE
1 PR154 2 +5VS
1
10P_0402_50V8J CSP2 PC1426.98K_0402_1%

3P: 330p 1K_0402_1%
PC143 CSP2 0.047U_0402_16V7K
PR157 SW2
2P: 1000p
2
1 2 PC144
2 1
PR156 2 1
1 2 4.32K_0402_1%
PR158 1000P_0402_50V7K
1 2 PC145 49.9_0402_1%FB_CPU1 3300P_0402_50V7K 3P: 21K
8.25K_0402_1%
1 2 COMP_CPU1 CSREF
2
10_0402_1% 2P: 12.4K
1
FB_CPU3 PH4
PR160
680P_0402_50V7K
1 PR1592
PR162 PC147
2
CSREF 43 CSP1 SW1

6.98K_0402_1%
3P: 6.04K
CSCOMP
1 2 0.047U_0402_16V7K 100K_0402_1%_TSM0B104F4251RZ
PC146
2
PR161
2P: 4.32K 1000P_0402_50V7K
4700P_0402_25V7K
1 2
1
1
FB_CPU2 9.53K_0402_1%
1
TRBST#
PC148 3P: 1500p
1.21K_0402_1% CSREF
2P: 1200p
3P: 2200p
2
PC149
2P: 3300p 1 2
CSSUM
1200P_0402_50V7K
3P: 348 3P: 3.65K 1 PR1632
2
2P: 1.21K 2P: 9.53K 169K_0603_1%

.1U_0402_16V7K
1 2 PC151 1 PR1652 SW1

24.9K_0402_1%
PC150
2
330P_0402_50V7K 169K_0603_1% PUT COLSE

1
TO VCORE
PR164
3P: 23.7K 1 PR167 2 SW2

HOT SPOT
2P: 24.9K 1 PR166 2
165K_0402_1%
1
75K_0402_1%NTC_PH201
PR168 PC152
1 2 1 2 PH5
CSCOMP DROOP CSREF
1K_0402_1% 1000P_0402_50V7K 2 1
PUT COLSE
TO VCORE 220K_0402_5%_ERTJ0EV224J
3P: 806 Phase 1
A
2P: 1K Inductor A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 4019IE B
5 4 3 2 1
5 4 3 2 1
D D
PL20
CPU_B+ HCB2012KF-121T50_0805 CPU_B+
2 1
10U_0805_25V6K
@820P_0402_25V7
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_25V7K
5
B+
0.1U_0402_25V6
PL21
@820P_0402_25V7
2200P_0402_25V7K
5
1
HCB2012KF-121T50_0805
1
1
PC157
1
PC158
PC156
PQ24
1
1
PC164
2 1
1
PC155
PC154
1
PC161
PC159
PQ23 1 1
PC153
PC160
PR169 CPU_B+
2
2
+ +
2
1 2 PR170 4
2
2
2
2
2
0_0603_5% 4 PC162 PC163 1 2
HG1_1 HG2_1
42 HG1 +VCC_CORE 100U_25V_M
2
@100U_25V_M
2
42 HG2 0_0603_5%
PL22
+VCC_CORE
0.36UH 20% FDUM0640J-H-R36M S TR MDU1516URH 1N POWERDFN56-8 PL23
3
2
1
S TR MDU1516URH 1N POWERDFN56-8 0.36UH 20% FDUM0640J-H-R36M
3
2
1
1 2
1 2
42 SW1 42 SW2
1
5 <BOM Structure>
5
PQ25 <BOM Structure>
PR171 PQ26 PR172
@4.7_1206_5%
@4.7_1206_5%
2
PR173
2
4 PR174
2 1 2 1
4
42 LG1 CSREF 42 42 LG2 10_0402_1% CSREF
SNUB_CPU1
SNUB_CPU2
10_0402_1%
S TR MDU1512RH 1N POWERDFN56-8
3
2
1
S TR MDU1512RH 1N POWERDFN56-8
3
2
1
1
PC165 SW1 SW2
@680P_0402_50V7K
1
2
PC166
C @680P_0402_50V7K C
2
PL30
HCB2012KF-121T50_0805
2 1
10U_0805_25V6K
@820P_0402_25V7
0.1U_0402_25V6
10U_0805_25V6K
GFX_B+
2200P_0402_25V7K
B+
1
1
1
PC169
PC171
PC170
1
1
PC167
PC168
2
2
5
QC 45W CPU DC 35W CPU

VID1=0.9V VID1=1.05V
PR175 IccMax=94A IccMax=53A
4 PQ27
1 2
HG1A_1
Icc_Dyn=66A Icc_Dyn=43A
42 HG1A 0_0603_5%
Icc_TDC=52A Icc_TDC=36A
R_LL=1.9m ohm R_LL=1.9m ohm
S TR MDU1516URH 1N POWERDFN56-8
+GFX_CORE OCP~110A OCP~65A
3
2
1
PL24
0.36UH 20% FDUM0640J-H-R36M
1 2
1
42 SW1A
5
PR176
<BOM Structure>
@4.7_1206_5%
PQ28
2
B B
4
42 LG1A S TR MDU1512RH 1N POWERDFN56-8
1 SNUB_GFX1
2 PR1771
3
2
1
CSREFA 42
10_0402_1%
PC172
@680P_0402_50V7K SW1A
2
DC 35W GT2
VID1=1.23V
IccMax=33A
Icc_Dyn=20.2A
Icc_TDC=21.5A
R_LL=3.9m ohm
OCP~40A

A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A8581 A
C B
4019IE
5 4 3 2 1
PBL22 LA-7391P M/B

5 4 3 2 1
+VCC_CORE Below is 458544_CRV_PDDG_0.5 Table 5-8.

1 +VCC_CORE +GFX_CORE
5 x 22 µF (0805)
1
1
PC173
1
10U_0805_6.3V6M PC175
PC176 PC177 Socket Bottom 5 x (0805) no-stuff
2
PC174 10U_0805_6.3V6M 10U_0805_6.3V6M

10U_0805_6.3V6M sites
2
10U_0805_6.3V6M
2
2
2
D +GFX_CORE D
7 x 22 µF (0805)
Socket Top 2 x (0805) no-stuff
22U_0805_6.3V6M
sites
22U_0805_6.3V6M
1 1
22U_0805_6.3V6M
PC187
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
PC184
1
22U_0805_6.3V6M
1
PC180 1 1
22U_0805_6.3V6M
1 1
PC183
1
PC188
PC189
PC182
PC185
PC186
10U_0805_6.3V6M
PC190
PC178 PC179 PC181
2
10U_0805_6.3V6M 10U_0805_6.3V6M
10U_0805_6.3V6M
2
10U_0805_6.3V6M 2 2
2
2
2 2 2 2 2 2 +1.05VS_VCCP
+VCC_CORE
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1
+1.05VS_VCCP
22U_0805_6.3V6M
1
22U_0805_6.3V6M
22U_0805_6.3V6M
1 1 1 1
22U_0805_6.3V6M
1 1 1
PC202
PC200
PC201
PC197
PC205
1
PC206
PC196
1 1
PC204
PC203
1
PC199
PC198
PC191
PC192 PC193 PC194 2 2 2 2 2 2
22U_0805_6.3V6M PC195 2 2 2 2
2
22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 2
22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M 1
22U_0805_6.3V6M
2 2 2 1 1 1
PC207
2
PC209
PC208
PC210
2 2 2 2
22U_0805_6.3V6M
1
330U_D2_2V_Y
1 1
330U_D2_2V_Y
1 1
PC216
+
PC217
1 1 1
PC218
+
PC211 PC212 PC213
22U_0805_6.3V6M 22U_0805_6.3V6M PC214 PC215
2 22U_0805_6.3V6M 22U_0805_6.3V6M 2
2 2 22U_0805_6.3V6M
2 2 2
C 1 2 C
1
330U_D2_2V_Y
330U_D2_2V_Y
PC219
+
PC220
+
2 2
1 1 1 1
1 1
PC221 PC224 PC225 PC226
PC222 PC223 22U_0805_6.3V6M 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M
2 22U_0805_6.3V6M 22U_0805_6.3V6M 2 2 2
2 2
+VCC_CORE
1 1 1 1
+ PC227 + PC228 + PC229 + PC230
330U_D2_2V_Y 330U_D2_2V_Y 330U_D2_2V_Y
470U_D2_2VM_R4.5M
2 2 2 2
B B
A A

5 4 3 2 1
5 4 3 2 1
100P_0402_50V8J
<21>
<21>
<21>
<21>
<21>
DGPU_PWR_EN
<21>
<14,16,38>
GPU_VID4
GPU_VID5
GPU_VID3
GPU_VID2
GPU_VID1
GPU_VID0
1
@ PR808
2 1
OPT@ PC233
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
PR809 OPT@ PL31
45,53 SUSP#
0_0402_5%
0_0402_5%
2 1
10K_0402_1%
HCB2012KF-121T50_0805
0_0402_5%
0_0402_5%
2
+5VS +VGA_B+
OPT@ 0_0402_5%
2
1 2
2
2
4700P_0402_25V7K
2200P_0402_50V7K
4.7U_0805_25V6M
0.1U_0402_25V6
1 OPT@ PR188
1 OPT@ PR184
2
D PR190 OPT@ D
4.7U_0805_25V6M
OPT@ PR183
2
2
1
10_0603_1%
2
B+
OPT@ PC238
OPT@ PR187
1
1
1
1
OPT@ PR189
OPT@ PC234
OPT@ PC237
OPT@ PC236
OPT@ PR185
1
1
OPT@ PR186
+3VS
OPT@ PC235
1
1
PR191
2
1
2
2
1
2
1
2
OPT@
1
OPT@ PR192
32 3211_EN
VID6
VID5
VID4
VID3
VID2
VID1
VID0
0_0402_5% MDU1516URH 1N POWERDFN56-8 OPT@ PQ32 MDU1516URH 1N POWERDFN56-8
PC239 OPT@
5
2 1 1U_0805_25V6K
OPT@ PQ33
2
3211_VCC
25
26
3211_PWRGD
27
28
29
30
31
<14,17,45> VGA_PWROK
OPT@ PC240
OPT@ PR194 0.22U_0603_25V7K
VID6
VID5
VID4
VID3
EN
VID2
VID1
VID0
0_0603_5% 1 2 4
1 2 4
24
1 2 VCC OPT@ PL32
1
OPT@ PWRGD 23 0.22UH_PCMB104T-R22MS_35A_20%
PC241 PR193 @ BST CPU_BOOST-1 1 2
2 CPU_BOOST
3
2
1
68K_0402_1% IMON
3
2
22
1
1 2
DRVH
3 3211_DRVH
CLKEN# 21
MDU1511RH 1N POWERDFN56-8
SW
MDU1511RH 1N POWERDFN56-8
1000P_0402_50V7K 4 3211_SW
+VGA_CORE
5
1 2 FBRTN 20
1
ADP3211AMNR2G_QFN32_5X5 PVCC
5 2 1 +5VS 1
470U_D2_2VM_R4.5M
1
OPT@ PC242 OPT@ PC244 3211_FB FB OPT@ PU15 19
220P_0402_50V7K DRVL PR195 +
OPT@ PC245
47P_0402_50V8J 6 3211_DRVL OPT@ PC243
1 2 COMP 4.7_1206_5%
1 2 3211_COMP 18 2.2U_0603_10V6K
2
PGND 4
1
2
OPT@ PR197 7 4 2
1 2 OPT@ PC246 GPU 17
OPT@ PQ34
20K_0402_1% 3211_VCC PC247
OPT@ PQ35
AGND
470P_0402_50V8J
3211_COMP-1 8
CSCOMP
OPT@ PR196 ILIM 680P_0603_50V7K
33
2
3211_ILIM
CSREF
AGND
RAMP
1K_0402_1%
LLINE
CSFB
IREF
RPM
3
2
1
3
2
1
RT
2
16
15
14
13
12
11
10
C
OPT@ PR198 9 C
4.53K_0402_1%
2 3211_IREF
3211_RAMP
3211_CSFB
3211_CSCOMP
3211_RT
1
23211_RPM
274K_0402_1%
3211_CSCOMP
2
80.6K_0402_1%
200K_0402_1%
OPT@ PR201
OPT@ PR199
OPT@ PR200
Avoid high dV/dt

1
499K_0402_1%
2
OPT@ PR204
1
2
PR203
1
1
1
PR202 0_0402_5%
0_0402_5%
2
1
OPT@ PC249 PR205 OPT@
1
OPT@ 820P_0402_50V7K 124K_0402_1%

1
OPT@ PR207 PC248

2 1
2
2
2
OPT@ 1K_0402_1% 1200P_0402_50V7K
OPT@ 2 1
PR206
150K_0603_1%
+VGA_B+ 3211_RAMP-1 OPT@
1
<23>
<23>
VSSSENSE_VGA
VCCSENSE_VGA
PC251 OPT@
1
Connect to input caps 1000P_0402_50V7K

2
OPT@ PC250
+VGA_CORE
1000P_0402_50V7K
Near VGA Core
2
1 1
470U_D2_2VM_R4.5M
1
470U_D2_2VM_R4.5M
1
470U_D2_2VM_R4.5M
470U_D2_2VM_R4.5M
+
@ PC288
Shortest the +
OPT@ PC252
+
OPT@ PC289
+
OPT@ PC254
B
@ PR208
net trace B
0_0402_5% 2 2
2 2
2 1
1
OPT@
+VGA_CORE PR209
Under VGA Chip 0_0402_5%
22U_0805_6.3V6M
1
22U_0805_6.3V6M
1 1
22U_0805_6.3V6M
OPT@ PC262
2
OPT@ PC260
OPT@ PC264
1 1 PR741 OPT@
22U_0805_6.3V6M
22U_0805_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
OPT@ PC261
OPT@ PC263
14.7K_0402_1%
4.7U_0603_6.3V6M
1 2
1
1
2
1
1 2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
OPT@ PC266
OPT@ PC257
2 2
OPT@ PC256
OPT@ PC259
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
2 2
OPT@ PC265
3211_CSCOMP
PH702 OPT@
OPT@ PC255
+3VL
1
OPT@ PC267
100K_0402_1%_NCP15WF104F03RC
OPT@ PC258
2
2
2
1
2
OPT@
2
2
2
PC716
10.5K_0402_1%
2
2
PR742
0.1U_0603_25V7K
2
2
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
OPT@ +3VL OPT@

PR744
1
PU701 OPT@
4.7U_0603_6.3V6M
1
OPT@ PC269
4.7U_0603_6.3V6M
1 14.7K_0402_1%
4.7U_0603_6.3V6M
OPT@ PC268
47U_0805_6.3V6M
1 8
1
1
OPT@ PC502
VCC TMSNS1
4.7U_0603_6.3V6M
1
4.7U_0603_6.3V6M
OPT@ PC272
1
OPT@ PC270
OPT@ PC271
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
1
1
4.7U_0603_6.3V6M
2 7
1
2
OPT@ PC279
2
4.7U_0603_6.3V6M
OPT@ PC275
4.7U_0603_6.3V6M
GND RHYST1
1
OPT@ PC276
2
1
2
OPT@ PC277
1
OPT@ PC274
1
2
OPT@ PC278
6
OPT@ PC273
3
OT1 TMSNS2
2
2
4 5 1 2
2
2
2
OT2 RHYST2 @ PR743

<41> PWR_GPS_DOWN#
G718TM1U_SOT23-8 10.5K_0402_1%
100K_0402_1%_NCP15WF104F03RC
0.1U_0402_10V7K
GPU Skin temperature protection: Protection at 105 degree C
2
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
0.1U_0402_10V7K
1
0.1U_0402_10V7K
OPT@ PC280
PH703
1
1
1
0.1U_0402_10V7K
Recoveyr at 85 degree C
1
OPT@ PC282
OPT@ PC286
OPT@ PC283
OPT@ PC287
1
OPT@ PC281
OPT@ PC284
A A
OPT@ PC285
2
@
2
2
2
2
2
1
2
Requlator temperature protection: Protection at 105 degree C

Recoveyr at 85 degree C

Title
Issued Date 2011/10/31 Deciphered Date 2012/12/31
C B
4019IE
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
For DVT can't power on and need to disable EC VCIN0_PH Reserve PR20 PR21 for DVT can't power on issue
1 Page 47 2012/02/24 VCIN1_PH pin detect
D
PVT D
3D mark06&3D mark Vantage score don't meet SPEC need to Add PC288 PC289 470U_D2_2VM_R4.5M
Page 57 support GPS function PC248 1200P_0402_50V7K
2 2012/02/24 PR209 0_0402_5%
Change PC242 to 220P_0402_50V7K
PC246 to 470P_0402_50V8J
PC244 to 47P_0402_50V8J
PR197 to 20K_0402_1% PVT
PR198 to 4.53K_0402_1%
PC249 to 820P_0402_50V7K
PR205 to 124K_0402_1%
PR206 to 150K_0603_1%
Delete PR208 0_0402_5%
3 Page 49 2012/02/24 For DVT SMT PC56, PC57 footprint did not match issue Change PC56,PC57 footprint from D2 to C_6SVPE220MX PVT
C C
Reserve GPU Skin and Requlator temperature protection circuit
3D mark06&3D mark Vantage score don't meet SPEC need to for if temperature over spec issue PVT
support GPS function Add PC716 SE042104K80 0.1U_0603_25V7K
4 Page 57 2012/02/24
PR741,PR744 SD034147280 14.7K_0402_1%
PR742 SD034105280 10.5K_0402_1%
PH702 SL200000U00 100K_0402_1%_NCP15WF104F03RC
Change PH1 protect action to EC Change PH1 pull high vcc from +3VL to +EC_VACC
5 Page 47 2012/02/24 Change PH1 GND from normal GND to EC_AGND PVT
Delete PU7 74LVC1G17GW TSSOP and change to PQ109 SSM3K7002FU_SC70-3

6 Page 48 2012/02/27 Update Green power Circuit Add PR10 0_0402_5% to connect GREEN_LATCH# PVT
Reserve PR178 0_0402_5%
7 Connect the Green_PWR4 net to EC GPIO for AC decete for Green power
Page 48 2012/03/02 Update Green power Circuit circuit ACOK will drop once time issue PVT
B Add one control signal in order to disable B+ to VSB B

PVT
8 Page 47 2012/03/06 circuit in AC S5 for LOT6 system little than 0.5W issue Reserve PR22 to add VSB_EN
For System can power on immediately after HW shutdown Change PU1.3 output name from EN0 to MAINPOWN
9 Page 47 2012/03/06 Dis-connect EN0 to PU8.13
49 Connect MAINPOWN to PQ18.2
For EU Erp lot6 fail, need to cut off +VSB when system
10 Page 47 2012/04/23 at S5 Add PR22, delete PR14,PR15 Pre_MP
ChangePR56,PR80,PR92,PR95,PR108,PR110,PR115,PR120,PR142,PR144,PR183, Pre_MP
Page 47 2012/04/23 Change to new footprint PR184,PR185,PR186,PR187,PR188,PR189,PR192,PR809 footprint
11 48,50,51 from R_0402 to R0402_0ohm
52,53,54
57
A A

5 4 3 2 1
5 4 3 2 1
QAQ1x HW PIR from EVT to DVT LA-8581P REV:0.1 -> 0.2 <2011.12.05~2012.01.02. >
Rev.Item Date Impact Page Change Cause Modify Description
0.2 1 12/05 Circuit, Layout, BOM 37 Sourcer require to change crystal to small size. Change X1 from "SJ100009A00" to "SJ10000EV00"
2 12/21 Circuit, Layout 41 EVT can't power on issue. Change R739 pull up power source from "+3VALW" to "+3VALW_EC".
3 12/21 Circuit, Layout 26,35,42,36 Vpro require PCIE port1 can't connect to LAN. Swap PCH PCIE port1 and port5.
D D
4 12/21 Circuit, BOM 43 SW7, SW8 part number error. change SW7,SW8 part number to "SN100005G00"
5 12/21 BOM 27 just reserve pull up resistor for SLP_LAN#. Add @ to R282.
6 12/26 BOM 34 TPM IC FW update from FW3.16 to FW3.19. Change U37 from "SA00000GG40" to "SA00000GG70".
7 12/26 Circuit, BOM 33 Add Vpro & non-Vpro WIN8 BIOS ROM power source selection. Add R421, R422.
8 01/05 BOM 40, 43 issue: redetect USB HDD when resume from S3. Add @ to RU27, delete @ to R90; add @ to R9, delete @ to R10.
9 01/05 BOM 41 Board ID issue Add "Rev02@", "Rev03@","Rev04@","Rev10@" serial Rb to distinguish the boards.
10 01/09 Circuit, layout 40 LID_SW# will cause system can't power on at DC mode if use +3VALW, not +3VL. Change U34 Pin2 VDD from +3VALW to +3VL if EC use +3VL.
11 01/09 Circuit, layout,BOM 43 PWR ON LED will flash when doing Crisis. Add a pull down resistor R169 100K to PWR_ON_LED; Reserve a 0ohm resistor R93.
12 01/09 Circuit, layout,BOM 36 DVT will build Vpro SKU, delete EC port80 debug signals to WLAN connector. Delete R684, R1336 and the EC port80 debug signals to WLAN connector.
13 01/09 Circuit, layout,BOM 13,15 No need reserve VGA HDMI connection. Change PCH net "DGPU_HPD_INT#" to PCH_GPIO6;
24
Delete U13,CV197,RV140,RV149,C430,C378,C455,C377,C376,C434,C456,C432,R432,R435,R443,Q65,R439,R437RV132,L88.
C C
14 01/10 Circuit, layout 37,35,26,42 BIOS prefer LAN connect to PCIE port6 for Vpro. Swap PCIE port5 and port6 connection.
15 01/10 BOM 33, Distinguish with Vpro SKU. Change UPCH1 and U59 BOM Structure to "8111E@" for non-Vpro SKUs.
16 01/11 Circuit, layout 43 +USB_VCCE no bulk capacitor. Change C2,C7,C8 power source from +USB_VCCB to +USB_VCCE.
17 01/11 Circuit, layout 41 power CPU OTP issue, and power modified schematic. Delete net EC pin27 "PWR_GPS_DOWN#" and EC pin 76 "PWRMOS_TEMP", delete R732.
QAQ1x HW PIR from DVT to PVT LA-8581P REV:0.2 -> 0.3 <2012.02.24~2012.03.07. >
0.3 1 02/24 Circuit, BOM 35 LL1 and CL13 change after EVT, DVT schematic missed and used MEMO for change. Change LL1 from 4.7uH "SHI00004T00" to 2.2uH "SHI0000AA00". CL13 from 22uF "SE000000I10" to 4.7uF "SE107475K80".
2 02/24 BOM 37 DVT board card reader JMB389 can't detect 4IN1 card. Delete R39 BOM structure "388@".
3 02/24 BOM 27 HDMI HPD signal level is too low for HDMI detection. Add "@" to RH142.
4 02/24 Circuit, layout,BOM 41,13 PVT add GPU GPS feature. Add R266 "@", R267 "@", R268 at Page13, add "@" to DV6.
B B
Change net ACIN_BUF to GPS_DOWN#, add net PWR_GPS_DOWN#, EC_GPS_DOWN#, PWRMOS_TEMP.
5
6 02/24 Circuit, layout,BOM 28 requirement from Sourcer and buyer. Change RP1, RP3 from row resistor "SD309820180" to single ones "SD028820180"-R320,R321,R322,R323,R324,R327,R329,R330.
7 02/24 BOM 35 UL5 BOM structure error with vPro SKU. Delete UL5 BOM structure "8111E@".
8 03/01 Circuit, layout,BOM 35 LAN vendor Realtek suggest:Reserve CLKREQ_LAN# pull up 10Kohm to +3V_LAN. Reserve CLKREQ_LAN# pull up 10Kohm to +3V_LAN: add RL25 and unmount it.
9 03/01 BOM 35 LAN vendor Realtek suggest:Reserve UL1 pin28 "EC_SWI#"pull up 10Kohm to +3V_LAN. Modify reserved resistor RL3 from 100Kohm to 10Kohm.
10 03/01 Circuit, layout,BOM 35 LAN vendor Realtek suggest: 6pcs decoupling capacitor for UL1 Pin 12, 27, 39, 42, 47, 48. Add one more piece capacitor CL12 close to UL1.
11 03/01 Circuit, layout,BOM 41 Reserve and add pull up for added net of EC pin27,68. Reserve R732 10Kohm and add R733 100Kohm pull up to +3VS for EC pin27,68, add R734 0ohm for PWR_GPS_DOWN# connect to EC.
12 03/01 Circuit, layout,BOM 13 Reserve a 0ohm resistor for "GPS_DOWN#" to "PWR_GPS_DOWN#". Reserve a 0ohm resistor R270 for "GPS_DOWN#" to "PWR_GPS_DOWN#".
13 03/02 Circuit, layout 41 power circuit removed net "PWR_MOS_TEMP", added net "GREEN_PWR4". Remove net "PWR_MOS_TEMP", add net "GREEN_PWR4" to EC pin 76.
14 03/05 BOM 26 Adjust crystal loading capacitors' value according to matching test result. Change Y3 from SJ10000DJ00 to SJ10000E800, C869 from SE071150J80 to SE071100J80, C225 from SE071120J80 to SE071100J80.
35 Change YL1 from SJ10000DJ00 to SJ10000E800, CL26 and CL27 from SE071270J80 to SE071120J80.
A A
37,34 Change C54 and C82 from SE071120J80 to SE071150J80; C766,C767 from SE071150J80 to SE071180J80.
13 Change YV1 from SJ10000DK00 to SJ100009700, CV46 and CV47 from SE071180J80 to SE071100J80.
15 03/05 Circuit, layout,BOM 39 Refer to QAL50/51 design for smart card to add pull high to US4 pin26. Add RS22 10Kohm pull up to +3V_SC for US4 Pin26. and change reserved pull down resistor RS21 from 0ohm to 10Kohm.

5 4 3 2 1
5 4 3 2 1
QAQ1x HW PIR from DVT to PVT LA-8581P REV:0.2 -> 0.3 <2012.02.24~2012.03.07. >
0.3 16 03/05 Circuit, BOM 28,39 smart card device lost at USB 3.0 port. Change smart card reader from USB port 2 to port 5.
17 03/06 BOM 31 PCH VCCDSW3_3 change power connection from +3VALW_PCH to +3VALW. Add "@" to R415, delete "@" to R382.
18 03/06 Circuit, layout, BOM 35,36, ErP lot 6 fail, reserve a EC pin VSB_EN to control VSB; Delete reserved net AOAC_ON (EC pin 38) and DRAMRST_GATE (EC pin 98) and their test point T23,T24.
39,29 reserve LAN WAKE to EC and PCH GPIO27. Use these two pins for new added net VSB_EN_R and EC_PME#
D 41,45 Reserve net GPIO27_WAKE#, EC_PME# for LAN WAKE, reserve net EC_PME# to WLAN, WWAN and PCIE Express card wake. D
thus, add R702@, RH122@, RH171, R331@, RL8(8111E@),RL9@, RL10@, R100@, R102, R761@, R767@,R768@.
Reserve net VSB_EN, thus add R765@, R766, R817, R818@, R819@; delete R816@, add @ to R754.
19 03/06 Circuit, layout, BOM 25 Reserve big size crystal Y6 for 32.768KHz. Reserve big size crystal Y6 for 32.768KHz.
20 03/08 BOM 40,43 UU1 SA000047500 was forbidden, change material requirement from buyer. Change UU1 from SA000047500 to SA000033H00; Correct U6 description and value.
21 03/08 BOM 43,44 Change C4,C6 from SE053475Z05 to normal part SE053475Z80. Change C4,C6 from SE053475Z05 to normal part SE053475Z80.
QAQ1x HW PIR from PVT to Pre-MP LA-8581P REV:0.3 -> 1.0 <2012.04.18~2012.04.25. >
1.0 1 04/19 Circuit, BOM,layout 25 Reserve +5VS for MOS Q10 gate of audio sync signal to PCH HDA sync signal. Add 0ohm 0402 resistor R189@ and R190.
2 04/19 BOM 25,34 Change 32.768KHz crystal P/N, and RTC capacitor C204 from 15pF to 18pF. Change Y2, X3 from SJ10000BM00 to SJ100001K00. change C204 from SE071150J80 to SE071180J80.
3 04/19 BOM 39 to solve issue of "Smart Card also show in Device Manager after plug out it". Change US4 from SA000042I00 to SA000042I10.
C C
4 04/19 Circuit,layout 45 Reserve 820Kohm resistor to GND for +3VALW_PCH and +1.05VS_DGPU DC/DC MOS GATE. Add 820Kohm R432@ and R435@.
5 04/19 BOM 45,41 For ErP lot6, add +3VALW to +3VALW_PCH DC/DC circuit. Delete @ for U25, Q46, Q49, R813, C837, C839, C838, R804, C836, R807, R754.
6 04/20 BOM,layout cost down: change some 0ohm resistors to short pad. cost down: change some 0ohm resistors to short pad.
7 04/23 BOM 42 vPro: Intel suggest to change R1232 from 2.2K to 10K. vPro: change R1232@ from 2.2K to 10K.
8 04/23 BOM 42 vPro: Intel suggest to change C470 from 10uF to 22uF. vPro: change C470 from 10uF to 22uF.
9 04/23 BOM 35 vPro: Intel suggest to change CL34 from 0.1uF to 1uF. vPro: change CL34 from 0.1uF to 1uF. keep CL34 0.1uF for 8111E LAN.
04/23 Circuit, BOM,layout 42 vPro: Reserve LAN WAKE to EC. vPro reserve R559@ 0ohm for LAN WAKE connect to EC.
04/25 Circuit,layout 35 There is not enough space for LAN GND ESD diodes. Remove DL3@, DL4@.
EMI test OK without the two ESD diodes.
B B
A A

5 4 3 2 1

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5 4 3 2 1

LA-8581P REV1.0 Schematic

Intel Ivy Bridge/Pather Point

Security Classification Compal Secret Data Compal Electronics, Inc.

VGA (DDR3) Socket-rPGA988B/989 Dual Channel 204pin DDRIII-SO-DIMM X2

page 13,14,15,16,17,18,19,20,21 DMI X4 FDI

LCD Conn. SATA port 0

page 36 page 36 page 25 ~ 32

USB&Function/B SIO ENE KB9012 TPM 1.2

Touch Pad Int.KBD

Security Classification Compal Secret Data Compal Electronics, Inc.

Ipeak=5A, Imax=3.5A, Iocp min=7.9 DESIGN CURRENT 5A +5VALW

DESIGN CURRENT 30A +GFX_CORE

DESIGN CURRENT 26A +VGA_CORE

DESIGN CURRENT 2A +0.75VS

DESIGN CURRENT 6A +VCCSA

Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails起点主板维修网 ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ BOM configu table

B+ AC or battery power rail for power circuit. N/A N/A N/A

+VGFX_CORE Core voltage for UMA graphic ON OFF OFF

Power Device Address Power Device Address

PCH SM Bus address ZZZ DA8@ ZZZ DAZ@

Power Device Address

+3VS DDR DIMMA 1001 000x b

PCI EXPRESS* - GRAPHICS

+1.05VS_VCCP C17 PEG_TX[7] J27 PCIE_CTX_GRX_P6 PCIE_CTX_C_GRX_P6 G20 VSS227

Security Classification Compal Secret Data

1 2 PM_SYNC TRST# XDP_TMS_R

@ C379 FAN_SPEED <41>

Security Classification Compal Secret Data

DDR SYSTEM MEMORY B

CONN@ TYCO_2013620-2_IVY BRIDGE

R118 0_0402_5% DRAMRST_CNTRL_PCH <10,26>

CFG[1:0]: reserved configuration lane. AH27

PEG DEFER TRAINING

1: (Default) PEG Train immediately

Security Classification Compal Secret Data Compal Electronics, Inc.

起点主板维修网 ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ JCPU1F POWER

PEG AND DDR

R26 VCC89 AJ35 short@

Security Classification Compal Secret Data Compal Electronics, Inc.

AH23 VAXG49 L26

AH21 VAXG50 J26 @ 1

AH18 VAXG52 J24 330U_X_2VM_R6M SA: System Agent

AH17 VAXG53 H26

+1.8VS +1.8VS_VCCPLL @ R92

1 VCCPLL3 VCCSA_VID[1] 0_0402_5%

VCCSA_VID Configuration --CPU EDS Page99.

Security Classification Compal Secret Data Compal Electronics, Inc.

R55 +1.5V +1.5V <7> DDR_A_D[0..63]

3A@1.5V <7> DDR_A_DQS[0..7]

VTT1 PM_SMBCLK <12,26,36,39>

205 206 +0.75VS

Compal Secret Data Compal Electronics, Inc.

RD10 +1.5V +1.5V +1.5V Layout Note:

2 2 DDR_B_D1 VSS4 DQS#0

13 DM0 DQS0 14 DDR_B_DQS#0

127 NCTEST VREF_CA 128

DDR_B_D33 135 136

DQS#4 DM4 1K_0402_1%

A 201 VDDSPD SDA 202 A

起点主板维修网 ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ PEX_RX2 P7 VID_4

<26> CLK_PCIE_VGA# CV44

Voltage Rails起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ BOM configu table

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ JCPU1F POWER

起点主板维修网　ｗｗｗ．ｑｄｚｂｗｘ．ｃｏｍ PEX_RX2 P7 VID_4