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Partial 5/3 Level Topology for Solar Grid-tie Inverters

Conference Paper · October 2014


DOI: 10.1109/ECCE.2014.6954188

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Partial 5/3 Level Topology for Solar Grid-tie Inverters
Antonio Ginart1, Senior Member IEEE , Richard Liou1,2, Student Member IEEE, Andres Salazar1 Member IEEE,
Carlos Restrepo1 Member IEEE, Michael Ernst 1 Member IEEE
1 2
SOLARMAX, GA 30093, USA Georgia Institute of Technology, GA 30332, USA

Abstract— Solar inverters are designed specifically to levels that the inverter produces (multilevel inverters).
handle photovoltaic (PV) panels, to efficiently extract the Increasing the switching frequency faces two key
most amount of power, and to transform it properly so obstacles: the need for faster power devices such as
that it can be injected into the grid. The singularities of wide-band gap devices that can be driven at such high
the application allow for opportunities that can be
exploited for better performance. Inverters for PV
frequencies, and for faster and more powerful
applications are designed to operate at very low voltage microcontrollers in order to achieve proper active
variations, almost at a fixed frequency, and with a power monitoring of complex systems such as solar inverters,
factor usually greater than 0.8. While keeping these thus leading to higher costs. Driven by the trending
inverter-specific characteristics in mind, a new topology is lower cost of power semiconductors, the solar industry
proposed. In this work, such new topology provides therefore has, progressively, moved into the use of
operational characteristics close to a 5-level topology. This multilevel inverters as the more yielding of the two
achievement is accomplished by adding just a few more approaches.
power-electronic components required for a 3-level In general, a grid-tie PV system is comprised of the
topology. A complete 3-phase system is designed and
devices shown in Figure 1. This consists of the PV
simulated. Its good performance is demonstrated, and its
benefits and limitations are pointed out. Furthermore the panel’s field arrangement connected in series to provide
feasibility of this new topology is also explored and the input voltage range to the inverter. The inverter
verified by implementing a low-power inverter system block could include a voltage booster stage. A
with the proposed topology. transformer that may be or not included in the inverter
unit is used for the final connection to the grid.
I. INTRODUCTION
DC-AC
Inverter
The solar industry is under increased pressure to deliver
solutions fitted to meet low-cost, high efficiency and Controller
good performance demands. In order to meet those Booster
demands, the industry is seeking means and methods PV Panel
DC LINK
that offer the same performance at a more aggressive
Inverter
price point. For that it is important to have a clear
+ Transformer
understanding of the application and the specific Booster
Filter Grid
singularities of the PV domain, including those of all
components in the power generation/conversion V
process. As part of this chain, solar inverters have very
peculiar characteristics that single them out from those
-
~
used in more traditional applications like motor drivers
[1]. The more outstanding of those characteristics are Figure 1. PV grid-tie inverters parts and diagram representation.
that PV inverters are designed to operate at very low
voltage variation, almost fixed frequency, and with a
power factor usually greater than 0.8. These special II. STATE OF ART MULTILEVEL INVERTER
characteristics present the opportunity to elaborate a
specialized inverter that meets the requirements of Over the past 30 years multilevel inverters have been
being low-cost while maintaining very high part of different research topics focused on several
performance. There are two main complementary hard- areas of interest including new topologies, new
switching techniques that produce a sinusoidal wave controls, and new modulation schemes. One of the
with low-distortion: (1) by generating a high frequency main multilevel inverter topologies is the cascade
PWM and (2) by instating the variation of DC voltage multi-cell inverter, which is based on a series

978-1-4799-5776-7/14/$31.00 ©2014 IEEE 5736


connection of H-bridge modules with separated DC III. PRINCIPLE OF OPERATION
sources. This topology was first introduced in 1975 by
[2] and became widely used only until the mid-90s [3].
In both the MNPC and the NPC, the principle operation
A recent improvement was found in [4] where a 9 level
can be explained as two buck converters, one each for
cascade inverter topology is presented. The authors
the positive and negative part of the sinusoidal. The
combined the classical 5 level cascade topology with a
two buck converters disconnect alternatively to avoid a
clamping voltage element in order to produce the nine
short circuit between each other. Using the NPC
levels, reducing the number of elements used by the
structure, Figure 3 shows how a three level inverter can
classical 9 level cascade multi-cell inverter. Multi-cell
be described as two buck converters.
inverters have presented problems in field applications Positive Buck
where uniform operation among the cells is difficult
due to weather and aging problems. + main
V V
The neutral–point diode clamped inverter (NPC) 2 2
topology was developed as an alternative for the -
cascade multi-cell concept, and it was described for the
first time in [5]. Since then, the 3 level (3L) clamped V SW
diode inverter has become favorably accepted for the R R
design of high-power medium and low voltage +
applications [6]. New topologies based on the 3L NPC V V
have been proposed and are discussed in [7]. At the 2 2 main
same time a new concept of multilevel clamping is - Negative Buck
introduced (MNPC), producing an alternative topology Figure 3. Basic operation of the NPC inverter.
in which a classical 3 level NPC can be selectively
clamped by a dedicated switching unit in order to Using the diagram description detailed at the top of
increase the number of voltage levels, see Figure 2. Figure 4, the fractional 5/3 level topology emerges
from the 3 level MNPC. This new topology has the
+ +
ability to behave as a 3 level topology for the low
V V voltage sections of the sinusoidal and as a 5 level
2 2
topology for the generation of the high voltage part of
- - the sinusoidal.
Grid Grid
Load Load
+ +
+ +
V V
2 2
V V
2 2 - -
- -
V
Figure 2. Diagram of NPC and MNPC 3 level inverter topologies.
+
In addition to the diode clamping concept, the flying
capacitor topology has also been introduced in different V V
researches [8]. In such circuits, capacitors are used to 2 2
- -
clamp the device voltage to one capacitor voltage from
a capacitor voltage divider [3]. However, in some cases
flying capacitor topologies have been combined with +
V
the NPC to produce additional voltage levels using 4
fewer elements than a traditional topology. It is -
+
described in [9], where a hybrid 5 level topology is V
4
proposed. - Grid
V
The most common multilevel inverters used in the solar + Load
V
application are the NPC and the modified NPC [10], 4
generally known as MNPC [12] or NPC2. -
Theoretically the NPC topology requires components +
V
that withstand half voltage, but the MNPC arrangement - 4
could deliver a more efficient inverter topology. With
the improvement of power semiconductors, the NPC Figure 4. Evolution from MNPC to 5/3 level topology.
topology has been increasingly implemented in
commercial solar inverters.

5737
The comparison between the standard voltage semiconductor technologies can favor the selection of
generated by a three level topology and the 5/3 level topologies that match the semiconductor strengths. In
topology is shown in Figure 5. The three level topology order to make a comparison among NPC, MNPC, and
is shown on the left, while the 5/3 level topology is 5/3, a theoretical framework has been developed in a
shown on the right. way that assumes the same state of the art technology
for 600V and 1200V IGBTs. The comparison of the
performance among topologies was also developed
below assuming a cos(Φ) close to one and similar
operation in current and voltages.

The set of equations that govern the system are shown


below:
Figure 5. Comparison of three level and 5/3 level topologies. ON
∂i(t )
The basic operation of the 5/3 topology is detailed in VDC −V TSon−VLN sin( wt − φ ) = Ri(t ) + L (1)
Figure 6. The positive generation of a sine wave is ∂ (t )
accomplished by steps 1 and 2, while the negative part
OFF
is generated by steps 3 and 4. It is important to mention
that even though steps 2 and 4 are not able to take ∂i (t )
− VTSoff − VLN sin( wt − φ ) = Ri (t ) + L ( 2)
reactive power, it is not a significant problem for solar ∂ (t )
inverters that are usually specified to operate with a Where:
power factor greater than 0.8. Operation with low VTSon is the total voltage drop in the semiconductor
power factor is allowed but only in 3 level topology during the ON period.
mode. VTSoff is the total voltage drop in the semiconductor
during the OFF period.
1 2 3 4 VDC has the value of V/2 for NPC and MNPC and
1 additionally V/4 for the 5/3 topology.
PWM PWM

off on 1) Conduction losses:


The voltage drop in the semiconductor defines the
1 conduction losses in the inverter.
on off

³
The average power can be computed using (3).
on off 1 T
P= V (t ) I (t )dt (3)
off T 0
on
Based on linearization the power dissipated can be
PWM PWM
computed as follows:
V (t ) = Vto + Rds ⋅ I (t ) (4)

T ³0
Substituting (4) in (3):
1 T
P= [Vto + Rds ⋅ I (t )]I (t )dt (5)

P = Vto (T ) ⋅ I Average + Rds (T ) ⋅ I Rms (6)

2) Switching losses:
The energy released by switching is given as
Et (T , V , I , φ ) = Eon + Eoff
. (7)
Figure 6. 5/3 level sequences of switching and wave generation. For constant, T, V, I, and cos(Φ):

IV. PERFORORMANCE AND DESIGN PSW _ Loss = E t ⋅ f SW


CONSIDERATION (8)

To explore Et dependence on current during switching


Comparisons among topologies are highly dependent
the other parameters are assumed to be constant:
on actual semiconductor technology applied to each
topology. For this reason the advancement in

5738
E SW = ( Et ( I1 ) ⋅ + Et ( I 2 ) ⋅ +..... + Et ( I n )) (9) topology VCE2 is on all time, while in the MNPC it is
only on in the OFF period. The 5/3 topology carries the
advantages of the MNPC with the addition of lower
From empirical data Et can be linearized as a function switching losses by the IGBT due to the open drain-
of the current: source voltage drop (VDS) reduction during about half
Et ( Ip) of the conduction (ON) period.
E SW (n) = Et (n) I (n ) = I (n ) (10)

= t [I (1) + I (2) + .. + ( I n )] = t ¦ I (n) (11)


IP
E E n VCE1 VCE2
E SW
IP IP 1
+
As a consequence, the power losses as a function of the
current can be calculated as show in (12).
V VD
I Average 2
Psw _ Loss = Et f SW ⋅ (12)
-
IP
(a)
For a similar analysis as a function of voltages:
VCEAverage
Psw _ Loss = Et f SW ⋅
VCE max (13) VCE1

3) Topology comparison + VCE2


The comparison among topologies is made assuming
IGBT trench stop technology or similar. 600 Volts
V
technology is assumed for all switches in the NPC 2
topology. For the MNCP and 5/3 topologies the main VD
switching device is assumed to be 1200V. Table 1
- (b)
compares the average conduction and switching losses
Figure 7. Graphical comparison between NPC and MNPC topologies.
between 600V and 1200V IGBTs for 40-60 Amps from
two leading IGBT manufacturers Infineon and
Fairchild.
TABLE 2. CONDUCTION AND SWITCHING SEMICONDUCTORS IN NPC,
TABLE 1. COMPARISON AMONG 600V AND 1200V IGBTS MNPC AND 5/3
600V 1200V PWM PWM
NPC MNPC ON OFF
Conduction(VDS) 100% 110% NPC VCE1+ VCE2 VD+ VCE2
SW Losses Et 100% 170% MNPC VCE1a VD+ VCE2
5/3 VCE1a/VCE1 VD+ VCE2
a. 1200V IGBT
The graphical comparison of conduction and switching
losses for the different switches in MNPC and NPC
configurations are shown in Figure 7. In the NPC For NPC and MNPC a half wave sinusoidal passes through
topology, for a cos(Φ) close to one during PWM ON the main switches. In the case of 5/3 the main clamping
period, VCE1 and VCE2 present a voltage drop. In PWM semiconductors deal with the top of the sinusoidal (π/4-
OFF period only VD and VCE2 present a voltage drop. 3π/4), while the central clamping devices see the lower part
In the case of MNPC in PWM ON period only VCE1 of the sinusoidal (0−π/4 and 3π/4-π), as seen in Figure 8.
presents a drop voltage, and in PWM OFF period only
VD and VCE2. In conclusion, it is clear that in the NPC

5739
fact that during the ON period both
b DC link capacitors
supply current, but in the OFF perriod only the centrals do.
V/2 Figure 10 shows this phenomenon and
a the proposed balance
circuit.
V/4
Ip
ʋ/4 3ʋ/4 ʋ 2ʋ
Figure 8. NPC and MNPC currents and 5/3 clam
mping currents.

Based on Figure 8 the estimation of the average current


through the semiconductor is shown in Tablle 3.
TABLE 3: CURRENT SEMICONDUCTORS AVERAGE IN N
NPC, MNPC AND 5/3
Main Clamping C
Clamping
Main C
Central Figure 10. Unbalanced discharge capacitorr circuit and DC/DC converter
capacitor voltage balanccer circuit.
NPC Ip Ip
0-π π π V. SIMULA
ATION
MNPC Ip Ip
0-π π π A complete 25KW 3-phase system 480V is simulated using
5/3 Ip Ip Ip PSIM. The PWM switching frequen ncy was slowed down to
2 2π
3 kHz to present detailed results. Thhe AC filter and DC link
π 2π capacitance are typical of a 3 leveel inverter of this power
0−π/4 3π/4-π π
π/4-3π/4 rating. To balance the capacitorss, a low power DC/DC
converter is incorporated into the deesign. At 25 KW, the DC
Using (2) to (12) and information shown inn Tables 3 and 4 voltage stabilizer delivers 1KW witth an estimated efficiency
a theoretical comparison can made among the topologies of 95% and increases the losses off the system by about 50
regarding the losses ratio. The losses ratio is defined as the watts.
amount of conduction losses versus swittching losses. A
losses ratio of one implies only conduction losses, while 0.5 2000uf
implies half conduction losses and half sswitching losses.
The voltage capacitor compensator requuired in the 5/3
topology is assumed constant and 2% of thee total losses. 500uH

G
DC
V R
DC I
D

20uf

Figure 11. Diagram of the 3 phasse 5/3 level inverter.

The simulation results are shown inn Figures 11 and 12.


Figure 11 shows line to neutral volltage and current. On the
bottom line to line voltage is shownn. In Figure 12 the RMS
load current and the RMS currentt injected to compensate
voltages in the capacitors are 23A A and 2.2A respectively,
showing that the current needed to balance the voltage is
less than 10% of the load current.
Figure 9. Relative losses based in power loss distribution.

4) Capacitor Voltage Compensator Circcuit:


The central two capacitors experience llarger a current
discharge than the two external capacitors. T
This is due to the

5740
VI. EXPERIMENTA
AL RESULTS

As a proof of concept a modular siingle phase 500V and 12


Amp inverter was built. The 5/3 inv verter design is based on
a Fairchild FGH40T100SMD IGBT T (1000 V, 40 Field Stop
Trench) and STTH3010 (STMicroelectronics 1000V, 30A)
clamping diodes. The control of thee inverter is based on the
TI microcontroller TMS320F28335. The signals from the
microcontroller were sent to their respective isolated gate
drive circuits. The switching frequeency of the inverter is set
to 16 kHz.
Microcontroller

Clamping Diodes

+
+ IGBTS

Drivers
Figure 11. Top - line to neutral voltage and current, bbottom - line to line
voltage.
0

Load
Current (A)

- IGBTS

Figure 13. 5/3 one phase inverter.

The output of voltage and currentt is shown in Figure 14.


Because it is only single phase, a large variation of the
uit. A three phase system
voltage is experienced in the circu
will minimize this variation.
Current (A)

Figure 12. Top - capacitor compensator current, botttom - load current.

MNPC and the proposed technology are com mpared under the
same load, line voltage, AC filter, and P
PWM frequency.
Using MNPC as a base for THD (100%), thhe 5/3 L inverter
produces 17% less THD for the voltage andd 39% less in the
current.
Figure 14. Output voltagee and current.
TABLE 4. COMPARISON OF 5/3 AND MNP
PC THD
The thermal image of the 5/3 invertter is shown in Figure 15.
MNPC 5/3
The two main IGBTs are at high her temperatures due to
THD THD
being exposed to larger stress com mpared to the clamping
Voltage L-N 100% 83%
devices.
Load Current 100% 61%

5741
[8] Barbosa, P.; Steimer, P.; Steinke, J.; Winkelnkemper, M.;
Celanovic, N., "Active-neutral-point-clamped (ANPC)
multilevel converter technology," Power Electronics and
Applications, 2005 European Conference on , vol., no., pp.10
pp.,P.10, 0-0 0
[9] Fazel, S.S.; Bernet, S.; Krug, D.; Jalili, K., "Design and
Comparison of 4-kV Neutral-Point-Clamped, Flying-
Capacitor, and Series-Connected H-Bridge Multilevel
Converters," Industry Applications, IEEE Transactions on ,
vol.43, no.4, pp.1032,1040, July-aug. 2007 Design and
comparison of 4-KV neutral point-clamped. Fazel
[10] A. NABAE, I. TAKAHASHI, H. AKAGI, A new neutral-
point-clamped PWM inverter, IEEE Trans. on Industry
Applications, Vol. 17, No. 5, sept.-oct 1981, pp. 518-523.
[11] Ingo Staudt, “3L NPC & TNPC Topology” Application Note
Figure 15. Thermal imaging of 5/3.
AN-11001 Semikron 2012-09-03
http://www.semikron.com/skcompub/en/Application_Note_3
VII. CONCLUSION L_NPC_TNPC_Topology.pdf
[12] Zixin Li, Ping Wang, Yaohua Li, and Fanqiang Gao A, “A
Novel Single-Phase Five-Level Inverter With Coupled
A novel low cost topology that exhibits performance similar
Inductors,” IEEE TRANSACTIONS ON POWER, VOL. 27,
to a 5 level topology was simulated and experimentally NO. 6, JUNE 2012 pp. 455-452.
validated. The main drawback is that the topology requires
an extra circuit to balance the capacitors. A single full
bridge DC-DC converter is proposed to balance the
capacitors. Future work is needed to produce experimental
results of a full 3-phase system.

ACKNOWLEDGMENT

The authors thank Mr. Richard Riley for his contribution


to this paper.

REFERENCES
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