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CHAPTER IV

DESIGN OF A LOW POWER AND AREA EFFICIENT NEW

RECONFIGURABLE FIR FILTER FOR DSP APPLICATIONS

4.1 Reconfigurable FIR Filter

The explosive growth in mobile computing and portable multimedia applications

has increased the demand for low power digital signal processing (DSP) systems. One of
the most widely used operations performed in DSP is Finite Impulse Response (FIR)
filtering. The input-output relationship of the linear time invariant (LTI) FIR filter can be
expressed as the following equation (4.1):

Where N represents the length of FIR filters, Ck the coefficient and n is the input
data at time instant. In many applications, in order to achieve high spectral containment
and/or noise attenuation, FIR filters with Fairly Large Number of taps are necessary.
Many previous efforts for reducing power consumption of FIR filter generally focus on
the optimization of the filter coefficients while maintaining a fixed filter order. In this
approach (Seok-Jae Lee 2011) FIR filter structures are simplified to add and shift
operations, and minimizing the number of additions/subtractions is one of the main goals
of the research. However, one of the drawbacks encountered in this approach is that once
the filter architecture is decided, the coefficients cannot be changed; therefore, these
techniques are not applicable to the FIR filter with programmable coefficients.
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Filters are signal conditioners (Chen.K.H 2006). Each one functions by accepting
an input signal, blocking pre-specified frequency components, and passing the original
signal minus those components to the output. In a typical digital filtering application,
software running on a digital signal processor (DSP) reads input samples from an A/D
converter, performs the mathematical manipulations dictated by theory for the required
filter type, and outputs the result via a D/A converter.

An analog filter, by contrast, operates directly on the analog inputs and is built
entirely with analog components, such as resistors, capacitors, and inductors. There are
many filter types, but the most common are low pass, high pass, band pass, and band
stop. A low pass filter allows only low frequency signals (below some specified cut-off)
through to its output, so it can be used to eliminate high frequencies.

A low pass filter is handy, in that regard, for limiting the uppermost range of
frequencies in an audio signal; it’s the type of filter that a phone line resembles. A high
pass filter does just the opposite, by rejecting only frequency components below some
threshold.

Their impulse response, which can be either finite or infinite. The methods for
designing and implementing these two filter classes differ considerably. Finite impulse
response (FIR) filters are digital filters whose response to a unit impulse (unit sample
function) is finite in duration. This is in contrast to infinite impulse response (IIR) filters
whose response to a unit impulse (unit sample function) is infinite in duration. FIR and
IIR filters each have advantages and disadvantages, and neither is best in all situations.
FIR filters can be implemented using either recursive or non recursive techniques, but
usually non recursive techniques are used.

FIR filters are widely used in digital signal processing (DSP) systems that are
characterized by the extensive sequence of multiplication operations (Muhammad 1999).
FIR filters are widely used in various DSP applications. In some applications, the FIR
filter circuit must be able to operate at high sample rates, while in other applications, the
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FIR filter circuit must be a low-power circuit operating at moderate sample rates. The
low-power or low-area techniques developed specifically for digital filters can be found
in. Parallel (or block) processing can be applied to digital FIR filters to either increase the
effective throughput or reduce the power consumption of the original filter. While
sequential FIR filter implementation has been given extensive consideration, very little
work has been done that deal directly with reducing the hardware complexity or power
consumption of parallel FIR filters . Traditionally, the application of parallel processing
to an FIR filter involves the replication of the hardware units that exist in the original
filter.

The topology of the multiplier circuit affects the resultant power consumption.
Choosing multipliers with more hardware breadth rather than depth would not only
reduce the delay, but also the total power consumption. A lot of design methods of low
power digital FIR filter are proposed, for example, implementing FIR filters using just
registered address and hardwired shifts.

4.2 Transposed Direct Form Of FIR Filter

As shown in Fig.4.1, FIR filtering operation performs the weighted summations of
input sequences, called as convolution sum, which are frequently used to implement the
frequency selective low-pass, high-pass, or band-pass filters .Generally, since the amount
of computation and the corresponding power consumption of FIR filter are directly
proportional to the filter order, if we can dynamically change the filter order by turning
off some of multipliers, significant power savings can be achieved. However,
performance degradation should be carefully considered when we change the filter order.
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Fig 4.1 Transposed direct form of an FIR filter

In the fixed point arithmetic of FIR filter, full operand bit-widths of the multiplier
output is not generally used (Mahesh.R 2007). In other words, as shown in Fig. 4.1, when
the bit-widths of data inputs and coefficient are 16, the multiplier generates 32-bit
outputs. However, considering the circuit area of the following adders, the LSBs of
multiplier outputs are usually truncated or rounded-off, (e.g., 24 bits are used in Fig.4.1)
which incurs quantization errors. When we turn off the multiplier in the FIR filter, if we
can carefully select the input and coefficient amplitude such that the multiplication of
those two numbers is as small as the quantization error, filter performance degradation
can be made negligible.

4.3. Architecture of Proposed Reconfigurable FIR Filter

The proposed coefficient representation technique uses signed digit to represent
each sub-coefficients. In conventional coefficient partitioning method, the main
coefficient may be assumed signed value, but the sub-coefficients are not signed. From
the bit word length sub-coefficients case, their values are in 0 ~ 2m-1 range.
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Fig 4.2 Transposed direct form of an FIR filter.

Eight partial products are calculated by pre-computer block using shift/sum
operation and distributed to each tap's PE block. In practical implementation just four ×1,
×3, ×5, ×7 partial products are implemented in pre-computer block and other products
(×2, ×4, ×6, ×8) are composed by simple hardware shift operation of above four partial
products inside PE block. The required four sub-coefficients to compose the desired
coefficient are selected by four 8:1 multiplexers, which are controlled by Mux control
block. This block uses hi,j bits of each sub coefficient to control the selection bits of
multiplexers. Note that it is need to eight partial products (×1, ×3, ×5, ×7, ×9, ×11, ×13
and ×15 in practical implementation) and four 16:1 multiplexers in conventional
reconfigurable FIR filter architecture.
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The selected four partial products in PE block, after hardwire shift operation are
combined by add/sub operation while controlled by Add/Sub control block. This block
uses the sign bit of each sub-coefficient, and control the add/sub block. To implement the
multiplication by zero for each sub coefficient, the multiplexer blocks are followed by
AND gates, which is controlled by Mux control block. Three full add/sub blocks are used
to combine the partial products of sub coefficients. Implementing the reconfigurable filter
is as small as a single multiplier.

4.3.1 Precomputer:
The multiplications, 1x, 3x, 5x, 7x, 9x, 11x, 13x and 15x performed by the pre
computer are simply implemented by the Adder, fig. 4.3 shows the whole pre computer
structure.

Fig 4.3 Structure of the pre-computer.

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Fig 4.4 Programmable element for Proposed Reconfigurable FIR filter.

4.4 Results & Simulation

The results presented establish a clear area advantage of Proposed FIR

architecture over prior architecture for typical filter parameters with comparable Low
power and Low area. The Proposed architecture achieved high clock frequency compared
to direct form architectures. This technique was validated on Spartan-III devices and
the proposed method was observed to have significant area and power reductions over
traditional Distributed Arithmetic based techniques.
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Fig 4.5 Simulation Result of Proposed Reconfigurable FIR Filter.

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Fig 4.6 Synthesis Result of Proposed Reconfigurable FIR Filter for area.
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Fig 4.7 Synthesis Result of Proposed Reconfigurable FIR Filter for power.
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Table 4.1 Comparison of Delay, Clock Frequency and Power of Direct Form and
Proposed.

METHODS DIRECT FORM PROPOSED

LUT 27 20

Slices 43 21

Power (mW) 389 300

450

400 389

350

300
268

250
Lut
Slices
200
power(mW)

150

100

43
50 27
14 20
0
Direct Form Proposed

Fig 4.8 Performance comparison of PSM and Proposed.

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4.5 Conclusion

This research work presents a modified reconfigurable FIR filter, using which it is
possible to implement reconfigurable higher order filters for low power. The Proposed
architecture results provide low area and low power filter implementations. It also
provides the flexibility of changing the filter coefficient word lengths dynamically. The
architectures were implemented on Spartan-III XC3S200-5PQ-208 FPGA and
synthesized. The proposed reconfigurable architecture provides low area and low power.