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Analog Electronic Circuits

Book · January 2006

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D.K. Kaushik
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PREFACE

The present book Analog Electronic Circuits primarily intended for use of
students of B.E. /B.Tech., M.Sc. (Physics) and B.Sc. (Electronics) students of all Indian
Universities. The subject matter of this book has been developed in a systematic, logical
and concise form to meet the requirements of the students. The efforts have been made by
the author in making the subject matter thoroughly exhaustive and nothing of importance
has been left.
The book has been divided into eleven self contained chapters. Beginning with
Transducers and IC fabrication, a good back ground on feedback Amplifiers has been
made. Operational Amplifiers and their applications have been discussed at length in two
chapters (fourth and fifth) with a large number of examples. The sixth chapter deals with
Regulated Power Supply. Oscillators and Multivibrators have been described in adequate
details in chapters seventh and eighth. Chapters ninth, tenth and eleventh give the
detailed discussion on Active Filters, Bridge Circuits and Switching Devices & Circuits.
I am sure and confident that the teachers and students will find this book a good
and useful text book and to the point.
I am deeply indebted to Prof. P. J. George, Chairman, Depatment of Electronic
Science, Kurukshetra University, Kururkshetra for giving me inspiration and enormous
encouragement in writing this book.
It is my privilege to thank Shri Anil Bansal, Chairman, Jind Institute of
Engineering and Technology, Jind for showing the keen interest in the completion of this
book.
I am grateful to Dr. R. K. Tomar, Principal Dayanand College, Hisar for inspiring
me in writing this book.
The author gratefully acknowledges the motivation received from all the
colleagues and friends.
The author also wishes to thank Mr. K.K.Kapoor, Mr. Tarun Kapoor and Mr.
Sumit Kapoor, Publishers, Dhanpat Rai Publishing Company, New Delhi for their keen
interest in publishing the first edition of the present book.
I thank my wife Mrs. Pratibha Kaushik and son Er. Amit Kaushik for their
cooperation and understanding during the time the book was under preparation. Special
thank goes to my nephew Vishal Gaur for the interest taken by him in getting the
manuscript and diagrams of the book computerized.
Any constructive comments, suggestions and criticism from the teachers and
students for further improvement of the subsequent edition will be highly appreciated and
thankfully acknowledged.

HISAR D. K. KAUSHIK
Contents
Chapter1Transducers

1.1 Classification of Transducers


1.2 Selection Criteria for Transducer
1.3 Resistance Strain Gauge
1.4 Types of Strain Gauges
1.5 Potentiometric Transducer
1.6 Resistance Thermometer
1.7 Thermistor
1.8 Thermocouple
1.9 Photoelectric Transducer
1.9.1 Vacuum Photo tube
1.9.2 Gas Filled Phototubes
1.9.3 Photomultiplier Tubes
1.9.4 Photo Conductive Cell
1.9.5 Photo Voltaic Cell
1.9.6 Photo Junctions
1.10 Capacitive Transducers
1.11 Inductive Transducers
1.11.1 Change in Self Inductance with Number of Turns
1.11.2 Change in Self Inductance with Change in Permeability
1.11.3 Variable Reluctance Type Transducers
1.11.4 Linear Variable Differential Transducer (LVDT)
1.12 Piezoelectric Transducer
1.13 Microphones
1.13.1 Carbon Microphone
1.13.2 Moving Coil Microphone
1.13.3 Crystal Microphone
1.13.4 Capacitor Microphone
1.14 Loudspeaker

Chapter 2 IC Fabrication
2.1 Integrated Circuit Technology
2.2 Advantages of Integrated Circuits (ICs)
2.2.1 Limitations of the Integrated Circuits
2.3 Basic Monolithic Integrated Circuits
2.3.1 Wafer Preparation
2.3.2 Epitaxial Growth
2.3.3 Masking and Etching
2.3.4 Diffusion of Impurities
2.3.5 Metallization
2.4 The Planar Technology
2.5 Monolithic Integrated Circuits Technology
2.5.1 P-N Junction Isolation
2.5.2 Dielectric Isolation
2.5.3 V-groove Isolation
2.6 Formation of Monolithic Integrated Circuit Components
2.6.1 N-P-N Transistors
2.6.2 Diodes
2.6.3 Resistors
2.6.4 Capacitors
2.6.5 P-N-P Transistors
2.7 Monolithic Junction Field Effect Transistors
2.8 MOS Field Effect Transistors
2.9 IC Crossovers
2.10 Complete Integrated Circuit Formation

Chapter 3 Feedback Amplifiers


3.1 Classification of Amplifiers
3.1.1 Voltage Amplifiers
3.1.2 Current Amplifiers
3.1.3 Transconductance Amplifiers
3.1.4 Transresistance Amplifiers
3.2 Classification of Feedback
3.3 Feedback Topologies
3.4 Effect of Feedback on Transfer Gain
3.4.1 Transfer Gain for Voltage Series Feedback Topology
3.4.2 Transfer Gain for Voltage Shunt Feedback Topology
3.4.3 Transfer Gain for Current Series Feedback Topology
3.4.4 Transfer Gain for Current Shunt Feedback Topology
3.5 Effect of Feedback on Input Resistance
3.5.1 Input Resistance for Voltage Series Feedback Topology
3.5.2 Input Resistance for Voltage Shunt Feedback Topology
3.5.3 Input Resistance for Current Series Feedback Topology
3.5.4 Input Resistance for Current Shunt Feedback Topology
3.6 Effect of Feedback on Output Resistance
3.7 Practical Feedback Circuits

Chapter 4 Operational Ampliers


4.1 The Basic Operational Amplifier
4.2 The Inverting Amplifier
4.2.1 Practical Inverting Amplifier
4.3 The Non-Inverting Amplifier
4.3.1 Input Resistance of Voltage Series Feedback Amplifier
4.3.2 Output Resistance of Voltage Series Feedback Amplifier
4.3.3 Frequency Response of Voltage Series Feedback Amplifier
4.3.4 Stability in Voltage Series Feedback Amplifier
4.3.5 Distortion in Voltage Series Feedback Amplifier
4.4 Difference Amplifier
4.5 Common Mode Rejection Ratio
4.6 Emitter Coupled Differential Amplifier
4.6.1 Emitter Coupled Differential Amplifier Using Constant Current Bias
4.6.2 Use of Current Mirror as Constant Current Source
4.7 IC 741 Operational Amplifier

Chapter 5 Applications of Operational Amplifier


5.1 Error Voltages and currents in Operational Amplifiers
5.1.1 Input Bias Current
5.1.2 Input Offset Current
5.1.3 Input Offset Voltage
5.1.4 Thermal Drift
5.2 Applications of Operational Amplifiers
5.2.1 Sign Changer
5.2.2 Phase Shifter
5.3 Summing Amplifier
5.3.1 Non-inverting Summing Amplifier
5.4 Current –to –Voltage Converter
5.5 Voltage –to – Current Converter
5.6 D.C. Voltage Follower
5.7 A.C. Coupled Amplifier
5.7.1 A.C. Voltage Follower
5.8 Bridge Amplifier
5.9 Integrator
5.9.1 Practical Integrator
5.10 Differentiator
5.11 Logarithmic Amplifier
5.12 Antilogarithmic Amplifier
5.13 Logarithmic Multiplier

Chapter 6 Regulated Power Supply


6.1 Voltage Regulator
6.1.1 Percentage Regulation
6.1.2 Classification of Voltage Regulators
6.2 Series Voltage Regulator
6.2.1 Simple Series Regulator Circuit
6.2.2 Improved Series Regulator Circuit
6.2.3 Feedback Type of Voltage Regulator
6.3 Shunt Voltage Regulator
6.3.1 Zener Diode Shunt Regulator
6.3.2 Basic transistor Shunt Regulator
6.3.3 Improved Shunt Regulator
6.4 Regulators Using Operational Amplifiers
6.4.1 Series Voltage Regulator Using operational Amplifier
6.4.2 Modified Zener Biasing
6.4.3 Short Circuit Protection
6.5 Shunt Voltage Regulator Using OP-AMP
6.6 Adjustable Voltage regulator ICs
6.6.1 IC 723 Voltage Regulator
6.6.2 Three Terminal Adjustable Voltage Regulator ICs
6.6.3 Three Terminal Fixed Voltage Regulator ICs
6.7 Switch Mode Power Supply (SMPS)

Chapter 7 Sinusoidal Oscillators


7.1 Principle of Operation
7.2 Negative Resistance
7.3 Classification of Oscillators
7.4 R C Phase Shift Oscillator
7.4.1 Transistor Phase Shift Oscillator
7.4.2 Operational Amplifier Phase Shift Oscillator
7.5 The Wien Bridge Oscillator
7.6 L-C Oscillator
7.7 Tuned Drain FET Oscillator
7.7 Tuned Collector Oscillator
7.8 General Form of Resonant Circuit Oscillators
7.9 Transistor Hartley Oscillator
7.10 Transistor Colpitt’s Oscillator
7.11 Crystal Oscillator

Chapter 8 Multivibrators
8.1 Bistable Multivibrator
8.2 Triggering Methods of Bistable Multivibrator
8.2.1 Asymmetrical Triggering
8.2.2 Symmetrical Triggering
8.3 Monostable Multivibrator
8.3.1 Collector Coupled Monostable Multivibrator
8.3.2 Emitter Coupled Monostable Multivibrator
8.4 Astable Multivibrator
8.5 Comparator
8.6 Schmitt Trigger
8.7 Astable Multivibrator using an Operational Amplifier
8.8 Monostable Multivibrator using an Operational Amplifier
8.9 Triangular Waveform Generator
8.10 Timer IC 555
8.10.1 Monostable Operation
8.10.2 Astable Operation
8.10.3 Saw tooth Generator
8.10.4 Voltage Controlled Oscillator

Chapter 9 Active Filters


9.1 Active Filters
9.2 First Order Low Pass Filter
9.3 Second Order Low Pass Filter
9.4 First Order High Pass Filter
9.5 Second Order High Pass Filter
9.6 Higher Order Filters
9.7 Band Pass Filters
9.7.1 Wide Band Pass Filter
9.7.2 Narrow Band Pass Filter
9.8 Band Rejection Filters
9.8.1 Wide Band Rejection Filter
9.8.2 Narrow Band Rejection Filter

Chapter10 Bridge Circuits


10.1 Wheatstone Bridge
10.1.1 Thevenin’s Equivalent Wheatstone Bridge
10.1.2 Slightly Unbalance Wheatstone Bridge
10.1.3 Sources of Errors in Wheatstone Bridge
10.2 Kelvin Bridge
10.2.1 Practical Kelvin Double Bridge
10.3 A C Bridges
10.4 Maxwell Bridge
10.5 Hay Bridge
10.6 Schering Bridge
10.7 Wien Bridge
10.8 Wagner Ground Connection

Chapter11Switching Devices and Circuits


11.1 Unijunction Transistor
11.2 Unijunction Transistor Relaxation Oscillator
11.3 Silicon Controlled Rectifier
11.4 Half Wave Series Static Switch
11.5 Phase Control Circuit
11.6 SCR Half Wave Rectifier
11.7 SCR Full Wave Rectifier
11.8 Silicon Controlled switch
11.8 The Triac
11.10 The Diac
11.11 Dimmer Circuit
1
Transducers
The electronic instruments are generally used for the precise measurement of the
physical quantities. These instruments should be quite accurate and rugged. For the
design of such instruments it is essential to know which physical quantity is to be
measured and how the measuring quantity is converted to the electrical quantity. The
electrical quantity is processed by different processing device and final readout of the
quantity is taken by the output device. In every measuring electronic instrument an input
device is used which converts the physical quantity to electrical quantity. Such a device is
known as transducer. So transducer is very essential and important part of the instrument;
and the accuracy and sensitivity of the measuring quantity will depend on the accuracy
and the type of transducers used. In this chapter we shall discuss various types of
transducers with their applications and principle of converting measuring quantity from
one form to another.
1.1 CLASSIFICATION OF TRANSDUCERS
As discussed above, the input quantity to be measured for the instrumentation
system is non-electrical. So in the instrumentation system the non-electrical quantity is
converted to electrical quantity. The device that converts the non-electrical quantity to
electrical one is known as transducer. Broadly speaking transducer is a device which
converts energy from one form to another. In electronic instrumentation system mostly
electrical transducers are used, so we shall discuss in this chapter only the electrical
transducers and their classifications. Transducers may be classified in several ways
depending on their applications, method of energy conversation, and nature of the output
signal and so on. However, according to electrical principle involved, the transducers are
classified into following two categories:
1. Passive Transducers
2. Active or Self-generating Transducers
Passive Transducers
In passive transducers external power is supplied so passive transducers
are also known as the externally powered transducers. Electrical resistance, inductance
and capacitance are the three parameters mainly used for passive transducers. The
physical quantity to be measured is made to vary any of these three parameters. When the
electrical supply is applied then there is change in the resistance, inductance or
capacitance due to the variation in the physical quantity to be measured, which in turn
provide a change in voltage, current or frequency. Such transducers are listed below:
• Resistance Strain Gauge
Resistance of a wire changes when elongated or compressed by externally
applied stress. It is used for the measurement of stress and strain.
• Potentiometric Device
Position of the slide contact varies by an external force causing the change
in resistance. It is used for the measurement of pressure and displacement.
• Resistance Thermometer
Resistance of pure metal wire varies with temperature. It is used for the
measurement of temperature and radiant heat.
• Photo Conductive Cell
Resistance of the cell varies with the incident of light. It is used in
photosensitive relay.
• Capacitance Transducers
Variation in capacitance is produced by variation of the distance between
plates by an externally applied force. It is used for the measurement of
displacement.
• Capacitor Microphone
Sound pressure varies the capacitance between a fixed plate and a
movable diaphragm. It is used in speech music and noise.
• Magnetic Circuit Transducers
Self inductance or mutual inductance of a coil excited by an a.c. signal is
varied by changes in the magnetic circuits. It is used for the measurement
of pressure and displacement.
• Differential Transformers
Differential voltage of two secondary windings of a transformer is varied
by varying the position of the magnetic core by an externally applied
force. It is used in force, pressure and displacement.
• Reluctance Pickup
The reluctance of the magnetic circuit is varied by changing the position
of the iron core of a coil. It is used pressure and displacement.
Active or Self-generating Transducers
In this category of transducers an analog voltage or current is produced when
simulated by some physical form of energy. No external power is required in this class of
transducers but these are just based on the principle of energy conversion. Such
transducers are listed below:
• Thermocouple
In thermocouple transducers an e.m.f. is generated across dissimilar metals
when junction is heated. The thermocouples are the important active
transducers used for the measurement of temperature.
• Photovoltaic cell
A voltage is generated in a semiconductor junction when light radiations
fall over the junction.
• Piezoelectric pickup
An e.m.f. is generated when the external pressure is applied to certain
crystalline materials such as quartz.
1.2 SELECTION CRITERIA FOR TRANSDUCER
As discussed above the accuracy of a measurement system depends on the
transducer being used. Thus selection of the appropriate transducer is an important point
in getting the accurate results. Selection of a transducer depends on the physical quantity

1
to be measured, the principle of the transducers to be used and the accuracy required. The
following factors must be considered while selecting a transducer for the measurement of
a physical quantity:
1. Operating Principle: Generally, the transducers are selected on the
operating principle used by them. They must be resistive, inductive,
capacitive etc.
2. Sensitivity: The transducer must be sensitive enough so that sufficient
amount of the output is available.
3. Operating Range: The transducers have good resolution of the entire
range of the physical quantity being measured. The rating of the
transducers should be sufficient so that it is not damaged while working in
its specified operating range.
4. Environmental Compatibility: The transducers should be able to work
under its given range of temperature. Further the transducers should be
able to withstand pressure shocks and vibrations etc.
5. Usage and Ruggedness: While selecting a transducer, the ruggedness
both of mechanical and electrical intensities of transducer versus its size
and weight must be considered.
6. Insensitive to Unwanted Signals: The transducers should be insensitive
to the unwanted signals and should, however, be highly sensitive to the
desired signals.
1.3 RESISTANCE STRAIN GAUGE
If a metal conductor is stretched or compressed, its resistance changes due to the
change in length and diameter of the conductor. There is also a change in the value of the
resistivity of the conductor when subjected to strain; this property is called the piezo-
resistive effect. The property of the material indicates a dependence of the resistivity on
the mechanical strain. It is used measurement of strain hence known as strain gauge. The
resistance of a wire or conductor, when no stress is applied, is given by:
ρxL
R= … (1.1)
A
where ρ is the specific resistance of the material in Ω− m ,
L is the length of the wire or the conductor in m,
A is the cross sectional area of the conductor in m2 .
If D is the diameter of the conductor, then the area of cross-section A is given by:
π D2
A = πr2 = … (1.2)
4
where r is the radius of the conductor which is the half of the diameter D.
From equations (1.1) and (1.2) we get the resistance of the conductor as:
4 ρL
R= … (1.3)
π D2
Now when the stress is applied it will be subjected to the strain due to which there
will be a change in diameter D and in the length L. Let the length of the conductor
increases by ∆ L and the diameter decreases by ∆ D . The resistance of the conductor will
increase and becomes equal to R S which is given by:

2
4 ρ (L + ∆L )
R =
π (D − ∆D )
S 2

 ∆L 
4 ρL  1 + 
=  L  … (1.4)
2
 ∆D 
πD 2  1 − 
 D 
Since ∆D is very small quantity, so equation (1.4) can be rewritten as:
D
 ∆L 
4 ρL  1 + 
RS =  L  … (1.5)
 2 ∆D 
πD 2  1 − 
 D 
Now the Poisson’s ratio µ is defined as the ratio of strain in the lateral direction
to the stain in the axial direction.
So ∆D/D
µ =
∆L/L
∆D ∆L
or = µ … (1.6)
D L
From equations (1.5) and (1.6), we have:
 ∆L 
4 ρL  1 + 
R =  L 
S
 ∆L 
π D 2 1 − 2 µ 
 L 
 ∆L   ∆L 
4 ρL  1 +  1 + 2 µ 
R S =  L  L 
 ∆L   ∆L 
π D 2 1 − 2 µ 1 + 2 µ 
 L  L 
 ∆L ∆L  ∆L  
2

4 ρL  1 + 2 µ + + 2µ  
 L L  L   … (1.7)
R S = 
  ∆L  
2

π D 2 1 − 4 µ 2  
  L  

2
In this equation 
∆L 
 is a very small quantity, so it may be neglected in
 L 
equation (1.7), which is rewritten as:
4 ρL  ∆L 
RS =  1 + (1 + 2 µ)  … (1.8)
π D2  L 
From equations (1.3) and (1.8), we get:
 ∆L 
R S = R  1 + (1 + 2 µ)  … (1.9)
 L 
The increased resistance R S may also be given by:
R S = R + ∆R … (1.10)
where ∆R is amount of resistance increased in the original resistance R of the
conductor due to the application of stress.

3
Equating the equations (1.9) and (1.10), we get the amount of resistance increased
∆L
as: ∆R = R( 1 + 2 µ)
L
or ∆R/R … (1.11)
= (1 + 2 µ)
∆L/L
The quantity ∆R/R is called the gauge factor (represented by K) of the strain
∆L/L
gauge, which is defined as the ratio of the change in resistance ∆R/R to the change in
length ∆L/L .
∆R/R
i.e. K =
∆L/L
∆L/L is also known as the strain ( σ ), as it the ratio of the change in length to the
original length of the conductor.
σ = ∆L/L
∆R/R
So K = … (1.12)
σ
The relation between the gauge factor K and the Poisson’s ratio can be given from
equations (1.11) and (1.12) as:
K = (1 + 2 µ) … (1.13)
The gauge factor is constant for the particular material of the wire or the
conductor and it is different for different materials. In general the gauge factor varies
from 0.5 to 6. The sensitivity of the strain gauge is described in terms of the gauge factor;
as larger the value of gauge factor, larger will be change in resistance. So it is desirable to
have the larger value of gauge factor of the strain gauge.
The effect of applied stress on the resistance change of the strain gauge can also
be calculated as per Hook’s law. The Hook’s law is expressed as:
S
σ=
E
where S is the stress, which is defined as the force applied per unit area (Kg/m2),
and E is the Young’s Modulus (Kg/m2).
1.4 TYPES OF STRAIN GAUGES
There are two different types of strain gauges namely:
(i) Unbonded Gauges
(ii) Bonded Gauges
Unbonded Gauges
In the unbonded strain gauge the resistance wire is stretched between a stationary
frame and armature that is supported in the center of the frame as shown in figure (1.1).
The diameter of the resistance wire is about 25 µm. The armature can move only in one
direction. Since the resistance wire would buckle under compressive forces, an internal
preload greater than any expected external compressive load is employed. Now the
applied motion to the right increases the tension in wires 1 and 3 and reduces the tension
in wires 2 and 4. A motion applied to the left side does just the reverse, and so motion in
both directions can be measured so long as the preload is not overcome. The four
resistance wires are generally connected in four arms of a bridge respectively as shown in
figure 1.2. With no external load applied i.e. only preload present, the bridge is balanced

4
R1 R2
as = .
R4 R3
When the external load is applied, the resistance of the strain gauge changes, the
bridge will be unbalance. It will give rise an output voltage which is proportional to the
strain.

Fig. 1.1

Fig. 1.2
Bonded Gauges
The strain gauge used for the measurement of strains is usually the bonded type.
Bonded type strain gauges use the elements of wire in a flat grid or helical grid and are
called wire wound strain gauges. Such gauges are shown in figure 1.3. The other types of
bonded strain gauges are thin metal foil printed and etched to form a grid type material as
shown in figure 1.4. Such gauges are called Foil type stain gauge. The foil type gauges
have much greater heat dissipation capacity as compared with wire wound gauge on
account of their greater surface area for the same volume. Because of this reason this type
of strain gauge are used for the higher operating temperature. The bonded gauges are
available in sizes from 15 cm to about 0.4 mm length. Gauges are cemented to a thin
paper sheet or resin base. The size and shape of the gauges vary with their applications.

5
Fig. 1.3

Fig. 1.4
The shape of the sensing element is selected according to the strain to be
measured: they may be uniaxial, biaxial or multiaxial. Uniaxial gauges often have long,
narrow sensing elements (shown in figure 1.5) to maximize the strain sensing material in
the direction of

(a) (b) Fig. 1.5

6
interest. Gauge length is selected according to the strain field to be investigated. For most
strain measurements, the 6 mm gauge length gives good performance.
Measurement of strains in two or more directions can be accomplished by placing
single element gauges at the proper locations. But this can however, be simplified and the
accuracy can be increased by using multi-element, rosette gauges. Two-element rosette
(foil type) is shown in figure 1.6. This type of gauge is used for the force transducer. For
the stress analysis, the axial and transverse elements are chosen of different resistances so
that the combined output is proportional to stress while the output of the axial element
alone in proportional to the strain. Three element rosettes are used to determine the
direction and magnitude of principal strains resulting from complex loading. A 60o foil
type of three elements can also be designed.

Fig. 1.6
Example 1.1 A strain gauge with a gauge factor 2 is fastened to a beam which is
subjected to a strain of 1x10-6. If the original resistance of the gauge is 120 Ω , calculate
the change in resistance.
Solution. We know that the gauge factor is given by:
∆R/R
K =
σ
Given R = 120Ω σ = 1x10 −6 K = 2
The change in resistance is given by:
∆R = R.K .σ
= 120 x 2 x10 −6
= 240 µ Ω
Example 1.2 A metallic wire has Poisson’s ratio of 0.35. Find the gauge factor.
Solution. We know :
K = (1 + 2 µ)
Given µ = 0.35
The gauge factor K is:
K = 1 + 2 x0.35
= 1.7

7
Example 1.3 In the bridge circuit of figure of 1.7 R2 = R3 = 130Ω and R4 = 130Ω when
unstrained and R4 = 130.5Ω when strained. If the gauge factor is 2, calculate the strain.

Fig. 1.7
Solution. When the bridge is balanced it is given:
R R
RS = R1 = 2 4 = 130Ω when unstrained.
R3
R R
When strained R S + ∆R S = 2 4
R3
= 130.5Ω
∆RS = 130.5 − 130 = 0.5Ω
∆RS 0.5
=
RS 130
The gauge factor K is given by:
∆RS RS
K=
σ
∆RS RS 0.5 130
or Strain σ= =
K 2
= 0.0077
1.5 POTENEOMETRIC TRNSDUCER
Potentiometric transducer contains resistance element with a sliding contact or
movable contact. Its motion may be translational or rotational. The potentiometer is very
common, low cost and simple form of transducer which converts the linear or rotational
displacement into an e.m.f. The potentiometers for linear and rotational movable contact
are shown in figure 1.8. If V is the input voltage across the fixed resistance than the
voltage across the movable point and one point of the fixed resistance will depend on the
sliding position of the potentiometer.

8
(a) Fig. 1.8 (b)

The output voltage is, therefore, given by:


R2
V0 = V …. (1.1)
R1 + R2
where ( R1 + R2 ) is the total resistance of the potentiometer.
Following are the limitations of the potentiometric transducers:
1. the potentiometer output is insensitive to variation in displacement of
movable contact between two consecutive turns of potentiometer.
2. Because of the mechanical friction between the wiper (movable contact) and
the resistance element, its life is limited.
Despite of these limitations it is widely used due to its high electrical efficiency.
Example 1.4 A resistance position (potentiometric) transducer with a resistance of 10
KΩ and a shaft stroke of 10 cm is applied with a voltage of 5V. What is the value of
output voltage when the wiper is 2.5 cm form the reference point?
Solution. The resistance R2 of 2.5 cm displacement is:
2.5
R2 = x10 K Ω
10
= 2.5 K Ω
The output voltage is given by:
R2
V0 = V
R1 + R2
2500
= x5 volts
10000
= 1.25 volts
1.6 RESISTANCE THERMOMETER
The resistance thermometer falls in the category of passive transducers. It utilizes
the property that the resistance of a conductor changes when its temperature is changed.
It has been observed that the resistance of pure metals such platinum, copper or nickel
increases with the increase in temperature. These materials have high temperature

9
coefficient of resistance due to which substantial change in resistance occurs for a
relatively small change in temperature. Such materials are wired and used for the
construction of Resistance Thermometer. The relation between the temperature and the
resistance of the metallic wires is given by:
Rt = R0 (1 + α .∆ t) …. (1.2)
where Rt is the resistance of the metallic wire at t oC temperature,
R0 is the resistance of the metallic wire at 0 oC temperature,
∆ t is the difference in temperature between operating and reference
temperature, and

α is the temperature coefficient of resistance which is defined as the


resistance change per unit resistance per oC. The value of
α = 0.00385 / o C for platinum.
Figure 1.9 shows the Resistance-temperature detector or Resistance Thermometer
consisting of a platinum or nickel or copper wire wrapped around the mica insulator. The
wrapped wire is enclosed in a quartz tube.

Fig. 1.9

For the measurement of temperature the resistance thermometer is connected to


one arm of Wheatstone bridge as shown in figure 1.10. Under ordinary condition the
bridge is balanced showing zero deflection in the galvanometer, now due to the change of
temperature, the resistance of the copper wire of the resistance thermometer changes,
consequently the bridge is unbalanced and current flows through the galvanometer, the
change in the galvanometer is the measure of the change in resistance, which is
proportional to the magnitude of temperature change. The galvanometer may then be
calibrated in terms of temperature.

10
Fig. 1.10
1.7 THERMISTOR
For the precise measurement of temperature, thermistors are most commonly used
particularly at lower temperature. It is suited in the range of – 100 to +350 oC.
Thermistors are semiconductor devices that behave as resistance with a negative
temperature coefficient of resistance. Thermistors are made up of manganese, nickel and
cobalt oxides which are milled, mixed in proper proportions with binders, pressed into
the desired and sintered at high temperature. These are commercially available in the
form of beads, probes, discs and rods as shown in figure 1.11.

Fig. 1.11
Beads are small in size with 0.15 mm in diameter and are either glass coated or
sealed in the tubes of solid glass probes. Because of very small size of beads, very
localized temperature measurement and fast response (in ms) is possible. These probes
are used for measuring the temperature of the liquid.
Other semiconductor thermistors are carbon resistors, and silicon and germanium
crystal elements. Carbon resistors (0.1 to 1 W rating) with room temperature resistance of
2 Ω to 150 Ω are used for the measurement of cryogenic temperatures in the range from 1
o
K to 20 oK. As the temperature decrease from 20 oK, the resistors exhibit a large increase
in resistance. Silicon with different amounts of impurities (boron) can be designed to
have either a positive or negative temperature coefficient over a particular temperature
range. Germanium (doped with gallium, arsenic or antimony) is used for cryogenic
temperature over a range from about 0.5 oK to 100 oK. It exhibits a large decrease in
resistance with increasing temperature.
1.8 THEMOCOUPLES
The thermocouples work on the principle of Seeback effect. According to this
effect when two dissimilar metallic wires are joined together, the temperature difference
between the junctions produces a voltage between the two wires. The magnitude of this

11
voltage depends on the material used for the wires and the temperature difference
between the two junctions. The voltage is known thermo e.m.f. and this device is called
as the thermocouple. The practical thermocouple is shown in figure 1.12 which consists

Fig. 1.12

of two dissimilar wires joined at one end A and the other ends B & C are connected to the
to the voltage measuring device. The end A is known as sensing junction which is placed
in or on the unit under test. The other ends B & C are known as the reference end because
it kept at a constant temperature (reference temperature).
When the junction A is heated or kept on the unit under test, thermo e.m.f.(in mV)
is produced between it and the reference junction. The magnitude of this voltage is
proportional to the temperature difference between the sensing junction and the reference
junction. Since the reference junction is at the room temperature or the constant
temperature, so the voltage is basically proportional to the temperature of the sensing
junction. This voltage is then calibrated in terms of the temperature of the sensing
junction.
The thermocouples are made of different material wires depending upon the
desired temperature range. The various thermocouples with the values of e.m.f. produced
per 100 oC temperature difference between the two junctions are given below:
1. Iron – constantan 5.5 mV
2. Cromel – alumel 4.0 mV
3. Cromel – Constantan 7.5 mV
4. Nickel – nickel iron 2.0 mV

To increase the sensitivity of the device several thermocouples may be connected


in series with all measuring junctions at one temperature and all reference junctions at
another temperature as shown in figure 1.13. Such an arrangement is called thermopile.
The output voltage will increase n times if n thermocouples are connected in series.

Fig. 1.13
1.9 PHOTOELECTRIC TRANSDUCERS
In photoelectric transducers electric conduction (or flow of electrons) takes place
by the incidence of light energy. There are four types of photo electric devices namely
Photo emissive, Photo-conductive, photo-voltaic and photo junction devices.

12
In photo- emissive devices, when the light energy falls on a cathode of low work
function, the electrons are emitted from the cathode surface. The emitted electrons are
attracted by a positive anode. The cathode and anode are enclosed in a glass enclosure.
The enclosure may be a vacuum or gas filled. So they are vacuum type photo tube or gas
filled type photo tube. The high amplifying devices are the photo multiplier tubes. In the
next sub-section we shall discuss the photo multiplier tubes.
In photo-conductive devices, the resistance of a material is changed when it is
illuminated. Such devices are also called photo resistors or light dependent resistors.
The photo-voltaic or solar cells generate an output voltage proportional upon the
incident of light.
Photo-junctions employ a P-N, P-N-P or N-P-N structure. The P-N junctions also
called the photo diodes are operated in reverse bias and the charges in them are released
by light energy. P-N-P or N-P-N structure also known as photo transistors operate by
exposing the base to the light.
1.9.1 Vacuum Photo tube
Figure 1.14(a) shows the internal construction of a vacuum phototube which
consists of a cathode (made up of cesium antimony surface) and a small wire anode. The
cathode is a large semicircle which is surrounding the cathode. Both these electrodes are
enclosed in an evacuated glass enclosure. The symbolic representation of photo tube is
shown in figure 1.14(b).

(a) (b)
Fig. 1.14
Now when a positive potential is applied at the anode with respect to the cathode,

Fig. 1.15

13
the anode current will flow if the light is incident on the surface of the cathode. The
anode current is directly proportional to the amount of light falling on the cathode. Fir the
fixed amount of light incident on the cathode, graph between the anode current and anode
voltage may be plotted by using the arrangement shown in figure 1.15.
The anode characteristic curve for a typical photo tube is shown in figure 1.16.

Fig. 1.16
The graph between the current and light flux falling on the cathode may also be
plotted and gives the linear relation over wide range as shown in figure 1.17.

Fig. 1.17

1.9.2 Gas Filled Phototubes


In gas filled phototubes, as the name indicates a small amount of inert gas
(usually argon) in introduced in the photo tube discussed above. At certain anode voltage,
the gas also becomes ionized due to which the anode current is increased.
1.9.3 Photomultiplier Tubes
The photo tubes emits very small amount of photoelectric current when light
incident on the cathode of the tube. The photomultiplier tube however utilizes the
principle of secondary emission to provide current amplification. The photomultiplier
tube consists of an evacuated glass enclosure containing a photo cathode, an anode and
several electrodes which are kept at successively higher voltages. The electrodes are
known as Dynodes. Figure 1.18 illustrates the principle of the photo multiplier tube. The
electrons are emitted from the cathode when the light falls on the cathode which is

14
attracted by the first dynode. The secondary electrons are librated when the electrons
incident on the first dynode. In this way 5 to 10 secondary electrons are emitted for every
primary electron striking the dynode. The process of secondary emission is repeated for
every dynode. The secondary electrons are finally attracted by the anode.

Fig. 1.18
The gain of the photomultiplier depends on the number of dynodes and the
properties of the dynode material. If 100 V per stage is applied to each dynode of a
typical ten-dynode photomultiplier tube, then the current amplification will be of the
order of 106. Magnetic fields affect the gain of the tube because some electrons may be
deflected from their path between stages and therefore never reach the dynode or the
anode. The µ-metal magnetic shields are often placed around the photomultiplier tube to
minimize the effect of magnetic field.

1.9.4 Photo Conductive Cell

Photo-conductive devices also called Photo cell, photo resistors or light dependent
resistors, have a photoconductive material whose resistance changes when it is
illuminated. Many materials are photoconductive to some extent but commercially
important are cadmium sulfide, germanium and silicon. The cadmium sulfide is most
commonly used for this purpose.
The typical photoconductive cell with top view and side view is shown in figure
1.19. In photoconductive cell the photoconductive material such as cadmium sulfide is
deposited in the Zig Zag pattern on the ceramic substrate. Electrodes of tin or indium are
provided to connect to the circuit. The assembly is enclosed in a metal case with a glass
window over the photo conductive material. When the light energy falls on the
photoconductive material the electrons jump across the forbidden gap of the
semiconductor to the conduction band and thus its conductivity increases.

15
Fig. 1.19
The photo cells (photo resistor) can generally be used to control the relay circuit.
Figure 1.20 shows the use of photo cell in relay control circuit. When the photo cell is

Fig. 1.20

exposed to light energy the resistance of the cell decreases; resulting thereby the flow of
large amount of current through the relay circuit. The relay becomes energized and the
normally open pins of the relay become shorted. On the contrary when light is interrupted
to fall on the cell, a very small amount of current flows through the coil of the relay
which becomes de-energized.

1.9.5 Photo Voltaic Cell


Photo voltaic cell is a device that develops an e.m.f. depending on the incident
light. The photo voltaic cell also called the solar cell consists of a thin layer of P – type
silicon crystal into which a very thin layer of N – type material is diffused (fig. 1.21). The
efficiency of conversion depends on the spectral and the intensity of illumination. The

Fig. 1.21

16
positive terminal of the cell is taken at the back of P – type silicon and the negative
terminal is taken by a grid of metallic lines. The construction of the cell is shown in
figure 1.21. A spectral sensitivity characteristic is shown in figure 1.22.

Fig. 1.22
When the light flux incidence on the solar cell the electrons receive enough
energy to cross the forbidden energy gap of the semiconductor and reach the conduction
band and thus current flows. The current continues till the illumination of light is there.
The current delivered by the solar cell to external circuit is very small. However this can
be increased by connecting the solar cell in parallel. The solar cell can also be connected
in series to increase the voltage.
1.9.6 Photo Junctions
Photo junctions are available in the form of diodes and transistors known photo
diodes and photo transistors. The P – N junctions or photodiodes operate in reverse bias
and if the light energy falls on the junction then the leakage current flows whose
magnitude varies in proportion with the intensity of the light. The photo diodes are
generally sealed in a metal can with a les and window fitted for the exposure of light to
the junction. The dark current (when the photo diode is not exposed to any light) of a
typical photo diode is nearly 10 µA which is equal to the inherent leakage current of the
normal P – N junction diode. The symbolic representation of the photo diode is shown in
figure 1.23. The photo diodes can be used in similar manner as the photo conductive cell.

Fig. 1.23
The sensitivity of the photo diode can be increased to a greater extent if one more
junction is added to it. It results the formation of photo transistors. The construction
details and symbolic representation of a typical NPN photo transistor is shown in figure
1.24. The photo transistor is junction transistor with the emitter junction exposed to light.
It can be seen from the symbol of photo transistor that its base is floating. The base
current is controlled by the light flux in developing charges in the emitter base circuit.

17
Fig. 1.24
One application of photo transistor is illustrated in figure 1.25. The light incident

Fig. 1.25
on the photo transistor causes the increase in current in resistance R. The voltage drop
across it increases which drives the relay.

1.10 CAPACITIVE TRANSDUCERS


In capacitive transducers the change in pressure is detected by the variations in the
capacitance of a parallel plate capacitor whose one end is free to move with change in
pressure. The capacitance of a parallel plate capacitor is given by:
kA ε o
C= farad …. (1.3)
d
where A is the area of each plate in m2,
d is the spacing between the plates in m,
ε o is the absolute permittivity in the free space,
k is the dielectric constant.

Figure 1.26 shows the working of the capacitive transducer. Since the capacitance
1
of the capacitor is inversely proportional to the plate separation ( C ∝ ), so any
d
variation in d causes a corresponding change in the capacitance. It is clear from figure
1.26 that when a pressure is applied to a diaphragm, which acts as one plate of the
capacitor, changes the distance between the diaphragm and the static plate. So when the

18
pressure increased the spacing d decreases resulting thereby the decrease in the capacity
of the capacitor. Similarly, the decrease in pressure results the increase the capacity of the
capacitor. The change in the capacity gives the pressure on the diaphragm. The resultant
change in capacitance could be measured with an a.c. bridge, but it is usually measured
with an oscillator circuit. The frequency of the oscillator circuit gets changed with the
change in pressure on the diaphragm. So the change in frequency is the measure of the
magnitude of the applied pressure.

Fig. 1.26
1.11 INDUCTIVE TRANSDUCERS
In inductive transducers self inductance or mutual inductance of a coil excited by
an a.c. signal is varied by changes in the magnetic circuits. These are mainly used for the
displacement. The displacement to be measured is arranged in such a way so that there is
a variation in self inductance or mutual inductance.
The self inductance of a coil is given by:
N2
L= Henery …. (1.4)
R
where N is the number of turns
and R is the reluctance of the magnetic circuit.
The reluctance of the magnetic circuit is given by:
l
R= … (1.5)
µA
where l is the length of the magnetic circuit
A is area of cross section of the magnetic circuit
µ is effective permeability of medium in and around of the coil.
From the equations (1.4) and (1.5), the self inductance of a coil may be given by:

N 2µ A
L= … (1.6)
Rl
From this equation it is clear that the variation in self inductance is possible if any
of the following variables is varied.
1. Number of turns of the coil
2. Geometric configuration
3. Permeability of the magnetic material or magnetic circuits

19
Let us now consider the case of a general inductive transducer, the inductive
transducer has N number of turns and a reluctance R. When a current i is passed through
it, the flux is given by:
Ni
φ= … (1.7)
R
Differentiating this equation with respect to time, we get:

dφ N dl Ni dR
= x − 2x … (1.8)
dt R dt R dt
The first term of the right hand side of this equation predominates over the other
term. Since the current varies very rapidly, perhaps a million times per second, so the first
term on the right hand side of equation (1.8) becomes very large. We may, therefore,
neglect the second term and the relationship reduces to:
dφ N dl
= x … (1.9)
dt R dt
The e.m.f. induced in the coil is given by:

E=N … (1.10)
dt
N 2 di
Therefore E= … (1.11)
R dt
The self inductance is given by:
E N2
L= = … (1.12)
di dt R
The output from an inductive transducer can be had either in the form of change
in voltage or change in inductance.
1.11.1 Change in Self Inductance with Number of Turns
In this case the output may be caused by change in number of turns. Figures
1.27(a) and (b) show the inductive transducers used for measurement of linear and
angular displacements respectively. Figure 1.27(a) shows an air cored transducer for
measurement of linear displacement, where as figure 1.27(b) shows an iron transducer
used for measurement of angular displacement. In both the cases as the number of turns
are changed the self inductance and hence the output also changes.

(a) (b)
Fig. 1.27

20
1.11.2 Change in Self Inductance with Change in Permeability
An inductive transducer which works on the principle of change in permeability
lead to the change in self inductance is shown in figure 1. 28. The iron core is surrounded
by a winding. If the iron core is inside the winding its inductance is high due to the
increase in permeability, but when the iron is moved out of the winding, permeability of
the flux path decreases resulting in reduction of self inductance of the coil. This
transducer can be used for the measurement of displacement.

Fig. 1. 28

1.11.3 Variable Reluctance Type Transducers


Variable reluctance type transducer is shown in figure 1.29 which consists of a
coil wound on a ferromagnetic core. The displacement to be measured is applied to a
ferromagnetic target. The target does not make a physical contact with the core on which
the coil is mounted. The core and the target are separated by an air gap.

Fig. 1.29

The inductance of the coil depends upon the reluctance of the magnetic circuits.
The self inductance of the coil is given by:

21
N2
L= … (1.13)
Ri + R g
where N is the number of turns of the coil
Ri is the reluctance of the iron parts
Rg is the reluctance of the air gap
The reluctance of the iron part is negligible as compared to that of the air gap. So
the self inductance may be approximated as:
N2
L≈ … (1.14)
Rg
The reluctance of the air part of magnetic circuit is given by:
lg
Rg = … (1.15)
µ o Ag
where l g is the length of the air gap
Ag is the area of the flux path through air
µ o is the permeability
As µ o and Ag are constant, R g is proportional to the length of the air gap l g .
Therefore inductance L is inversely proportional to the length of the air gap l g
1
i.e. L∝
lg
When the target is near to the core, the length of the air gap is small and so the
self inductance of the coil is large, if on the other hand the target is away from the core,
the length of the air gap is large and hence inductance larger resulting the smaller value
of self inductance. Therefore, it is concluded that the inductance of the coil is a function
of the distance of the target from the core i.e. length of the air gap. Since it is the
displacement which is changing the length of the air gap, the self inductance is a function
of the displacement. So the self inductance of the coil is a non-linear function of the
displacement. The self inductance of the coil can be measured with the help of a.c.
bridge.

1.11.4 Linear Variable Differential Transducer (LVDT)


The linear variable differential transducer (LVDT) is displacement transducer
base on variable inductance which is a function of displacement and is realized by
variation in mutual inductance. It consists of three coils one primary coil and two
secondary coils S1 and S2. The primary coil is kept at the centre and one secondary coil S1
is placed at the left of the primary coil and the other secondary coil S2 at the right of the
primary coil. All coils are linearly arranged on a cylindrical coil former with the magnetic
core, which is free to move inside the coils.
The magnetic core is normally made of soft material like iron and its alloys with
nickel, cobalt, but now a days ferrite are also used as core material to achieve higher
sensitivity.

22
Fig. 1.30
Figure 1.30 shows the basic construction of LVDT. The primary coil is energized
with an alternating voltage of amplitude between 5 to 30 V and frequency between 50 Hz
to 20 KHz. The two secondary coils are exactly identical in design with same number of
turns. The voltage induced in the two secondary coils S1 and S2 are equal for the centrally
placed core.
When both secondary coils are connected in a normal positions, they gives two
separate voltages across it i.e. secondary coil S1 gives the output voltage Es1 and
secondary coil S2 gives the output voltage Es2, the connection of such type is shown in
figure 1.31(a). In order to convert the output from S1 to S2 into a single voltage signal, the
two secondary coils S1 and S2 are connected in series opposition, as shown in figure
1.31(b). Hence the output voltage of the transducer is the difference of the two voltages.
Therefore the differential output voltage may be given by:

23
(a) (b) Fig. 1.31
When the core is at its normal position, the flux linking with both secondary
windings is equal and hence equal e.m.fs. are induced in them. Therefore, at null position
Es1=Es2. Since the output voltage of the transducer is the difference of the two voltages,

Fig. 1.32
the output voltage Eo is zero at null position. This point is called as null point, but in
actual there is some residual voltage due to harmonics in excitation voltage and stray
capacitance between the primary and secondaries as illustrated in figure 1.32. Now if the
core is moved to the left of the null position, more flux links with winding S1 and less
with winding S2. Accordingly output voltage Es1, of the secondary winding S1, is more
than Es2, the output voltage of the secondary winding S2. Similarly, if the core is moved
to the right of the null position, the flux with winding S2 becomes larger than that linking
with winding S1. This results Es2 becoming larger than Es1. The output voltage in this
case is Eo=Es2-Es1 and is in phase with Es2 i.e. the output voltage of secondary winding
S2.

24
From the above discussion it is clear that the amount of voltage change in either
secondary winding is proportional to the amount of movement of the core; hence, there is
an indication of amount of linear motion. By noting which output voltage is increasing or
decreasing, one can determine the direction of motion. In other words any physical
displacement of the core causes the voltage of one secondary winding to increase while
simultaneously reducing the voltage in other secondary winding. The difference of the
two voltages appears across the output terminals of the transducer and gives a measure of
the physical position of the core and hence the displacement.
As the core is moved in one direction from the null position, the differential
voltage i.e. the difference of the two secondary voltages will increase while maintaining
in phase relationship with the voltage from the input source. In the other direction from
the null position, the differential voltage will also increase, but will be 180o out of phase
with the voltage from the source (figure 1.33). By comparing the magnitude and phase of
the differential output with that of the source, the amount and direction of the movement
of the core ad hence of displacement may be determined.

Fig. 1.33
The output voltage of LVDT is a linear function of core displacement within a
limited range of motion, say, about 5mm from the null position. Figure 1.32 shows the
variation of output voltage against displacement for various positions of core. The curve
is practically linear for small displacement (upto 5mm). Beyond this range of
displacement, the curve starts to deviate from a straight line. Generally, LVDTs are used
where the displacement is available from mm to few cm.
Advantages of LVDTs
1. High range of displacement measurement can be possible.
2. As compared to other displacement transducers this is very sage, there is no
friction and having the electrically isolated.
3. It is highly immune from the external atmospheric effects.
4. It gives high output and therefore there is generally no need for intermediate
amplification devices.
5. It is having low power consumption.
6. There are no sliding contacts and hence there is less friction and less noise.
7. LVDT shows a low hysteresis and hence repeatability is excellent under all
conditions.

25
Disadvantages of LVDTs
1. These are sensitive to stray magnetic fields.
2. Some times the performance will be affected by vibrations.
3. The temperature also affects the output.
1.12 PIEZOELECTRIC TRANSDUCER
The piezoelectric transducers works on the principle of piezoelectric effect i.e.
when pressure is applied to certain crystals (e.g. Quartz, Rochelle Salt and Ceramics etc),
an e.m.f. is produced across the opposite faces and vice-versa. The piezoelectric
transducers are the self generating type transducers. Figure 1.34 shows the piezoelectric
transducer. The crystal C is placed between a solid base and the force summing
membrane F which is used to convert the applied force into displacement. When the
pressure is applied from the top surface of the crystal, a potential difference is developed
across its opposite faces. The e.m.f. Vo developed across the crystal is directly
proportional to the magnitude of pressure. However, if the applied pressure is decreased
the magnitude of e.m.f. decreased.

Fig. 1.34
Advantages
1. It is simple, robust and has high stiffness.
2. The output voltage is of considerable magnitude.
3. It has a very good high frequency response.
4. No external power is required so it falls in the category of active transducer.
Disadvantages
1. It can not measure static pressure since the crystal can produce the voltage
when the applied pressure is changing.
2. The output voltage is affected by the change in temperature.
3. The high frequency limit is imposed by the mechanical resonance of the
piezoelectric device.
1.13 MICROPHONES
Microphones are acoustic transducers which convert sound wave (acoustic
energy) into a varying electric current that can be amplified and transmitted to distant
places with different links. Microphones are the following types:
1. Carbon microphone

26
2. Moving coil microphone
3. Crystal microphone
4. Capacitor microphone
1.13.1 Carbon Microphone
Figure 1.35 illustrates the construction of carbon microphone. It consists of metal
diaphragm which vibrates due to the falling of the sound waves. Due to these vibrations a
varying pressure is applied on the very fine carbon granules packed between the carbon
block and the diaphragm. The fine granules offer appreciable resistance which depends
upon its closeness. When the pressure is increased on the carbon granules then due to the
increase in the contact area of the granules the resistance decreases. On the other hand
due to the decrease of the pressure the resistance increases. This way the variation of the
resistance of microphone is in accordance with the variation of the sound waves. This
device when externally connected with a voltage source then the resulting current would
a function of sound pressure. The most common application of the carbon microphones is
in telephone. The frequency range of these microphones is limited to a maximum of
about 5 KHz. The output impedance of these microphones is low and sensitivity is high.
However the following are their drawbacks:
1. They are noisy i.e. back-ground hiss is generated.
2. They are not good for high quality reproduction.
3. Due to the presence of moisture in the atmosphere the carbon granules cling
together which reduces the resistance of the microphone and hence sensitivity
is decreased.

Fig. 1.35

1.13.2 Moving Coil Microphone


The moving coil microphone also called the dynamic microphone use the
electromagnetic transduction principle. It consists of a light diaphragm shaped like a
hollow cone which is clamped to a case around its outer rim as shown in figure 1.36. The
diaphragm is made either of stiff cardboard or fibre or plastic materials and has
corrugations pressed into it. An a.c. voltage is generated when a coil is moved in a
magnetic field. A membrane is mechanically linked to a moving coil surrounded by a
permanent magnet, the membrane and the coil are suspended so that they can move back
and forth. The pressure of sound waves force the membrane towards the magnet, moving
the coil across the magnetic field. The voltage developed across the coil terminals is a

27
direct result of the motion of the coil which clearly depends upon the sound waves. This
voltage can further be amplified for driving the loudspeaker. These microphones are self
generating and have low sensitivity and low output impedance. Their frequency response
is limited to 20 KHz. These microphones are never used in precision instruments.

Fig. 1.36
1.13.3 Crystal Microphone
The construction detail of a crystal microphone is illustrated in figure 1.37, which
consists of a piezoelectric crystal such as quartz, tourmaline and Rochelle salt etc. An
e,m.f. may be developed across the electrodes of the crystal due to its piezoelectric
effect. As shown in figure 1.37, the centre of the diaphragm is attached to a drive pin
whose other end is connected to one electrode of the crystal. When sound waves fall on
the diaphragm, it vibrates to and fro thereby subjecting the crystal to mechanical stress.
An alternating voltage is developed across the electrodes E of the crystal which is in
accordance with sound waves incident on the diaphragm.

Fig. 1.37

28
These microphones have high frequency response. These are used for audio
frequencies if the Rochelle salt crystal is used, however, it can be extended to several
megahertz if quartz crystal is used inside the microphone.
1.13.4 Capacitor Microphone
In capacitor microphones parallel capacitor is used as a transducer. One plate of
this capacitor is a moving diaphragm. A constant charge is maintained on the plates of the
capacitor from a d.c. voltage called polarizing voltage. When the sound waves falls on
the movable plate or diaphragm it moves to and fro thereby changes the capacity of the
capacitor. The changes in the capacity of the capacitance cause a change in the capacitor
voltage. The variation in capacitor voltage is in accordance with the variation in the
sound waves, which can be amplified to the desired level. The frequency range of these
microphones high to about 50 KHz and sensitivity is reasonably good.
1.14 LOUDSPEAKER
Loudspeaker is a transducer which converts the varying current into sound waves;
it is just the opposite of the microphone. Figure 1.38 shows the construction of a
loudspeaker which consists of large diaphragm generally made of stiff paper mounted on
a large size baffle board. The moving coil also called speech coil is wound on a light
cylindrical former of cardboard which is attached to the diaphragm. This coil can move in
and out parallel to its axis in the strong radial field of the electromagnet. When the
amplified output from the microphone is passed through the coil, it moves in and out as
per the strength of the varying current carried by it. Since the diaphragm is attached to the
speech coil so any variation in the coil will lead vibration in the diaphragm resulting
thereby vibratory motion in the air in front of it. This way sound is reproduced from the
loudspeaker.

Fig. 1.38

PROBLEMS

1. What is a transducer? List the different types of transducers. What is the


difference between self generating and passive transducer?

29
2. Name different classes of transducers. Give two example of each class. What
points are to be considered while selecting a transducer?
3. What is resistance strain gauge? Define the gauge factor of a resistance stain
gauge and find the expression for the strain gauge in terms of other parameters.
4. Describe the principle of operation of a pressure transducer.
5. Distinguish between bonded and unbonded strain gauge. What are advantages of
using a foil type strain gauge?
6. Discuss the principle and working of resistance thermometer.
7. Differentiate between a Thermistor and Thermocouple.
8. What is resistance Thermometer? Discuss its operation and construction details.
How Wheatstone bridge is used to measure the change in resistance of the
Resistance Thermometer?
9. Name different types of photoelectric transducers. Discuss the working of photo
multiplier tube.
10. What is the difference between Photo-emissive, Photo-conductive and Photo-
voltaic transducers? Discuss in detail the Photo-voltaic cell.
11. What is photo conductive cell? Describe its working and use.
12. What is the difference between Photo-diode and photo-transistor? Discuss the use
of photo-transistor.
13. Describe the principle of operation of LVDT. Mention its advantages and
disadvantages.
14. Describe the principle of operation of a pressure transducer employing each of the
following principles:
i) Resistive Transducer
ii) Inductive Transducer
iii) Capacitive Transducer
15. Describe the essential difference between a variable reluctance type of transducer
and an LVDT.
16. Discuss Piezoelectric transducer. Mention its advantages and disadvantages.
17. Name the various types of Microphones. Discuss carbon microphone.
18. What is the difference between moving coil microphone?
19. Discuss the principle and working of the vacuum photo tube.
20. Write short on the following:
i) Loudspeaker
ii) Crystal Microphone
iii) Capacitor Microphone

__________

30
2
IC Fabrication
A discrete electronic circuit is built by soldering separate electronic components
on a board. In this case separately fabricated electronic components are assembled. In
early 1960s, a new field popularly known as microelectronics was developed which
reduced the size of electronic circuits drastically. This field of electronics leads the
development of small size electronic circuits known as integrated circuits. An integrated
circuit (IC) is a complete electronic circuit in which both the active and passive
components are fabricated on an extremely small silicon wafer. The ICs are produced by
the same process as individual transistors and diodes are fabricated. In such
microelectronic circuits different components are isolated from each other by isolation
diffusion within the silicon wafer and are interconnected by the aluminum layer that
serves as wires. In this chapter the discussion on the basic processes involved in the
fabrication of integrated circuits will be made.
2.1 INTEGRATED CIRCUIT TECHNOLOGY
A number of active and passive components combined to form one package
which can perform the desired function of an electronic circuit, is known as the integrated
circuit. On the basis of the fabrication technology, the integrated circuits can be divided
into following two categories.
1. Monolithic ICs
2. Hybrid ICs
In monolithic ICs, all the active and passive components are fabricated on a single
crystal wafer of semiconductor usually silicon. A monolithic circuit has the advantage
that since all its components are contained on a single chip, many such units can be
processed to together.
Hybrid circuits are formed either by interconnecting a number of monolithic
circuits or individual transistors bonded to an insulating substrate with passive
components like resistors and capacitors connected externally with proper connection. In
such ICs, active components are first formed within a silicon wafer (using monolithic
technique) which is subsequently covered with an insulating layer such as SiO2. Passive
components are then employed on the insulating layer. Further proper connections are
made.
The discussion in this chapter will be made mainly on monolithic ICs.
As per the applications of ICs, the monolithic ICs can further be divided into two
main classes.
1. Analog or Linear ICs
2. Digital ICs
The analog ICs perform linear operations such as signal operations. Operational
amplifiers, simple amplifiers, audio amplifiers, power amplifiers, voltage comparators
and voltage regulators etc. fall in the category of analog ICs.
Digital ICs contain circuits whose input and output voltages are limited to two
possible levels – low or high. It is so because digital signals are actually binary. Logic
gates, flip-flops, counters, memory chips, calculator chips and microprocessor chips etc
are the digital ICs. In recent years these digital ICs found applications in almost every
field.
Both digital and analog ICs can be fabricated using either bipolar technology or
MOS technology. However, MOS technology is almost exclusively used for digital
circuits.
2.2 ADVANTAGES OF INTEGRATED CIRCUITS (ICs)
The integrated circuits have the following advantages over the use of discrete
components circuits:
Extremely small size
With the invention of the transistor in1948, the size of the electronic circuit was
considerably reduced. Further the invention of integrated circuit technology leads the
reduction in size of the electronic circuit to thousands of times smaller than a discrete
circuit. Inside the ICs the various components and their interconnections can only be
distinguished with the help of a powerful microscope.
Very small weight
Due to high packing density of the various electronic active and passive
components inside a semiconductor chip, the weight of the circuit has drastically reduced.
So ICs are basically of small weight and small size, which are the primary considerations
of the military equipments.
Low cost
The costs of integrated circuits are very low. Since the batch procedure is
employed, so a large number of ICs can be fabricated in one lot which reduces the cost of
each IC.
Low power consumption
Because of their small size, ICs are more suitable for low power operation than
bulky discrete circuits.
Extremely high reliability
Miniaturization of components and the batch fabrication of hundreds of circuits in
one lot have not only reduced the size, cost and weight of the circuit but also improved
the reliability of the circuit. The reliability of the integrated circuits is improved because
all the components are fabricated simultaneously and there are no soldered joints.
Improved performance
The high frequency performance of integrated circuits has improved because the
compactness of the components in the circuit has reduced the capacitance of
interconnections. This also helps in improving switching speed.
Easy replacement
It is always economical to replace the ICs in case of failure, as it can not be
repaired.
2.2.1 Limitations of the Integrated Circuits
Integrated circuits have some serious limitations:

32
1. Coils or inductors can not be integrated directly.
2. Capacitors and resistors are limited in maximum value.
3. Low noise and high voltage operation are not obtained easily.
4. Power dissipation is limited.
2.3 BASIC MONOLITHIC INTEGRATED CIRCUITS
The word monolithic is derived from the Greek mono means ‘single’ and litho
means ‘stone’. Thus a monolithic circuit is built into a single stone or single crystal. In
monolithic integrated circuits the active elements (diodes and transistors) and passive
elements (resistors and capacitors) are formed in the silicon slice by diffusing impurities
into the selected regions to form the P-N junctions. The diffusion operations are carried
out on the top surface of the silicon slice and also the element contact regions are formed
on the same surface so that they can be interconnected to form the complete circuit.
Various steps involved in the fabrication of monolithic integrated circuits will now be
discussed in detail.
Wafer Preparation
A P-type silicon bar is taken and cut into thin slices called wafer (fig. 2.1). These
slices are cut using a large diameter stainless steel saw blade with industrial diamonds
embedded into the inner diameter cutting edge. Thus circular slices or wafers of about
600 to 1000 µm thick are produced. The cutting process is water cooled, and because of
the width of the blade, more than one-third of the crystal is lost as sawdust during the
cutting process. While slicing the wafer, its surface is heavily damaged. Therefore, the
wafers undergo a number of polishing steps to remove the damaged silicon and to
produce planar or flat surface which is necessary for further steps of IC fabrication.

Fig. 2.1
The sawing operation leaves a damaged layer (about 20 to 50 µm thick) on the
wafer which is removed by lapping and etching. A mechanical two sided lapping
operation is performed under pressure using the mixture of Al2O3 and glycerin. This
operation produces a wafer with flatness uniform to within about 2 µm . After lapping,
still there exists a sufficient surface damage on the crystal which is further removed with
a chemical etching. For etching a chemical solution of nitric acid and hydrofluoric acid is
used.
Finally the surface of the wafer is polished to mirror like finish. For this the
etched wafer is mounted on large circular stainless steel polishing plates and either wax
or vacuum is used to hold them. These plates are then mounted on a polisher, and the

33
wafers are pressed against a tough polishing pad made of artificial fabrics. A polishing
solution may be used that chemically etches and mechanically polishes the wafer
simultaneously. Thus the wafer is polished to a mirror like finish. It will be ready for use
for device fabrication after thorough cleaning.
2.3.2 Epitaxial Growth
The word epitaxial is derived from Greek epi means upon and taxial means to
carry or to arrange. So epitaxial layer is special layer or growth upon which all the active
and passive components can be formed or arranged. Epitaxial growth is a process or
chemical reaction to form a thin film of single crystal (mono-crystalline) silicon from a
gaseous solution or vapour phase with certain conduction properties on the surface of
another silicon wafer or slice. The epitaxial layer may be either P-type or N-type. The
basic chemical reaction used to describe the epitaxial growth of pure silicon is the
hydrogen reduction of silicon tetrachloride.

As the epitaxial film of specific impurity concentrations is required and so it is


necessary to introduce impurities such as phosphine (PH3) for N-type doping or biborane
(B2H6) for P-type doping into silicon tetrachloride. Hydrogen is bubbled through the
volatile silicon compound, causing it to vaporize.
Figure 2.2 illustrates how the epitaxial layer of silicon is grown on the silicon wafer. This
system consists of a long cylindrical quartz tube encircled by a radio

Fig. 2.2

frequency induction coil. The silicon wafers are placed on a rectangular graphite rod
called a boat. The boat is inserted in the reaction chamber where the graphite is heated to

34
about 1200 oC with the help of induction coil. At the input of reaction chamber a control
console permits the introduction of various gases required for the growth of appropriate
epitaxial layers. Silicon and dopant atoms from the vapour skid about on the surface of
the growing epitaxial film until they find a correct position in the lattice and become
fastened into the growing structure by inter-atomic forces. It can be observed from figure
2.3 that the atoms of newly grown layer are arranged in single crystal fashion on the
single crystal substrate. The lattice structure too of the newly grown layer is an exact
extension of the substrate crystal structure.

Fig. 2.3
2.3.3 Masking and Etching
As discussed above all the active and passive components are to be formed on the
epitaxial layer, so a silicon dioxide layer is deposited over the epitaxial layer. The
oxidation of the silicon slice is carried out by heating at a temperature around 1000 oC in
a flow of oxygen or steam. The later is more often used, as it results in a faster rate of
oxide growth. Typical oxide thickness is about 0.04 mil (0.001 mm) produced by heating
in steam at 1000 oC for about four hours. The layer of silicon dioxide on the surface of a
silicon wafer or slice prevents the diffusion of impurities into the wafer.
Now the selective removal of silicon dioxide is required to form the openings
through which impurities may be diffused. This selective diffusion is the basis of all
silicon monolithic integrated circuit fabrication. The selective removal of silicon dioxide
is carried out by a photolithographic technique using photoresist material. Through the
proper masking and exposure of the photoresist material to ultraviolet light and then
etching will provide the required openings in the silicon dioxide layer. Following steps
are used for this purpose.

35
1. The wafer is coated with a uniform film of a photosensitive emulsion (such as
the Kodak photoresist KPR). A spinner is used for coating the wafer with
photoresist uniformly. A wafer is placed on a flat holder on the top of a
rotating shaft. Vacuum is to hold the wafer to the holder. An appropriate
amount of photoresist is placed at the centre of the wafer with the help of
dropper. The shaft is then rotated. As the wafer rotes the photoresist spreads
uniformly over the surface of the wafer. The wafer is then removed from this
unit and baked in an oven to remove the excess solvent. After cooling to room
temperature the wafer is ready for exposure to ultraviolet light through an
appropriate mask.
2. A mask of desired pattern of opening is prepared to place over the film of
photoresist material. In the early days of IC fabrication when the circuits were
simple, the draftsmen used to prepare the mask from rubylith. The rubylith is
a double layered sheet (red as the top layer and white as the bottom layer).
The red layer could be cut to the desired pattern with a razor knife. This
pattern used to be 100 to 1000 times the actual mask size. It was reduced to
the proper size using a photographic camera. For most present day integrated
circuits, mask making is automated by using computer controlled drawing
boards and other equipments.
3. The mask thus prepared is placed over the photoresist, which is then exposed
to ultraviolet light through the mask as shown in figure 2.4(a). The photoresist
becomes polymerized under the transparent regions of the mask.
4. The mask is now removed and the wafer is developed by using a chemical
(such as trichloroethylene) which dissolves the unexposed (un-polymerized)
portions of the photoresist film and leaves the surface pattern as shown in
figure 2.4(b).

Fig. 2.4

36
5. The polymerized photoresist is not removed rather fixed and become resistant
to the corrosive etches used next.
6. The chip is now immersed in an etching solution of hydrofluoric acid, which
removes the oxide from the areas through which dopants are to be diffused
(figure 2.4c). Those portions of silicon dioxide which are protected by the
photoresist are unaffected by the acid.
7. Further impurities are diffused through the openings and then the photoresist
mask is removed with a chemical solvent (hot H2SO4) and by means of a
mechanical abrasion process.

2.3.4 Diffusion of Impurities


The next important step in the fabrication of integrated circuits is the diffusion of
appropriate dopant impurities into the silicon chip. The diffusion of impurities is
accomplished in a high temperature furnace. Impurity atoms are introduced onto the
surface of a silicon wafer and diffuse into the lattice because of their tendency to move
from regions of high concentration to low concentration. The diffusion of impurity atoms
into silicon crystal takes at a very high temperature typically 900 to 1100 oC which is of
course below the melting temperature of the silicon. The melting temperature of the
silicon is about 1420 oC. In practice the diffusion process is carried out in two steps. In
the first step the silicon slice is heated in the impurity dopant vapour to form a high
concentration of dopant on the surface. This step is called the deposition step. In the
second step, called as diffusion step, the slice is removed to another furnace where it is
heated to a higher temperature so that the dopant atoms on the surface move or diffuse
into the silicon.
The diffusion rate of impurities into semiconductor lattice depends on the
following factors:
(i) mechanism of diffusion,
(ii) temperature,
(iii) physical properties of impurity,
(iv) the properties of the lattice environment,
(v) the concentration gradient of impurities, and
(vi) the geometry of the parent semiconductor.
The equation governing the diffusion of neutral atoms is given by Fick’s law as:

∂N ∂2N
=D 2 … (2.1)
∂t ∂x
where N is the particle concentration in atoms per unit volume as a function of
distance x from the surface and time t, and D is the diffusion constant in area per unit
time.
The solution of this equation gives the impurity concentration N at some distance
x from the origin, usually the surface of the semiconductor as shown in figure 2.5.

37
Fig. 2.5
Depending on the boundary conditions, equation (2.1) will have two types of
solution. These two solutions will provide two types of impurity distribution namely:
(i) constant source diffusion following Complementary Error
Function ( efrc ),
(ii) limited source diffusion following Gaussian Distribution Function.
Constant Source Diffusion (Complementary error function)
In constant source impurity diffusion ( efrc ), the impurity concentration at the
semiconductor surface is maintained at a constant level throughout the diffusion cycle,
i.e. N(o,t) = constant = No
The solution to the diffusion equation can most easily be obtained by considering
total diffusion inside the material in which the initial concentration changes abruptly in
the same plane at x = 0 from No to zero. So the solution to the equation (2.1) with the
boundary conditions N(o,t) = No = constant and N(x,t) = 0, is given by:
 x 
N ( x, t ) = N o 1 − erf 
 2 Dt 
x
= N o erfc … (2.2)
2 Dt
x x
where erfc is the error-function complement of .
2 Dt 2 Dt
x
The error-function of is defined as:
2 Dt
x 2 D .t
 x  2 λ
= ∫ e dλ
2
erf  … (2.3)
 2 Dt  x 0
where λ is an integration variable.
Figure 2.6 shows graph of complementary error function for the range value of its
argument.

38
Fig. 2.6
The change in concentration of impurities with distance for different values of
time is shown in figure 2.7.

Fig. 2.7
Limited Source Diffusion (Gaussian distribution)
If a specific number Q of impurity atoms per unit area are deposited on one face
of the wafer, and then if the material is heated, the impurity atoms will again diffuse into

silicon. When the boundary conditions ∫ N ( x)dx = Q
0
for all times and N ( x) = 0 at t = 0

for is applied to equation (2.1) we get the solution as:


Q  x2 
N ( x, t ) = exp −  … (2.4)
πDt  4 Dt 
The impurity profile given by the equation (2.4) is known as the Gaussian
distribution. The Gaussian distribution for two times is plotted in figure 2.8. It may be
noted from this figure that as time increases, the surface concentration decreases.

39
Fig. 2.8
The difference between two types of diffusion technique is that for the case of
modelling the depletion layer of a P-N junction the complementary error function is
modelled as a step junction and the Gaussian as a linear graded junction. The Gaussian
distribution is used when moderately high sheet resistivity is desired or when multiple
diffusions are need. Transistor bases are made by this type of distribution.
2.3.5 Metallization
Metallization is the final step in the formation of the integrated circuits. With this
process components of ICs are interconnected by aluminium conductor. It also provide
the bonding pads around the circumference of the chop for later connection of wires. It is
carried out by evaporating aluminium over the entire surface and then selectively etching
away the aluminium to leave behind the desired interconnecting conduction pattern and
bonding pads.
2.4 THE PLANAR TECHNOLOGY
The combination of oxidation, selective oxide removal, and diffusion forms the
basis of the planar technology. The technology is called the planar because the device
fabrication process is carried out from one surface plane. A large majority of silicon
devices are fabricated using the planar technology. The details of the fabrication of a P-N
junction planar diode are discussed below.
An N+ silicon substrate of approximately 150 µm is taken upon which a thin
layer of N-type silicon is grown by the epitaxial process (fig. 2.9a). The wafer is then
cleaned and a silicon dioxide layer is grown over it (fig. 2.9b). The window cutting is
done with help of photolithographic technique. For this the top surface of the wafer is
then coated with a photoresist material (fig. 2.9c).
The proper mask of the appropriate dimension is placed over it and which is then
exposed to ultra violet light (fig. 2.9d). The photoresist gets polymerized in the region
where the light has fallen but remains unpolymerized, the region which is not exposed to
light. The exposed photoresist is developed and unpolymerized area is washed away. It
leaves a solid film of the polymerized photoresist. The wafer is now etched by the
hydrofluoric acid which removes the area not covered by the photoresist but remains
unaffected beneath the photo resist. The polymerized photoresist is then removed by
dissolving it in an organic solvent which leaves the oxide layer with window in the
desired area as shown in figure 2.9(e).

40
The Boron is diffused through the window to produce P-type region. This way P-
N junction is formed (fig. 2.9f). To make the contact with the P-region a thin film of Al is
deposited on the top surface (fig. 2.9g). The excess metal film may further be removed by
using again the photolithography technique. The contact metal is also deposited on the
back surface (fig. 2.9h), and Ohmic contacts to both sides of the junction are made by
appropriate heat treatment. This way final structure of P-N junction planar diode is
formed.

Fig. 2.9
Using the similar steps discussed above one fabricate the planar N-P-N transistor
also. Figure 2.10 shows the device structure of planar N-P-N transistor.

41
Fig. 2.10
2.5 MONOLITHIC INTEGRATED CIRUCITS TECHONOLGY
Monolithic integrated circuit technology is basically an extension of the diffused
planar process discussed in the forgoing section of this chapter. The active and passive
components are formed in the silicon slice by diffusing the impurities into selected
regions. The various elements are formed so that they can be fabricated simultaneously
by same sequence of diffusions. All operations are carried out on the top surface of the
silicon slice and all contact regions are formed on this same surface so that they can be
interconnected to form the complete electronic circuit by evaporating metallic films of
proper pattern. The elements, which are electrically conducting are formed in the
integrated circuits in the close proximity in the silicon wafer. It is, therefore, necessary to
have the electrical isolation between the components. The isolation between the
components is provided either by a reverse bias P-N junction or by an isolating dielectric
material.
2.5.1 P-N Junction Isolation
In this isolation technique each element is surrounded by a reverse bias P-N
junction diode, which offers a high resistance between the components. For this N-type
epitaxial layer is grown on a P-type silicon surface (figure 2.11a). The wafer is oxidized
and windows are etched through the oxide on the N-type side using photolithography and
oxide etching. The Boron impurities are diffused through the windows. The Boron
diffusion thus reaches up to the P-type substrate. The N-type islands are thus formed
which are separated by P+ regions (figure 2.11b). The components are now formed in
these islands. All these islands are electrically isolated from each other by reverse
biasing the P-N junctions. The reverse biasing is done by applying a negative potential to
the P-type substrate.
A bipolar N-P-N transistor can be fabricated in the N-type Island by performing
p-type diffusion through a window in the oxide and then by performing emitter diffusion.
A major disadvantage of this transistor is that it has a high collector series resistance
because N-type epitaxial layer is lightly doped.
The problem of high collector resistance can be reduced considerably if a
selective N+ layer is grown before the epitaxial layer as shown in figure 2.11(c). This
layer is known as Buried layer. The buried layer provides a low resistance path for the

42
electrons to flow from active region of the transistor to the collector Ohmic contact.
Figure 2.11(d) shows an isolation region with a buried layer.

Fig. 2.11

2.5.2 Dielectric Isolation


In this type of isolation, a layer of silicon dioxide is formed around each element.
This method is illustrated in figure 2.12. An n-type silicon substrate is considered for this
dielectric isolation over which an N+ diffusion is carried out over the entire surface. The
wafer is then oxidized and windows are etched in the oxide layer using photolithography
technique. The etching of the silicon dioxide is followed by the etching of the silicon in
the windows to obtain etched channels as shown in figure 2.12 (a). A silicon dioxide
layer is then grown to cover the wafer, and polycrystalline silicon is deposited over the
oxide layer as shown in figure 2.12(b). The structure is now turned upside down, and the
N-type silicon is lapped off to obtain the isolated regions of the N-type silicon shown in
figure 2.12(c). Each of these islands is isolated by the layer of silicon dioxide supported
by polycrystalline silicon. The desired components may be fabricated in these islands.
This type of isolation eliminates the substrate bias and results the low parasitic
capacitance.

43
Fig. 2.12
2.5.3 V-groove Isolation
There is another method of isolation known as V-groove method. This method is
shown in figure 2.13. This method is the combination of dielectric and P-N junction
isolations discussed. In this method an N-type silicon substrate is considered to which N+
diffusion is performed. Over this diffused layer silicon dioxide layer is grown, which is
then subjected to form the windows through the oxide layer as shown in figure 2.13(a).
The wafer then undergoes an orientation dependent etching process using the proper
mask. The etched surface develops groove with <111> side walls as shown in figure
2.13(b). In the groove sidewalls are at an angle of 54.74o with respect to top surface of
the silicon wafer or we can say that the depth of the groove will be determined by the
width of the windows. This wafer is then oxidized to cover it with a layer of silicon
dioxide. Further polycrystalline silicon is deposited to fill the groove as shown in figure
2.13(c). The structure is now turned upside down, and the N-type silicon is lapped off to
obtain the isolated regions of the N-type silicon shown in figure 2.13(d). Each of these
islands is isolated by the layer of silicon dioxide supported by polycrystalline silicon. The
desired components may be fabricated in these islands. In this method N+ diffused layer
serves as a buried layer to reduce the collector resistance for the N-P-N transistors.

(a)

44
(d)
Fig. 2.13
2.6 FORMATION OF MONOLITHIC INTEGRATED CIRCUIT COMPONENTS
In this section the formation of active and passive components inside the
integrated circuit will be discussed. The most important components in the integrated
circuits are diodes, transistors, resistors and capacitors.
2.6.1 N-P-N Transistors
For the formation of N-P-N transistors in a monolithic integrated circuit, an N-
type epitaxial layer is grown on the P-type substrate. A silicon dioxide layer is deposited
over the epitaxial layer. By using photolithographic technique discussed earlier windows
are formed in the silicon dioxide layer. The wafer is then exposed to third group
impurities like boron at high temperature. The epitaxial layer is thus divided into a
number of islands. The transistors are now formed in these islands by repeated diffusion.
In one island using the proper masking boron is diffused to form the base of the
transistor. After the base diffusion, the wafer is again masked and fifth group impurities
like phosphorous are introduced into it to form emitter of the transistor. The impurity
concentration of emitter is kept quite high. At the same time another N+ region is diffused

45
into N-type collector region to form a low resistance collector. The formation of such an
N-P-N transistor is shown in figure 2.14. Since the anode of the isolation diode covers the
back of the entire wafer, it is necessary to make the collector contact on the top as shown
in this figure. The transistor fabricated with method has the following drawbacks:
(i) It produces undesirable parasitic shunt capacitance due to the
formation of isolation diode as discussed earlier.
(ii) The collector contact at the top increases the length of the collector and
hence the resistance of the collector is not reduced much.
(iii) It provides the leakage current path.
The discrete planar technology discussed earlier has some advantage over this
method, yet the monolithic epitaxial transistor is better as in the integrated transistors are
located physically close together due to which their electrical characteristics are closely
matched.

Fig. 2.14
The collector series resistance in monolithic epitaxial transistor may be reduced
by placing a heavily doped N+ buried layer as discussed earlier. In this case N+ buried
layer is formed on the P-type substrate. Over this buried layer N-type epitaxial layer is
grown. Then the normal procedure is followed to form the complete transistor as shown
in figure 2.15. In the formation of N-P-N transistors isolation diffusion, base diffusion
emitter diffusion, contact window openings and etching of the metallization pattern are
carried.

Fig. 2.15
2.6.2 Diodes
The formation of P-N junction diodes in a monolithic integrated circuit is done by
using the basic structure of N-P-N transistor. Advantage of using the transistor in the

46
formation of diode is that no separate diffusion is to be performed for the fabrication the
diodes in the monolithic ICs. There are five different ways to connect a transistor as a
diode which are shown in figure 2.16 and these are:
(i) an emitter base junction diode with the collector shorted to base,
(ii) an emitter base junction diode with an open collector,
(iii) a collector base junction diode with an open emitter,
(iv) a collector base junction diode with emitter shorted to base, and
(v) a collector base junction diode with emitter shorted to collector.

Fig. 2.16
Out of these five different ways of connecting the transistor as a diode, first three
are most commonly used. Any configuration out of these three may be fabricated in the
monolithic ICs depending upon the circuit requirements. The fabrication of these three
configurations is illustrated in figure 2.17.

Fig. 2.17

47
2.6.3 Resistors
Silicon is a resistive material. Its resistivity depends upon the concentration of
current carriers (electrons and holes). A resistor can be formed in a silicon wafer by
diffusing a suitable impurity into a defined region, the value of the resistor so formed
depends on
(i) the concentration of the impurity,
(ii) the dimension of the region at the surface, and
(iii) the depth to which the impurity is diffused in.
Most resistors in integrated circuits are formed at the same time as the P-type base
region of the N-P-N transistor is made. The resistors are made by having the connecting
leads at the two ends of the diffused layers. The diffusion layers are extremely thin so
that it is more convenient to express the resistivity of the layer in terms of sheet resistance
RS of the layer.
Sheet Resistance: Consider a sheet of resistive material of resistivity ( ρ ), of
length of L and width w, thickness y and cross-sectional area A = Ly as shown in figure
2.18. The resistance of this sheet in Ω/ is given by:
ρL ρ
RS = = …. (2.5)
Ly y

It is clear from this equation that sheet resistance RS is independent of the size of
the square; it only depends on the resistivity of the material and the thickness of the layer.
In order to design a resistor of 200Ω from a material of 20 Ω/ , we may put 10 squares
in succession and make contact to the ends.

Fig. 2.18
Figure 2.19 shows the top and cross-sectional view of a resistor fabricated by a P-
diffusion in one of the N-island. The resistance of the diffused layer may be given by:
L
R=ρ … (2.6)
yw

48
From equations (2.5) and (2.6) the resistance of the diffused layer can also be
given as:
L
R = RS … (2.7)
w
Here L is the length of the diffused layer and w is the width of the diffused layer

(a) (b)
Fig. 2.19
as shown in figure 2.19(a). RS is the sheet resistance of the layer which is expressed in
and can accurately be measured using Four Probe technique. Thus the resistance R of the
diffused layer can be measured by knowing the sheet resistance RS and the ratio of the
length and the width of the layer. In order to obtain a high value of resistance, the width
w should be made small. The width w can not be made small beyond a certain limit
because of the limitations of the photolithographic resolution and heat dissipation.
Further a straight path resistor can give rise to an inconvenient layout of the circuit.
Practically long resistor bodies are folded in a meander as shown in figure 2.20.

Fig. 2.20
The values of RS for base diffusion are generally in the range of 100 to 500 Ω/ .
To obtain high resistance values having minimum occupied space in the integrated
circuits, it will therefore be necessary to obtain surface layer with higher sheet resistance
RS than is available for standard base diffusion. Higher sheet resistance may be obtained
by using the pinched base resistor shown in figure 2.21. It is fabricated by diffusing an N+
emitter region over the centre of the base resistor. Typical values of sheet resistance that
can be obtained with this design are 2 to 10 K Ω/ .

Fig. 2.21

49
2.6.4 Capacitors
Two types of capacitors are commonly used in monolithic circuits namely:
(i) Junction Capacitors, and
(ii) Dielectric or MOS Capacitors
Now we shall describe both these two types of capacitors.

Junction Capacitors: It is well known that when a P-N junction is reverse biased, the
depletion region acts like an insulator which is essential for making a capacitor. The two
regions (P-type or N-type regions) on either side of the depletion region act as the plates
as they have low resistance path. The reverse biased P-N junctions can, therefore, act like
the capacitors. So in monolithic circuits the capacitors are formed by having reverse
biased P-N junctions. The capacity of these capacitors is inversely proportional to the
width of the depletion region. The width of the depletion region depends on the impurity
concentration profile in the vicinity of the junction. Junction capacitors can be made with
three separate junctions available in ICs. These are base-emitter, base-collector and
collector-substrate capacitors associated with the N-P-N transistor structure. Figure 2.22
(a) shows the structure of junction capacitor formed by the reverse biased collector base
junction J2 which separates the N-epitaxial layer from the upper N-type diffusion layer.
The additional junction J1 appears between the N-epitaxial layer and the substrate. A
parasitic capacitance C1 is associated with this reverse biased junction. The equivalent
circuit of the junction capacitance is shown in figure 2.22(b), in which C2 is the desired
capacitance which should as large as possible relative to C1. The series resistance R
represents the resistance of the N-type layer.

Fig. 2.22

Figures 2.23(a) and (b) show emitter-base and collector-base junction capacitors.
The types of junction capacitors discussed in this section have the following drawbacks:
(i) The P-N junction must always be kept reverse biased. The value of the
capacitance varies with the reverse voltage.
(ii) For the emitter-base junction, the breakdown voltage is only about 7
volts. For the collector-base junction the breakdown voltage is higher
but the capacitance per unit area is quite low.

50
Fig. 2.23
MOS Capacitors:
The disadvantages of the junction capacitors are removed in MOS (Metal Oxide
Semiconductor) capacitors. These capacitors are most widely used in monolithic ICs.
Figure 2.24 shows the side view of the MOS capacitor with a SiO2 layer between the two
electrodes (Metal and Semiconductor). The silicon dioxide layer behaves like a dielectric.
In the formation of this type of capacitors an N+ layer is diffused into the silicon at the
same time as the emitter diffusion is formed. This layer forms the bottom electrode of the
capacitor. On the top of this N+ layer a silicon dioxide layer is formed. The thickness of
the silicon dioxide layer is controlled very accurately. The capacity of the MOS capacitor
depends on the thickness of this SiO2 layer. The top electrode is formed from the
deposition metal film. The metal film is deposited at the same time as the interconnection
pattern is formed in the integrated circuits. The MOS capacitors are voltage independent
and has low loss factor.

Fig. 2.24
2.6.5 P-N-P Transistors
It has been observed in the following sections of this chapter that the IC
fabrication process was basically developed for N-P-N devices. The N-P-N transistors are
preferred because of its high frequency performance and high current gain. In some
applications, however, P-N-P transistors in monolithic ICs are also needed along with the
N-P-N transistors. We will now discuss the structures of P-N-P transistors. The P-N-P
transistors may either be developed in lateral or in vertical form.
Lateral P-N-P Transistors: Figure 2.25 shows the cross-sectional view of the lateral P-
N-P transistor. It is the most common form of the P-N-P transistor fabricated in the
integrated circuits. In the design of this device P-type emitter and collector regions are
formed at the same time the bases of the N-P-N transistors are formed. The N+ base of

51
the P-N-P transistor are fabricated during the formation of emitters of the N-P-N
transistors. The main advantage of the structure is that no additional processing steps
such as masking and diffusion are carried out.

Fig. 2.25
In the lateral P-N-P transistor, action takes place in the lateral direction, i.e.
parallel to the device surface. The minority carrier transport across the base region is
most efficient at or near the surface of the device, where the separation between the
collector and emitter WB is minimal. The value of the base width of the lateral P-N-P
transistor is quite larger due to which the current gain is low.
Vertical P-N-P transistors: The cross-sectional view of vertical P-N-P transistor is
shown in figure 2.26. This can also be fabricated simultaneously and by the same
processes as are used with N-P-N transistors. In the vertical P-N-P transistor, the
fabrication of P-type emitter of P-N-P transistor is done at the time base of N-P-N device.
Secondly the N+ base region of P-N-P transistor and N-type emitter of N-P-N transistor
are fabricated simultaneously. The collector of the vertical transistors is made of P-type
substrate which is common to rest of the circuit and it is all the times a.c. grounded.
Therefore, vertical P-N-P transistor is available only in this grounded collector
configuration. The performance of the vertical P-N-P transistor is considerably good to
that of a lateral transistor.

Fig. 2.26
2.7 MONOLITHIC JUNCTION FIELD EFFECT TRANSISTORS
The typical construction for an N-channel junction Field Effect Transistor (JFET)
illustrated in figure 2.27. It can easily be seen that this structure is compatible with N-P-N
transistor fabrication sequence. It consists of a P-type substrate upon which an N-
epitaxial layer is deposited. Further P-type impurities are diffused into this N-channel to
form the gate of the field effect transistor. Heavily doped two N-regions in the epitaxial
layer are formed which are known as source and drain of the field effect transistor as
shown in figure 2.27.

52
Fig. 2.27
The construction details of P-channel junction field effect transistor is shown in
figure 2.28. It is similar to the N-channel JFET and can easily be understood.

Fig. 2.28
2.8 MOS FIELD EFFECT TRANSISTORS
In this section the construction details of the simple Metal Oxide Semiconductor
Field Effect Transistors (MOSFETs) will be discussed. In fact MOS technology now is
the basis for most of the LSI and VLSI digital memory and microprocessor circuits. The
most important advantage of this technology is that it more packing density i.e. more
circuit elements can be fabricated on a single chip with this technology.
Figure 2.29 shows the cross-section view of the P-MOSFET structure in which N-

Fig. 2.29
type substrate is considered. By having the proper silicon dioxide layer over the substrate
and window cuttings P-type impurities are diffused for the formation of source and drain.

53
Finally the gate connection is formed from the silicon dioxide layer as shown in figure
2.29. The N-MOS structure is shown in figure 2.30. It is similar to P-MOS except that the
N+ regions are diffused into the P-type silicon substrate.

Fig. 2.30
2.9 IC CROSSOVERS
Very often the layout of a monolithic circuit requires two conducting paths to
cross over each other. Such type of crossover can not made directly. So there should be
means that can avoid such crossing of conductors used for interconnection. The method
should be compatible with IC process i.e. no extra steps should be used for the design of
such circuits. Figure 2.31 shows the two conductors crossing each other. One conductor

Fig. 2.31
is shown by dotted line while the other by dark line. This type of crossing can be done by
using the Buried Crossover method. This method is illustrated in figure 2.32. In this
method an N+ diffusion is made and contact windows are opened at each end. Sufficient
space should be provided between contact windows, so that the conductor can be
deposited on the oxide layer above N+ diffusion. The other conductor has its path beneath
the oxide layer i.e. through the N+ layer. Further this method is compatible with the IC
process as no extra step is to be performed. The N+ diffusion can be performed at the
same time as the emitter diffusion.

Fig. 2.32
In another type of crossing occurring between a conductor and a resistor is shown
in figure 2.33(a). This type of crossing can be provided by using the diffused base resistor
as shown in figure 2.33(b). The sufficient space should be provided between the pads for
a metal strip shown by dark block. The main advantage of this technique is that the

54
crossover takes no additional chip area and adds no extra series resistance or shunt
capacitance because the P-type resistor mad is already the part of the circuit.

Fig. 2.33
2.10 COMPLETE INTEGRATED CIRCUIT FORMATION
Now we will discuss the formation of a complete circuit. For this a very simple
circuit having all the possible components is assumed. Such a circuit is shown in figure
2.3. This circuit contains a capacitor, a diode, a transistor and a resistance. In this circuit
formation in the form of an integrated circuit, the elements are formed simultaneously by
the same sequence of oxidation, selective oxide removal, diffusion and metallization. The
construction details of this circuit are given in the followingsteps:

Fig. 2.34

Step-I: For this a P-type silicon wafer is considered a silicon dioxide is formed over
the surface of the wafer as shown in figure 2.35.

Fig. 2.35
Step-II: By using photolithography technique a window is formed. Through this
window the N type impurities are diffused to form an N+ layer as shown in
figure 2.36. This layer provides the low series collector resistance for the
transistor.

55
Fig. 2.36
Step-III: After the formation of N+ layer, the oxide layer is removed, and an N-type
epitaxial layer is grown over the whole surface of the wafer as shown in figure
2.37. This epitaxial layer works as the base for all the circuit elements to be
formed in the integrated circuit.

Fig. 2.37
Step-IV: The surface is re-oxidized; windows are etched in the silicon dioxide layer.
The number of windows formed will depend upon the number of elements to
be formed and P-type isolation diffusion is carried out. It defines the regions
of the N-type layer for each element as shown in figure 2.38.

Fig. 2.38
Step-V: The P-type regions are formed by diffusing P-type impurities through the
window as shown in figure 2.39. These P-regions are for the base of the
transistor, anode of the diode and the first electrode of the capacitor.

Fig. 2.39

56
Step-VI: For the formation of the emitter of the transistor, the collector contact and the
cathode of the diode and the second electrode of the capacitor, the N+
diffusion regions are formed as shown in figure 2.40.

Fig. 2.40
Step-VII: Finally, the metallization for making the contacts to each of the elements and
for interconnection to these elements is done. The metallization pattern is
deposited on the silicon dioxide layer covering the surface of the wafer. This
forms the complete circuit which is shown in figure 2.41.

Fig. 2.41
Figures 2.42 through 2.46 shows the plan view of the last four steps of the
integrated circuit discussed.

Fig. 2.42

Fig. 2.43

57
Fig. 2.45

Fig. 2.46

PROBLEMS
1. What are the advantages of integrated circuits over conventional circuits? What
are their drawbacks?
2. What are the necessary steps involved in the fabrication of a monolithic integrated
circuit? Give the brief description of each step.
3. Describe Photolithography technique.
4. What is the necessity of the epitaxial growth in the formation of integrated
circuits? Discuss how the epitaxial layer is grown.
5. Write short note on the following:
(i) Wafer prepration
(ii) Masking and etching
6. Discuss various methods for the isolation between the components in the
fabrication of integrated circuits.
7. Describe the diffusion of impurities in the silicon chip. What is Impurity profile?
Name and explain the different types of impurity profiles.
8. Discuss the formation of P-N junction planar diode.
9. Discuss the formation of N-P-N transistor in a monolithic IC.
10. How many different ways are there to connect the transistor as diode in a
monolithic IC? Give the details of thee important ways.
11. How resistors are formed in a monolithic IC?
12. How capacitors are formed in a monolithic IC?
13. Discuss the formation of MOS capacitor in a monolithic IC.
14. Describe the different ways of formation of PNP transistors in a monolithic IC.
15. Define buried layer. Why is it used?
16. Describe a lateral P-N-P transistor. Why is its current gain low?
17. Describe the formation of junction field effect transistor.
18. How MOS FETs are formed?

58
19. Explain the different methods of IC crossovers.
20 Give the brief discussion for the formation of monolithic IC of the circuit given
below:

21. Give the brief discussion for the formation of monolithic IC of the circuit given
below:

22. Give the brief discussion for the formation of monolithic IC of the circuit given
below:

_________

59
3
Feedback Amplifiers
When a fraction of output signal is applied back to the input of an amplifier, a
feedback is said to have been introduced in the circuit. If the feedback signal gets added
with the input signal then the feedback is said to be positive feedback. In the positive
feedback the gain of the amplifier goes on increasing and such type of feedback is used in
oscillators. If on the contrary the feedback signal gets subtracted with the input signal
then feedback is called as the negative feedback. The negative feedback is generally
applied in amplifiers; it has many advantages except that the gain of the amplifiers is
reduced. In this chapter the discussion will be made on the feedback amplifiers.
3.1 CLASSIFICATION OF AMPLIFIERS
The amplifiers are classified into the following four broad categories:
(i) Voltage Amplifiers
(ii) Current Amplifiers
(iii) Transconductance Amplifiers
(iv) Transresistance Amplifiers
3.1.1 Voltage Amplifiers
Figure 3.1 shows an amplifier represented by a two port network, in which the input is
driven by a voltage source eS whose source resistance is RS. Thevenin equivalent of this
amplifier is shown in figure 3.2. Let Ri and Ro are the input and output resistances of the
amplifier respectively. RL is the external load resistance connected to the output

Fig. 3.1
terminals of the amplifier. If the amplifier’s input resistance Ri is large compared with
source resistance RS, the voltage ei appearing at the input terminals of the two port
network is almost the same as the source voltage eS (i.e. ei ≈ e S ). Further if the load
resistance RL is large compared with the output resistance Ro of the amplifier, then the
output voltage of the amplifier is given by:
e0 ≈ AV ei ≈ AV eS
where AV is the gain of the amplifier.
Under these conditions the amplifier provides output voltage proportional to the
input voltage. The proportionality factor is independent of the magnitude of the source
and load resistance. Such an amplifier is called a voltage amplifier.

-
Fig. 3.2
An ideal voltage amplifier is one which has infinite input resistance and zero
output resistance. AV represents the open circuit voltage amplification or gain of the
e
amplifier as AV = 0 for RL = ∞ . The term AV is also known as the transfer function of
ei
this circuit since when it is multiplied by input voltage gives the output voltage.
3.1.2 Current Amplifiers
Figure 3.3 shows an amplifier represented by a two port network, in which the
input is driven by a current source IS whose source resistance is RS. External load
resistance RL is connected to the output terminals of the amplifier. Figure 3.4 shows
Norton’s equivalent of this amplifier. Let Ri is the input resistance of the amplifier and Ro
is the output resistances of the amplifier.

Fig. 3.3
If the amplifier’s input resistance Ri is small compared with source resistance RS,
the current source will behave like an ideal current source and the current Ii at the input
terminals of the two port network will be almost the same as the current delivered by
current source IS (i.e. I i ≈ I S ). Further if the load resistance RL is small compared with the
output resistance Ro of the amplifier, then the output current I0 delivered by the amplifier
will be:
I L ≈ Ai I i ≈ Ai I S
where Ai is the gain of the amplifier.

Fig. 3.4
Hence the amplifier provides the current to the load which is proportional to the
magnitude of input current. The proportionality factor Ai is independent of the magnitude
of the source and load resistance. Such an amplifier is called current amplifier.

61
An ideal current amplifier in one which has zero input resistance and infinite
output resistance. In practice the current amplifier has low input resistance and high
output resistance. Ai represents the current amplification or gain of the amplifier. It is
also known as the transfer function of this circuit.
3.1.3 Transconductance Amplifiers
Another class of the amplifiers is known as the Transconductance amplifier which
has been shown in figure 3.5. The input to this circuit is the voltage source VS whose
source resistance is RS (Thevenin’s equivalent). The output is a current source which is
represented by the Norton’s equivalent.

Fig. 3.5
If the input resistance Ri of the amplifier is much larger than the source resistance
RS, then source voltage eS will be equal to the input voltage of the amplifier i.e. ei ≈ e S . If
the output resistance RO of the amplifier is much greater than RL then:
I L ≈ G m ei ≈ G m e S
Under these conditions, this amplifier provides output current Io proportional to
the input voltage ei. The term Gm is the proportionality factor, known as the
transconductance or the gain of the amplifier. It is basically the transfer function which
when multiplied by the input voltage gives the output current.
An ideal transconductance amplifier is one which has infinite input and output
resistances and supplies an output current proportional to the signal voltage and the
output current is independent of RS and RL.
3.1.4 Transresistance Amplifiers
Figure 3.6 shows an amplifier driven by a current source IS having the source
resistance RS. The current source is represented by the Norton’s equivalent. This
amplifier gives an output voltage eo. The output is represented by the Thevenin’s
equivalent.

Fig. 3.6
If Ri << RS then the input current source will behave like an ideal current source,
then the current Ii will be nearly equal to the IS. If the output resistance R0 of the amplifier
is very much less than the load resistance, then this amplifiers provides an voltage eo
proportional to the input current given by:
eo ≈ Rm I i

62
The proportionality factor Rm is independent of both RS and RL and is called as
the transresistance. This is known as the transfer function of this amplifier. When this
factor is multiplied by the input current gives an output voltage.
An ideal transresistance amplifier is one which has zero input resistance and
infinite output resistances and supplies an output voltage proportional to the signal
current.
The characteristics of the four ideal amplifiers are summarized in table 3.1.

Table 3.1
Parameter Types of amplifier
Voltage Current Transconductance Transresistance
amplifier amplifier amplifier amplifier
Input resistance Ri ∞ 0 ∞ 0

Output resistance Ro 0 ∞ ∞ 0

Transfer characteristics eo = AV eS I L = Ai I S I L = Gm e S e o = Rm I S

3.2 CLASSIFICATION OF FEEDBACK


Feedback means a fraction of the output of a system is applied back to the input.
It may be of two types:
1. Positive feedback or Regenerative feedback
2. Negative feedback or Degenerative feedback
If the fraction of the output is feedback to the input and the feedback signal is in
phase with input, or the polarity of the feedback signal is same to that of the input. The
feedback is said to be as positive or regenerative feedback. In the positive feed back the
output of the system goes on increasing and this type of feedback is generally used in
oscillator applications.
If the fraction of the output sampled is in out of the phase or opposite in polarity,
the feedback is called as negative feedback or degenerative feedback.
The negative feedback is used to stabilize the output of the system and this kind
of feedback is generally used in amplifiers, automatic controlled systems. The negative
feedback results the reduction of overall voltage gain of the system however, it offers
various improvements in the operation of the system.
1. It offers high input impedance to the system.
2. It results the low output impedance.
3. It offers good stabilization.
4. It improves the frequency response of the system.
5. It offers reduced noise.
3.3 FEEDBACK TOPOLOGIES
There are four following basic ways to connect the sampled feedback signal to the
input. Both the output voltage and current can be feedback to input either in series or
parallel.
1. Voltage series feedback topology
2. Voltage shunt feedback topology

63
3. Current series feedback topology
4. Current shunt feedback topology
Here, voltage feedback means that fraction of the output voltage is fedback to the
input terminals; and the current feedback refers the tapping off some fraction of output
current through the feedback network. Series refers to connect the feedback signal in
series with the input signal voltage; whereas the shunt feedback refers to connect the
feedback signal in parallel to the input current source.
The series feedback tends to increase the input resistance of the system, whereas,
the shunt feedback tends to decrease the input resistance. However, voltage feedback
tends to decrease the value of the output impedance, whereas, the current feedback
increases the output impedance.
3.4 EFFECT OF FEEDBACK ON TRANSFER GAIN
The effect of feedback on transfer gain is that it reduces the amplification by a
factor of (1 + A β) , i.e.
A
Gain with Feedback A f =
(1 + A β)
It will now be discussed for each of the different topologies.
3.4.1 Transfer Gain for Voltage Series Feedback Topology
The Voltage series feedback topology has been shown in fig 3.7. In this feedback
a fraction ef of the output voltage is applied back to the input terminals in series with it.

Fig. 3.7
ef e0
In this figure, β = is feedback factor and A = is the amplification factor or
e0 ei
gain of the amplifier without feedback.
The input voltage with the application of feedback is given by:
ei = e S − e f … (3.1)
So e0 = Aei = A(eS − A β e0 ) … (3.2)
ef
Since β=
e0
hence Ae S = (1 + A β)e0
The voltage gain with feedback is given by:
e A
Af = 0 = …. (3.3)
eS (1 + Aβ )

64
This equation shows that the transfer gain of the system with feedback is reduced
by a factor (1 + A β) .
3.4.2 Transfer Gain for Voltage Shunt Feedback Topology
The fig. 3.8 illustrates the voltage shunt feedback topology, in which the feedback
signal If is in parallel or in shunt with the input signal.

Fig. 3.8
If e0
In this figure, β = is feedback factor and A = is the transfer function of the
e0 Ii
amplifier without feedback.
IS = I f + Ii … (3.4)
The transfer function of this amplifier with feedback is given by:
e AI i
Af = 0 = … (3.5)
IS Ii + I f

Where, I f = β e0 and the transfer function without feedback is given by:


e0
A=
Ii
Putting the value of A in equation in equation (3.5) we get the transfer function
with feedback as:
AI i A
Af = = … (3.6)
I i + β AI i 1 + β A
From this equation it is clear that the transfer gain with feedback is reduced by a
factor of (1 + A β) .
3.4.3 Transfer Gain for Current Series Feedback Topology
ef
The current series feedback circuit is shown in figure 3.9, in which β = is
I0
I
feedback factor and A = 0 is the transfer function of the amplifier without feedback.
ei

65
Fig. 3.9
The transfer gain of the amplifier with feedback is given by:
I I0 I0
Af = 0 = = … (3.7)
eS ei + e f ei + β I 0
I0
Since A= , so transfer gain with feedback is given by:
ei
Aei A
Af = = … (3.8)
ei + β Aei 1 + β A
Hence, Transfer Gain with feedback is reduced by a factor of (1 + A β) than that of
without feedback.
3.4.4 Transfer Gain for Current Shunt Feedback Topology
The current shunt feedback topology is shown in figure 3.10, where the current
gain of the amplifier is given by:
I
A= 0 … (3.10)
Ii
If
and the feedback factor is given by: β =
I0

Fig. 3.10
The current gain of the amplifier with feedback is given by:

66
I0 I0 I0
Af = = = … (3.11)
I S Ii + I f Ii + β I0
AI i 1
Af = = … (3.12)
I i + Aβ I i 1 + Aβ
So from the above discussion it is clear that for all the feedback topologies i.e.
voltage series, voltage shunt, current series and current shunt feedbacks, the transfer gain
of the feedback amplifier is reduced by a factor of (1 + A β) than that of without feedback.
3.5 EFFECT OF FEEDBACK ON INPUT RESISTANCE
It will now be discussed how the input resistance of the feedback amplifier is
affected for different feedback topologies. If the feedback signal is applied back to the
input of the amplifier in series with it (regardless of whether the feedback is obtained by
sampling the output current or voltage) it increases the input resistance. Since the
feedback voltage ef opposes eS, the input current Ii is less than it would be if ef were
absent. Hence the input resistance with feedback Rif = ei I i is greater than the input
resistance without feedback. This will be shown in the following subsections.
On the contrary if the feedback signal is applied in shunt to the input of the
amplifier (regardless of whether the feedback is obtained by sampling the output current
or voltage) it decreases the input resistance of the feedback amplifier. Since I S = I i + I f ,
then the current IS drawn from the signal source is increased over it would be if there
were no feedback current. Hence the input resistance with feedback Rif = ei I S is
decreased in this type of feedback. This will also be shown below.
3.5.1 Input Resistance for Voltage Series Feedback Topology
Consider the voltage series feedback connection as shown in figure 3.11. The input
resistance for this case may be obtained as follows:

Fig. 3.11
From the fig. 3.11 we have:
eS = ei + β e0 = Ri I i + β e0 ... (3.13)
or Ri I i = eS − β e0 … (3.14)
since e0 = Aei … (3.15)
From equations (3.14) and (3.15) we have:
Ri I i = eS − β Aei = eS − β ARi I i … (3.16)

67
or eS = Ri I i (1 + β A) … (3.17)
The input resistance with feedback will therefore be given by:
e
Rif = S = (1 + A β) Ri … (3.18)
Ii
From this equation it is clear that the input resistance of this voltage series feedback
topology increases with feedback. It is equal to input resistance without feedback
multiplied by the factor (1 + A β) .
3.5.2 Input Resistance for Current Series Feedback Topology
The calculation of input resistance for current series feedback topology is the same as
that calculated for voltage series feedback topology. For this consider the current series
feedback topology arrangement as shown in figure 3.12.

Fig. 3.12
From the fig. 3.12 we have:
eS = ei + β I 0 = Ri I i + β I 0 ... (3.19)
or Ri I i = eS − β I 0 … (3.20)
since I 0 = Aei … (3.21)
From equations (3.20) and (3.21) we have:
Ri I i = eS − β Aei = eS − β ARi I i … (3.22)
or eS = Ri I i (1 + β A) … (3.23)
The input resistance with feedback will therefore be given by:
e
Rif = S = (1 + A β) Ri … (3.18)
Ii
From this equation it is clear that the input resistance of this current series feedback
topology increases by the factor (1 + A β) times the input resistance without feedback.
3.5.3 Input Resistance for Voltage Shunt Feedback Topology
Consider the voltage shunt feedback topology shown in figure 3.13. The input
resistance for this may be calculates as:
e ei ei
Rif = i = = … (3.19)
I S I i + I f I i + β e0
But e0 = Aei

68
ei e I
So Rif = = i i
I i + A β I i (1 + A β)
Ri
or Rif = .. (3.20)
(1 + A β)
ei
where = Ri , is the input resistance without feedback.
Ri

Fig. 3.13
The input resistance of this topology is reduced by a factor (1 + A β) times the
input resistance without feedback.
3.5.4 Input Resistance for Current Shunt Feedback Topology
The input resistance for the current feedback topology can be calculated in the
similar manner as that of the voltage shunt feedback topology. For the current shunt
feedback topology consider the circuit shown in figure 3.14.

Fig. 3.14
The input resistance for this topology may be calculates as:
e ei ei
Rif = i = = … (3.21)
I S Ii + I f Ii + β I0
But I 0 = AI i
ei e I
So Rif = = i i
I i + A β I i (1 + A β)

69
Ri
or Rif = .. (3.22)
(1 + A β)
ei
where = Ri , is the input resistance without feedback.
Ii
The input resistance of the current shunt feedback amplifier is reduced by a factor
(1 + A β) times the input resistance without feedback.

2.6 EFFECT OF FEEDBACK ON OUTPUT RESISTANCE


The output resistances for the different topologies are dependent on whether
voltage or current feedback is there. For voltage feedback arrangements (i.e. voltage
series or voltage shunt feedback topology) the output resistance is decreased, while for
current feedback arrangements (i.e. current series or current shunt topology) the output
resistance is increased. We will now calculate the output resistances for voltage series
feedback and current series feedback arrangements only.

Output Resistance for Voltage Series Feedback

The voltage series feedback circuit given in figure 3.11 is reproduced here in
figure 3.15, for the calculation of output resistance. The output resistance is calculated for
this circuit by applying a voltage e to the output with eS shorted (eS = 0). The resulting
current will be I and the ratio of e and I will be the output resistance of this circuit.

Fig. 3.15
The voltage e is then
e = IR0 + Aei … (3.23)
For eS = 0 ei = − e f
So e = IR0 − Ae f
But ef = βe
Hence e = IR0 − A β e
or e + A β e = IR0 … (3.24)
The output resistance with this feedback arrangement is given by:
e R0
R0 f = = … (3.25)
I 1 + Aβ

70
This equation clearly shows that the output resistance of the voltage series
feedback is reduced from that without feedback by the factor (1 + A β) .

Output Resistance for Current Series Feedback

Figure 3.16 shows the circuit arrangement for the current series feedback which is
the reproduction of figure 3.12. For the calculation of the output resistance for this
arrangement let us apply a signal e to the output with eS with shorted out. It results the
current I at the output and the ratio of e and I gives the output resistance.

Fig. 3.16
For short circuiting the input source (eS = 0) we have:
ei = e f
e e
I= − Aei = − Ae f … (3.26)
R0 R0
But ef = β I
e
So I= − Aβ I … (3.27)
R0
or R0 I (1 + A β) = e
The output resistance of this arrangement is thus given by:
e
R0 f = = R0 (1 + A β) … (3.28)
I
From this equation it is clear that the output resistance of the current series
feedback is increase by (1 + A β) times the output resistance without feedback.
The effect of negative feedback on input and output resistance for various types of
feedback topologies is summarized in table 2.2.

71
Table 2.2

3.7 PRACTICAL FEEDBACK CIRCUITS


In this section some practical feedback amplifier circuits will be discussed that
will demonstrate the effect of feedback on various topologies. The basic introduction of
these circuits will only be discussed.
Voltage Series Feedback circuit: Figure 3.17 shows a field effect transistor stage with
voltage series feedback. A part of the output signal eo is obtained from the feedback
network consisting of resistors R1 and R2. The feedback voltage ef is connected in series
with the input signal eS. The difference of these two signals will be the input voltage ei.

Fig. 3.17
The emitter follower circuit of figure 3.18 also provides voltage series feedback.
The signal voltage eS is the input voltage ei. The output voltage eo is also the feedback
voltage in series with the input voltage.

72
Fig. 3.18

Current Series Feedback Circuit


Another feedback arrangement is current series feedback shown in figure 3.19, in
this circuit output current Io is sampled out and return in proportional voltage in series
with the input. This circuit is a single transistor amplifier stage. Since the emitter of this
amplifier has an unbypassed emitter, so the current through RE provides a feedback
voltage that opposes source signal. The output will be reduced. The current series
feedback may be removed either by shorting the emitter directly to ground or by using a
bypass capacitor in parallel with the emitter resistance RE as is usually done.

Fig 3.19

Voltage Shunt Feedback Circuit


Figure 3.20 shows the circuit diagram of voltage shunt feedback arrangement. In
this circuit a portion of the output voltage is coupled through the resistance RB in parallel
or in shunt with the input signal at the base of the transistor. This feedback stabilizes the
overall gain while decreasing both the input and output resistances.

73
Fig. 3.20

Current Shunt Feedback Circuit


Figure 3.21 shows a two-stage amplifier employing current shunt feedback. The
resistance RF and the capacitance CF provides the feedback in the circuit. This feedback
circuit develops a feedback voltage in parallel with the input voltage. The unbypassed
emitter resistor RE of the second transistor provides the current sensing.

Fig. 3.21

PROBLEMS
1. Mention the four broad categories of the amplifiers. Using the block diagram
explain the voltage amplifier.
2. What do you mean by current amplifier? Explain it using a suitable block
diagram.
3. Discuss transconductance amplifier. What is the transfer function of this
amplifier?
4. Discuss transresistance amplifier. What is the transfer function of this amplifier?

74
5. What do you understand by feedback in amplifiers? How many types feedbacks
are there? Discuss negative feedback. What are the advantages of negative
feedback?
6. Mention the names of the four feedback topologies. Find the expression of
transfer function of voltage series feedback topology.
7. Discuss voltage shunt feedback using a suitable block diagram. Find the
expression of transfer function of this feedback topology.
8. Find the expression of transfer function of the current series feedback topology.
9. What do you mean by the transfer function of a circuit? Find the expression of
transfer function of the current shunt feedback topology.
10. Show that input resistance with feedback in voltage series feedback topology is
increased by a factor (1 + A β) times than that without feedback.
11. Show that input resistance with feedback in current series feedback topology is
increased by a factor (1 + A β) times than that without feedback.
12. Show that input resistance with feedback in voltage shunt feedback topology is
decreased by a factor (1 + A β) times than that without feedback.
13. Show that input resistance with feedback in current shunt feedback topology is
decreased by a factor (1 + A β) times than that without feedback.
14. Explain how the output resistance is affected in voltage series feedback topology.
15. Explain how the output resistance is affected in current series feedback topology.
16. Draw and explain in brief a practical circuit for voltage series feedback topology.
17. Draw and explain in brief a practical circuit for current series feedback topology.
18. Draw and explain in brief a practical circuit for voltage shunt feedback topology.
19. Draw and explain in brief a practical circuit for current shunt feedback topology.

____________

75
4
Operational Amplifiers
Operational amplifiers are basically differential amplifiers available in the form of
linear integrated circuits (ICs). These ICs are low cost and widely used in instrumentation
amplifiers and other signal processing systems. The name operational amplifier was
originally adopted for a series of high performance DC amplifiers used in analog
computers. These amplifiers were used to perform mathematical operations applicable to
analog computation such as summation, scaling, subtraction, integration, and
differentiation etc. with feedback arrangement. The applications of operational amplifiers
has become so widely diversified that this original terminology is inappropriate since
Operational amplifiers are now used as a basic building block for phase shifting, filtering,
signal conditioning, multiplexing, detecting, etc. In this chapter detailed discussion on the
characteristics of operational amplifiers and differential amplifiers will be made.

4.1 THE BASIC OPERATIONAL AMPLIFIER:

The Operational Amplifier (OP AMP) has two-input terminals, one marked as ‘+’
is called as non-inverting terminal and other marked as ‘–‘ is known as inverting
terminal; and an output terminal as shown in figure 4.1. The signal applied to the
inverting terminal gives an output of inverted polarity i.e. there is 1800 phase reversal
between the input and output. Similarly the signal applied to the non-inverting terminal
gives the output of same polarity.

Fig. 4.1
If the gain of the operational amplifier is A , and e1 & e2 are the two signals
applied to the inverting and non-inverting terminals of the operational amplifier
respectively, then its output is difference to the two signals multiplied by the gain of the
operational amplifier which is given in equation 4.1. This is illustrated in figure 4.2.
e0 = A.e = A.(e2 − e1 ) … (4.1)

77
The ideal operational amplifier has the following characteristics:
1. Gain tends to infinity.
2. Input impedance tends to infinity.
3. The output impedance tends to zero.
4. The band width tends to infinity.
5. The output voltage is zero when the differential input (e2 − e1 ) is zero.
The equivalent circuit of ideal operational amplifier is shown in figure 4.3.

Fig. 4.2

Two very important concepts follow from these basic characteristics:


Since the voltage gain is infinite, any output signal developed will be the result of an
infinitesimally small input signal. Therefore:
The differential input voltage ( e ) is zero.
Also, if the input impedance is infinite:
There is no current flow into either input terminal.
These two properties are the basics for op amp circuit analysis and design.
The practical Operational amplifier has the following characteristics:
1. Gain is large not infinite, it is of the order of 10 5 to 10 6 .
2. Input impedance is large enough.
3. The output impedance is very low of the order of 10 Ω to 1 K Ω .
4. The band width is large.
5. The amplifier draws negligible currents for the sources connected to its input
terminals.
The figure 4.2 illustrates that the Operational amplifier is in open loop mode i.e.
when no feed back is applies. The voltage obtained at the output terminals can either
positive saturation voltage ( + VSat ) or negative saturation voltage ( − VSat ) depending on
e1 > e2 or e2 > e1 respectively, since the gain of the amplifier tends to infinity. The
operational amplifier is said to work as a switch or a comparator. For linear applications
of the operational amplifiers, it is to be used in closed loop mode i.e. by providing
negative feedback in the circuit.
The use of operational amplifiers in Inverting and Non-inverting mode will be
discussed with the introduction of negative feed back.

4.2 THE INVERTING AMPLIFIER:


The Operational amplifier used in inverting mode is shown in figure 4.3. Here the
input signal ei is applied to the inverting terminal of the Operational amplifier through a

78
resistance R1 . The non-inverting terminal is grounded. The output terminal of the
operational is connected to the inverting terminal through a feedback resistance R f . This
shows the voltage shunt feedback as the output is fed back in shunt with the input. This
arrangement forms a negative feed back because any increase in the output signal results
in a feedback signal to the inverting input, causing a decrease in the output signal.

Fig. 4.3
From the figure 4.3:
e0
e0 = − A.e or e=− …. (4.2)
A
where e is the differential input and A is the open loop gain of the operational
amplifier. The negative sign is inserted as the signal voltage is applied to the inverting
input.
For simplicity it is assumed that the operational amplifier is ideal and no current
flows to the input terminals of the amplifier (or e = 0 ). So the current i1 flowing through
R1 will be equal to the current i f flowing through the feedback resistance R f i.e. i1 = i f
ei
i1 = … (4.3)
R1
e
and if = − 0 … (4.4)
Rf
e0 e
Also − = 1
Rf R1
Rf
or e0 = − ei … (4.5)
R1
The voltage gain with feedback (also called closed loop gain) is given by:
e Rf
Af = 0 = − …. (4.6)
ei R1
Thus the voltage gain is given by the ratio of the feedback resistance R f and the
input resistance R1 . The negative sign indicates that the output voltage is inverted with
respect to the input voltage.
For the ideal operational amplifier the input impedance of the amplifier tends to
infinity due to which no current flows through the input terminals of the amplifier. The

79
differential input e → 0 or in other words the node P is at the ground potential. The point
P is, therefore, said to at the virtual ground or virtual earth. Due to the point P at the
virtual earth, the effective input impedance is R1 .
4.2.1 Practical Inverting Amplifier:

The voltage gain in the inverting mode will now be calculated by considering the
practical operational amplifier. For this purpose the practical operational amplifier having
finite input resistance Ri (not infinite) and finite output resistance R0 (not zero) is
considered in inverting configuration as shown in figure 4.4. The circuit can be analysed
using the Miller’s theorem. The equivalent circuit having the two miller resistances is
shown in figure 4.5. According to the Miller’s theorem, the resistance R f connected in
 Rf 
the feedback path may be replaced by two resistances; one   is connected
 1 − AV 
 R f . AV 
between the inverting terminal and the ground, and the other   is connected at
 AV −1 
the output terminals.

Fig. 4.4

Fig. 4.5
From figure 4.5, the output voltage is given by:

80
 R f AV 
 
A − 1
e0 = Ae.  
V
… (4.7)
 R f AV 
 R0 + 
 AV − 1 
e0
where AV ≅ is the voltage gain taking the loading effect of R f into account,
e
which is given by:
e0 A
AV = = … (4.8)
 
 1 + R 0 ( AV − 1) 
e
 R f . AV 

 R R0 
or AV 1 + 0 − =A
 R f R f . AV 
 R  R0
or AV 1 + 0  + =A
 R f  R f . AV
 
 A + R0 
 R f 
or AV = 
 
1 + R0 
 R 
 f 

A + R0 Y f
= … (4.9)
1 + R0 Y f
The voltage e between the input terminals may be calculated by converting the
voltage source ei into its equivalent current source as shown in figure 4.6.

Fig. 4.6
From the figure 4.6, e is given by:
 e  Rf 
e =  i . R1 R i 
 R1   1 − AV 
 e  R1 R f R i 
=  i . 
 
 R1   R f R i + R1 R i + R1 R f 

81
 ei .Y1 
=  … (4.10)
Y +Y +Y 
 1 i f 

where Y’s are the admittances (or conductances) of the resistances R’s.
1 1 1
i.e Y1 = , Yi = and Yf =
R1 Ri Rf
From equation (4.10), we have:
e  Y1 
=   … (4.11)
ei  Y1 + YI + YF 

The closed loop gain of this inverting amplifier (also called voltage shunt
feedback amplifier) is given by:
e e e e
A f = 0 = 0 . = AV . … (4.12)
ei e ei ei
From equations (4.11) and (4.2), we have:
AV Y1
Af =
Y1 + Y f (1 − AV ) + Yi
If AV → ∞ , then the gain with this feedback arrangement is given by:
 Rf 
A f ≈ −  … (4.13)
 R1 
This expression for A f is the same as given in equation (4.6) for ideal operational
amplifier.
The input resistance with feedback R if is obtained from figure 4.5 as:
Rf
R if = R1 + Ri … (4.14)
1 + AV
Since Ri and AV are generally very large for the operational amplifier,
Rf
so Ri ≅ 0
1 + AV
Therefore R if = R1 … (4.15)
Example 4.1. An operational amplifier is used in inverting configuration (with voltage
shunt feedback). If R1 = 10 KΩ , then what will be the value of feedback resistance R f to
obtain a voltage gain of -100.
 Rf 
Solution. We know A f = − 
 R1 

82
 Rf 
− 100 = − 
 10 KΩ 
So R f = 100 x10 KΩ = 1MΩ
Example 4.2. An operational amplifier, whose open loop gain is 10 5 input and output
resistances are 1MΩ and 50Ω respectively, is used in the inverting configuration (with
voltage shunt feedback) as shown in figure (4.4). If R1 = 10 KΩ and R f = 100 KΩ , then
using the exact formula calculate the closed loop gain of the amplifier.
Solution. We know the closed loop gain of the inverting amplifier is given by:
AV Y1
Af =
Y1 + Y f (1 − AV ) + Yi
A + R0Y f
where AV =
1 + R0 Y f
10 −3
10 5 + 50 x
So AV = 100
10 −3
1 + 50 x
100
10 + 0.50 x10 −3
5
=
1 + 0.50 x10 −3
≈ 10 5
10 −3
10 5
Now A f = −3 10
−3
10 10
+ (1 − 10 5 ) + 10 −6
10 100
10
= −4
10 + 10 − 10 −5 x10 5 + 10 −6
−5

10
= −4
10 + 10 −5 − 1 + 10 −6
10
=
−1
= −10
4.3 THE NON-INVERTING AMPLIFIER:
The use of operational amplifier in the non-inverting configuration is shown in
figure. The signal ei is applied to the non-inverting terminal and a fraction of the output
voltage is applied back to the inverting terminal through two resistances R f and R1 .
The feedback voltage e f at the node P is given by:

…. (4.16)
where β is called the feedback factor, which is given by:

83
…. (4.17)

Fig. 4.7

The voltage appearing across the input terminals of the operational amplifier is
the difference of the input signal and the feedback voltage i.e. the feedback voltage gets
subtracted from the input voltage. Hence this feedback is negative feedback. Further
feedback voltage is in series with the input, so this arrangement is also known as voltage
series feedback arrangement. Such an amplifier is also called as Voltage Series Feedback
Amplifier. The voltage e is given by:
…(4.18)
The open loop gain A of the amplifier is given by:
e
A= 0 … (4.19)
e
From equations (4.18) and (4.19), we have:

… (4.20)
The overall gain also called gain with feedback or closed loop gain of this
amplifier is given by:

… (4.21)
From this equation it is clear that the closed loop gain of the amplifier is less than
the open loop gain. The closed loop gain decreases with the increase of the negative
feedback (as β increases A f decreases).
Putting the value of feedback factor β from equation (4.17) in equation (4.21), we
get:
A
Af =
AR1
1+
R1 + R f

84
A( R1 + R f )
= … (4.22)
R1 + R f + AR1
Generally, open loop gain A of the operational amplifiers is very large, for the
practical operational amplifiers it is of the order of 10 5 . Therefore,
AR1 >> ( R1 + R f ) and ( R1 + R f + AR1 ) ≅ AR1
The equation (4.22) reduces to:
 Rf 
A f = 1 +  … (4.23)
 R1 

This equation clearly indicates that the gain of the voltage-series feedback
amplifier depends only on the external resistors R f and R1 , and not on the open loop gain
of the operational amplifier.

Example 4.3. An operational amplifier is used in non-inverting configuration (figure


4.7) with negative feedback (voltage series feedback). The open loop gain of the amplifier
is 10 5 . If the feedback resistances are R1 = 1KΩ and R f = 2 MΩ . Calculate the gain with
feedback.
Solution. The feedback factor is given by:

10 3
=
10 3 + 2 x10 6
1
=
2001
= 0.5 x10 −3

10 5
=
1 + 10 5 x0.5 x10 −3
10 5
=
1 + 10 5 x0.5 x10 −3
10 5
=
51
≈ 2000
4.3.1 Input Resistance of Voltage Series Feedback Amplifier:
To calculate the input resistance of non-inverting negative feedback amplifier,
consider the circuit shown in figure 4.8. In this circuit Ri is the input resistance of the
operational amplifier (without feedback). Let iin is the input current flowing through the
input terminal of the operational amplifier.

85
Fig. 4.8
Now the input resistance Rif of this feedback amplifier is given by:
e
Rif =
iin
ei
= … (4.24)
(e Ri )
Further

… (4.25)
Using the equations (4.24) and (4.25), we have
e
Rif = i
e0 A

…. (4.26)
From this equation it is clear that input resistance of the operational amplifier
with feedback is times larger than without feedback.
4.3.2 Output Resistance of Voltage Series Feedback Amplifier:
The output resistance with feedback of the non-inverting operational amplifier
can be calculated by considering the circuit shown in figure 4.9, in which output circuit
has been replaced by its equivalent circuit. Further to find the output resistance with
feedback, input source (whose source is also zero) is shorted and an external voltage e0
is applied to the output. Let i0 is the current delivered by the external voltage e0 , i0' is
the current to the output terminal of the amplifier and i f is the current flowing through
the feedback resistance.

86
Fig. 4.9
The output resistance may be given by:
e
R0 f = 0 … (4.27)
i0
Applying KCL to the output node, we have:
i0 = i0' + i f … (4.28)
The output resistance R0 of the open loop amplifier is very much smaller, such
that the current i0' >> i f , so i0 ≈ i0'
Now applying the KVL to the output loop we have:
e0 − A.e = R0 i0
e0 − A.e
or i0 = … (4.29)
R0
Also e = −e f as ei is zero.

… (4.30)
Using the equations (4.29) and (4.29), we have:

… (4.31)
From this equation it is clear that the output resistance of the voltage series

So this feedback arrangement produces a better voltage source, which can deliver
the large amount of current to the load.

Example 4.4. An operational amplifier is used in non-inverting configuration (figure


4.7) with negative feedback (voltage series feedback). The open loop gain of the amplifier

87
is 10 5 , input and output resistances are 1KΩ and 150Ω respectively. What should be the
value of feedback factor β, so that maximum power is transferred from the source to the
input of the amplifier? The source resistance of the signal is 200 KΩ . Calculate the
output resistance with feedback and also the overall power gain of the amplifier in db if
the output is connected to a load of 500Ω .

Solution. According to the maximum power transfer theorem, the maximum power will
be transferred from the signal source to the input of the feedback amplifier, if the input
resistance of the amplifier is equal to the source resistance.
i.e.

The output resistance with feedback is given by:

150
= = 0.75Ω
200
The voltage gain of the feedback amplifier is

10 5
= = 500
200
The input power is given by:
ei2
Pi =
Rif
The output power is given by:
2
e 2 ( A f ei )
P0 = 0 = provided RL >> R0 .
RL RL
P0 A 2f R if
The power gain AP = =
Pi RL
500 x500 x 200 KΩ
=
500Ω
= 10 8

The power gain in db = 10 log(10 8 )


= 80 db.
Example 4.5. The input and output resistances of an operational amplifier are 200 KΩ
and 150 Ω respectively. When negative feedback is applied in the non-inverting
configuration to increase the input resistance to 20MΩ, the gain of the amplifier reduces
to 500. Find

88
(i) the open loop gain of the operational amplifier,
(ii) the output resistance with negative feedback,
and (iii) the feedback factor.
Solution. We have
(i)

A
500 =
100
So the open loop gain is A = 5x10 4
(ii) The output resistance with negative feedback is:

150
= = 1.5Ω
100
(iii) We have

or β = 19.8 x 10-4

4.3.3 Frequency Response of Voltage Series Feedback Amplifier:


Figure (4.10) shows the variation of open loop gain with frequency of the applied
signal (log - log plot) of a typical operational amplifier. The band width of the operational
amplifier is the range of frequencies for which the gain remains constant. Now by
applying the negative feedback in the non-inverting amplifier, its effect on frequency
response is to be studied. For this it is assumed that the gain A( f ) varies with frequency
f like a simple low pass filter.

Fig. 4.10

89
Thus the gain A( f ) (gain as a function of frequency) is of the form:
A0
A( f ) = … (4.32)
 f 
1 + j 
 f0 
where A0 is the pass band gain at f → 0 or d.c. gain, and f 0 is called as the
cutoff frequency.
Now after the application of negative feedback, the gain with feedback is given
by:

Af 0
=
 
1 + j f 
 ff0 
 

From this equation it is clear that the bandwidth of the non-inverting amplifier
with feedback (voltage series feedback) increases with the increase of feedback i.e. it
increases by a factor of times the bandwidth of the open loop amplifier.
However, the gain of the feedback amplifier decreases by the same amount. The gain
bandwidth product remains to be constant. The gain bandwidth product is the product of
the gain and the cutoff frequency.
Example 4.6. An operational amplifier has an open loop gain of 104 and the time
constant associated with –3 db point is 20 msec. After application of negative feedback in
the non-inverting configuration –3 db point shifts to 10 KHz. Calculate the low frequency
gain of the amplifier.
Solution. The time constant associated with –3 db point is 20 msec.
The frequency at this point (also called cutoff frequency) is:

90
1000
f0 = = 50 Hz
20
After application of the negative feedback the cutoff frequency becomes 10 KHz.
So

Further
10 4
= = 50
200
This is the low frequency gain of the feedback amplifier.
4.3.4 Stability in Voltage Series Feedback Amplifier:
It has been observed that the open loop gain of the operational amplifier varies
due to temperature variations as the semiconductor devices are very much temperature
dependent. It means the gain of the amplifier is not perfectly stable. Now we have to
study the effect of negative feedback in the non-inverting configuration (voltage series
feedback arrangement) on the gain of the operational amplifier.
The gain of the voltage series feedback amplifier is given by:

… (4.34)
Differentiating this equation with respect to open loop gain A , we get:

… (4.35)

….(4.36)
dA f dA
The factor is the fractional change in gain with feedback and is the
Af A
fractional change in gain without feedback. From this equation it is clear that the
variation of gain with feedback is times smaller than this variation without
feedback. It means the stability of the operational amplifier with negative feedback is
times larger than without feedback.

Example 4.7. An operational amplifier has an open loop gain of 104 and its output
resistance is 1KΩ. Due to manufacturing tolerances and supply voltage variations etc.
the gain of the amplifier varies by 30%. If negative feedback in the non-inverting
configuration is used to reduce the gain variation by 2% , what should be value of
feedback factor β, the corresponding closed loop gain and output resistance of the
operational amplifier.

91
Solution. We have

dA f dA
= 2% (required) and = 30%
Af A
So
or
To find the feedback β, we take the minimum value of open loop gain; since
dA f
higher values than this, will be within the given limit of 2%.
Af
30
Thus Amin = 10 4 − x10 4
100
= 10 − 3000
4

= 7000

So
Now the closed loop gain will be:

= 666.7
Output resistance with feedback is

1000
= = 66.7Ω
15
4.3.5 Distortion in Voltage Series Feedback Amplifier:
It is well known that the distortion arises in an amplifier because of the non-
linear characteristics of the active devices. The linear input-output relation relationship is
obtained only in the small signal conditions. The non-linearity arises in the large signal
due to the shifting of the operating point in the characteristics of the active devices. It will
be shown that the negative feedback reduces the distortion thus improving the linearity of
the input-output relationship of the amplifier.
The output of an amplifier can be shown of having the harmonic present as :
e0 = Ae + e0 d … (4.37)
where e0 d is the distortion term i.e. the net rms voltage of the harmonic generated
and e is the differential voltage at the terminals of the operational amplifier and it is
equal to input voltage ei for the open loop circuit. By the introduction of negative
feedback e becomes:
… (4.38)
From equations (4.37) and (4.38), we have:

92
or

The term e0 df is the distortion term with feedback, which is equal to:

… (4.39)
It indicates that the harmonic distortion is reduced by a factor of in the
presence of negative feedback in the non-inverting operational amplifier (voltage series
feedback amplifier).
4.4 DIFFERENCE AMPLIFIER:
The difference amplifier is one which gives the output proportional to the difference of
the two input signals. Such amplifiers are used in signal processing circuits. The
differential amplifier is shown in figure 4.11. It will now be analysed that the output is
proportional to the difference of the two input signals e1 and e2 applied to the inverting
and non-inverting inputs respectively of an operational amplifier as illustrated in figure
4.11.

Fig. 4.11
From this figure, the voltage V2 available at the non-inverting terminal of the
operational amplifier is given by:
e2 .R2
V2 = … (4.40)
( R1 + R2 )
The voltage at the inverting terminal of the amplifier can be obtained by applying
superposition theorem as:
e1 .R2 e0 .R1
V1 = + … (4.41)
( R1 + R2 ) ( R1 + R2 )
In the equations (4.40) and (4.41), it was considered that no current flows to the
input terminals of the amplifier, as the operational amplifier is ideal. Further for ideal

93
operational amplifier, the potential difference between the two input terminals must be
zero as A → ∞ .
i.e. e=0
So V2 = V1 … (4.42)
Using the equations (4.41) and (4.42), we have:
e2 .R2 e1 .R2 e0 .R1
= +
( R1 + R2 ) ( R1 + R2 ) ( R1 + R2 )
or e0 R1 = (e2 − e1 ) R2
R2
or e0 = (e2 − e1 ) … (4.43)
R1
This equation indicates that the output is proportional to the difference of the two
R
input signals and the gain of the difference amplifier is 2 .
R1
The disadvantage of this difference amplifier is that the input resistances at the
two inputs of the operational amplifier are not equal. The input resistance for e1 is R1 , as
the input is connected to the inverting input of the operational amplifier. However the
input resistance for e2 is very high as it is connected to the non-inverting input of the
operational amplifier. So the source resistances of comparable magnitude will have the
effect of unbalancing the gain for the two inputs.
Such problem may be avoided if we use a circuit shown in figure 4.12. In which
two operational amplifiers are used, the amplifier 1 is used as unity gain buffer amplifier.
This amplifier gives an output of unity gain i.e. the output of this amplifier is almost
equal to e1 but will have very low source resistance. This output may be connected to the
inverting input of the second operational amplifier through a resistance R1 as shown in
figure 4.12.

Fig. 4.12
The output voltage of this circuit is given by:
R
e0 = 2 (e2 − e1 ) …. (4.44)
R1
which is the same as obtained in equation (4.43).

94
A more versatile and high performance difference amplifier is illustrated in figure
(4.13), in which three operational amplifiers are used. It is most commonly used
differential amplifier. It is useful with high impedance sources such as high impedance
bridges, EEG probes etc. This amplifier is also called as the instrumentation amplifier.
In this circuit the two signals are connected to the non-inverting terminals of the
two operational amplifiers. Thus both the operational amplifiers offer very high input
resistances to the two inputs. The outputs of these two amplifiers are connected as the
two inputs of a difference amplifier.
The output voltage e01 of operational amplifier 1 is obtained by applying
superposition theorem. According to this theorem e01 is the algebraic sum of voltages
when e1 = 0 and e2 is assumed to be present secondly e2 = 0 and e1 is present.

Fig. 4.13

So in the first case ( e1 = 0 ) the node Y is at the virtual earth and the output of the
 R 
operational 1 will be e2 1 + 1  as it will work in the non-inverting mode. In the second
 R3 
R 
case ( e2 = 0 ), the output voltage will be equal to − e1  1  as operational amplifier 1
 R3 
will work in inverting mode and e1 gets applied to the inverting terminal of this
operational amplifier. The output voltage e01 will be algebraic sum of these two voltages
given by:
 R  R 
e01 = e2 1 + 1  − e1  1  … (4.45)
 R3   R3 

95
Similarly one can find the output voltage e02 by applying the superposition
theorem to the second operational amplifier as given below:
 R  R 
e02 = e1 1 + 2  − e2  2  … (4.46)
 R3   R3 
The final output e0 (output of the third operational amplifier) is proportional to
the difference of the outputs e01 and e02 given by:
Rf
e0 = (e02 − e01 ) … (4.47)
R4
Putting the values of e01 and e02 from equations (4.45) and (4.46) in equation
(4.47) we get:
R f   R2  R   R   R 
= e1 1 +  − e2  2  − e2 1 + 1  + e1  1 
R4   R3   R3   R3   R3 
Rf   R1 R2   R R 
= e1 1 + +  − e2 1 + 1 + 2 
R4   R3 R3   R3 R3 
 R f  R R 
=  1 + 1 + 2 (e1 − e2 ) … (4.48)
 R4  R3 R3 
Thus the output is proportional to the difference of the two input signals.
4.5 COMMON MODE REJECTION RATIO:
In equation (4.43) it has been shown that the output of difference amplifier is
proportional to the difference of the two input signals. If e1 = e2 then output e0 = 0 , i.e.
the output is zero when both the inputs are same or common. It is true if the operational
amplifier is ideal, however for the practical operational amplifier the output will be some
small voltage when the inputs are in common mode. If the two inputs are
(say) e1 = 150 µV and e2 = 100 µV, then output will be different if the two inputs are
e1 = 1050 µV and e2 = 1000 µV. In both these cases the difference of the two signals ed
is same as 50 µV but the output is different. The output voltage depends not only upon
the difference signal (ed = e1 − e2 ) at the input terminals of the operational amplifier, but
is also affected by the common mode voltage. The common mode voltage eC is defined
as the average voltage of the two input signals.
e + e2
i.e. eC = 1 … (4.49)
2
Let the output voltage e0 linearly depends on the input voltages e1 and e2 . The
output voltage is given by:
e0 = a1e1 + a 2 e2 … (4.50)
where a1 and a 2 are constants and represents the gains of the two input signals.
The input voltages e1 and e2 may also be written in the following forms:
e +e  e −e 
e1 =  1 2  +  1 2  … (4.51)
 2   2 

96
 e + e2   e1 − e2 
e2 =  1 −  … (4.52)
 2   2 
Putting the values of e1 and e2 from equations (4.51) and (4.52) in equation
(4.53), we get
 e + e2 e1 − e2  e + e e −e 
e0 = a1  1 +  + a2  1 2 − 1 2 
 2 2   2 2 
 e + e2  a1 − a 2
= (a1 + a 2 )  1  + ( 2 )[e1 − e2 ] … (4.53)
 2 
e1 + e2
The first term of this equation is the common mode gain and the second
2
term (e1 − e2 ) is the differential input. The output voltage e0 can thus be written as:
e0 = AC .eC + Ad .ed … (4.54)
where
AC = a1 + a 2 is called the common mode gain,
a1 − a 2
and Ad = is called the differential gain.
2

The ratio ( Ad AC ) is called as the common mode rejection ratio (CMRR)


denoted by ρ , which tells us how good a differential amplifier is. It is figure of merit for
the differential amplifier. The larger the common mode rejection ration better is the
amplifier. The amplifier will completely reject the common mode inputs, if AC → 0 and
the amplifier will give the sufficient output if the differential gain Ad is finite and large.
So the common mode rejection ratio is given by:

… (4.55)
The CMRR is generally expressed in decibels (db).

Example 4.8. The differential mode gain of an operational amplifier is 2000 and
common mode rejection ratio is 1000. Calculate the output voltage if inputs in two
terminal are 2 mV and 1.9 mV. Calculate the percentage error if operational amplifier is
ideal.
e +e 2 + 1.9
Solution. We have eC = 1 2 = mV
2 2
= 1.95mV
and ed = e1 − e2 = (2 − 1.9)mV
= 0.1mV
Further e0 = AC .eC + Ad .ed
AC .eC
or = Ad .ed (1 + )
Ad .ed

97
1.95
= 2000 x0.1(1 + )mV
0.1x1000
= 200(1 + 0.0195)mV
= 203.9mV
For ideal operational amplifier, ρ → ∞
so e0 = Ad .ed
= 2000 x 0.1mV
= 200mV
3.9 x100
Percentage error =
200
= 1.95%

Example 4.9. For an operational amplifier the differential mode gain is 10 5 and
common mode rejection ratio is 100 db. Find the common mode gain of the operational
amplifier.
A
Solution. Common mode rejection ratio ρ= d
AC
ρ = 100 db
or
ρ = 10 5
10 5
AC = 5 = 1
10
So the common mode gain is unity.

4.6 EMITTER COUPLED DIFFERENTIAL AMPLIFIER:


Operational amplifiers are available in the form of integrated circuits. The
internal circuit of the operational amplifier has three stages. The first stage of commercial
integrated circuit operational amplifier has the emitter coupled differential amplifier. The
purpose to of this amplifier is to provide high common mode rejection ratio (CMRR) so
that it can have high gain to the difference mode signal and cancel common mode signals.

98
Fig. 4.14
Figure (4.14) shows the circuit diagram of an emitter coupled differential amplifier. This
circuit contains two identical transistors whose emitters are coupled. It is further assumed
that the circuit is symmetrical. The symmetrical circuit means the transistors are identical
having identical parameters also the collector resistors are identical. If eS1 = eS 2 = eS then
differential gain ed will be zero and the output voltage will be equal to e0 = AC .e S .
However, if RE → ∞ , then I E1 = I E 2 = 0 because of the symmetry of the circuit. The
collector currents of each transistor will be equal to their respective emitter current. The
output voltage e0 will be zero as e01 = e02 . This will prove to be an ideal differential
amplifier.
This circuit will now be analysed using the finite value of RE . The common
mode gain will be evaluated by setting eS 1 = eS 2 = eS . The voltage eS will be common
mode voltage. This circuit can be bisected as shown in figure 4.15(a), in which the
resistance RE is replaced by a resistance of value 2 RE . Two such circuits having emitter
resistance of value 2 RE , when connected in parallel gives rise a emitter resistance of
value RE as given in the original circuit shown in figure 4.14.
Let AI is the current gain of the circuit of figure 4.15(a), then this circuit may
replaced by its equivalent circuit as given in figure 4.15(b) using the dual of the Miller’s
theorem.

99
(a) (b)
Fig. 4.15
The expression of current gain in terms h-parameters of the transistor T1 is given
by:

… (4.56)
'
where R is the effective load resistance given by:
L

Putting the value of RL' in equation (4.56), the current gain is given by:

or AI + h0 e RC AI + 2 R E h0 e AI − 2 RE h0e = −h fe
or AI (1 + h0e RC + 2 RE h0e ) = 2 RE h0e − h fe
2 RE h0e − h fe
or AI = … (4.57)
1 + h0 e ( RC + 2 R E )
For the circuit of figure 4.15(a), the input resistance is given by:
RI = hie + hre AI RL + 2(1 − AI ) RE … (4.58)
RL = 2 RE + RC … (4.59)
Using the equations (4.58) and (4.59), we have:
RI = hie + hre AI (2 RE + RC ) + 2(1 − AI ) RE … (4.60)
The voltage gain (also called the common mode gain) of this circuit is given by:

100
AI RC
AV = AC = … (4.61)
RS + R I
Putting the values of AI and RI from equations (4.57) and (4.60) respectively to
equation (4.61), the common mode gain is obtained as:
 2 RE h0e − h fe 
RC  
 1 + h ( R + 2 R ) 
AC =
0 e C E

 2h0e RE − h fe   2h0e R E − h fe 
RS + hie + hre ( RC + 2 R E ).  + 2 R E − 2 R E  
 1 + h0 e ( R C + 2 R E )   1 + h0 e ( RC + 2 R E ) 
 2 R E h0 e − h fe 
RC  
 1 + h0e ( RC + 2 R E ) 
AC =
 2h0 e R E − h fe 
RS + hie + 2 R E +  (hre ( RC + 2 RE ) − 2 R E )
 1 + h0e ( RC + 2 RE ) 
If hre ( RC + 2 RE ) << 2 RE and h0e RC << 1 then
(2 RE h0e − h fe ) RC
AC =
( RS + hie + RE )(1 + 2 RE h0e ) + (2 R E h0 e − h fe ).( −2 R E )
(2 R E h0 e − h fe ) RC
or AC = … (4.62)
( RS + hie )(1 + 2 R E h0 e ) + 2 RE (1 + h fe )
Further if h fe >> 2 R E h0 e and 2 RE h0 E << 1 , then the common mode voltage gain may be
approximated as:
(−h fe ) RC
AC = … (4.63)
( RS + hie ) + 2 RE (1 + h fe )
The difference mode gain Ad can be obtained by setting eS 1 = −eS 2 = (eS 2) .
From the symmetry of figure 4.14, if eS 1 = −e S 2 , then I E1 = − I E 2 so that the current
flowing through the resistance R E is zero. The voltage drop across this resistance will be
zero and thus the emitters of these transistors will be grounded for small signal condition.
Under these conditions the circuit of figure 4.146 can be used to obtain the differential
gain Ad .

Fig. 4.16

101
The current gain of this circuit is given by:

… (4.64)
and the input resistance is given by:
RI = hie + hre AI RC … (4.65)
The expression for differential mode gain Ad is given by:
e0
Ad =
eS
e0 AI RC
and AV = = −2 Ad = … (4.66)
( e S 2) RI + RS
 − h fe 
RC  
 1 + h R
0e C 
or − 2 Ad =
 re RC h fe
h 
RS + hie −  
 1 + h0e RC 
If ( R S + hie ) >> hre h fe RC then

− h fe RC
− 2 Ad =
( RS + hie )(1 + h0e RC )
If h0 e RC << 1 then the expression for the differential mode gain Ad is finally
given by:
− h fe RC
Ad = … (4.67)
2.( RS + hie )
In order to reject the common mode signal, the common mode rejection ratio
should be large enough for which the common mode gain AC should be as small as
possible. From the equation (4.63) it is clear that to have a smaller value of AC , the
resistance R E should be infinitely large as other terms of this equation are constants. This
leads to ideal assumptions. However, for practical purposes if RE is kept large enough,
the emitter supply voltage VEE has to be increased so that the proper quiescent current is
maintained. If the operating currents of the transistors are allowed to decrease, this will
lead to higher hie values and lower values of h fe . The common mode rejection ratio will
tend to decrease because of both these effects.
4.6.1 Emitter Coupled Differential Amplifier Using Constant Current Bias:
The problem that we had in case of emitter coupled differential amplifier that the
larger value of emitter coupled resistance RE will, however, provide the smaller value of

102
common mode gain AC , this in turn forces to increase the emitter supply voltage VEE to

Fig. 4.17
maintain the proper quiescent current, can be solved by using a constant current source in
place of emitter coupled resistance RE . Figure 4.17 shows the circuit diagram of
differential amplifier in which the emitter coupled resistance RE is replaced by a constant
current source comprising a transistor T3 , diode D and resistances R1, R2 and R3. This
modified circuit presents a very high effective emitter resistance for the two emitter
coupled transistors T1 and T2. This effective resistance is of the order of hundreds of kilo-
ohm even if R3 is as small as 1 KΩ.
It can be verified that the current I Q is constant and independent of signal
voltages eS1 and eS 2 .
By applying KVL to the base circuit of transistor T3, we have:
R2
VBE 3 + R3 I 3 = V D + (VEE − VD ) … (4.68)
R1 + R2
where VBE 3 is the voltage drop across the base emitter voltage of transistor T3 and
the voltage VD is the voltage drop across the diode D.

If the base current of transistor T3 is negligibly small than its emitter current is
approximately equal to the collector current which is given by:
 R2 R1  1
I Q ≈ I 3 = VEE + VD − VBE 3  …(4.69)
 R2 + R3 R1 + R2  R3
If the circuit parameters are chosen such that

103
R1
VD = VBE 3
R1 + R2
 R2  1
then I Q = VEE  … (4.70)
 R2 + R3  R3

From equation (4.70), it is clear that the transistor T3 acts as a constant current
source for the transistors T1 and T2 of the differential amplifier, as the current I Q is
constant and independent of signal voltages eS 1 and eS 2 .

The diode D connected in the base circuit of transistor T3 also make the current
I Q independent of temperature. In the absence of his diode D, the current I Q varies with
temperature because of the base emitter voltage VBE 3 of transistor T3 decreases
approximately at the rate 2.5 mA/ 0C. When the diode D is connected in the circuit the
voltage drop VD across the diode D, is approximately equal to the base emitter voltage of
the transistor T3, and also both will have same temperature variation. The two variations
cancel each other leaving the current I Q almost independent of temperature. The terms
R1
VD and VBE 3 of equation (4.69) will not precisely cancel the temperature
R1 + R2
variation. So in place of single diode two diodes in series are generally connected which
will almost satisfy the equation (4.69).

It can be demonstrated that the common mode gain is zero, if it is assumed that
the two transistors T1 and T2 identical and the transistor T3 supplies the true constant
current. Assume that eS 1 = eS 2 = eS , so that from the symmetry of the circuit, the
collector current I C1 = I C 2 . However, since the total current increase is I C1 + I C 2 = 0 if
e02 I R
I Q is constant, then I C1 = I C 2 = 0 and common mode gain AC = = − C2 C = 0 .
eS eS
4.6.2 Use of Current Mirror as Constant Current Source:
The constant current source discussed in the preceding section makes use of a
transistor in the active region, which provides the constant collector current. An improved
circuit for providing a constant current source is shown in figure 4.18. This circuit
contains two identical transistors whose transfer characteristics (VBE versus IC) are same
i.e. the same VBE for the two transistors should produce same collector current.

104
Fig. 4.18

From the figure (4.18), the base emitter voltage of transistor T1 is equal to base
emitter voltage of transistor T2, since both the transistors are connected in parallel.
i.e. VBE1 = V BE 2
It follows that I C1 ≅ I C 2 … (4.71)
Further collector emitter voltage VCE1 of transistor T1 is equal to its base emitter
voltage VBE1 , since the collector of the transistor T1 is connected to its base i.e.
VCE1 = V BE1 .
Applying KVL to the collector circuit of transistor T1, it is found that:
RI + VBE1 − VEE = 0
V − V BE1
or I = EE
R
Now applying KCL to the collector of transistor T1, we have:
I = I C 1 + I b1 + I b 2 … (4.72)

Let the two transistors have high β so that I b1 and I b 2 are small relative to I C 1 ,
then it leads to I ≅ I C1 … (4.73)
From equations (4.71) to (4.73), we have:
VEE − VBE1
I C1 ≅ I = ≅ IC2 … (4.74)
R
Using this equation (4.74), an appropriate value of resistance R may be chosen to
have a desired value of the collector current. This circuit is also called a current mirror
circuit because the output current is the mirror image of the input current.

105
4.7 IC 741 OPERATIONAL AMPLIFIER:
The pin configuration and complete schematic circuit diagram of most commonly
used operational amplifier (OP-AMP) 741 are shown in figures 4.19 and 4.20
respectively. Dual-in-line package (DIP) OP-AMP 741 is an eight pin IC. Pin 1 and pin 5
are offset null, which are used to eliminate the effect of offset voltage at the output. For
this external 10 KΩ potentiometer is connected between these two points and the middle
terminal of the potentiometer is to be connected to the terminal (pin 4). The detail of
the offset voltage will be discussed in the next chapter. Pin 2 and pin 3 are the inverting
and non-inverting terminals of OP-AMP respectively. The output terminal is pin 6. To
pin 4 and pin 7, and supplies are to be connected respectively. Pin 8 is not
connected terminal.

Fig. 4.19

The schematic diagram of this IC is quite complex, so only simplified qualitative


discussion is being made. The resistance values given in the circuit are in Ω. This circuit
is broadly classified in to three stages. The first stage is the input stage. It consists of
transistors it consists of transistors T1, T2, T3, T4 and associated biasing circuit. These
transistors form a differential amplifier. Transistors T1-T3 and T2-T4 are in CE-CB
configuration, which provide high gain per stage needed to achieve the adequate open
loop gain in the amplifier. Transistors T5-T6 also forms a differential amplifier for offset
null. The offset pins are provided to OP-AMP which are used eliminate the offset voltage
with the help of external circuit. The current mirror circuits are used to provide the bias
currents to the input stage. The output of the first stage taken at the junction of transistors
T4 and T6 is connected to second stage which is an intermediated current booster stage.
This stage consists of an emitter follower (T16), which drives the common emitter
amplifier (T17) followed by another emitter follower (T21). The high input resistance of
T16 helps prevent loading the output of the input stage. The transistor T21 in emitter
follower configuration provides a buffer between the intermediate and third stage, the
output stage. The output stage is the complementary symmetry power amplifier stage. It
consists of an n-p-n transistor T14 and a p-n-p transistor T20. A 30 pf capacitor connected
between the collectors of transistors T6 and T17 provides frequency compensation to the
amplifier. The bandwidth of the amplifier is thus controlled and the undesired oscillations
are prevented at the output when the operational amplifier is used in negative feedback.

106
107
Table 4.1 illustrates the specification of some commonly used operational
amplifiers for comparison purposes.

Table 4.1

(i) 741 (ii) 725 (iii) LM 108


Parameters Conditions Min Typ. Max. Min Typ. Max. Min Typ. Max. Units

Input offset RS<10 KΩ 1.0 5.0 0.5 0.3 0.5 mV


voltage

Input offset 20 200 5.0 0.05 0.2 nA


Current

Input Bias 80 500 75 0.8 2.0 nA


Current

Input 0.3 2.0 1.5 30 70 MΩ


Resistance

Large signal (i)& (ii) 5x10 4 2x10 5 10 6 3x10 6 8x10 4 3x10 5


voltage gain RL>2 KΩ
e0=eS=10V
(iii) RL>10
KΩ

CMRR RS<10KΩ 70 90 150 120 130 96 110 db

Power supply
rejection ratio RS<10KΩ 30 150 2.0 5.0 30 150 µv/v

Average input (i)& (ii)


offset voltage RS=50Ω 20 130 0.6 1.0 1.0 5.0 µv/0c
drift (iii) with
external
trimming
Average input
offset current 0.5 130 90 2.0 10 pA/
0
drift c

108
Example 4.10. Figure (4.21) shows the circuit diagram of differential amplifier using
an ideal operational amplifier.
(i) Show that the output voltage is given by:
 R '  R + R R1  ed  R '  R + R ' R1 
'
e0 = eC  − 1 − .  +  − 1 + . 
 R  R '
R1 + R2  2  R  R '
R1 + R2 
(ii) Show that the common mode rejection ratio of the amplifier is given by:

 R '  R ' R1
also (iii) Show that the output voltage is e0 = ed  −  if = .
 R R R2

Fig. 4.21
Solution. (i) Applying the superposition theorem, we have:
 R'   R' 
e0 = − .e1 + V2 1 + 
R  R
 R'   e .R  R + R ' 
= − .e1 +  2 1   … (4.75)
R  R1 + R2  R 
R1
Since V2 = e2
R1 + R2
e e
It may be written e1 = (eC + d ) and e2 = (eC − d ) … (4.76)
2 2
e1 + e2
as ed = e1 − e2 and eC =
2
From equations (4.75) and (4.76), it is obtained:
 R'  e  .R1  R + R '  e
e0 = − .(eC + d ) +   (eC − d )
R 2  R1 + R2  R  2

 R' R + R' .R1  ed  R' R + R' .R1 


= eC  − + .  +  − − . 
 R R R1 + R2  2  R R R1 + R2 

109
 R'  R + R  ed  R '  R + R ' R1 
'
R1
= eC  − 1 − .  +  − 1 + . 
 R  R '
R1 + R2  2  R  R '
R1 + R2 
… (4.77)
Equation (4.77) shows the required result.
(ii) From this equation we have the common mode voltage gain and differential mode
gain as:
1  R '  R + R ' R1 
Ad = −  1 + . 
2  R  R '
R1 + R2 
 R '  R + R ' R1 
AC = − 1 − . 
R
  R '
R1 + R 2 

Hence the common mode rejection ratio is given by:

… (4.78)
This is the required result.
R ' R1
(iii) If =
R R2
R' R
1+ =1+ 1
R R2
R + R ' R1 + R2
or =
R' R1
Putting this value in equation (4.7), we have:
 R' 
e0 = ed  − 
 R
as the common voltage gain becomes zero.
Example 4.11. In the circuit of figure (4.22), if the input resistance of the operational
amplifier is infinity, then show that the output admittance is given by:
1  R1  1
Y0 f = 1 − A. +
R0  
R1 + R f  R1 + R f

Fig. 4.22

110
Solution.

Fig. 4.23
To find the output admittance, a voltage source, say eS , is connected at the output
and input is short circuited as shown in figure 4.23. The output admittance is given by:
I
Y0 f = … (4.79)
eS
The input resistance of the operational amplifier is infinite.
Further I = I0 + I f
eS
eS = ( R f + R1 ).I f or If =
R f + R1
eS = R0 I 0 + A.e and e = R1 .I f
eS = R0 I 0 + A.R1 I f
A.R1eS
or e S = R0 I 0 +
( R1 + R f )
 A.R1 
or e S 1 − = R0 I 0
 (R + R ) 
 1 f 
e  A.R1 
or I 0 = S 1 − … (4.80)
R0  ( R1 + R f ) 
From equations (4.79) and (4.80), we have
e  A.R1  eS
I = S 1 − +
R0  ( R1 + R f )  R1 + R f
I 1  R1  1
or Y0 f = = 1 − A. +
eS R0   
R1 + R f  R1 + R f
Proved.

Example 4.12. It is desired to design a current source with a current of 1.0 mA using
current mirror circuit (ref. figure 4.18). Assume the silicon transistors have very high
current gain β. Find the value of resistance R. ( VEE = 30volts. ).
Solution. For silicon transistor VBE1 = 0.7 volt

111
V EE − V BE1
So I=
R
V − VBE1
R = EE
I
30 − 0.7
= = 29.3KΩ
1mA
Example 4.13. For the amplifier shown in figure 4.24, e1 and e2 represent undesirable
voltages. Show that, if Ri = ∞ , R0 = 0 and A1 < 0 and A2 < 0 ,
 R1 
(
e0 = A2 A1 (e ' − e1 ) − e2 ) where e ' = e0 
R +R
.

 1 f 
A1 A2 R1
Also show that, if >> 1 ,
( R1 + R f )
 R f  e 
e0 = −1 +  e1 + 2  .
 R1  A1 

Fig. 4.24
Solution. (i) Referring to figure 4.24, we have
e01 = (e ' − e1 ). A1 … (4.81)
and e0 = (e01 − e2 ). A2 … (4.82)
Put the value of e01 from equation (4.81) to equation (4.82), we get:
(
e0 = A2 A1 (e ' − e1 ) − e2 ) … (4.83)
The value of e ' is given by:
 R1 
e ' = e0   … (4.84)
R +R 
 1 f 
(ii) Equation (4.82) may be rewritten as:
e0 = A1 A2 (e ' − e1 ) − e2 A2 … (4.85)
'
Put the value of e from equation (4.84) in equation (4.85), we get:

112
AAR 
= e0  1 2 1  − A1 A2 e1 − e2 A2
R +R 
 1 f 

 AAR 
or e0 1 − 1 2 1  = − A2 ( A1e1 + e2 )
 R +R 
 1 f 

 AAR   e 
or e0 1 − 1 2 1  = − A1 A2  e1 + 2 
 R +R  A1 
 1 f  
A1 A2 R1
if >> 1
( R1 + R f )
AAR   e 
then − e0  1 2 1  = − A1 A2  e1 + 2 
R +R  A1 
 1 f  
 R f  e 
or e0 = −1 +  e1 + 2 
 R1  A1 

PROBLEMS

1. What is an operational amplifier? Describe the characteristics of an ideal operational


amplifier. How does the practical operational amplifier differ from an ideal
operational amplifier?
2. How an operational amplifier is used in inverting configuration. Find the expression
for voltage gain of an ideal operational amplifier used in inverting configuration with
negative feedback (voltage shunt feedback). What do you understand by the term
virtual ground.
3. What do you understand by feedback? How can an operational amplifier be used in
voltage shunt feedback arrangement? Deduce an expression for voltage gain of such
an arrangement. Assume that the operational amplifier has infinite open loop gain.
4. Deduce an expression for voltage gain of a practical inverting amplifier. The
operational amplifier has finite input and output resistances and finite open loop gain.
What will be the input resistance of such an amplifier?
5. Show that the expression for voltage gain of a practical operational amplifier used in
voltage shunt feedback arrangement is:
AV Y1
Af =
Y1 + Y f (1 − AV ) + Yi
The symbols have their usual meaning.
6. How an operational amplifier is used in non-inverting configuration. Find the
expression for voltage gain of an operational amplifier used in non-inverting
configuration with negative feedback (voltage series feedback).
7. What is the effect of negative feedback in non-inverting amplifier on the input
resistance of the operational amplifier?
8. What is the effect of negative feedback in non-inverting amplifier on the output
resistance of the operational amplifier?

113
9. Consider the circuit shown in figure (4.25). Deduce the expression for voltage gain of
such an amplifier.

Fig. 4.25

10. If the open loop gain of the operational amplifier is very large, show that the closed
loop gain of voltage series feedback amplifier depends only on the external
components and not on the parameters of operational amplifier.
11. Discuss the effect of negative feedback in non-inverting amplifier on the stability of
the operational amplifier. Show that the stability increases by a factor of
times on the application of negative feedback in non-inverting amplifier.
12. What is the effect of negative feedback in non-inverting amplifier on the frequency
response of the operational amplifier?
13. Discuss the effect of negative feedback in non-inverting amplifier on distortion.
14. Derive an expression for input resistance of a voltage series feedback amplifier.
15. Derive the expressions for output resistance and voltage gain of a voltage series
feedback amplifier.
16. Discuss the stability of a voltage series feedback amplifier.
17. List and explain the function of all the basic building blocks of an operational
amplifier.
18. Show that the input resistance for the non-inverting amplifier of figure (4.8) is given
by:
 R1 
Rif = Ri 1 + .A 
 R +R 
 1 f 
(Hint: First derive the expression Rif = Ri (1 + A β) and then put the value of β in this
equation.)
19. Derive the expression for the output voltage of an ordinary differential amplifier
(having only one operational amplifier). Mention its draw backs.
20. Derive the expression for the output voltage of the following circuit (fig. 4.26) and
show that it is proportional to the difference of the two input signal.

114
Fig. 4.26
21. Draw the circuit of an instrumentation amplifier using three operational amplifiers.
Find the expression for the output voltage of this amplifier. What are its advantages
over the ordinary differential amplifier?
22. What is meant by ideal differential amplifier? Define the terms differential mode
gain, common mode gain and common mode rejection ratio of a differential
amplifier. Show that the common mode rejection ratio is figure of merit of the
differential amplifier.
23. Draw the circuit diagram of an emitter coupled differential amplifier. Find the
expression of common mode gain and differential mode gain of this amplifier.
24. Draw the circuit diagram of an emitter coupled differential amplifier using constant
current Bias. Show that the common mode gain is zero, if it is assumed that the two
transistors are identical and the transistor of constant current bias supplies the true
constant current.
25. What is current mirror circuit? Discuss the use of current mirror as constant current
source
26. An operational amplifier is used in inverting configuration (with voltage shunt
feedback). If R1 = 20 KΩ , then what will be the value of voltage gain of this amplifier
if the feedback resistance R f = 2MΩ . (Ans: –1000)
27. An operational amplifier, whose open loop gain is 10 4 input and output resistances
are 100 KΩ and 100Ω respectively, is used in the inverting configuration (with
voltage shunt feedback) as shown in figure (4.4). If R1 = 15 KΩ and R f = 150 KΩ ,
then using the exact formula calculate the closed loop gain of the amplifier.
(Ans.: –9.9934)
28. An operational amplifier is used in non-inverting configuration (figure 4.7) with
negative feedback (voltage series feedback). The open loop gain of the amplifier
is 10 4 . If the feedback resistances are R1 = 10 KΩ and R f = 1MΩ . Calculate the gain
with feedback. (Ans.: 100)
29. An operational amplifier is used in non-inverting configuration (figure 4.7) with
negative feedback (voltage series feedback). The open loop gain of the amplifier
is 10 4 , input and output resistances are 1KΩ and 100Ω respectively. What should be
the value of feedback factor β, so that maximum power is transferred from the source
to the input of the amplifier? (Ans.: 0.0099)

115
30. An operational amplifier having open loop gain 10 4 is used in non-inverting
configuration (figure 4.7). The output resistance of the operational amplifier is 100Ω,
calculate the value of feedback factor to transfer maximum power from the output of
the amplifier to the load resistance of 50Ω. Find also the closed loop gain.
(Ans.: β = 10- 4, A f = 5000)
31. An operational amplifier having the following data is used in non-inverting
configuration (ref. figure 4.7).
A = 10 4 R1 = 10 KΩ R f = 1MΩ
Ri = 1MΩ R0 = 100Ω
and Unity gain bandwidth = 1MHz. Calculate the close loop parameters A f , Rif ,
R0 f and f 0 f .
(Ans. A f = 100 , Rif = 100MΩ , R0 f = 1Ω and f 0 f = 10 KHz )
32. For the differential amplifier of figure 4.11, R1 = 5 KΩ , R2 = 1MΩ , e1 = 5mV and
e2 = 15mV , compute the output voltage of this circuit. (Ans.: 2 volts)
33. The differential mode gain of an operational amplifier is 12000 and common mode
rejection ratio is 1000. Calculate the output voltage if inputs in two terminal are 5 mV
and 5.2 mV. Calculate the percentage error if operational amplifier is ideal.
(Ans.: 2.46 volts)
34. The differential mode gain of an operational amplifier is 1000. The common mode
rejection ratio is 1000. Calculate the output voltage, if the voltages applied to the two
terminals of the amplifier are 2mV and 2.2mV. Find also the percentage error at the
output if the operational amplifier is perfect (CMRR is infinite).
(Ans.: 202.1mV, 1.05%)
35. Repeat the problem 34, if the common mode rejection ratio of the amplifier is 100.
(Ans.: 20.21mV, 10.5%)
36. For two sets of reading in differential amplifier,
(a) e1 = −100 µV e2 = 100 µV
(b) e1 = 950 µV e2 = 1050 µV , find the % difference in output voltages if
CMRR is 100. Repeat the calculation for CMRR is 10000.
(Ans.: 10%, 1%)

_________

116
5
Applications of Operational Amplifier
In the preceding chapter the characteristics of ideal and practical operational
amplifier in addition to its use in inverting and non-inverting configurations with their
limitations have been discussed. Discussions on internal circuit of commonly used
operational amplifier IC 741 and emitter coupled differential amplifier have also been
made in that chapter. In this chapter the error terms in the operational amplifiers such as
input bias current, input offset currents, input offset voltage with their effect on the output
and their compensation will be discussed. Some more applications of operational
amplifiers will also be discussed in detail so that one becomes familiar for use it.

5.1 ERROR VOLTAGES AND CURRENTS IN OPERATIONAL AMPLIFIERS


As discussed in the preceding chapter, the first stage of the operational amplifiers is the
differential amplifier stage which consists of symmetrical transistors having identical
parameters resulting thereby zero output voltage when the two inputs are equal. The
practical operational amplifier, however, gives non-zero output when both the inputs are
equal. It is caused by the mismatch of the input transistors. This mismatch results the
unequal biasing in the input transistors. The following error components are, therefore,
introduced in the operational amplifiers which limits the signal sensitivity of the
amplifier.
Input Bias Current
Input Offset Current
Input Offset Voltage
Thermal Drift
5.1.1 Input Bias Current
As discussed above due to the mismatch of the transistors, there will be unequal
biasing in the input transistors of the differential amplifier stage of the operational
amplifier. The inputs of operational amplifier are the base inputs. Therefore very small
d.c. base currents flow into the input terminals of the operational amplifier even if these
inputs are grounded. The input currents IB1 and IB2 flow into the inverting and non-
inverting inputs of the operational amplifier respectively, as illustrated in figure 5.1. In
general IB1 is not equal to IB2 although these are of the same order of magnitude, so these
can assumed to be as the constant current sources. The orders of magnitude of these
currents are 10 – 6 to 10 – 14 amperes. There is, however, a slight variation in these currents
with temperature making it difficult to compensate for them at all temperatures. The
direction of these two bias currents will be into the amplifier if n-p-n transistors are used
in differential stage of the operational amplifier. The input bias current is, therefore,
defined as the average of these two input currents. The input bias current is denoted by IB
and is given by:
I + I B2
I B = B1 … (5.1)
2
The input bias current is less than 500 nA for the commonly used operational
amplifier 741.

Fig. 5.1
There will be certain error voltage at the output of the operational amplifier due to
this input bias current. The error voltage also called the output offset voltage can be
significantly large for the large feedback resistors. In some applications this error voltage
will not be very large but it is necessary to know the magnitude of this voltage in the
inverting and non-inverting configurations and also some means of minimizing or
eliminating this voltage.
To find the output voltage obtained due to input bias current in the inverting or
non-inverting configuration, consider the general circuit shown in figure (5.2). No
external source is connected to the inverting and non-inverting terminals. So this circuit
may be used either in non-inverting or inverting configuration.

Fig. 5.2
It is assumed that the bias currents at inverting and non-inverting terminals are
almost equal so that I B1 = I B 2 = I B … (5.2)
Let e 0 IB is the very small output offset voltage due to the input bias current I B .
The voltage e2 is zero as the non-inverting terminal is grounded. The voltage e1 at the
inverting terminal of the operational amplifier is obtained by multiplying I B1 with the

118
parallel combination of resistances R1 and R f , since the resistance R f will be in parallel
with the resistance R1 if e 0 IB is very small.
So e1 = ( R 1 R f ) I B 1
 R1 R f 
or e1 =  I … (5.3)
 R + R  B1
 1 f 
Applying the KCL to the inverting terminal, we have
I 1 + I 2 = I B1
e e − e1 e1
or − 1 + 0 IB =
R1 Rf Ri
e 0 IB  1 1 1 
or = e1  + + … (5.4)
Rf R R R 
 i 1 f 
In the input resistance Ri of the operational amplifier is assumed to be very large,
1
then → 0 and equation (5.4) becomes:
Ri
 1 1 
e 0 IB = e1 R f  +
R 
 1 Rf 
 R1 + R f 
or e 0 IB = e1 R f   … (5.5)
 RR 
 1 f 
Put the value of e1 from equation (5.3) into equation (5.5), we have:
 R1 R f   R1 + R f 
e0 IB = I B1  R f  
R +R   RR 
 1 f   1 f 
or e0 IB = I B1 R f … (5.6)
Since I B1 = I B 2 = I B , so equation (5.6) becomes:
e0 IB = I B R f … (5.7)
From this equation it is clear that the output offset voltage will depend on the
value of the feedback resistor R f for the specific value of the input bias current. The
larger value of the feedback resistor will increase this error voltage at the output.
Now to eliminate or reduce the effect of input bias current on the output offset
voltage, let us develop a voltage at the non-inverting terminal of the operational
amplifier. If the voltage developed at the non-inverting input is approximately equal to
the voltage developed at the inverting terminal then it will lead to the output offset
voltage due to input bias current zero. To develop a voltage at the non-inverting terminal
a resistance RCom is connected between the non-inverting terminal of the operational
amplifier and the ground terminal as shown in figure (5.3). The specific value of this
resistance is now calculated.
The voltage e2 developed at the non-inverting terminal is given by:
e2 = RCom I B 2 … (5.8)

119
To eliminate the effect of input bias current we should have:
e1 = e2 … (5.9)
Put the value of e1 from equation (5.3) and e2 from equation (5.8) in equation
(5.9), we get:
 R1 R f 
  I = R Com I B 2
 R + R  B1
 1 f 

As I B1 = I B 2 , this equation becomes:


 R1 R f 
R Com =   … (5.10)
R +R 
 1 f 
Thus the specific value of the resistance RCom should be the parallel combination
of resistances R1 and R f . The use of this resistance RCom will, however, not completely
eliminate the output offset voltage due to input bias current as the two currents I B1 and
I B 2 are not exactly equal, but will minimize this error voltage to a greater extent. The
resistor RCom is known as the offset minimizing resistor.

Fig. 5.3
Figure 5.4 shows the circuit diagram of inverting amplifier in which offset
minimizing resistor RCom is used. This resistor will minimize the output offset voltage to

Fig. 5.4

120
almost zero ( e0 IB = 0 ) and the output will be corresponding to input signal ei connected
to the inverting terminal of the operational amplifier.
 Rf 
i.e. e0 = − ei . … (5.11)
 R1 
Similarly the circuit diagram of non-inverting amplifier with offset minimizing
resistor RCom is shown Figure 5.4. The output voltage will be corresponding to the input
signal ei connected to the non-inverting terminal with output offset voltage minimized to
almost to zero.
 Rf 
i.e. e0 = 1 + ei … (5.12)
 R1 

Fig. 5.5
5.1.2 Input Offset Current
As discussed above the bias current compensation will be possible if the both the bias
currents are equal. The input transistors of the differential amplifier stage of the
operational amplifier can never be made exactly identical even if the transistors are
fabricated inside an IC. So there is always be very small difference between the two bias
currents I B1 and I B 2 . The difference in these two bias currents is known as input offset
current I 0 S . The input offset current is given as:
I 0 S = I B1 − I B 2 … (5.13)
Now let us examine the effect of input offset current. When I B1 ≠ I B 2 , then there
will be a little difference between the two and the effect of bias currents will not be
completely eliminated. For this consider the circuit shown in figure 5.6. The voltage e1
and e2 are expressed as:
 R1 R f 
e1 =   I B1 … (5.14)
R +R 
 1 f 
and e2 = RCom I B 2

121
 R1 R f 
= I B2 … (5.15)
R +R 
 1 f 

Fig. 5.6
The output voltage due to e1 and e2 are obtained by using superposition theorem.
This voltage will be the output offset voltage e 0 I 0 S due to both I B1 and I B 2 , given by:
R
e 0 I 0 S = − R f I B 1 + (1 + f
). e 2 … (5.16)
R1
In this equation first term is the voltage due to I B1 alone and second term is the
voltage due to e2 (or I B 2 ) alone.
From equations (5.15) and (5.16), we have:
 R + R f   R1 R f 
e 0 I 0 S = − R f I B 1 +  1  . .I B 2
 
 R1   R1 + R f 
= − R f I B 1 + R f .I B 2
= (I B 2 − I B 1 )R f

= I0S R f … (5.17)
From this equation it is clear that the output offset voltage due to input offset
current will depend on the value of the feedback resistor R f . The effect of input offset
voltage is much less than the effect of the input bias current since input offset current is
always less than the input bias current.
5.1.3 Input Offset Voltage
In an ideal operational amplifier, the output voltage e0 will be zero when either
both the input terminals are grounded or the difference of the input voltages is zero. In a
practical operational amplifier there will be non-zero output voltage for such a situation.
This error voltage is because the two transistors of the differential amplifier are not
properly matched due to which the collector current in these transistors are not equal.
This voltage may be positive or negative, which is not predictable. This can, however, be
determined experimentally. This error voltage can be made equal to zero by applying a
small d.c. voltage of appropriate polarity to one of the input terminals, whose magnitude
will be the non-zero output voltage divided by the gain of the amplifier. So the voltage

122
applied to the input terminal to obtain the zero output voltage is known as the input offset
voltage (ref. figure 5.7). It is denoted by V0 S .

Fig. 5.7
Consider the non-inverting and inverting amplifier circuits shown in figures (5.8)
and (5.9) respectively, in order to examine the influence of the input offset voltage V0 S
on the outputs of these amplifiers. In the non-inverting amplifier, signal ei is applied to
the non-inverting input as shown in fig. 5.8; and this signal is applied to the inverting
terminal through the resistance R1 in the inverting amplifier as shown in fig. 5.9. Now the
signal ei is set to zero in both these two circuits. These circuits will become the same as
in figure 5.10.

Fig. 5.8

Fig. 5.9
The voltage drop across the resistance R1 with respect to figure 5.10 is given by:
 R1 
e1 =  .e0
R +R 
 1 f 

123
 Rf 
or e0 = 1 + .e1 … (5.18)
 R1 
Further V0 S = − e1 as the non-inverting input is grounded.
So V0 S = e1 … (5.19)
From equations (5.18) and (5.19), we have:
 Rf 
e0 = 1 + .V0 S … (5.20)
 R1 
This is the expression for the error voltage at the output of the amplifier (output
offset voltage) due to input offset voltage both in inverting and non-inverting
configurations. If this input offset voltage is not compensated in the operational amplifier,
the output offset voltage gets added algebraically with the output voltage obtained due to
the input signal both in the inverting and non-inverting configuration.

Fig. 5.10
Now when the input signal ei is applied to the inverting amplifier, the total
voltage obtained in this amplifier is given by:
Rf  Rf 
e0T = − .ei ± V0 S 1 +  … (5.21)
R1  R1 
First term of this equation is the output voltage due to input signal ei , and the
second term is due to the input offset voltage.
Rf
If >> 1 , this equation (5.21) reduces to:
R1
Rf Rf
e0T = − .ei ± V0 S
R1 R1
Rf
e0T = − (ei ∓ V0 S ) … (5.22)
R1
Similarly one can write expression for the total voltage obtained in the non-
inverting amplifier.
 Rf   R 
e0T = 1 + ei ± V0 S 1 + f 
 R1   R1 

124
 Rf 
= 1 + (e i ± V0 S ) … (5.23)
 R1 
From the equations (5.22) and (5.23), it is clear that the influence of input offset
voltage in the inverting and non-inverting amplifiers is approximately the same i.e. in
both these two cases the input offset voltage gets amplified by their respective gains and
added algebraically with the output of the amplifier.
To compensate the offset voltage in the operational amplifier, offset null pins are
provided in some operational amplifier ICs. As discussed in the previous chapter, pins 1
and 5 are provided in OPAMP IC 741 for this purpose. So to nullify the offset voltage,
input terminals (Inverting pin 2 and non-inverting pin 3) are grounded and a 10 KΩ
potentiometer is externally connected between the offset null pins 1 and 5 as shown in
figure 5.11. The variable terminal of the potentiometer is connected to pin 4 ( − V EE ) . To
nullify the offset voltage, adjust the variable terminal of the pot. to make the output
voltage zero. The operational amplifier is thus said to have been nullified. Now the
operational amplifier is ready for its use. The adjusted potentiometer will remain to be
externally connected for that amplifier.

Fig. 5.11
In some operational amplifiers offset null pins are not provided, for that external
biasing circuit is used. Figure 5.12 shows the external biasing circuit for the non-
inverting amplifier. In this arrangement keeping ei = 0 (non-inverting terminal to be
grounded), the potentiometer R2 is adjusted to have the output voltage zero.

Fig. 5.12
Similar external biasing arrangement is used for inverting configuration. Such
arrangement is shown in figure 5.13. In this case too ei is kept zero, and the
potentiometer R2 is adjusted to have the output voltage zero.

125
Fig. 5.13
Model of a Practical OPAMP
The model of a practical operational amplifier may be represented as shown in
figure 5.14. It consists of an ideal operational amplifier, a battery V0 S to account for the
input offset voltage and two current sources to show the influence of input bias currents.

Fig. 5.14
Using the practical model of the operational amplifier, the total output voltage
obtained for the circuit shown in figure 5.15 is given by:
 Rf   R 
e0 = V0 S 1 +  − I B1R f + I B 2 RCom 1 + f  … (5.24)
 R1   R1 
In this equation first term is output voltage due to input offset voltage, second
term due to input bias current I B1 and third term due to I B 2 .

Fig. 5.15

Example 5.1 An operational amplifier, with an input offset voltage of 5 mV and input
bias currents I B1 = I B 2 = 1 µA, is used in the inverting configuration with R f = 1.5MΩ

126
and R1 = 150 KΩ . What is the output voltage when input signal is grounded? What is the
gain of the signal? What should be the value of the compensating resistance to be
connecting between the non-inverting terminal and ground to compensate the input bias
current?

Solution. (i) When the signal is grounded the inverting amplifier becomes as shown
in figure 5.15, for which the output voltage is given by:
 Rf   R 
e0 = V0 S 1 +  − I B1R f + I B 2 RCom 1 + f 
 R1   R1 
 1.5 x10 6 
e0 = 5 x10 −3 1 +  − 1x10 −6 x1.5 x10 6 + 0
3 
 150 x10 
≅ −1.5V
Rf 1.5 x10 6
(ii) Gain of the signal = − =−
R1 150 x10 3
= −10
(iii) To compensate the effect of input bias current the compensating resistance should
R1 R f 1.5 x10 6 x150 x10 3
be: RCom = =
R1 + R f 150 x10 3 + 1.5 x10 6
= 136 KΩ
Example 5.2 The output voltage was checked for the three circuit configuration
shown in figure 5.16 (a through c). It was found to be 10mV, 110mV and -140mV
respectively for the three configurations. Find out the input bias current, input offset
current and input offset voltage. Open loop gain of the amplifier is very large.
Solution. Considering the model of the practical operational amplifier and also the
error terms, we have the general expression for the output voltage as:
 Rf   R 
e0 = V0 S 1 +  − I B1R f + I B 2 RCom 1 + f 
 R1   R1 

(a) (b) (c)


Fig. 5.16

(i) In this case R1 = ∞ , R f = R Com = 0


So e0 = V0 S = 10 mV

127
(ii) In this case R1 = ∞ , R Com = 0 , R f = 1M Ω
So 110 mV = 10 mV − I B1x10 6
I B 1 = − 100 nA
(iii) In this case R1 = ∞ , R f = 0 and R Com = 1 M Ω
So − 140 mV = 10 mV + 0 + I B 2 x10 6
I B 2 = −150 nA
I + I B2
Input bias current I B = B1 = −125nA
2
Input offset current I 0 S = I B1 − I B 2 = 50nA

5.1.4 Thermal Drift


In the forgoing sections the influences of input bias current, input offset current
and input offset voltage were discussed. No discussions on the variation of these factors
with temperature were made. It was assumed that these parameters are constant for a
given operational amplifier. The compensation methods used to nullify these parameters
are for the room temperature. There may be slight variations in these parameters with
temperature; such variations are called thermal drift.
Normally, the thermal drift in the input bias current is denoted by:
∆I B
and is expressed in nA/ 0C .
∆T
The thermal drift in the input offset current is denoted by:
∆I 0 S
and is expressed in nA/ 0C .
∆T
The thermal drift in the input offset voltage is denoted by:
∆V0 S
and is expressed in mV / 0C .
∆T
Forced air cooling is generally used to stabilize the ambient temperature and thus
minimize the effect of thermal drift.
5.2 APPLICATIONS OF OPERATIONAL AMPLIFIERS
The use of operational amplifiers as the inverting and non-inverting amplifiers has
been discussed in the previous chapter. There are a number of applications of operational
amplifiers. Now we shall discuss the applications of operational amplifiers.

5.2.1 Sign Changer


Rf
In the circuit inverting amplifier (figure 5.17), if the ratio is denoted by K, a real
R1
constant, we have e0 = − Ke1 . That is, the input voltage scale has been multiplied by the
factor − K to give the output voltage scale. Such circuit is called as Scale Changer. For
such applications, precision resistors are used to get accurate values for the scale
factor − K .

128
Fig. 5.17
5.2.2 Phase Shifter
If in the circuit of figure 5.17 (inverting amplifier) the resistances R f and R1 are replaced
by the impedances Z f and Z1 respectively. These impedances with their phase angles
are represented by Z f = Z f ∠θ f and Z 1 = Z 1 ∠θ 1 where ∠θ f and ∠θ 1 of the
impedances Z f and Z1 respectively. The output voltage is given by:
Z f ∠θ f
e0 = − ei … (5.25)
Z 1 ∠θ 1
If these impedances are equal in magnitude and differ in phase angle, the gain of
the amplifier is given by:
e
A f = 0 = −∠(θ f − θ 1 ) … (5.26)
ei
This equation clearly indicates that the circuit is capable of shifting the phase of
signal applied to the inverting input of the amplifier without changing its magnitude. The
amount of phase shift can be anything between 0 and 3600. Such a circuit may be referred
to Phase Shifter.
5.3 SUMMING AMPLIFIER
The summing amplifier also called as Adder, using an operational amplifier
whose open loop gain is A and input resistance is Ri , is shown in figure 5.18. Let e1 ,
e2 and e3 are the three signal to be added. These signal are applied to the inverting input
of operational amplifier through the resistances R1 , R2 and R3 respectively.

Fig. 5.18

129
Referring to figure 5.18, the currents i1 , i2 , i3 , ii and i f flowing through
resistances R1 , R2 , R3 , Ri , and R f respectively are given by:
e1 − e e2 − e e3 − e
i1 = i2 = i3 =
R1 R2 R3
e e − e0
ii = if = … (5.27)
Ri Rf
where e is the voltage drop across the input resistance Ri .
Also e0 = − A.e … (5.28)
Applying the KCL to the inverting terminal of the operational amplifier, we have:
i1 + i2 + i3 = i f + ii … (5.29)
From equations (5.27) and (5.29), it is obtained:
e1 − e e2 − e e3 − e e − e0 e
+ + = +
R1 R2 R3 Rf Ri
e1 e2 e3  1 1 1 1 1  e
or + + = e + + + + − 0
R1 R2 R3  
 R1 R2 R3 R f Ri  R f
e
Put the value of e from equation (5.27) as e = − 0 , we get:
A
e1 e2 e3 e  1 1 1 1 1  e
+ + =− 0 + + + + − 0
R1 R2 R3 A  R1 R2 R3 R f Ri  R f
 e1 e2 e3 
 + + 
 R1 R2 R3 
or e0 = − … (5.30)
1  1 1 1 1 1 A 
+ + + + +
A  R1 R2 R3 R f Ri R f 
This is the expression for output voltage of the adder circuit.
If A → ∞ and Ri → 0 (that is operational amplifier is ideal), then the equation
(5.30) may be reduced to:
e e e 
e0 = − R f  1 + 2 + 3  … (5.31)
 R1 R2 R3 
If R1 = R2 = R3 = R then we have:
Rf
e0 = − (e1 + e2 + e3 ) … (5.32)
R
Again, if R f = R then we obtain from equation (5.32):
e0 = −(e1 + e2 + e3 ) … (5.33)
From this equation (5.33) it is clear that the output voltage e0 is numerically equal
to the algebraic sum of the input voltages e1 , e2 and e3 . Hence it is called as the adder or
summing circuit.

130
5.3.1 Non-inverting Summing Amplifier
A non-inverting summing amplifier which gives the non-inverting summation of
input signals is shown in figure (5.19). Let the open loop gain of the amplifier is infinite
and input resistance of the OPAMP is zero. So the voltage e across the terminals of the
amplifier is zero. So the voltage ea at the terminal a will be equal to the voltage eb at the
terminal b.

Fig. 5.19
Applying KCL to the terminal a, is given by:
i1 + i 2 + i3 = 0
e1 − ea e2 − ea e3 − ea
or + + =0
R1 R2 R3
e a ea ea e e e
or + + = 1 + 2 + 3
R1 R2 R3 R1 R2 R3
 1 1 1  e e e 
or ea  + +  =  1 + 2 + 3 
 R1 R2 R3   R1 R2 R3 
 e1 e2 e3 
 + + 
 R1 R2 R3 
or ea = … (5.34)
1 1 1 
 + + 
 R1 R2 R3 
The voltage at the point b is given by:
 R 
eb =  e = e a … (5.35)
R + R 0
 f 
which is equal to ea , since the voltage e across the terminals of the amplifier is
zero.
Using the equations (5.340 and (5.35) we get:

131
 e1 e2 e3 
 + + 
 R f   R1 R2 R3 
e0 = 1 + 
 R   1 1 1 
 + + 
 R1 R2 R3 
It is the non-inverting weighted sum of three input.
Rf
If R1 = R2 = R3 = R = then we have:
2
e0 = (e1 + e2 + e3 ) … (5.36)
From this equation (5.36) it is clear that the output voltage e0 is numerically equal
to the algebraic sum of the input voltages e1 , e2 and e3 . It gives non-inverting output
hence it is called as the non-inverting adder or summing circuit.
Example 5.3 Consider an inverting summing amplifier. The input resistance of the
operational amplifier is 10 KΩ and its open loop gain is 100. Determine the magnitude of
the output voltage for the following parameters of the circuit.
e1 = 1 V, e2 = 4 V, e3 = −3 V, R1 = 5 KΩ, R2 = 4 KΩ, R3 = 10 KΩ, R f = 10 KΩ.
What will be output if is assumed that the operational amplifier is ideal?
Solution. (i) The expression for the output voltage is given by:
 e1 e2 e3 
 + + 
R
 1 R R 3 
e0 = −
2


1 1 1 1 1 1 A 
+ + + + +
A  R1 R2 R3 R f Ri R f 
Put the values of the terms in this expression, we get:
 1 4 3 
 + − 
=−  5 K 4 K 10 K 
1  1 1 1 1 1 100 
 + + + + + 
100  5 K 4 K 10 K 10 K 10 K 10 K 
18V 18
=− =− V
215 2.15
100
= −8.37 V
(ii) If the operational amplifier is ideal, the output voltage is given by:
e e e 
e0 = − R f  1 + 2 + 3 
 R1 R2 R3 
 1 4 3 
= −10 K  + − V
 5 K 4 K 10 K 
18
= −10 K V
20 K
= −9 V

132
5.4 CURRENT –TO –VOLTAGE CONVERTER
Current –to –Voltage Converter is a device that gives a voltage proportional to a
current source connected to its input terminal. The operational amplifier in inverting
configuration can be used as current –to –voltage Converter. The circuit diagram of such
a converter is shown in figure 5.20. A current source i S having the source resistance RS
is connected to the inverting terminal of the operational amplifier. Now we will see that
the output voltage of this circuit is proportional to the magnitude of the current source.
Since the point P is at the virtual earth, so the total amount of the current from the source
will flow through the feedback resistance R f .

Fig. 5.20
The output voltage will, therefore, be given as:
e0 = −i S R f … (5.37)
Since R f is a constant quantity for the circuit so the output voltage is proportional
to the input current. Hence it is called current –to –voltage Converter. It can also be
called as the current controlled voltage source.
5.5 VOLTAGE –TO – CURRENT CONVERTER
Voltage –to – Current Converter produces a current source whose magnitude is
proportional to voltage source applied to its input terminal. The operational amplifier in
non-inverting configuration can be used as Voltage –to – Current Converter. The circuit
diagram of such a converter is shown in figure 5.21. A voltage source e1 which is to be
converted to its equivalent current source is connected to the non-inverting terminal of
the operational amplifier. In this circuit the feedback resistance R f is replaced by the load
resistance RL . Now we will see that the current flowing through the load resistance is
proportional to the magnitude of the applied input voltage e1 .

Fig. 5.21

133
The output voltage of the non-inverting input is given by:
 R 
e0 = e1 1 + L  … (5.38)
 R1 
If the input resistance of the amplifier is infinitely large than the load current will
flow through the series combination of resistances RL and R1 . The load current will,
therefore, be given by:
e0
iL = … (5.39)
R1 + RL
Put the value of e0 from equation (5.38) into equation (5.39), we get:
e1
iL = … (5.40)
R1
This current i L is independent of the load resistance RL and is proportional to the
input voltage e1 , as the resistance R1 is constant for the circuit. Hence this circuit is
called as voltage –to –current Converter.
5.6 D.C. VOLTAGE FOLLOWER
If in the circuit of non-inverting amplifier (figure 5.22a), the value of resistance R f
is kept zero and the value of resistance R1 as infinite, then the gain of the amplifier
becomes unity and the circuit becomes as shown in figure 5.22(b). The output of such
circuit will be the same as the input e1 or output follows the input. This circuit is,
therefore, referred to as a voltage follower circuit or a unity gain buffer amplifier. As the
circuit has high input impedance and low output impedance, so it can be used as a buffer
device between a high impedance source and a low impedance load i.e. it works as an
impedance matching device.

(a) (b)
Fig. 5.22

5.7 A.C. COUPLED AMPLIFIER


It is sometimes required the amplification of an a.c. signal, for this a..c. coupled
amplifier shown in figure 5.23 is used. In this circuit any d.c. signal present in the input
signal is blocked by the capacitor C i.e. the value of the capacitor is chosen so that it

134
effectively couples input signal to the input terminal of the amplifier. The capacitor C
along with the resistance R sets the low frequency 3-db response for the overall response.

Fig. 5.23
In this circuit point P is at the virtual earth, so the total amount of the total amount
of current I will flow through the feedback resistor R f . The output voltage will
therefore by given by:
e0 = − IR f … (5.41)
The current I is given by:
eS
I = … (5.42)
 1 
 R + 
 j ω C 
Put the value of I from equation (5.42) in equation (5.41), we have:
eS
e0 = − Rf
 1 
 R + 
 j ω C 
 
e0 Rf  j ω 
or AVf = =−   … (5.43)
eS R  1 
 jω + 
 RC 
From this equation we have the low frequency cutoff (3-db) as:
1
ωL =
RC
1
or fL =
2 π RC
The high frequency response is obtained by knowing the frequency characteristics
of operational amplifier gain and the amount of voltage shunt feedback. However, the
mid-frequency gain of the amplifier is given by:
Rf
AVf = − .
R
5.7.1 A.C. Voltage Follower
Figure 5.24 shows a high input impedance a.c. voltage follower circuit. This
circuit is used as a buffer amplifier which is used to connect a high impedance source and
a low impedance load. This load may even be capacitive. In this circuit the resistances R1
and R2 are used to provide the RC coupling and allow a path for d.c. input current into

135
the non-inverting terminal of the operational amplifier. The capacitor C 2 is the
bootstrapping capacitor, in the absence of which a.c. signal source will observe an input
resistance of only R1 + R2 (i.e. if R1 = R2 = 100 KΩ , R1 + R2 = 200 KΩ ). The voltage
gain between the output and the non-inverting terminal is very close to unity as the
operational amplifier is connected as a voltage follower. In the presence of bootstrapping
capacitor C 2 the input impedance becomes quite large.

Fig. 5.24

5.8 BRIDGE AMPLIFIER


The bridge amplifier is used to amplify the output from a wheat stone bridge.
Figure 5.25 shows the basic circuit diagram of a bridge amplifier. The wheat stone
bridge, as is well known, consists of four arms and all these arms have the same nominal
value. Let constant potential E is applied between the points A and D of the bridge. When
the bridge is balanced zero output voltage is obtained between the points B and C. One
arm of the bridge may be used as a resistance transducer whose value changes with
temperature or some other physical parameter. Let the change in resistance with
temperature is ∆R . Due to this change in resistance in the AB arm of the bridge, there
will be change in voltage across the points B C. The voltage across BC can now be
measured with a differential amplifier. The output of the operational amplifier will be
∆R
proportional to the fractional change in resistance δ = of the AB arm of the bridge.
R

136
Fig. 5.25
From the figure (5.25), the voltage at the point C is given by:
E.R E.R
EC = =
R + R 2R
E
= … (5.44)
2
The voltage at the point B is given by:
E.R
EB =
(2 R + ∆R )
E.R
=
∆R
R(2 + )
R
E
= … (5.45)
(2 + δ )
The potential difference across the points B and C is given by:
 E E
E B − E C =  −  … (5.46)
 (2 + δ ) 2 
This potential difference is amplified using the differential amplifier, whose
differential gain is Ad . Let the input resistance of the operational amplifier is infinite
(i.e. Ri → ∞ ). The output voltage will then be given by:
e0 = Ad ( E B − EC ) … (5.47)

Put the value of ( E B − E C ) from equation (5.46) into equation (5.47), we get:
 1 1
e 0 = A d E  − 
 (2 + δ ) 2 
 2−2−δ 
= A d E  
 2 .( 2 + δ ) 
δ 1
= − Ad E .
2 2 +δ
δ 1
= − Ad E . … (5.48)
4  δ 
1 + 
 2 
If δ << 1 then equation (5.48) reduces to
δ
e0 = − Ad E … (5.49)
4
This equation indicates that the output voltage is proportional to the fractional
change in resistance.
5.9 INTEGRATOR
Another important application of operational amplifier is its use as integrator.
Figure 5.26 produces an output that is proportional to the integral of the input signal.
Hence this circuit is called an integrator. This circuit is designed by replacing the

137
feedback resistor in the inverting amplifier by a capacitor C. This circuit may be analysed
in the following way:

Fig. 5.26
Assume that the open loop gain A of the operational amplifier is infinitely large
and thus point P is at the virtual earth. Thus the total current I following through the
resistance R will flow through the capacitor C. The voltage eC developed across the
capacitor will form the output voltage e0 .
i.e. e 0 = − eC … (5.50)
as the positive terminal of the capacitor is at the virtual earth and the negative
terminal is connected to the output.
Further, the point P being at the virtual earth, the current I is given by:
e
I= i … (5.51)
R
where ei is signal voltage whose integration is to be obtained.
This current I will flow through the capacitor C and the voltage eC across the
capacitor given by:
de
I = C C eC … (5.52)
dt
ei de
Therefore, = C C eC
R dt
ei d ( − e0 )
or =C
R dt

d ( e0 ) 1
or =− ei … (5.53)
dt RC
The output voltage will be obtained by integrating both sides with respect to time
as:
t t
1
∫ d (e 0 ) = −
0
RC ∫0
ei .dt

t
1
RC ∫0
e0 = − ei .dt + e0 t =0
… (5.53)

138
where e 0 t = 0 is the constant of integration and is the output voltage at time t = 0 .
It is the initial output voltage.
This circuit, therefore, provides an output signal which is proportional to the
integral of the input signal. The output voltage also depend on the time constant RC. In
the input is a sine wave, the output will be a cosine wave; if the input is a square wave,
the output will be a triangular wave as shown in figure 5.27(a) and figure 5.27(b)
respectively. In these waveforms the time constant RC is assumed to be unity and the
initial output voltage is zero.

Fig. 5.27(a)

Fig. 5.27(b)

In the complex form the gain of the amplifier is given by:


e0 ( jω ) Z f ( jω )
=−
ei ( jω ) Z ( jω )
1
where Z f ( jω ) = and Z ( jω ) = R
jω .C

139
e 0 ( jω ) 1
=−
ei ( jω ) jω .RC
So the gain of the integrator is:
e ( jω ) 1
Af = 0 =
ei ( jω ) ω .RC
1
= … (5.54)
2π . fRC
The frequency ( f = f a ) at which the gain of the integrator A f becomes unity (or
zero db) is obtained by putting A f = 1 in equation 5.54, as:
1
1=
2π . fRC
1
fa = … (5.55)
2π . RC
It may be noted from the equation (5.54) that the gain of the integrator decreases
with the frequency of the input signal. However, if the input signal ei has an average
value (or if the input is d.c. itself), the gain of the integrator becomes infinitely large. The
operational amplifier will then saturate as the capacitor C will be fully charged. So the
operational amplifier will behave like an open circuit. Solution of this problem is to use a
practical integrator.
5.9.1 Practical Integrator
The problem, in the basic integrator circuit was that the operational amplifier
gives the saturated output, as the capacitor gets fully charged. To prevent the operational
amplifier for being saturated a switch across the capacitor C can be connected as shown
in figure (5.28). Initially the switch is closed so that the capacitor is fully discharged
(integrator is reset): and the switch is opened only for the duration of time for which the
integration is performed. This switch can be an electromechanical relay or some other
electronic switch like junction field effect transistor.

Fig. 5.28
Alternately a resistance R f is connected in parallel with the capacitance C in the
feedback path to avoid the saturation problem in the output of operational amplifier
during integration. This circuit known as the practical integrator is shown in figure 5.29.

140
Fig. 5.29
The input output relation of this circuit can be obtained as follows:
The gain of this circuit is given by:
e Zf
Af = 0 = − … (5.56)
ei Z
where Z f is the impedance in the feedback path which is the parallel combination
of resistance R f and the capacitance C and Z is equal to the resistance R.
1
Rf .
j ωC Rf
Zf = =
1 (1 + jω .CR f )
Rf +
jωC
e0 Rf
So =−
ei (1 + jω .CR f ) R
e0 Rf R
or =−
ei (1 + jω .CR f )
e0 Rf R
or Af = = … (5.57)
ei 1 + (ω .CR f ) 2
The feedback resistance R f prevents the gain of the amplifier for being infinite
for low frequency signals (or d.c. signals). For d.c. signals (ω = 0), equation (5.57)
reduces to:
e Rf
Af = 0 = … (5.58)
ei R
So the gain is finite is equal to the gain of the inverting amplifier.
To minimize the effect of input offset current a compensating resistance RCom may
be connected between the non-inverting terminal and ground.
Example 5.4 Consider a basic integrator circuit using operational amplifier (figure
5.26). The saturating level of operational amplifier is ± 15V . Calculate the time required
for the operational amplifier to saturate if ei = 0.5V (d.c.). Given R = 100 KΩ and
C = 0.1 µf.

141
Solution. (i) The expression for the output voltage is given by:
t
1
RC ∫0
e0 = − ei .dt

1
e0 = − ei .t
RC
1
− 15V = − 0.5V .t
100 x10 x 0 .1x10 − 6
3

t = 300m sec
This is the required time.
5.10 DIFFERENTIATOR
The mathematical operation of differentiation can be performed by the
differentiator circuit. The output of such circuit is the derivative of the input signal.
Figure 5.30 shows the basic circuit diagram of a differentiator. This circuit is similar to
integrator circuit with the difference that the resistance and capacitance are interchanged
i.e. the resistance R f is connected in the feedback path of the inverting amplifier and the
capacitor C is connected between the inverting input and the signal ei .

Fig. 5.30
The point P being at the virtual earth as the open loop gain A of the operational
amplifier is infinitely large, the total current I following through the capacitor C will also
flow through the resistance R.
Such that I = If
de i e
C = − 0
dt Rf
dei e0
as I =C and If =−
dt Rf
dei
So e0 = − R f C … (5.59)
dt
It may be noted from this equation that the output voltage e0 is proportional to the
time derivative of the input signal ei . The circuit is thus called the differentiator circuit.
In the complex form the gain of the amplifier is given by:

142
e0 ( jω ) Z f ( jω )
=−
ei ( jω ) Z ( jω )
1
where Z f ( jω ) = R f and Z ( jω ) =
jωC
e 0 ( jω )
= − jω .R f C
ei ( jω )
So the gain of the integrator is:
e ( jω )
Af = 0 = ω .R f C
ei ( jω )
= 2π . fR f C … (5.60)
The frequency ( f = f b ) at which the gain of the differentiator A f becomes unity
(or zero db) is obtained by putting A f = 1 in equation (5.60), as:
1 = 2π . f b R f C
1
or fb =
2π . R f C
Equation (5.60) indicates that the gain of the integrator increases with the increase
of signal frequency. It increases at a rate of 20 db/decade. At high frequency, the
integrator becomes unstable. Further, the input impedance decreases with the increase in
frequency, thereby making the integrator sensitive to high frequency noise.
By the introduction of resistance R in series with the capacitance C and a
capacitance C f in parallel with the resistance R f as shown in figure 5.31 will eliminate
the problem of stability and high frequency noise. Such a circuit is called as the practical
differentiator.

Fig. 5.31
The practical differentiator circuit is now analysed. The gain of the amplifier is
given by:
e0 ( jω ) Z f ( jω )
=−
ei ( jω ) Z ( jω )

143
1
R f .( )
jωC f Rf
where Z f ( jω ) = =
1 1 + jωR f C f
Rf +
jωC f
1 1 + j ω RC
and Z ( jω ) = R + =
jω C jω C
e 0 ( jω ) Z f ( jω ) j ω .C . R f
=− =−
ei ( jω ) Z ( jω ) (1 + j ω . R f .C f ).( 1 + j ω . R .C )
If R f .C f = R.C , we have:
e 0 ( jω ) Z f ( jω ) j ω .C .R f
=− =−
ei ( jω ) Z ( jω ) (1 + j ω . R .C ).(1 + j ω . R .C )
j ω .C . R f
=−
(1 + j ω . R .C ) 2
j ω .C . R f
=− … (5.61)
f 2
(1 + j )
fb
1
where fb =
2π .R.C
It is clear from this equation that the gain increases for frequency f < f b and
decreases for f > f b . So for good differentiation, the signal which has the time period
greater than of equal to R f C .

5.11 LOGARITHMIC AMPLIFIER

The logarithmic amplifier is used to have the output which is proportional to the
logarithmic function of the input signal. Figure 5.32 illustrates the circuit of the
logarithmic amplifier. In this circuit a diode D is used in the feedback of the inverting
amplifier.

Fig. 5.31

144
If the operational amplifier has the open loop gain to be infinitely large, then the
current I flowing through the resistance R will be equal to the current I f flowing through
the diode D.
e
i.e. I = If = i
R
The current I f will be the forward current of the diode, which is given by:

… (5.62)
where IS is called the reverse saturation of the diode,
KT
VT = has the dimension of voltage and is known as the thermal
q
voltage. At room temperature VT = 26 mV.
η is a constant whose value depends on the material of the
diode and the quality of the junction, its value is 1 for Ge
and 1 to 2 for Si.

Generally , so equation (5.62) can be approximated as:

Taking ln (natural log) on both side of this equation, we get:

Also e0 = −V f

ei
= − η VT ln( )
RI S
e
= − η V T ln( i ) … (5.63)
e ref
where e ref = R . I S
It may be noted from equation (5.63) that the output voltage of this circuit is
proportional to the logarithmic function of the input signal. The terms η, VT and e ref are
constant quantities for the particular diode. Hence this circuit is called as the logarithmic
amplifier. But the terms η, VT and I S are temperature dependent. So the temperature will
affect the output of the circuit.

145
146
The effect of temperature can be eliminated by using the circuit shown in figure
5.32. In this circuit two logarithmic amplifiers are used; the input signal is applied to one
logarithmic amplifier while a reference voltage is applied to the input of second
logarithmic amplifier. The difference of the two outputs of these logarithmic amplifiers is
taken by using a difference amplifier and whose output is further amplifies by using a
non-inverting amplifier.
Assume that both the diodes used in the circuit are made up of same material so
that their reverse saturation currents are equal. The outputs of both the two logarithmic
amplifiers are given by:

… (5.64)

… (5.65)
The output of the differential amplifier is given by:

… (5.66)
From the equation (5.66) it is clear that the output voltage is proportional to the
logarithmic of the input signal. The voltage eref is a constant quantity. This output is still
KT
a temperature dependent because of the terms η and VT . Since VT = , so the output
q
e0 is directly proportional to the temperature. It can be compensated for the temperature
by applying this output to a non-inverting amplifier. In this amplifier a temperature
dependent resistance RT with a positive temperature coefficient is connected.
The final output e01 is thus given by:

… (5.67)
The resistance RT keeps the slope of equation constant as the temperature
changes.
5.12 ANTILOGARITHMIC AMPLIFIER
The antilogarithmic amplifier which gives the output proportional to the
antilogarithmic of the input signal is shown in figure 5.33.

147
Fig. 5.33
Consider the operational amplifiers are ideal, the point P may assume to be at the
virtual earth. So the output of the first amplifier is given by:
 R2  I 
e01 = e1 − V f =  ei − η.VT ln f  … (5.68)
 R1 + R2  I
 S

 R2  I 
where e1 =  ei and V f = η.VT ln f 
 R1 + R2
  IS 
I 
Also e01 = −η.VT ln 2  … (5.69)
 IS 
Equating equations (5.68) and (5.69), we have:
 I   R2  I 
− η.VT ln 2  =  ei − η.VT ln f 
 I S   R1 + R2   IS 
 I   I   R2 
or − η.VT ln 2  + ln f  =  ei
  I S   I S   R1 + R2 
 I   R2 
or − η.VT ln 2  =  ei
I 
 f   R1 + R2 
I  1  R2 
or ln 2  = −  ei
I  η .V R + R
 f  T  1 2 
 1  R2  
−   ei 
 R +R 
 η .VT
or I2 = I f e  1 2  
…(5.70)
Final output e0 is given by:
e0 = R3 I 2 … (5.71)
From equations (5.70) and (5.71), it is obtained:
 1  R2  
−   ei 
 η .VT  R1 + R2
e0 = R3 I f e  
… (5.72)

This equation indicates that the output voltage of this circuit is proportional to the
antilogarithmic (exponential) function of the input signal as other terms are constant.

148
Hence it is known as antilogarithmic amplifier. The natural log is considered in
calculating the output voltages across the diodes, so antilog will be the exponential
function. For changing it to the base ten, equation (5.72) is to be multiplied by a
correction factor. The constant terms will take care of this correction factor.
5.13 LOGARITHMIC MULTIPLIER
The log and antilog amplifiers discussed in the forgoing sections can be used to
get the multiplication or division of two analog input signals. To understand the principle
of the logarithmic multiplier, consider the block diagram illustrated in figure (5.34). In
this circuit two signals ei1 and ei 2 whose multiplication is to be obtained, are applied to
two logarithmic amplifiers. The outputs of two logarithmic amplifiers are added by a
summing amplifier, whose output is connected to an antilogarithmic amplifier. The
antilogarithmic amplifier finally gives the product of the two input signals.

Fig. 5.34
The outputs of logarithmic amplifiers are given by:
e1 = K 1 ln( K 2 ei1 )
e2 = K 1 ln( K 2 ei 2 )
where K1 and K2 are two constants used in the two logarithmic amplifiers. The
output of the summing amplifier is given by:
e01 = K 1 (ln( K 2 ei1 ) + ln( K 2 ei 2 ) )
e01 = K 1 (ln( K 2 K 2 ei1ei 2 ) ) … (5.73)
The output of the antilogarithmic amplifier may be given by:

… (5.74)
K3 and K4 are taken two constants for the antilogarithmic amplifier. If K 4 K 1 = 1 ,
then we have:

= K 3 (ei1 .ei 2 ) … (5.75)


The equation (5.75) clearly indicates that the output of this circuit is proportional
to the product of two input analog signals.
For division the output of second logarithmic amplifier is subtracted from the
output of first logarithmic amplifier rather then addition. When the antilog operation of
the output of subtractor is performed using antilogarithmic amplifier, the division of two

149
input signals is obtained. Figure 5.35 shows the block diagram for performing the
division operation.

Fig. 5.35
The output of the subtractor circuit is given by:
e01 = K 1 (ln( K 2 ei1 ) − ln( K 2 ei 2 ) )
 e 
e01 = K 1  ln( i1 )  … (5.76)
 ei 2 
The output of the antilogarithmic amplifier may be given by:

If K1 = 1 , then we have:

e 
= K 3  i1  … (5.77)
 ei 2 
The output is proportional to the division of two signals.
Example 5.5 (a) For the amplifier shown (with output resistance zero) in figure (5.36),
prove that:
(i) The output voltage e01 due to input bias current I B1 is:
R ' RRi Av
e01 = − I B1
( Ri + R1 )( R ' + R) + RR ' − Av RRi
(ii) The output voltage e01 due to input bias current I B 2 is:
R1Ri (R' + R)Av
e02 = IB2
(Ri + R1)(R' + R) + RR' − Av RRi
I B1 RR '
(b) Show that (e01 + e02 ) is minimized if ≈ 1 and R1 = .
I B2 R + R'

Solution. (a) First the output voltage e01 ( e0 = e01 ) due to the input bias current
I B1 only ( I B 2 = 0 ) is calculated as:

150
FIG. 5.36
From figure (5.36), we have:
I + I ' = I B1 + I i … (5.78)
e01 = Ri I i Av
e01
Ii = … (5.79)
Ri Av
RI + I i ( Ri + R1 ) = 0 … (5.80)
( Ri + R1 ) ( R + R1 ) e01
or I =− Ii = − i . … (5.81)
R R Ri Av
Also R ' I ' = e01 + RI
or e01 = R ' I ' − RI … (5.82)
e01 R e R ( R + R1 ) e01
or I' = '
+ ' I = 01' − − ' i .
R R R R R Ri Av
RRi Av − R ( Ri + R1 )
= e01 … (5.83)
RR ' Ri Av
From equations (5.78), (5.79), (5.81) and (5.83), we get:
( R + R1 ) e01 RRi Av − R( Ri + R1 ) e
− i . + e01 '
= I B1 + 01
R Ri Av RR Ri Av Ri Av
 − ( Ri + R1 ) R ' + RRi Av − R( Ri + R1 ) − RR ' 
or e01   = I B1
RR ' Ri Av 
 
'
R RRi Av
or e01 = − I B1
( Ri + R1 )( R + R) + RR ' − Av RRi
'

First part proved.


(b) The output voltage e02 ( e0 = e02 ) due to the input bias current I B 2 only ( I B1 = 0 ) is
calculated as:
I + I ' = Ii …(5.84)

151
e02
e02 = Ri I i Av or Ii = … (5.85)
Ri Av
Also e02 = R ' I ' − RI
R ' ' e02
or I= I − …(5.86)
R R
eor02 = R ' I ' + I i ( Ri + R1 ) − R1 I B 2
e02
= R'I ' + ( Ri + R1 ) − R1 I B 2
Av Ri
e e02 R
or I ' = 02' − '
( Ri + R1 ) + 1' I B 2
R Av Ri R R
e [ A R − ( Ri + R1 )] R1
I ' = 02 v i + ' I B2 … (5.87)
Av Ri R ' R
From equations (5.86) and (5.87), it is obtained:
[
e A R R ' − ( Ri + R1 ) R '
I = 02 v i +
] R ' R1
I − 02
e
… (5.88)
' ' B2
Av Ri R R R R R
Using equations (5.84), (5.85), (5.87) and (5.88), we have:
e 02 [ ]
Av R i R ' − ( R i + R1 ) R '
+
R ' R1 e
I − 02 + 02 v i
e [A R − ( R i + R1 ) ] R1 e
+ ' I B 2 = 02
' ' B2 '
Av R i R R R R R Av R i R R R i Av
 1 ( R + R1 ) R ' R i + R1 1 1 1 1 1 
e 02  + i '
+ '
− ' + −  +  + '  R1 I B 2
 Av R Av R i R R Av R i R R R R R R 
R1 Ri ( R ' + R) Av
or e02 = − I B2
( Ri + R1 )( R ' + R) + RR ' − Av RRi
Proved (ii) part.
(b) Adding e01 and e02 we have:

e01 + e02 =
[
Ri Av R1 ( R ' + R) I B 2 − R ' RI B1 ]
( Ri + R1 )( R ' + R) + RR ' − Av RRi
[
Ri Av R ' RI B1 − R1 ( R ' + R) I B 2
=
]
Av RRi − ( Ri + R1 )( R ' + R) − RR '
e01 + e02 will have the minimum value if the numerator of this equation minimum
or zero, which is possible when:
R1 ( R ' + R) I B 2 = R ' RI B1
I
R ' R B1 = R1 ( R ' + R)
I B2
I B1 RR '
Further if =1 then R1 =
I B2 R + R'
Hence proved.

152
Example 5.5 For the circuit given in figure (5.37), show that the output voltage is
given by:
R  L  dei d 2e
e0 = − ei −  RC +  − LC 2 i
R1  R1  d t dt
Assume that the operational amplifier is ideal.

Fig. 5.37
Solution. Since the operational amplifier is ideal so the inverting terminal will at the
virtual earth and the current I will also follow through the series combination of the
inductance L and resistance R.
The current I is given by:
e de
I = i +C i … (5.89)
R1 dt
 dI 
e0 = − RI + L  … (5.90)
 dt 
Put the value of I from (5.89) to equation (5.90), we get:
 e de  d e de 
e0 = − R i + C i  + L  i + C i  

  R1 dt  dt  R1 dt 
R de L dei de 
= − ei + RC i + + LC i 
 R1 dt R1 dt dt 
R  L  de d e 
2
= − ei +  RC +  i + LC 2 i 
 R1  R1  dt dt 
Hence proved.

Example 5.6 Derive the input output relation for the circuit given in figure (5.38). Show
R R
that if 2 = 3 the circuit behaves as an ideal integrator.
R1 R4
Solution. Let the voltage at the point Y is eY . Then the voltage eC across the capacitor
C is given by:
 1 
eY  
 jω .C  eY
eC = = … (5.91)
 1  1 + jω .CR
 R + 
 jω .C 

153
Fig. 5.38

The output voltage e0 will be equal to eC as the operational amplifier 2 is used as


unity gain buffer amplifier.
eY
e 0 = eC = … (5.92)
1 + jω .CR
Since the operational amplifier 3 is used as inverting amplifier with a gain of
R4
(− ) , so the voltage e X at the point X is given by:
R3
 R  eY 
e X = − 4   … (5.93)
 R3  1 + jω .CR 
Further operational amplifier 1 is used as the difference amplifier, so the output
voltage of this amplifier may also be given as:
R 
eY =  2 (ei − e X )
 R1 
 R  R eY 
eY =  2  ei + 4 . 
R
 1  R 3 1 + jω .CR 
 R R 1   R2 
eY 1 − 4 . 2 .  =  ei
 R3 R1 1 + jω .CR   R1 
 R2 
 ei
eY =  R1 
 R4 R2 1 
1 − . . 
 R3 R1 1 + jω .CR 
R2 R3
If = then eY is given by:
R1 R4
 R2
  R2 

ei  ei
eY =  R1
 =  1
R
… (5.94)
 1   jω .CR 
1 −   
 1 + jω .CR   1 + jω .CR 

154
From equations (5.92) and (5.94), we get the output voltage as:
 R2 
 ei
R
.  1
1
e0 =
1 + jω .CR  jω .CR 
 
 1 + jω .CR 
 R  ei
=  2 
 R1  jω .CR
The output voltage in the time domain, we have:
R 1
R1 RC ∫
e0 = 2 . ei .dt … (5.95)

This is the equation of the ideal integrator and there will be no phase inversion.
R
The term 2 will give the gain at the output. The saturation problem will not arise in this
R1
case, as the output of the differential amplifier is connected to R C low pass circuit.
Further loading problem will also not arise as the final output is taken at the output of
unity gain buffer amplifier.
Example 5.7 For the circuit of figure (5.39), show that:
 R 2R 
e0 = 1 + 2 + 2 (V2 − V1 )
 R1 R 

Fig. 5.39
Solution. The resistances R1, R, and R1 form a ∆ network which may be converted to T-
network as shown in figure (5.40).

Fig. 5.40
The values of resistances R A , RB , RC are given by (delta to star conversion)

155
RR1
RA = = RC … (5.96)
R + 2 R1
R12
RB = … (5.97)
R + 2 R1
Now the voltage e X at the point X is given by:
 R + RB 
e X = 1 + A V1
 R2 
R + RB + R2
= A V1 … (5.98)
R2
The voltage eY at the point Y is given by:
R A + R2
eY = eX … (5.99)
R A + R B + R2
Put the value of e X from equation (5.98) in equation (5.99), we have:
R A + R2 R + R B + R2
eY = . A V1
R A + R B + R2 R2
RA + R2  R 
= .V1 = 1 + A V1 … (5.100)
R2  R2 
The voltage e0 is obtained by applying superposition theorem.
 R  R 
e0 = 1 + 2 .V2 −  2 eY … (5.101)
 RC   RC 
From equations (5.100) and (5.101), it is obtained:
 R   R  R 
e0 = 1 + 2 .V2 −  2 1 + A V1
 RC   RC  R2 
 R  R R 
= 1 + 2 .V2 −  2 + A .V1
 RC   RC RC 
The values RA and RB are same, so we have:
 R 
e0 = 1 + 2 .(V2 − V1 )
 RC 
Put the value of RC from equation (5.96), we obtain:
 R ( R + 2 R1 ) 
e0 = 1 + 2 .(V2 − V1 )
 RR1 
 R 2R 
= 1 + 2 + 2 (V2 − V1 )
 R1 R 
Hence proved.
Example 5.8 For the circuit of figure (5.41), show that:

156
 Rf 
e0 = −α t + α .R f C 
 R 
where input is sweep voltage ei = α .t . Assume the operational amplifier used is
ideal.

Fig. 5.41
Solution. Since point P is at the virtual earth, so the total current I flowing through the
parallel combination of R and C will also flow through the feedback resistance R f . The
output voltage e0 will be given by:
e0 = − IR f … (5.102)
The value of current I flowing through the parallel combination of R and C is
given by:
e de
I = i +C i
R dt
Put ei = α .t in this equation we have:
α .t d
I= + C (α .t )
R dt
α .t
I= + Cα … (5.103)
R
Thus the output voltage is thus obtained by using the equations (5.102) and
(5.103):
 α .t 
e0 = − R f  + Cα 
 R 
 Rf 
or = −α t + α .R f C 
 R 
Hence proved.
Example 5.9 For the circuit of figure (5.42), show that it works as a non-inverting
integrator and the expression for the output is given by:
2
RC ∫
e0 = ei dt
Solution. Let the voltage at the point P is e P . The output voltage will, therefore, be
given by:
 R
e0 = 1 + e P = 2e P
 R

157
Fig. 5.42
The voltage e P is obtained by applying the superposition theorem as:
 R. (1 jω .C )   R. (1 jω .C ) 
   
 R + . (1 jω .C )   R + . (1 jω .C ) 
eP = ei + e0
 R. (1 jω .C )   R. (1 jω .C ) 
 R +   R + 
 R + . (1 jω .C )   R + . (1 jω .C ) 
 R.   R. 
   
 1 + jω .CR   1 + jω .CR 
eP = ei + e0
 R.   R. 
 R +   R + 
 1 + jω .CR   1 + jω .CR 
 ei e0 
e P =  + 
 2 + jω .CR 2 + jω .CR 
 ei e0 
e0 = 2 + 
 2 + jω .CR 2 + jω .CR 
 2   ei 
e0 1 −  = 2 
 2 + jω .CR   2 + jω .CR 
2ei
e0 =
jω .CR
The output voltage in the time domain, we have:
2
RC ∫
e0 = ei dt
Hence proved.

PROBLEMS
1. What are the important error voltages and currents in an operational amplifier?
Give the brief discussion of each.
2. Define input bias currents in an operational amplifier. What is the cause of input
bias currents in the operational amplifier? Mention the effect of input bias current
on the operational amplifier used in inverting and non-inverting configurations.

158
3. What are input bias currents in an operational amplifier? Find the expression of
output offset voltage due to input bias currents in the operational amplifier used in
inverting and non-inverting configurations.
4. Discuss the method of reducing or eliminating the effect of input bias currents in
an operational amplifier used in inverting and non-inverting configurations.
5. What is input offset current? Discuss the effect of input offset current on the
operational amplifier used in inverting and non-inverting configurations.
6. Define input offset current. Show that the output offset current due to input offset
current will depend on the feedback factor resistor on the circuit given below (fig.
5.43).

Fig. 5.43
7. What is input offset voltage in an operational amplifier? What is cause of this
voltage in an operational amplifier? Describe the methods of reducing the effect
of input offset voltage.
8. Explain the input offset voltage in an operational amplifier. Find the expression
for the output offset voltage due to input offset voltage in an operational amplifier
used in inverting and non-inverting configurations.
9. Define input offset voltage. Show that the influence of input offset voltage in the
operational amplifier is approximately the same when used in inverting and non-
inverting configurations.
10. Draw the model of a practical operational amplifier. Derive the expression for
output voltage of the given circuit (fig. 5.44) by considering the model of
practical operational amplifier.

Fig. 5.44
11. What is thermal drift? How does it affect the performance of an operational
amplifier circuit?
12. Draw the circuit to use an operational amplifier as:

159
(i) a scale changer
(ii) a phase shifter
13. Draw the schematic diagram to use an operational amplifier as summing
amplifier. Derive the expression for the output voltage of this circuit.
14. Draw the schematic diagram to use an operational amplifier as non-inverting
summing amplifier. Derive the expression for the output voltage of this circuit.
15. Draw the current – to – voltage converter circuit and derive the expression for the
output voltage.
16. Draw the voltage – to – current converter circuit and derive the expression for the
output voltage.
17. What is buffer amplifier? Draw and explain the circuit of unity gain buffer
amplifier.
18. Write short note on the following:
(i) A.C. coupled amplifier
(ii) A.C. voltage follower
19. What is a bridge amplifier? How is a bridge amplifier used to find the fractional
change in resistance in one arm of a wheat stone bridge?
20. Draw and explain the circuit of an integrator circuit. What is the disadvantage of
the basic integrator circuit?
21. Draw and explain the circuit of a practical integrator circuit.
22. Figure 5.45 shows the circuit of practical integrator. Assuming ideal operational
amplifier, determine:
(i) The high frequency 3db point f a .
(ii) Expression for the gain of the circuit.

Fig. 5.45
23. Draw and explain the circuit of a differentiator circuit. What are its
disadvantages? How are these disadvantages removed in practical differentiator
circuit?
24. Draw and explain the circuit of a logarithmic amplifier. Mention its
disadvantages.
25. Discuss the logarithmic amplifier in which the effect of temperature is eliminated.
26. Draw and explain the circuit of an antilogarithmic amplifier.
27. Draw the schematic diagram to multiply/divide the two analog voltages using log-
antilog amplifiers.

160
28 An operational amplifier, with an input offset voltage of 6 mV and input bias
currents I B1 = I B 2 = 1 .5 µA, is used in the inverting configuration with
R f = 1MΩ and R1 = 100 KΩ . What is the output voltage when input signal is
grounded? What is the gain of the signal? What should be the value of the
compensating resistance to be connecting between the non-inverting terminal and
ground to compensate the input bias current? (Ans.: – 1.566 V, –10, 91 KΩ)
29. Consider an inverting summing amplifier. The input resistance of the operational
amplifier is 12 KΩ and its open loop gain is 120. Determine the magnitude of the
output voltage for the following parameters of the circuit.
e1 = 1 V, e2 = −3 V, e3 = 3 V, R1 = 5 KΩ, R2 = 5 KΩ, R3 = 10 KΩ, R f = 12 KΩ.
What will be output if the operational amplifier is assumed to be ideal?
(Ans.: +1.125 V, +1.2 V)
30. The resistance values of all the resistances are equal (15 KΩ) in the circuit shown
in figure (5.46). Find the value of output voltage e0 , if e1 = 5 V, e2 = 4 V,
e3 = 3 V. (Ans.: –2 V)

Fig. 5.46
31. The basic integrator circuit has R = 1 MΩ and C = 1 µF. When the input voltage
ei = 0.4t , determine the output as a function of time.
32. The basic differentiator circuit has R = 20 KΩ and C = 0.01 µF. When the input
voltage ei is as shown in figure 5.47, determine the output as a function of time.

Fig. 5.47

__________

161
6
Regulated Power Supply
It is well known that rectifiers and filters are used to get the d.c. power from an
a.c. source. The transformers are also used for changing the high voltage to low voltage
or vice-versa. The d.c. voltage thus obtained is not regulated. Voltage regulator circuit is
used at the output of the unregulated power supply. A regulated supply is one which
gives constant output voltage irrespective of change in line voltage, change in load
resistance or change in temperature. In this chapter methods of getting the regulated
power supply will be discussed. Some voltage regulator ICs will also be discussed in
addition to switch mode power supply (SMPS).
6.1 VOLTAGE REGULATOR
The d.c. power supply consisting of transformer, rectifier and filter is known as
unregulated power supply. Its output changes when the load current or line voltage or
temperature is varied. An electronic circuit which keeps the output voltage constant
irrespective of variations in load current, line voltage or temperature is called as the
voltage regulator circuit. This is added at the output of the unregulated power supply so
as to get a good d.c. power supply (Stabilized). The block diagram of the voltage
regulator circuit is shown in figure 6.1.

Fig. 6.1
The d.c. output voltage of power supply is a function of load current I L , input
voltage Vi and temperature T . When the load current varies, the voltage drop across the
source resistance of the circuit also varies and hence the change in output occurs.
Similarly the variation in temperature corresponds to change in the characteristics of the
devices used in the circuit and hence the output voltages.
So V0 = f ( I L ,Vi , T )
∂V0 ∂V ∂V
dV0 = dI L + 0 dVi + 0 dT
∂I L ∂Vi ∂T
= R0 dI L + SV dVi + S T dT
dV0
where R0 = , is the output resistance of the supply.
dI L
dV
SV = 0 , is called the stability factor or the input regulation
dVi
factor.
dV0
ST = , is called as temperature coefficient.
dT
For good power supply all three coefficients should be small so that the total
change in output voltage dV0 is also small.
6.1.1 Percentage Regulation
The percentage regulation or voltage regulation of a power supply is defined as
the change in output voltage when the current is varied from no load to full load as:

… (6.1)
Consider a voltage source having V as the open circuit voltage and R0 as the
source resistance (fig. 6.2). The output of this source is connected to the load resistance
RL.

Fig. 6.2
From this figure the output voltage V0 is also given by:
V0 = R L I L … (6.2)
This voltage is also called as full load voltage.
Applying the KVL to this circuit we have:
V0 = V − R0 I L … (6.3)
If IL = 0, i.e., the load resistance is removed from the circuit, then V0 = V . The
voltage V is also called as no load voltage.
From equation (6.2) we also have:

R0
= x100 … (6.4)
RL
From the equation (6.4), it is clear that for the particular load the regulation of the
power supply will be better if the output resistance is smaller i.e. the output resistance or
source resistance should be small for a good d.c. power supply.

163
6.1.2 Classification of Voltage Regulators
The voltage regulator circuits may be classified into following categories (Fig.
6.3). The discussions on these regulators will be made in the following sections of this
chapter.

Fig. 6.3
6.2 SERIES VOLTAGE REGULATOR
Series voltage regulator falls in the category of discrete transistor regulators.
The basic principle of a series voltage regulator may well be understood by considering
the functional block diagram given in figure 6.4. The control element in this diagram is
connected between the input unregulated supply and the regulated output. This series
element controls the amount of input voltage to produce the required constant output
voltage. The output voltage is sampled by a circuit that produces a feedback voltage to be
compared to a reference voltage.

Fig. 6.4
If the output voltage increases, the comparator produces a control signal to cause
the series control element to decrease the amount of output voltage. Thereby maintains
the constant output voltage. If on the other hand the output voltage decreases, the

164
comparator produces a control signal to cause the series control element to increase the
amount of output voltage. Hence maintains the constant output voltage.
6.2.1 Simple Series Regulator Circuit
Figure 6.5 shows the simple series voltage regulator circuit. The working of this
circuit may be explained as follows:

Fig. 6.5
The transistor T1 of this circuit behaves as the series control element. The
collector emitter terminals of the transistor are in series with the load resistance; hence it
is called as series regulator. The total load current must pass through the transistor that is
why it is known as pass transistor. The reference voltage VZ is provided by the zener
diode.
Applying the KVL to the output circuit, we have:
VZ = V0 + VBE
or V0 = VZ − VBE
If somehow the output voltage decreases, the base emitter voltage VBE increases
as the zener voltage VZ being the reference voltage (constant voltage). The increase in
VBE results the increase in base current IB and the transistor conducts more resulting
thereby an increase in the collector current I C . The load current I L will also increase as
I L = I C = h fe I B . This leads an increase in the output voltage or the constant output
voltage is maintained.
If on the contrary the output voltage increases, the base emitter voltage VBE
decreases which results the decrease in base current IB and resulting thereby the decrease
in the collector current I C . The load current I L will also decrease leading the decrease in
the output voltage. Thus the constant output voltage is maintained or the output voltage is
stabilized.

Fig. 6.6

165
It can be understood that this regulator circuit is basically an emitter follower in
which the emitter of the transistor T1 follows zener voltage (or reference voltage). For this
series regulator circuit is redrawn as shown in figure 6.6. It is well known that the voltage
gain of the emitter follower is approximately equal to unity so the output voltage is equal
to zener voltage VZ (as VBE < VZ ).
i.e. V0 = VZ − VBE ≈ VZ … (6.5)
The output resistance R0 of the power supply can be obtained by replacing the
transistor to its equivalent approximate h – parameter model as given in figure 6.7. Here
hie is the common emitter input resistance of the transistor T1 and rZ is the zener
resistance.

Fig. 6.7

The current IL is given by:


I L = I B + h fe I B = I B (1 + h fe ) … (6.6)
Now short circuit the voltage source VZ, to calculate the output resistance R0 . We
have:
V0 = (rZ + hie ) I B
IL
= (rZ + hie )
(1 + h fe )
V0 (hie + rz )
R0 = =
IL 1 + h fe
(hie + rz )
≡ … (6.7)
h fe
So the output resistance decreases by hfe times or the load current is increased by
hfe times.
6.2.2 Improved Series Regulator Circuit
An improved series regulator circuit is shown in figure 6.8. In this circuit
resistances R1 and R2 act as a sampling circuit, zener diode DZ provides a reference
voltage and the transistor T2 then controls the base current of transistor T1 to vary the
current passed by transistor T1 to maintain the constant output voltage.
In the output voltage somehow increases, the increased voltage sampled by
resistances R1 and R2 increase the voltage V2. This voltage causes the base emitter voltage
of transistor T2 to increase. The conduction of transistor T2 will be more. The collector
current of T2 will be more resulting thereby the reduction of base current of transistor T1.
Finally the conduction of T1 will be less and the load current decreases. Thus the output

166
voltage refuses to increase. On the contrary when the output voltage decreases, the
opposite operation takes and the output voltage increases. In this way constant output
voltage is maintained.

Fig. 6.8

The voltage V2 must be equal to:


V0 .R2
V2 = VBE 2 + VZ =
( R1 + R2 )
 R 
or V0 = 1 + 1 (VZ + VBE 2 ) … (6.8)
 R2 
Here VBE 2 is the base emitter voltage of transistor T2 and VZ is the voltage across
the zener diode DZ. By selecting the proper values of resistances R1, R2 and zener diode
DZ , regulator of the desired voltage may be designed.

6.2.3 Feedback Type of Voltage Regulator

The feedback type voltage regulator also called controlled transistor series voltage
regulator is shown in figure 6.9. In this regulator a portion of the output voltage is fed
back which is compared by a reference voltage, error if any is amplified and an automatic
correction procedure is done so that the output voltage is kept constant irrespective of
variation in input unregulated voltage, load current or temperature.

Fig. 6.9

167
This circuit gives better voltage regulation because the large fraction of the
increase in input voltage appears across the pass transistor, so that the output voltage tries
to remain constant. If the input increases the output must also increase (but to a smaller
extent), because it is this increase in output that acts to bias the pass transistor towards the
less current.
If there is a change in output voltage V0, a portion of it will appear across the
resistance R2 and therefore at the base of the transistor T2. The voltage VZ across the zener
diode is also the emitter voltage of the transistor T2. This emitter voltage is the reference
voltage. The difference of the base voltage of the transistor T2 and the reference voltage
VZ is the base emitter voltage of this transistor or the error voltage. The error voltage is
amplified by this transistor T2. There will be a corresponding change in collector current
IC2. The change in IC2 changes the base current IB1 of T1 resulting a change in voltage
from collector to emitter of T1. This change in collector emitter voltage of T1 keeps the
output voltage constant.
From the figure 6.9, we have:
V2 = V Z + V BE 2
and V0 = V1 + V2 = V1 + VZ + VBE 2 … (6.9)
The voltage V1 across the resistance R1 is given by:
V .R
V1 = 0 1 … (6.10)
R1 + R2
From equations (6.9) and (6.10), we have:
 R1 
V0 1 −  = VZ + V BE 2
 R1 + R2 
 R  V + VBE 2
or V0 = (VZ + VBE 2 )1 + 1  = Z … (6.11)
 R2  β
R2
where β is the feedback factor given by: β = .
R1 + R2
This type of regulator can be set to provide a wide range of output voltage by
varying R1 or R2. The zener diodes of different breakdown voltages can be connected in
the circuit by using the selector switch for different ranges of output voltages. The current
capacity of the series pass transistor T1 will limit the output current of the regulator. For
low output voltages more voltage will be developed across the base collector of the
transistor T1. So the VCE breakdown rating and power dissipating ratings will limit the
specifications of the regulator.
The expression for the output resistance R0 can be calculated as follows:
Neglecting VBE1, the current change ∆I = i in RS is given by:
v − v0 v
i= i ≈ i
RS RS
The load resistance RL is constant so for constant output voltage the load current
IL and IB1 must be constant.
Hence for constant IB1 i = ∆I C 2 = i C 2

168
(a) (b)

(c)
Fig. 6.10
The circuit for transistor T2 and its equivalent circuits are redrawn in figures
6.10(a) through (c). From these figures we have:
V0 .R2  R .R 
=  1 2 + hie 2  I B 2 + RZ I B 2 + RZ h fe 2 I B 2
R1 + R2  R1 + R2 
 R .R 
=  1 2 + hie 2 + RZ (1 + h fe 2 ) I B 2
V0 .R2
or … (6.12)
R1 + R2  R1 + R2 
Also I C 2 = h fe 2 I B 2 … (6.13)
From equations (6.12) and (6.13), it is obtained:
 R .R I
=  1 2 + hie 2 + RZ (1 + h fe 2 ) C 2
V0 .R2
R1 + R2  R1 + R2  h fe 2
R2 V0
or I C 2 = h fe 2 …(6.14)
R1 + R2  R1 .R2 
 + hie 2 + RZ (1 + h fe 2 )
 R1 + R2 
or I C 2 = GmV0
R2 1
or Gm = h fe 2 … (6.15)
R1 + R2  R1 .R2 
 + hie 2 + RZ (1 + h fe 2 )
 R1 + R2 
Now the circuit of figure 6.10 (c) may be replaced by the resistor 1/Gm and the
circuit becomes as shown in figure 6.11(a). We have:
1
Vi ≅ r0 I B1 (1 + h fe1 ) + ( RS + ) I B1
Gm

169
Vi
or I B1 = … (6.16)
 1 
 r0 (1 + h fe1 ) + ( RS + )
 Gm 
The voltage VB across the resistance 1/Gm is given by:
 1 
Vi  
 Gm 
VB = … (6.17)
 1 
 r0 (1 + h fe1 ) + ( RS + )
 Gm 
The output resistance will be calculated by drawing the equivalent circuits of
figure (6.11a) in figures (6.11 b & C).

(a) (b)

(c)
Fig. 6.11
Referring to these figures, we have:
r0 (1 + h fe1 ) I B1 + RS I B1 = VB

or (r (1 + h
0 fe1 ) + RS ) =
VB
… (6.18)
I B1
Resistance between base and ground will be the parallel combination of 1/Gm and
(r0 (1 + h fe1 ) + RS ) , which is given by:
1 1
= Gm +
R (r0 (1 + h fe1 ) + RS )
(r (1 + h ) + R )
R=
0 fe1 S

1 + G (r (1 + h ) + R )
… (6.19)
m 0 fe1 S

170
The circuit of figure (6.11 c) may now be reduced as shown in figures (6.12 a &).
From these figures we have:
(R + hie1 )I B1 = V0
The output resistance of the circuit is given by:
V
R0 = 0
IL
Also I L = (1 + h fe1 ) I B1

(a) (b)
Fig. 6.12
The voltage across the load resistance is given by:
(R + hie1 ) I L = V0
(1 + h fe1 )
 R + hie1 
or R0 =   … (6.20)
 1+ h 
 fe1 
Put the value of R from equation (6.19) to equation (6.20) as:
 h (r0 (1 + h fe1 ) + RS ) 1 
R0 =  ie1 +
1 + Gm (r0 (1 + h fe1 ) + RS ) 1 + h fe1 
.
1 + h
 fe1

 
 r0 + RS 
 (1 + h fe1 ) 
=
hie1
+ 
1 + h fe1 1 + Gm (r0 (1 + h fe1 ) + RS )
or

hie1
(1 + Gm (r0 (1 + h fe1 ) + RS )) + r0 + RS
1 + h fe1 (1 + h fe1 )
=
1 + Gm (r0 (1 + h fe1 ) + RS )
or

hie1 Gm (r0 (1 + h fe1 ) + RS )hie1 RS


+ + r0 +
1 + h fe1 1 + h fe1 (1 + h fe1 )
=
1 + Gm (r0 (1 + h fe1 ) + RS )
or

R + hie1
r0 + S
(1 + h fe1 )
or ≅
1 + Gm (r0 + RS ) + Gm r0 h fe1

171
RS + hie1
r0 +
(1 + h fe1 )
R0 ≅ … (6.21)
1 + Gm (r0 + RS )
This is the required expression for the output resistance of the feedback type voltage
regulator.

6.3 SHUNT VOLTAGE REGULATOR


The functional block diagram of shunt type voltage regulator is given in figure
6.13. The control element in this diagram is connected in shunt (in parallel) with the
regulated output, hence the name as shunt regulator. The control element maintains the
constant output voltage by shunting the current away from the load. The elements in the
diagram have the same working function as in the case of series regulators.

Fig. 6.13
In this type of regulator the input unregulated voltage provides the current to the
load and some of this current is pulled away by the control element to maintain the
regulated output voltage across the load. If there is a variation in the load voltage, then
the sampling current provides a feedback to the comparator so that the output is
maintained constant.
6.3.1 Zener Diode Shunt Regulator
Figure 6.14 shows a zener diode shunt regulator. A reverse current known as
zener current flows through the zener diode when it operates in the reverse breakdown
region. The voltage VZ across the zener diode remains almost constant in the breakdown
region even if the zener current IZ changes from IZmin to IZmax as shown in figure 6.15.

Fig. 6.14

172
Fig. 6.15
The maximum zener current IZmax will be decided by the power ratings PZ of the
zener diode.
P
i.e. I Z max = Z
VZ
The ideal zener diode acts as a voltage source VZ . However, there is a slight
increase in the zener voltage due to the increase in the current in the practical zener
diode, which has in fact a finite zener resistance. The zener resistance rZ is given by:
∆VZ
rZ =
∆I Z
In this circuit the zener diode is in shunt with the load, hence it is known as the
zener diode shunt regulator.
The series resistance RS is used to prevent the zener diode for being damaged
when the maximum zener current is drawn. The value of this resistance is chosen so that
it fulfills the following requirements:
(i) When the maximum load current is drawn and the input voltage is
minimum, then the sufficient current must be supplied to keep the zener
diode in the regulating region.
(ii) When the minimum load current is drawn and the input voltage is
maximum, then the zener current should not exceed the maximum
allowable value.
From the figure 6.14 we have : IS = IZ + IL
Vi max − VZ
Also I Z max = − I L min
RS
V − VZ
I Z min = i min − I L max
RS

173
Vi max − VZ
So RS min =
I Z max + I L min
V − VZ
and RS max = i min
I Z min + I L max
Hence RS should be so chosen so that it lies between RS min and RS max .
i.e. RS min < RS < RS max
The output resistance of this circuit is the parallel combination of RS and rZ .
RS rZ
i.e. R0 =
RS + rZ
The zener diode regulator has the disadvantages that (i) a large amount of power
is wasted in the zener diode and the series resistance RS in comparison with the load
power, (ii) the output resistance of this circuit is not very low due to which regulation is
not very good and (iii) the maximum load current is limited to I Z max − I L min .
6.3.2 Basic transistor Shunt Regulator (or BJT Shunt Regulator)
Figure 6.16 shows the circuit diagram of BJT shunt regulator circuit. The
transistor T1 connected in parallel with the load works as the regulating element.

Fig. 6.16
The total current I flowing through the resistance RS is the sum of the current IC
through the transistor T1 , current IL through the load and the current through the zener
diode.
i.e. I = IC + I L + IZ
≈ IC + I L … (6.22)
as IZ is very small.
If the output voltage gets reduced, the voltage across the resistance R1 and the
current IC also gets reduced, which enhances the current IL to maintain the output voltage
V0 constant. Similarly, for any change in the input voltage VI, there will be a
corresponding change in the voltage across RS and output voltage remains constant.
The output voltage V0 is given by:
V0 = VZ + VBE … (6.23)
Also VI = RS ( I C + I L ) − V0

174
V I − V0
or RS = … (6.24)
(I C + I L )
This gives the value of the resistance RS.
6.3.3 Improved Shunt Regulator
An improved shunt regulator is shown in figure 6.17, in which two transistors in
darlington mode are used to increase the load current. The working of this circuit is the
same as the basic shunt regulator discussed above. In this circuit the zener diode provides
the reference voltage so that the voltage across R1 senses the output voltage. As the
output voltage changes, the current shunted by the transistor T2 is varied to maintain the
output voltage constant. The transistor T1 provides a larger base current to transistor T2,
so that the regulator can handle a large load current.
The output voltage is given by:
V0 = VZ + VBE1 + V BE 2

Fig. 6.17
Example 6.1 Calculate the output voltage and zener current in the simple series
regulator circuit shown in figure 6.18. The load resistance RL is 1 KΩ. The hfe of the
transistor is 50.

Fig. 6.18
Solution. The output voltage is given by:
V0 = VZ − VBE
= 8.2 − 0.7 = 7.5 V
The current I is given by:

175
VI − VZ 18 − 8.2
I= =
RS 220
9. 8
= = 44.5 mA
220
The load current for 1 KΩ load resistance is calculated as below:
V 7.5
IL = 0 = x10 −3
RL 1
= 7.5 mA
Further I L ≈ IC = I E
The base current is given by:
I 7.5
IB = C = mA
h fe 15
= 500 µA

The zener current is : I Z = I − I B = 7.5 − 0.5 mA


= 7 mA
Example 6.2 A zener diode shunt regulator shown in figure 6.14 supplies a load current
which varies from 0 to 250 mA at 6 V. The input to the regulator varies from 10 V to 15
V. The zener diode stabilizes to a minimum current of 10 mA. Calculate the value of
series resistance RS and the power rating of the zener diode.
Solution. The maximum value of the resistance RS is given by:
V − VZ
RS max = i min
I Z min + I L max
10 − 6
=
(250 + 10)mA
4
= = 15.3 KΩ
260mA
Hence RS may be chosen to be equal to 15 Ω.
V − VZ
Now I Z max + I L min = i max
RS
(15 − 6)V
=
15
= 600mA
Since I L min = 0 , so I Z max = 600mA
Power rating of the zener diode = VZ .I Z max = 6Vx0.6 A
Example 6.3 A zener diode shunt regulator RS =1.5 KΩ, VZ =6 Vat 1.5 mA, and RZ =
15Ω. The input to the regulator varies from 15 V to 25 V. Calculate
(i) the change in output voltage, change in zener current and input regulation
factor SV ,
(ii) the ripple at the output if the ripple at input is 1 V (r.m.s.).
Solution. (i) There is no load resistance, IL = 0

176
Vi max − VZ
So I Z max = − I L min
RS
V − VZ 25 − 6
= i max =
RS 1.5 KΩ
= 12.7mA
V − VZ
Similarly, I Z min = i min − I L max
RS
V − VZ 15 − 6
= i min =
RS 1.5KΩ
= 6mA
The change in zener current is given by:
∆I Z = I Z max − I Z min
= 12.7 − 6 = 6.7 mA
The change in output voltage is given by:
∆V0 = ∆I Z .RZ
= 6.7 x10 −3 x15V
= 100.5mV
Input regulation factor:
∆V0
SV =
∆Vi
100.5 x10 −3
= = 0.01
25 − 15
RZ
(ii) The ripple at the output = Vi ( ripple) x
RS + RZ
1x15
= = 0.0099
1500 + 15
6.4 REGULATORS USING OPERATIONAL AMPLIFIERS
Voltage regulators can also be designed using operational amplifiers with
negative feedback. The output resistance of the operational amplifier is very small and
with feedback the output resistance further reduces by (1+Aβ) times. This idea helps
giving better regulation. Operational amplifiers can be used both in series regulators and
shunt regulators. In the following sections we shall, therefore, discuss the use of
operational amplifiers in series and shunt regulators.
6.4.1 Series Voltage Regulator Using operational Amplifier
The series voltage regulator using operational amplifier is shown in figure 6.19. In
this circuit a zener diode is used to supply the reference voltage to the operational
amplifier. The zener diode is biased with the unregulated supply. The biasing
arrangement for the operational has not been shown the figure; however, it is biased with
the unregulated voltage. The reference voltage VZ is applied to the non-inverting terminal

177
of the operational amplifier. The negative feedback is applied via the resistances R1 and

Fig. 6.19
R2. A fraction [β = R1 ( R1 + R2 ) ] of the output voltage is compared with the reference
voltage VZ. When the gain of the amplifier tends to infinity, the output voltage will be
given by:
 R 
V0 = VZ 1 + 2  … (6.25)
 R1 
The regulation of this circuit is given by:
R0'
% Regulation = x100 … (6.26)
RL
where R0' is the output resistance of the amplifier, which is (1 + Aβ) smaller than
the output resistance without feedback R0 . The R0' will therefore be:
R0
R0' = … (6.27)
(1 + Aβ )
From equations (6.26) and (6.27), we get regulation as:
R0
% Regulation = x100
(1 + Aβ ) RL
Further Aβ > 1 we have:
R0
% Regulation = x100 … (6.28)
Aβ .RL
RL is the minimum value of load resistance. So the large amount of current can
be drawn from the regulator. But the commonly used operational amplifier can not
deliver large amount of current to the load. Operational amplifier 741 can deliver only a
maximum current of 56 mA. In order to get a large amount of current an emitter follower
circuit may be introduced at the output of the amplifier as shown in figure 6.20.

178
Fig. 6.20
The emitter follower circuit forms the current booster stage, as its voltage gain is
unity and the output resistance of the amplifier will be reduced by hfe times. So the
current will also be increased by the same amount. That is, to draw a load current of
about 0.5 A from the amplifier, only 5 mA will be drawn from the operational amplifier if
hfe of the transistor is 100.
If still larger current is required then another transistor may be connected in the
Darlington mode as shown in figure 6.21.

Fig. 6.21

6.4.2 Modified Zener Biasing


In the series regulator using operational amplifier discussed above (fig. 6.19) the
zener diode is biased with the unregulated d.c. voltage. When there is a change in the
unregulated d.c. voltage, the bias current in the zener diode will also change due to which
there will be small change in the reference voltage VZ depending upon the incremental
resistance rZ of the zener diode.
If ∆VZ is the change in zener voltage due to its biasing with unregulated d.c.
voltage, the change in the output ∆V0 will be:

179
 R 
∆V0 = 1 + 2 ∆VZ … (6.29)
 R1 
 R 
Thus the variation in the output is 1 + 2  times larger than the change in the
 R1 
reference voltage. This problem can considerably be reduced if the regulated output V0
itself is used to bias the zener diode as shown in figure 6.22. The working of this
regulator in which modified zener biasing is used will be discussed. The operational
amplifier is biased using the unregulated supply. When the power supply to the
operational amplifier is switched on, the zener diode will offer high resistance as the node
P is at zero potential. If there is any noise at the point P say + ∆V , then it will result an
 R 
output voltage of 1 + 2 ∆V . This voltage gets applied to the point P. Till the voltage
 R1 
at the point P is less than the break down voltage of the zener diode, it will offer high
resistance and draw a small amount of current. The voltage at the point P will therefore
be approximately equal to the output voltage. There is then a regenerative feedback and
as soon as the voltage at the point P becomes equal to the breakdown voltage of the zener
diode, it will conduct and provide a low resistance path. It results the reference voltage as
VZ at the point P, giving thereby the required output voltage as:
 R 
V0 = 1 + 2 .VZ … (6.30)
 R1 

Fig. 6.22
If on the contrary, the noise at the point P is small negative voltage say − ∆V ,
when the power to the regulator is switched on. The point P will become more and more
negative due to regeneration. The zener diode in this case will in forward bias and as
soon as this voltage becomes equal to the knee voltage of the diode and thus it will
provide a low incremental resistance. The regeneration is thus stopped and the voltage at
the point P will be constant and equal to Vγ . The output will correspond to this voltage
as:

180
 R 
V0 = 1 + 2 .Vγ … (6.31)
 R1 
This is also a constant voltage but it is not a desirable voltage. So in this circuit
there are two possibilities, one the output voltage is due to VZ and other due to Vγ . The
output voltage will be unpredictable as the output will depend on the noise at the point P,
when the power to the operational amplifier is switched on. The noise is a random
phenomenon and one cannot ensure a positive noise at the point P. However, to ensure a
positive noise at the point P and to get the constant output voltage corresponding to VZ,
the circuit may be modified as shown in figure 6.23. In this arrangement additional start
up unit comprising the resistances RA and RB and a diode D is connected.
In this circuit the value of the resistor RB is so chosen so that the voltage drop
across this resistance is always less than the breakdown voltage of the zener diode. When
the power supply to the operational amplifier is switched on, the start up arrangement
ensures that a positive voltage at the point P. As the circuit reaches the steady state the
diode D becomes in reverse bias thus having been disconnected with rest of the circuit.

Fig. 6.23
6.4.3 Short Circuit Protection
The regulated power supply gives constant output voltage at the specified load
current. If the load current more than the specified limit is drawn from the regulator, then
it leads the destruction of the power supply. So it is desirous to use an arrangement which
can protect the power supply for being damaged when the output terminals are
accidentally shorted or more than the specified limit of the current is drawn from the
supply. Such an arrangement, known as short circuit protection or current limit circuit, is
shown in figure 6.24. The transistor T2 and the resistors RSC and r constitute the current
limiting circuit. The working of this circuit may be explained as given below:

181
Fig. 6.24
The value of resistance RSC is so chosen that for the specified load current IL, the
voltage drop RSC.IL becomes equal to the cut-in voltage of emitter base junction of the
transistor T2. When the load current IL drawn from the supply is at a low or normal level
(i.e. within the specified limit), this current will also flow through the resistance RSC
which produces a voltage drop across it. In this case this voltage drop will not be
sufficient to conduct the transistor T2 and therefore this transistor has no effect on the
performance of the regulator. When more than the specified limit of load current is
drawn, the voltage drop RSC.IL across RSC becomes quite large to conduct the transistor T2.
So the collector current of this transistor flows through the resistance r, producing a
voltage drop which drives the regulator output to near zero. Due to which the operational
amplifier output will saturate to its positive level. The value of resistance r is chosen so
that the maximum current drawn from the operational amplifier does not exceed its limit
when the operational amplifier output is at the saturation level. Its value should not be
very large, otherwise in the normal operating range there will be excessive voltage drop
across resulting a low output voltage. Such short circuit protection is widely used in
integrated circuits.
6.5 SHUNT VOLTAGE REGULATOR USING OP-AMP
Figure 6.25 shows the circuit diagram of a shunt regulator using an operational
amplifier. The working of this circuit may be explained as given below. A fraction of the
 R1 
output voltage V0  is applied to the non-inverting input of the operational
 R1 + R2 
amplifier, which is compared by the zener voltage (reference voltage) connected to the
inverting input. The output of the operational amplifier is a positive voltage which is
proportional to (V0 − VZ ) .

182
Fig. 6.25
If somehow V0 decreases, the amplifier output decreases, the transistor T1
conducts less due to less flow of base current. The less conduction of the transistor T1
means the flow of collector current will small. Thus the small collector current is
diverted from the load current resulting thereby the increase in the output voltage. The
reverse trend will happen if the output voltage is increased. This way it keeps the output
voltage constant. The advantage of this regulator is that it has an inherent current limiting
V 
circuit. The load current can not be more than  i  , which is the current that would be
 R3 
flowing through the resistance R3 , if the output of the regulator short circuited. The
power dissipation in the resistor R3 will necessarily be large.

6.6 ADJUSTABLE VOLTAGE REGULATOR ICs


With the advent of integrated circuits it is possible to have the regulated power
supply in form of ICs. The regulator ICs are available in following three forms:
1. IC 723 Voltage Regulator
2. Three Terminal Adjustable Voltage Regulator IC
3. Three Terminal Voltage Regulator IC
Now the details of these regulator ICs will be discussed.
6.6.1 IC 723 Voltage Regulator
A commonly used integrated circuit regulator is IC 723. It is silicon monolithic IC
designed as completer regulator capable of giving an output voltage ranging from 2 to 37
volts at current up to 150 mA. The salient features of this regulator IC are as follows:
(i) It has good load and line regulation (approx. 0.03%).
(ii) It is designed to give regulated output voltage ranging from 2V to 37V at
current 150 mA.
(iii) The output current capacity can also be increased to 10A using the suitable
Darlington pairs of transistors.
(iv) Short circuit protection is provided to both input and output.
A block diagram of IC 723 is shown in figure 6.26. It consists of a temperature
compensated reference source with a voltage reference amplifier. The output of this
voltage reference amplifier is available as a Vref pin in the IC. A gain differential

183
amplifier with its non-inverting and inverting terminals available separately in the IC, it is
used as an error amplifier in the regulator. At the output of this error amplifier darlington
pair of transistors is connected which are used to act as current sensor/limiter to protect
the IC for short circuit.

Fig. 6.26
This IC 723 is available in TO – 5 package and 14 pin dual in line package (DIP).
The pin diagram of 14 pin DIP IC is shown in figure 6.27.

Fig. 6.27
A basic voltage regulator using IC 723 is shown in figure 6.28. The connection of
this circuit is straightforward. In this circuit the reference voltage Vref is fed to the non-
inverting input of the error amplifier. A fraction of the output voltage is fed to the
inverting input. The output voltage is given by:
 R 
V0 = Vref 1 + 2  … (6.32)
 R1 
The reference voltage is typically 7.5 V. The transistor T1 acts as emitter follower
capable of delivering large amount of current to the load. The resistance RSC is chosen to
limit the load current. A small capacitor of 500 pf is connected between the frequency
compensating terminal and the inverting terminal to vent closed loop instability of the

184
circuit. More transistors may be connected in Darlington mode to enhance the current
capabilities. By varying the resistor R2, the output voltage may be varied.

Fig. 6.28
6.6.2 Three Terminal Adjustable Voltage Regulator ICs
Another commercially available three terminal adjustable voltage regulator ICs
are LM 317. It has three terminals one terminal is the input terminal to which the
unregulated supply is applied. The second terminal is the adjustable terminal or the
ground terminal which is used as a control terminal. The third terminal is the output
terminal. The variable output voltage can be obtained by using the additional resistances.
Figure 6.29 shows the typical connection for three terminal adjustable voltage regulator
IC LM317. This IC gives the variable voltage from 1.2 V to 37 V with a current up to
1.5A.

Fig. 6.29
The output voltage V0 is given as:
V0 = R1 I 1 + R2 ( I adj + I 1 )
= (R1 + R2 )I 1 + R2 .I adj … (6.32)

185
Vref
and I1 = … (6.33)
R1
From the equations (6.32) and (6.33), we have:
Vref
V0 = (R1 + R2 ) + R2 .I adj
R1
 R 
= Vref 1 + 2  + R2 .I adj … (6.34)
 R1 
Here Vref is the reference voltage between the output and adjustable terminals and
its value is 1.25 V. The value of Iadj is constant and very small. The voltage drop across
R2 will also be very small and hence R2 .I adj may be neglected.
 R 
So V0 = 1.251 + 2  … (6.35)
 R1 
This equation indicates that the output voltage V0 is a function of R2 for a given
value of R1 and can be adjusted by varying the value of R2.
6.6.3 Three Terminal Fixed Voltage Regulator ICs
Recently three terminal fixed voltage regulator ICs are available which offer fixed
output voltages. These regulators are capable of supplying 0.5 to 1 A current to the load.
Such regulators have only three terminals: input (Vi), output (V0) and a ground terminal
and no other external feedback connections are required. The functional block diagram of
three- terminal (fixed) voltage regulator is shown in figure 6.30.

Fig. 6.30

186
In this circuit the error amplifier is a non-inverting amplifier which constantly
compares a fraction of the output voltage developed across R2 against the reference
voltage at its non-inverting terminal. The error amplifier controls the base drive of the
series pass transistor in such a way that the output voltage remains constant, thus
achieving regulation. The reference voltage Vref is a temperature stabilized voltage
developed by a zener diode or a band gap circuit. The band gap type voltage reference is
generally preferred and is shown in figure 6.31. This circuit works on the principle that
the two transistors operating at different currents develop a predictable voltage ∆VBE at
the emitter of T2.

Fig. 6.31
It is well known that:
KT I 
∆VBE = log 1  … (6.36)
q  I2 
This voltage has a positive temperature, is amplified and added to the base emitter
voltage of transistor T2, which has a negative temperature coefficient.
R
Vref = V3 + B ∆VBE … (6.37)
RA
R
If the gain B is properly adjusted, the negative temperature coefficient of V3
RA
can be made to cancel the positive coefficient of ∆VBE producing nearly zero temperature
drift.
The fixed voltage regulators have the built in protection circuits. These include
current limiting to limit peak output current, safe area protection to limit dissipation in
the series pass transistor and thermal shutdown to limit the junction temperature to a safe
value. Figure 6.32 shows the working of the protection circuit.
Current Limit: When Vi − V0 is less than the breakdown voltage of the zener diode, the
current flowing through R3 will be zero and only the base current of the transistor T1
flows through R4. This current is negligibly small and thus the voltage across the base
emitter voltage of the transistor T1 will be equal to the voltage across the resistance RSC.
This resistance is known as current sense resistor. If the output current of the regulator
increases, the voltage drop across the current sense resistor RSC increases until this

187
voltage is sufficient to conduct the transistor T1. As soon as the transistor T1 is ON, it will
prevent the additional base derive from reaching the series pass transistor T and thus the
output current is limited.

Fig. 6.32
Thermal Shut Down:
For the thermal shut down of the regulator a transistor known as thermal shut
down transistor T2 is used as shown in figure 6.32. At the normal temperature of the
regulator the base of the transistor T2 is biased at 0.4 V which is not sufficient to conduct
this transistor. In the regulator this transistor is physically located very close to the pass
transistor T, which is the major source of heat generation. As the temperature of the
regulator increases the base emitter voltage required to turn on the transistor T2 decreases.
As the regulator temperature reaches in the range 150 oC – 190 oC, the thermal shut down
occurs due to the conduction of the transistor T2. This transistor removes all the base
drives from transistor T and turn off the output. Now when the regulator cools down its
normal working will take place.
Safe Area Protection:
When (Vi − V0 ) is greater than the breakdown voltage of the zener diode, the
current proportional to (Vi − V0 ) will flow through R3, R4 and the zener diode to the
output. The base emitter voltage of the transistor T1 will be greater than the voltage
across the resistance RSC. The transistor T1 will therefore be ON at the lower output
current and the current limit point of the regulator reduces.
The rate of reduction of current limit with the increase in (Vi − V0 ) is given by:
∆I SC R4
= … (6.38)
∆(Vi − V ) R3 I SC

188
The safe area circuitry causes the maximum output current to drop significantly
for large (Vi − V0 ) .
Details of ICs:
In IC forms the three terminal (fixed) voltage regulators are positive and negative
voltage regulators. These are available in 78XX for positive regulators and 79XX series
for negative regulators. The last two digits (XX) of the series indicate the output voltage.
For example, voltage regulator IC 7815 indicates that it gives the fixed output of 15 volts;
similarly, 7912 represents that it fixed output is –12volts. The 78XX and 79XX series
are available in the following options (table 6.1).
Table 6.1
Positive voltage regulators Negative voltage regulator
Regulator No. Output voltage Regulator No. Output voltage
7805 +5V 7905 –5V
7806 +6V 7906 –6V
7808 +8V 7908 –8V
7812 +12V 7912 –12V
7815 +15V 7915 –15V
7818 +18V 7918 –18V
7824 +24V 7924 –24V
Figure 6.33 shows the basic circuit configuration of a three terminal regulator IC
78XX for getting the output voltage as XX. The capacitor Cin is required at the input side
of the regulator if the IC is located away from the power supply filter, to filter out the
effects of stray inductances of input wires. The capacitor C0 used at the output terminal to
improve the transient response of the regulator.

Fig. 6.33
Figure 6.34 illustrates to design the power supply of +12 V regulated (fixed)

Fig. 6.34
output. The maximum input voltage (unregulated) is given as 37 V and minimum is 2V
more than the output voltage i.e. for getting 12 V (IC7812), minimum input voltage is
between 14V to 35 V. Similarly, to get +5V from IC 7805, the unregulated voltage may
vary from 7V to 35V.

189
The negative voltage regulator ICs of 79XX series are also used in the similar
fashion with the difference that the input voltage (unregulated) will be negative voltage
and output will be – XX volts.
With the use of positive and negative IC regulators, the dual power supply can
also be obtained. Figure 6.35 shows circuit of a dual power supply of getting ± 15 V using
7815 and 7915 regulators.

Fig. 6.35
Current Regulator Using 78XX ICs:
The voltage regulator ICs 78XX series can also be used as current source capable
of delivering constant current to the load. Such current regulator circuit is shown in figure
6.36 in which voltage regulator IC is used.
From this figure the load current IL is given by:
V
I L = 1 + IQ … (6.39)
R1
Since the current regulator keeps the voltage V1 constant, the current IL will
therefore be constant. The variation of the quiescent current IQ is negligible comparative
to I1 so the circuit behaves as a current source.

Fig. 6.36
6.7 SWITCH MODE POWER SUPPLY (SMPS)
The linear power supplies discussed so far are designed with discrete components,
operational amplifiers or the voltage regulator ICs. These supplies have extremely good
line and load regulation and have also very low output ripple. The switch mode power
supply (SMPS) on the other hand operates on the different principle. It works on high

190
frequency ranging between 15 to 20 KHz. Hence the size of components at such high
frequency becomes smaller than that at low frequency. In SMPS the iron core
transformers are not used as they saturate at such high frequency but ferrite core
transformers are used. The ferrite core transformers not only have the higher
permeability but also available in the small size and weight. Due to the small size and
weight of the transformer, size and weight of the complete switch mode power supply is
not very large.
Figure 6.37 shows the functional block diagram of a switch mode power supply.
With reference to this figure the basic principle of this supply can easily be understood.
In this supply the input a.c. is first converted to unregulated d.c. The d.c. output is
chopped by switching elements operating at a rapid rate, typically 20 KHz. The resultant
20 KHz pulse train is transformer coupled to an output network which provides final
rectification and smoothing of the d.c. output. To regulate the supply a control circuit
varies the duty cycle of the switching elements (on-off periods).

Fig. 6.37
Figure 6.38 illustrates simplified circuit of a typical switch mode power supply
(SMPS). In this circuit a pair of transistors (T1 and T2) is used as switching elements
which operate under the control of feedback network. The feedback network consists of a
voltage comparison amplifier and a pulse width modulator. The voltage comparison
amplifier continuously compares a fraction of the output voltage with a reference voltage
(Vref); which develops a control voltage (Vcontrol) for the turn-on comparator. This control
voltage is further compared with a triangular ramp waveform by the turn-on comparator.
The ramp voltage is occurring at 40 KHz frequency. When the ramp voltage is more
positive than the control level, a turn-on signal is generated. Any increase or decrease in
the control voltage will vary the width of the turn-on voltage which in turn alters the
width of drive pulses to both the transistors T1 and T2. The steering logic ensures the
alternately switching of the transistors T1 and T2. Each transistor thus operates at 20 KHz
frequency. When the transistor T1 is ON, current flows in the upper half of the primary
windings of the transformer and completes its path through the center tap terminal.
Similarly, when the transistor T2 is ON, current flows in the opposite direction in the
lower half of the transformer winding, thus providing the transformer action. The wave
forms of the supply at various points are given in figure 6.39, for supporting the action of
the supply. In this circuit control voltage automatically monitors the duty cycle to
maintain the output voltage constant.

191
Fig. 6.38

Fig. 6.39

The advantages of SMPS are as follows:

192
(i) Efficiency of the switch mode power supplies is very high; it ranges from 65
to 85% as compared to linear power supplies whose efficiencies lies
between 30 to 45%. The high efficiency is due to smaller heat dissipation as
switching transistors are continuously on and off.
(ii) On account of the higher switching rate, the sizes of transformer, inductor
and filter capacitors are very small. The overall weight and size of SMPs are
small compared to the linear power supplies.
(iii) The input ripple is less of a problem in SMPs as compared to linear power
supplies.
The disadvantages of this supply are:
(i) Due to fast switching action, there is electromagnetic interference (EMI).
This can however be eliminated by using the proper shielding.
(ii) The control circuitry is expensive, quite complex and somewhat less
reliable.

Example 6.4 A voltage regulator using operational amplifier shown in figure 6.40 is
capable of supplying a current up to 200 mA. The output resistance and open loop gain
of the operational amplifier are 400 Ω and 104 respectively. The hfe of the transistor is
100. Find the output voltage and load regulation of the regulator if feed back resistances
are of equal magnitude and VZ = 6V.

Fig. 6.40
Solution. The output voltage V0 is given by:
R
V0 = VZ (1 + 2 )
R1
= 6 x(1 + 1) = 12V
Since R1 = R2 .
The load resistance of the regulator is given by:
V 12V
RL = 0 =
I L 200mA
= 60Ω
The output resistance of the regulator at the emitter of the transistor is given by:

193
R0 400
R0emitter = = = 4Ω
h fe 100
Due to feedback in the operational amplifier the output resistance decreases by
(1 + Aβ) times.
So the output resistance of the regulator becomes:
R
R0 f = 0 emitter
(1 + Aβ )
R1
where β= = 0.5
R1 + R2
4Ω
R0 f = 4 = 8 x10 −4 Ω
10 x0.5
R0 f
Load regulation = x100
RL
8 x10 −4 x100
= = 0.008%
60
Example 6.5 A voltage regulator, using operational amplifier and short circuit
protection shown in figure 6.41, is capable of supplying an output of 16V current up to
200 mA. The short circuit protection is also provided for this current. The unregulated
voltage is 24 Volts, VZ = 8 volts, RZ =15Ω and IZ.=20 mA. If the value of resistance R1 =
10 KΩ, find the values of resistances r, R2 , RS and RSC . Find the value of ripple content
at the output, if 1 volt (r.m.s.) ripple exist on the unregulated voltage.

Fig. 6.41
Solution. To bias the zener diode at a current of 20 mA, we have:
V − VZ (24 − 8)V
RS = i =
IZ 20mA
16V
= = 800Ω
20mA
The output voltage is given by:

194
R2
V0 = VZ (1 + )
R1
R
or 16 = 8(1 + 2 )
R1
So R2 = R1 = 10 KΩ
For short circuit protection, voltage across RSC should be 0.6 V for maximum
load current:
RSC .I L max = 0.6V
0.6V
or RSC = = 3Ω
200mA
The value of r may be chosen so that when the output is short circuited, the
amount of current drawn from the operational amplifier should not be more that 56 mA
of current. When output is short circuited, the operational output may saturate at 24V.
24V
So < 56mA
r
24V
or <r
56mA
or r > 429Ω
It may be taken as 1 KΩ.
The ripple across the zener diode is given by:
VZ RZ
V ripple ( zener ) =
(RS + RZ )
1Vx15
= = 18.4mV
(800 + 15)
The ripple at the output of regulator is given by:
R
V0 ( ripple) = Vripple( zener ) (1 + 2 )
R1
V 0 ( ripple ) = 18 . 4 x 2 = 36 . 8 mV
The percentage ripple is given by:
V0( ripple) 36.8mV
= x100 = x100
V0 16
= 0.23%

PROBLEMS

1. What is difference between an unregulated and regulated power supplies? Explain


the terms: stability factor, output resistance and temperature coefficient of a
regulated power supply. Discuss also the percentage regulation.
2. What is the difference between a series and shunt voltage regulators? Discuss
with the help of a function block diagram, the basic principle of a series voltage

195
regulator. Draw the circuit of a simple series voltage regulator and explain its
working.
3. Draw and discuss the circuit of a simple series voltage regulator. How regulated
output voltage is obtained with this circuit? Calculate the expression of its output
resistance.
4. Draw and discuss the circuit of improved series voltage regulator.
5. Explain the circuit of feedback type series voltage regulator and calculate the
expression of its output resistance.
6. Show that the output resistance of a feedback type series voltage regulator (fig.6.9
in the text) is given by:
R + hie1
r0 + S
(1 + h fe1 )
R0 ≅
1 + Gm (r0 + RS )
The symbols have their usual meanings.
7. Discuss with the help of a function block diagram, the basic principle of a shunt
voltage regulator. Draw the circuit of a zener diode shunt voltage regulator and
explain its working.
8. Draw and explain the circuit of BJT shunt voltage regulator.
9. Draw and discuss the circuit of improved BJT shunt voltage regulator.
10. Discuss how the regulated output voltage is obtained using series voltage
regulator using operational amplifier. Find the expression for the percentage
regulation of this circuit.
11. How a large amount of current can be drawn from the circuit of series voltage
regulator using operational amplifier?
12. Discuss the modified zener biasing of series voltage regulator using operational
amplifier. How the start up circuit is used in such a regulator.
13. Discuss how the short circuit protection is provided in series voltage regulator
using operational amplifier.
14. Describe the circuit of a shunt voltage regulator using operational amplifier.
15. Draw and explain the internal block diagram of a voltage regulator IC 723. How
can this IC be used to get the variable (adjustable) output voltage?
16. Explain how the three terminal adjustable voltage regulator IC LM 317 is used to
get the adjustable output voltage.
17. Draw the internal functional block diagram of three terminal fixed voltage
regulator ICs 78XX series. Explain the band gap circuit for getting the reference
voltage inside this 78XX series of voltage regulators.
18. Explain the circuits of current limit, thermal shut down and safe area protection
used in the functional block diagram of three terminal fixed voltage regulator ICs
78XX series.
19. Draw the circuit for getting the ± 15 volts regulated power supply by using 7815
and 7915 ICs.
20. What is the basic principle of a switch mode power supply (SMPS)? Explain with
a suitable circuit diagram the operating principle of such a power supply. Mention
its merits and demerits.

196
21. Calculate the output voltage and zener current in the simple series regulator
circuit shown in figure 6.18. The load resistance RL is 1 KΩ. The hfe of the
transistor is 50. (Ans.: 5.3 V, 5.2 mA)
22. A zener diode shunt regulator supplies a load current which varies from 0 to 200
mA at 8.2 V. The input to the regulator varies from 12 V to 18 V. The zener diode
stabilizes to a minimum current of 15 mA. Calculate the value of series resistance
RS and the power rating of the zener diode. (Ans.: 15 Ω, 5.4W)
23. A voltage regulator using operational amplifier shown in figure 6.40 is capable of
supplying 10 V a current up to 100 mA. The output resistance and open loop gain
of the operational amplifier are 500 Ω and 104 respectively. The hfe of the
transistor is 50. Find load regulation of the regulator if feed back resistances are
of equal magnitude and VZ = 5V. (Ans. 0.002%)
24. A voltage regulator, using operational amplifier and short circuit protection
shown in figure 6.41, is capable of supplying an output of 12V current up to 100
mA. The short circuit protection is also provided for this current. The unregulated
voltage is 20 Volts, VZ = 6 volts, RZ =10Ω and IZ.=10 mA. If the value of
resistance R1 = 20 KΩ, find the values of resistances r, R2 , RS and RSC . Find the
value of ripple content at the output, if 1 volt (r.m.s.) ripple exist on the
unregulated voltage.

__________

197
7
Sinusoidal Oscillators
Oscillators convert d. c. electrical power into a. c. power. It produces the wave
forms of different frequencies and shapes. In general there are two categories of
oscillators: namely sinusoidal oscillators and relaxation oscillators. The sinusoidal
oscillators produce the sinusoidal signals of fixed frequencies, where as non-sinusoidal
signal (such as square, saw tooth wave shapes etc.) are produced in the relaxation
oscillators. In this chapter different types of sinusoidal oscillators with their design and
working principle will be discussed. Positive feedback is used in oscillator circuits and
the oscillators may be designed using the bipolar junction transistors, field effect
transistors or the operational amplifiers.
7.1 PRINCIPLE OF OPERATION
It is well known that the amplifiers are generally used with negative feedback.
The gain of the amplifier with negative feedback is given by:
 A 
A f =   … (7.1)
 1 + Aβ 
where A is the gain of amplifier without feedback and β is the feedback factor.
In oscillators the positive feedback is applied, which will later on be illustrated. If
the feedback is so connected that the feedback voltage is in phase with the externally
applied input voltage, then the positive feedback is said to exist and the gain of the
amplifier is given by:
 A 
A f =   … (7.2)
 1 − Aβ 
From this equation it is clear that if loop gain (Aβ) is equal to unity, then gain
with feedback will become infinite. In this case the amplifier will give an output even in
the absence of the input voltage i.e. the amplifier will become an oscillator. The condition
of unity loop gain is known as Berkhausen criterion.
In general A and β are in complex nature and are the functions of frequency, so A
is written as A ∠θ and β is written as β ∠ φ . In positive feedback, the feedback
voltage should be in phase with the input voltage.
So for Aβ = 1 means
( A ∠ θ )( β ∠ φ ) = A β ∠ (θ + φ ) = 1∠ 0
Thus the basic conditions for oscillations are:
(i) the magnitude of the loop gain must be equal to unity, and
(ii) the loop phase shift must be zero.
Consider the block diagram shown in figure 7.1(a), to analyze the positive
feedback amplifier in a more illustrative way. Let eS is an external input voltage applied
to an amplifier. When there is no feedback, input voltage to the amplifier ei is equal to
eS . The output voltage e0 will be equal to AeS , where A is the gain of the amplifier. Now
the feedback is applied so that a fraction of the output voltage β e0 is added to the
externally applied signal eS . The input voltage to the amplifier increases to
ei = eS + β .e0 . This voltage will further be amplified by A times.
So that e0 = A(eS + β .e0 ) … (7.3)
or e0 (1 − Aβ .e0 ) = AeS
e0  A 
or Af = = 
eS  1 − Aβ 
which is the equation 7.2.
If the external voltage is put equal to zero (as shown in figure 7.1b), the equation
7.3 reduces to e0 = Aβ .e0
or Aβ = 1

(a)

Fig. 7.1
(b)

199
So in the absence of external input if the amplified output of the feedback voltage
becomes equal to the previous output then Aβ = 1 and A f → ∞ . The circuit will tend to
oscillate and sustained oscillation (shown in figure 7.2 a) will be obtained.
If Aβ > 1 , the amplifier input voltage will go on increasing and becomes
infinitely large. In this case the sustained oscillations will be produced but amplitude will
grow till saturation type non-linearity arises (ref. figure 7.2b).
If Aβ < 1 , transient oscillations will be produced but will not be sustained. In this
case each succeeding cycle feedback from the output will be less than the one preceding
it and hence oscillations will decay (ref. 7.2c).

Fig. 7.2
In the positive feedback amplifier, when no external signal is applied, a noise at
the output will be available. The noise originates due to biasing of the amplifying device
when power is switched on. The noise has the wide range of frequencies i.e. it contains
all possible sinusoidal frequencies; out of these frequencies a particular frequency is
selected. So for the selection of particular frequency a frequency selector circuit should
be incorporated in the oscillator. Usually LC or RC network is provided for this purpose.
So the amplifier circuit, the frequency selector circuit and the feedback network
(positive) would provide infinite gain at the desired frequency and sustained oscillations
will be obtained. But if due to any reason (power supply variation, temperature variation
etc.) the amplitude of the sinusoidal output increases (or decreases), it would continue to
increase (or decrease) due to feedback arrangement and thus steady state will not be
reached. In order to remove this difficulty an automatic amplitude controller may also be
incorporated with amplifier or with the frequency selector circuit. The oscillator circuit
consisting of these four blocks is shown in figure 7.3. In usual practice the frequency
selector and the automatic amplitude controller could be considered as part of either ante
amplifier or the feedback network.

200
Fig. 7.3
7.2 NEGATIVE RESISTANCE
The behaviour of oscillator circuits can also be understood in terms of the concept
of negative resistance. A negative resistance is provided to compensate for the losses in
the circuit. The positive feedback can be considered as a way to synthesize a negative
resistance in the circuit. Such oscillators, in which the mode of operation is negative
resistance, are known as negative resistance oscillators. In the negative resistance
oscillators the internal positive feedback provides the required negative resistance. In
order to understand the concept of negative resistance, consider the circuit shown in
figure 7.4(a).

(a) (b)
Fig. 7.4
In this circuit the operational amplifier is used in the non-inverting configuration,
having two equal resistances ( R1 ) in the feedback path.
The gain of this circuit is given by:
e
Af = 0
ei
 R 
= 1 + 1  = 2 … (7.4)
 R1 
A resistance R is connected between the output terminal and the non-inverting
terminal of the operational amplifier. In this circuit one can see that at the input there is
an input voltage ei and at the output there is 2ei voltage. The voltage across the resistance
R will be equal to ei with the polarity shown in the figure. Since the output is at higher

201
ei
potential so the current I = will be flowing back to the input terminal. A negative
R
resistance of magnitude R, therefore, seems to be present at the input of the amplifier.
This can also be proved by applying the Miller’s theorem at the input. According to
Miller’s theorem the resistance R may be removed and a resistance R ' is supposed to be
connected between the non-inverting terminal and the ground (as shown in figure 7.4 b).
The magnitude of R ' is given by:
R R
R' = = = −R … (7.5)
1− A 1− 2
i.e. it offers the negative resistance in the circuit.

7.3 CLASSIFICATION OF OSCILLATORS


The oscillators may be classified according to frequency range of operation as
given in table 7.1.
Table 7.1

The oscillators may further be classified into the following types:


1. RC Oscillators
2. LC Oscillators
3. Crystal Oscillators
The important RC oscillators include RC phase shift oscillator and Wien-bridge
oscillators. The Hartley and Colpitt’s oscillators fall in the category of LC oscillators. All
these oscillators will now be discussed in detail in the following sections of this chapter.
7.4 R C PHASE SHIFT OSCILLATOR
Figure 7.5 shows the circuit diagram of a phase shift oscillator. It consists of an

Fig. 7.5
RC network connected to a field effect transistor in common source configuration. One
RC network can produce a maximum phase shift of 90o at an infinite frequency. So to
have a phase shift of 180o at finite frequency, three RC networks are needed. The active

202
device, the field effect transistor also produces a phase shift of 180o. Thus a total phase
difference of 360 or 2π may be obtained with the arrangement shown in figure 7.5. Thus
at a particular frequency the circuit will oscillate, provided the amplification of the
common source amplifier is sufficiently large. The frequency at which the circuit will
oscillate is known as frequency of oscillation. Now we shall calculate the frequency of
oscillation of this RC phase-shift oscillator. For this small signal equivalent circuit of this
oscillator is shown in figure 7.6.

Fig. 7.6
To calculate the feedback factor of this circuit, the RC network is redrawn as shown in
figure 7.7.

Fig. 7.7
We get the network equation of this circuit as:
( R − j ω .C ) −R 0   I 1  V0 
 −R (2 R − j ω .C ) −R  I  =  0  … (7.6)
  2   
 0 −R (2 R − j ω .C )  I 3   0 
The current I 3 may be calculated as:
( R − j ω .C ) −R V0
−R (2 R − j ω .C ) 0
0 −R 0
I3 = … (7.7)
( R − j ω .C ) −R 0
−R (2 R − j ω .C ) −R
0 −R (2 R − j ω .C )
V0 ( R 2 )
=
or
( )
( R − j ω .C ) (2 R − j ω .C ) − R 2 + R(− R (2 R − j ω .C ) )
2

203
V0 ( R 2 )
=
or
( ) (
( R − j ω .C ) 3R 2 − 1 (ω .C ) − (4 jR ω .C ) − 2 R 3 + jR 2 ω .C )
2
)
Put α = (1 ω .C.R )
V0 ( R 2 )
I3 =
( )
So we have:
(1 − jα )(3 − α 2 − 4 jα ) − 2 + jα R 3
'
The voltage V is obtained by multiplying the current I 3 by resistance R in the
f

third loop, i.e.


V0
V f' = I 3 R =
( )
… (7.8)
(1 − jα )(3 − α − 4 jα ) − 2 + jα
2

 V f' 
The transfer function   of the RC network is given from equation 7.8 as:
 V0 
 
'
Vf 1
=
V0 1 − 5α − 6 jα + jα 3
2

The negative of the feedback factor which is equal to the transfer function is given
by:
V f' 1
−β = = … (7.9)
V0 1 − 5α − j (6α + α 3 )
2

The feedback factor will be real (or phase shift will be 180 o) if
α2 = 6 or α= 6 …(7.10)
1 1
or ω= or f = … (7.11)
6 RC 2π 6 RC
This is known as the frequency of oscillations of this RC phase shift oscillator.
Putting the value of α from equation (7.10) in equation 7.9, we get:
1
β=
29
The minimum gain A of the amplifier required for the circuit to oscillate should
be at least 29 as A β ≥ 1 . Hence the amplification factor of the field effect transistor
should not be less than 29.
7.4.1 Transistor Phase Shift Oscillator
In the RC phase shift oscillator a transistor in common emitter configuration may
be used as an active element. Figure 7.8 shows such an oscillator circuit. In this oscillator
three RC networks are used in the feedback path to produce a phase shift of 180o at finite
frequency. Further a phase shift of 180o is produced by the transistor amplifier. Thus a
total phase difference of 360 or 2π may be obtained with this arrangement also. In the
phase shift oscillator using a transistor as the active element, voltage shunt feedback is
used instead of voltage series feedback as is done in case of RC phase shift oscillator
using field effect transistor. In this circuit R1, R2 and RE are used to bias the emitter base
and collector base junctions of the transistor. The capacitor CE is the bye pass capacitor to
keep the emitter at the signal ground. The series combination of the resistances R3 and Ri

204
form the resistance R of the third loop. The resistance Ri is input resistance of the
transistor which is approximately equal to hie.

Fig. 7.8
For the purpose of analyzing this circuit, we redraw the approximate h-parameter
model for the transistor (neglecting hoe and hre) as shown in figure 7.9. We assume that
the current IB enters the base of the transistor and the loop current gain (I 3 I B ) is
calculated.

Fig. 7.9
To get the network equation of this circuit, the current source HfeIB is converted
to a voltage source (Thevenin’s equivalent) as shown in figure 7.10.

Fig. 7.10
We now get the network equation of the circuit shown in figure 7.10 as:

205
( RC + R − j ω .C ) −R 0   I 1  − h fe I B RC 
 −R (2 R − j ω .C ) −R I  =  0  … (7.12)
  2   
 0 −R (2 R − j ω .C )  I 3   0 

The current I3 is given by:


( RC + R − j ω .C ) −R − h fe I B RC
−R (2 R − j ω .C ) 0
0 −R 0
I3 =
( RC + R − j ω .C ) −R 0
−R (2 R − j ω .C ) −R
0 −R (2 R − j ω .C )
− h fe I B RC R 2
=
or
( ) (
( RC + R − j ω .C ) 3R 2 − 1 (ω .C ) − (4 jR ω .C ) − 2 R 3 + jR 2 ω .C )
2
)
− h fe I B RC R 2

=
or
( ) (
R( RC R + 1 − j ω .CR ) 3R 2 − 1 (ω .C ) − (4 jR ω .C ) − 2 R 3 + jR 2 ω .C )
2
)
… (7.13)
Put (RC R ) = K and α = (1 ω .C.R ) in the equation (7.13), we get:
− h fe I B K
I3 = … (7.14)
( K + 1 − jα )(3 − α 2 − 4 jα ) − 2 + jα
I3 − h fe K
or =
I B ( K + 1 − jα )(3 − α 2 − 4 jα ) − 2 + jα
− h fe K
=
1 + 3 K − α ( K + 5 ) − j (( 6 + 4 K )α − α 3 )
or 2
… (7.15)

The factor (I 3 I B ) will be real if:


(6 + 4 K )α = α 3 or α 2 = 6 + 4K
2
 1 
or   = 6 + 4K
 ω CR 
1 1
or ω=
CR 6 + 4 K
1 1
or f = … (7.16)
2 π CR 6 + 4K
This is the expression for frequency of oscillation. For sustained oscillation, as per
Barkhausen criterion, the magnitude of the loop current gain (I 3 I B ) should be greater
than unity. So put α 2 = (6 + 4 K ) in equation (7.15) we get:
I3 − h fe K
=
I B (1 + 3 K ) − α 2 ( K + 5)

206
I3 − h fe K
or =
I B (1 + 3 K ) − ( 6 + 4 K )( K + 5 )
I3 − h fe K
or =
IB − 23 K − 4 K 2 − 29
I3 h fe
or = >1
IB 29
23 + 4 K +
K
 29 
or h fe >  23 + 4 K +  … (7.17)
 K 
From this equation (7.17), one can find that the minimum value of hfe will be
obtained for K = (RC R ) = 2.7 . The value of hfe for this value of K will be 44.5. It is
concluded that the transistor whose short circuit current gain (hfe) is less than 44.5 can not
be used in this phase shift oscillator.
7.4.1 Operational Amplifier Phase Shift Oscillator
The operational amplifier can also be used as an active element in the design of
RC phase shift oscillator. Such an oscillator circuit a transistor is shown in figure 7.11. In
this oscillator too three RC networks are used to produce a phase shift of 180o at finite
frequency. Further a phase shift of 180o is produced by an inverting amplifier. Thus a
total phase difference of 360 or 2π is obtained. The similar analysis, as in the case of
phase shift oscillator using field effect transistor, can be made to calculate the frequency
of oscillation.

Fig. 7.11

The frequency of oscillation will be given by:


1
f =
2π 6 RC
At this frequency the feedback factor β will be:
1
β=
29

207
The minimum gain A of the amplifier required for the circuit to oscillate should
be at least 29 as A β ≥ 1 . This gain is obtained by the non-inverting amplifier. The
frequency of oscillations can be changed by the values of R’s or C’s.
Example 7.1 A two stage phase shifting network shown in figure 7.12 is used in a FET
oscillator. Show that the frequency of oscillation of this oscillator is given by
1
f =
2πRC
and the gain must exceed 3.

Fig. 7.12
Solution. We get the network equation of this circuit as:
( R − j ω .C ) j ω .C   I 1  V0 
= … (718)
 j ω .C
 ( R − 2 j ω .C )  I 2   0 
The current I 2 may be calculated as:
( R − j ω .C ) V0
( j ω .C ) 0
I2 =
( R − j ω .C ) ( j ω .C )
( j ω .C ) ( R − 2 j ω .C )

− V0 ( j ω .C )
=
( )
or
( R − j ω .C ) ( R − 2 j ω .C ) + 1 ω 2 C 2
− V0 ( j ω .C )
= 2
( )
or
R − (2 jR ω .C ) − ( jR ω .C ) − (2 ω 2 C 2 ) + (1 ω 2 C 2 )
V0 jω .C
= 2
( )
or
R − (3 jR ω .C ) − (1 ω 2 C 2 )
V0
=
or
(
jω .CR + 3R − ( j ω .C )
2
) … (7.19)

V0 R
V f' = I 2 R =
( )
Also
jω .CR + 3R − ( j ω .C )
2

V0
or = … (7.20)
(3 + j (ω .CR − (1 ω .CR) )
V f' 1
or = … (7.21)
V0 (3 + j (ω .CR − (1 ω .CR) )

208
The imaginary part will be zero if:
1
ω .CR =
ω .CR
1 1
or ω2 = 2 2 or f =
C R 2π RC
V0
At this frequency the gain should be 3 as = 3 (equation 7.21). Proved.
V f'
Example 7.2 Show that a two stage phase shifting network shown in figure 7.13 can not
produce 180o phase shift at finite frequency.

Fig. 7.13

Solution. We get the network equation of this circuit as:


( R − j ω .C ) −R   I 1  V0 
= … (7.22)

 −R (2 R − j ω .C )  I 2   0 
The current I 2 may be calculated as:
( R − j ω .C ) V0
−R 0
I2 =
( R − j ω .C ) −R
−R ( R − 2 j ω .C )
V0 R
=
( )
or
( R − j ω .C ) (2 R − j ω .C ) − R 2
V0 R
=
( )
or
2 R − ( jR ω .C ) − (2 jR ω .C ) − (1 ω 2 C 2 ) − R 2
2

V0 R
= 2
( )
or … (723)
R − (3 jR ω .C ) − (1 ω 2 C 2 )
2
V0 R
V f' = I 2 R =
( )
Also
R − (3 jR ω .C ) − (1 ω 2 C 2 )
2

'
V 1
=
f
or
V0 (
1 − (3 j ω .CR ) − (1 ω 2 C 2 R 2 ) )
… (7.24)

1
In order to have a phase shift of 180o, one should have as zero or infinite. If
ω .CR

209
1 V f'
is zero, than will be one and phase shift will be zero not 180o. So it is not
ω .CR V0
possible to produce a phase shift of 180o at the finite frequency.
V f'
Example 7.3 (a) Show that the ratio for the three stage RC phase shifting network
V0
shown in figure 7.14 is given by:
V f' 1
=
V0 (
1 − (5 α ) + j (6 α − 1 α 3 )
2
)
6
and frequency of oscillations is given by: f =
2π RC
where α = (1 ω .C.R ) .
(b) If this network is used with a field effect transistor, the gain required for oscillation is
29.

Fig. 7.14
Solution. (a) The network equation of this circuit is given by:

( R − j ω .C ) j ω .C 0   I 1  V0 
 j ω .C ( R − 2 j ω .C ) j ω .C   I 2  =  0  … (7.25)

 0 j ω .C ( R − 2 j ω .C )  I 3   0 
The current I 3 may be calculated as:
( R − j ω .C ) j ω .C V0
j ω .C ( R − 2 j ω .C ) 0
0 j ω .C 0
I3 =
( R − j ω .C ) j ω .C 0
j ω .C ( R − 2 j ω .C ) j ω .C
j ω .C ( R − 2 j ω .C )
− V0 (1 ω 2 .C 2 )
=
or
( )
( R − j ω .C ) ( R − 2 j ω .C ) + (1 ω 2 .C 2 ) − ( j ω .C ) (( j ω .C ) ( R − 2 j ω .C ) )
2

− V0 (1 ω .C ) 2 2
=
( )
or
R − (6 R ω .C 2 ) − (5 jR 2 ω .C ) + ( j ω 3 .C 3 )
3 2

210
− V0 (1 ω 2 .C 2 R 3 )
=
(
1 − (6 ω 2 .C 2 R 2 ) − (5 j ω .CR ) + ( j ω 3 .C 3 R 3 ) )
Put α = (1 ω .C.R )
− V0 (α 2 R)
I3 =
( )
So we have: … (7.26)
1 − 6α 2 − 5 jα + jα 3
The voltage V f' is obtained by multiplying the current I 3 by (− j ω C ) in the
third loop, i.e.
jV0α 3
V f' = I 3 R =
( )
… (7.27)
1 − 6α 2 − 5 jα + jα 3
 V f' 
The transfer function   of the RC network is given from equation 7.27 as:
 V0 
 
'
Vf 1
=
( )
… (7.28)
V0 1 − (5 α ) + j (6 α − 1 α 3 )
2

The feedback factor will be real (or phase shift will be 180 o) if
1 6 1
= or = 6
α
3
α α
6 6
or ω= or f = … (7.29)
RC 2π RC
This is known as the frequency of oscillations of this RC phase shift oscillator.
(b) Putting the value of α from equation (7.29) in equation 7.28, we get:
V f' 1
=
V0 29
The minimum gain A of the amplifier required for the circuit to oscillate should
be at least 29.
Example 7.4 (a) Show that the input impedance of the network given in figure 7.15 is
 1 − 5α 2 − j (6α − α 2 ) 
given by: Z i = R 
 3 − α 2 − 4 jα 
where α = (1 ω .C.R ) .
(b) Show that the input impedance at the frequency of oscillation α = 6 is given by:
Z i = (0.83 − j 2.70) R

Fig. 7.15

211
V0
Solution. (a) The input impedance Z i = can be obtained if the network equation is
I1
solved for I1.
The network equation will be same as given in equation (7.6), which is
rewritten here as:
( R − j ω .C ) −R 0   I 1  V0 
 −R (2 R − j ω .C ) −R  I  =  0  … (7.30)
  2   
 0 −R (2 R − j ω .C )  I 3   0 
The current I 1 may be calculated as:
V0 −R 0
0 (2 R − j ω .C ) −R
0 −R (2 R − j ω .C )
I1 =
( R − j ω .C ) −R 0
−R (2 R − j ω .C ) −R
0 −R (2 R − j ω .C )

=
(
V0 (2 R − j ω .C ) − R 2
2
)
or
(
( R − j ω .C ) (2 R − j ω .C ) − R + R(− R (2 R − j ω .C ) )
2 2
)
=
(
V0 3R − 1 (ω .C ) − (4 jR ω .C )
2 2
)
or
(
( R − j ω .C ) 3R − 1 (ω .C ) − (4 jR ω .C ) − 2 R 3 + jR 2 ω .C )
2 2
) ( )
Put α = (1 ω .C.R )

I1 =
(
V0 R 2 3 − α 2 − 4 j α )
( )
So we have:
(1 − jα )(3 − α 2 − 4 jα ) − 2 + jα R 3

=
(
V0 3 − α − 4 jα 2
)
( )
… (7.31)
(1 − 5α 2 ) − j (6α − α 3 R
V
The input impedance Z i = 0 is given by:
I1
V0  (1 − 5α 2 ) − j (6α − α 2 ) 
Zi = = R  … (7.32)
I1  3 − α 2 − 4 jα 
Proved.
(b) Now the input impedance at the frequency of oscillation can be obtained by
putting α = 6 in equation (7.32). It is given by:
 (1 − 30) − j (6 6 − 6 6 ) 
Z i = R 

 3 − 6 − j 4 6 
 − 29 
= R 

 − 3 − j4 6 

212
 29 (3 − j 4 6 ) 
= R 

 (3 + j 4 6 ) (3 − j 4 6 ) 
 29 
= R (3 − j 4 6 )  … (7.33)
 105 
Z i = (0.83 − j 2.70) R Proved.
It may be noted from this equation that the input impedance remains constant if
the capacitance C is varied to vary the frequency of oscillations. However, if the
resistance R is varied the input impedance will also vary.
7.5 THE WIEN BRIDGE OSCILLATOR
The Wein bridge oscillator falls in the category of RC oscillator. It consists of a
bridge known as Wein Bridge which has a parallel combination of one arm and a series
combination in an adjacent arm. Such a bridge is shown in figure 7.16. The parallel arm
contains the parallel combination of a resistance R3 and a capacitance C3 and the series
arm, however, contains the series combination of a resistance R4 and a capacitance C4.
The ratio arms of the bridge contain resistances R1 and R2. The impedance Z3 of the
parallel arm is given by:
R3 (1 jω .C3 )
Z3 =
(R3 + (1 jω .C3 ) )
R3
= … (7.34)
(1 + jω .C3 R3 )
The impedance Z4 of the series arm is given by:
j
Z 4 = R4 − … (7.35)
ω .C 4

Fig. 7.16
R1 Z 4
The bridge will be balance when = … (7.36)
R2 Z 3
From equations (7.34) to (7.36), we have:

213
j
R4 −
R1 ω .C 4
=
R2 R3
(1 + jω .C3 R3 )
 
(1 + jω .C3 R3 ) R4 − j

R1  ω .C 4 
or =
R2 R3
jR2 C R R
or R1 R3 = R2 R4 − + jω .C3 R3 R2 R4 + 3 2 3
ω .C 4 C4
Comparing the imaginary parts, we get:
R2
= ω .C 3 R3 R2 R4
ω .C 4
1
or ω2 =
C 3 R3 R2 R4
1 1
or ω= or f =
C 3 R3 R2 R4 2π C 3 R3 R2 R4
If R3 = R4 = R (say) and C 3 = C 4 = C (say) then
1
f0 = … (7.37)
2 π RC
This is frequency of oscillations. Thus the Wein Bridge can be used as a

Fig. 7.17

214
frequency selective network to have the sustained oscillations. This bridge can be
connected with an operational amplifier as shown in figure 7.17 and the circuit will be
called as Wein bridge oscillator.
Let us now analyze the circuit. The feedback factor is given by:
V V − V1 V2 V1
−β = i = 2 = − … (7.38)
V0 V0 V0 V0
VZ V2 Z3
We have V2 = 0 3 or = … (7.39)
Z3 + Z4 V0 Z 3 + Z 4
V R V1 R2
and V1 = 0 2 or = … (7.40)
R1 + R2 V0 R1 + R2
From equations (7.38) to (7.40), we get:
 Z3 R2 
Vi = V2 − V1 = V0  −  … (7.41)
 Z 3 + Z 4 R1 + R2 
Z3 R2
and −β = − … (7.42)
Z 3 + Z 4 R1 + R2
The expressions for Z3 and Z4 at frequency of oscillation are given by:
R R
Z3 = = (1 − j ) … (7.43)
(1 + jω .CR ) 2
j  j 
Z4 = R − = R 1 − 
ω .C  ω .CR 
= R(1 − j ) … (7.44)
From equations (7.41) through (7.44), we have:
 R 
 (1 − j )
2 R2 
Vi = V0  − 
 (1 − j ) R + R(1 − j ) R1 + R2 
 2 
1 R2 
= V0  −  … (7.45)
 3 R1 + R2 
1 R2 
and −β = −  … (7.46)
 3 R1 + R2 
The bridge will be balanced when R1 and R2 are so chosen so that Vi is zero. From
 R2  1
equation (7.45) it is clear that Vi = 0 when   = or R1 = 2 R2 .
 R1 + R2  3
From the equation (7.46) it is clear that the phase of the feedback factor is zero (as
required) since it is real quantity at the frequency of oscillation. But the magnitude of β
 R2  1
should not be zero, for this   < or R1 > 2 R2 .
 R1 + R2  3
If R1 > 2 R2 , the gain of the amplifier will be greater than 3 and Aβ > 1 . The
circuit will, however, oscillate but saturation type of non-linearity will be introduced in

215
the output and output will not be exactly sinusoidal. At R1 = 2R2 , the bridge will be
balanced and Vi will be zero; in this condition the circuit will not oscillate. In order to get
the sinusoidal output some automatic arrangement may be introduced in the circuit, such
as the resistance R2 may be replaced by a sensistor which has a positive temperature
coefficient.
The continuous variation of frequency may be accomplished by using two
capacitors mechanically ganged and frequency range may be accomplished by a band
switch for switching in different values for two identical resistors.
Example 7.5 In the Wein bridge circuit shown in figure 7.18 contains a series
combination of resistance R , capacitance C and inductance L; and a resistance R3 is
replaced by the parallel combination of resistance and capacitance in the parallel arm.
Find the expression for frequency of oscillations and minimum gain of the amplifier if:
(a) R1 is infinite
(b) R1 is finite.

Fig. 7.18
Solution. From the equation (7.42) the expression for the feedback factor (− β ) is given
by:
Z3 R2
−β = − … (7.47)
Z 3 + Z 4 R1 + R2
From the figure (7.18) the impedances Z3 and Z4 are given by:
 1 
Z 3 = R3 and Z 4 = R + j  ω .L −  … (7.48)
 ω .C 
Using the equations (7.47) & (748), we have:

216
 
 R3 R2 
−β = −  … (7.49)
 1 R1 + R2 
 R3 + R + j (ω .L − ) 
 ω .C 
1 1
It will be real when ω .L − =0 or ω 02 =
ω .C LC
1 1
ω0 = or f0 =
LC 2π LC
This is known as the frequency of oscillation.
At the frequency of oscillation, equation (7.49) reduces to:
 R3 R2 
− β =  − 
 R3 + R R1 + R2 
 R R + R2 R3 − RR2 − R2 R3 
=  1 3 
 ( R3 + R )( R1 + R2 ) 
 R1 R3 − RR2 
=   … (7.50)
 ( R3 + R )( R1 + R2 ) 
(a) If R1 = ∞ then from equation (7.50) it is obtained:
 RR2 
 R3 − 
−β =  R1 
 R2 
 ( R3 + R)(1 + ) 
 R1 
 R3 
or − β =  
 ( R3 + R) 
Since A β ≥ 1 so the minimum gain required will be:
 R + R3 
Amin =  
 R3 
(b) If R1 is finite the magnitude of the feedback factor β must be greater than
zero, so from equation (7.50) it is obtained:
R1 R3 > RR2
R1 R2
or >
R R3
Since A β ≥ 1 so the minimum gain required will be:
 ( R + R)( R1 + R2 )   R + R3 
Amin =  3  Amin =  
 R1 R3 − RR2   R3 
7.6 L-C OSCILLATOR
It is well known that the parallel combination of an inductance and a capacitor can
produce electrical oscillations. Such a combination is called as the tank circuit. Now

217
consider an inductance L having a small resistance R as the leakage resistance connected
in parallel with a capacitor C as shown in figure 7.19(a). Before connecting the capacitor
to the inductance, it is initially fully charged. Soon after connecting the charged capacitor
to the inductance the damped oscillations shown in figure 7.19(b) will be obtained across
the parallel combination. The damping in the output will be due to the leakage resistance
R. The energy will dissipate in this leakage resistance R. If there were ideal inductance
and capacitance alone, the energy would just transfer back and forth between inductance
L and capacitance C. Thus the sustained oscillations could occur.

(a) (b)
Fig. 7.19
To maintain the continuous oscillations in the practical tank circuit, the power
must be fed to the circuit to overcome the losses due to the leakage resistance. The
applied power should have the same frequency as that of oscillations in the tank circuit.
The impedance of the tank circuit is given by:
 1 
 ( R + jω .L ) 
 jω .C 
Z=
 1 
 R + jω .L + 
 jω .C 
 R + jω .L 
=   … (7.51)
 1 − ω LC + jω .CR 
2

If the leakage resistance is of very small value comparative to the inductive


reactance jω .L , then the resistance R may be neglected in the numerator and the equation
7.51 will become as:
 jω .L 
Z =   … (7.52)
 1 − ω LC + jω .CR 
2

The impedance of the tank circuit will become purely resistive and will be equal
 L  1 1 1
to Z =   at ω =
2
or ω 0 = or f 0 = .
 CR  LC LC 2π LC
This is known as resonance frequency. So at resonance frequency the equivalent
L
circuit of the tank circuit will be a pure resistance of value Req = .
CR

218
This equivalent resistance may be compensated by a negative resistance of
L
magnitude (− ) placed in parallel with the tank circuit. The parallel combination gives
CR
an infinite shunt resistance. Thus once the oscillations start in the tank circuit it will
continue indefinitely without damping.
It is well known that an operational amplifier with positive feedback presents a
negative resistance at the input. Thus such an operational amplifier connected with the
tank circuit at the non-inverting input as shown in figure 7.20 can be used to get the
sustained oscillations. It is necessary to have the feedback resistance R f to be less than or
L
equal to the equivalent resistance of the tank circuit
CR

Fig. 7.20
7.7 TUNED DRAIN FET OSCILLATOR
Another type of resonant circuit oscillator is the tuned grid FET oscillator. Figure
7.21(a) shows such an oscillator, in which primary of the transformer is connected in the
drain circuit. Let is the R is leakage resistance of the winding (of inductance L). The
voltage drop across the inductor (drain to ground) is 180o out of phase with the applied
input voltage to the field effect transistor. It will independent of the magnitude of the
drain resistance of the filed effect transistor. If the direction of the winding of the

(a) (b)
Fig. 7.21

219
secondary of the transformer which is connected to the gate is such that it introduces an
additional phase shift of 180o; the total phase shift will thus be of 0o. Let M is the mutual
inductance due to which an induced voltage will be developed between the gate and the
source of the FET. If this voltage is in phase and greater (or equal) to the input voltage,
then sustained oscillations will be produced in the circuit. This circuit will be called as
tuned drain oscillator. The resonant circuit is biased with the parallel combination of Rg
and Cg connected in series with the gate.
To calculate the frequency and the condition of oscillations, let us draw the
equivalent circuit of this oscillator as shown in figure 7.21(b). Let µ is the amplification
factor and rd is the drain resistance of the FET.
With reference to figure 7.21(b), the voltage V1 is given by:
V1 = − jω .M .I
jω .MVi
=− … (7.53)
( R + jω .L )
The voltage Vi is given by:
µ.V g Z
Vi = − …(7.54)
rd + Z
 1 
 ( R + jω .L) 
 jω .C 
where Z= … (7.55)
 1 
 R + jω .L + 
 jω .C 
Put the value of Z from equation (7.55) to equation (7.54), we get:
 1 
 ( R + j ω .L ) 
 µ .V jω .C 
 g
1 
 ( R + jω .L + )
jω .C 
Vi = −
 1 
 ( R + jω .L)
jω .C 
 (rd + )
 1 
 R + jω .L + 
 j ω .C 
1
µ .V g ( R + jω .L)
jω .C
or =−
 1  1
rd  R + j (ω .L − )  + ( R + j ω .L )
 ωC  jω .C
Vi µ .( R + jω .L)
or =− … (7.56)
Vg  1 
jω .C.rd  R + j (ω .L − )  + ( R + jω .L )
 ωC 
From equation (7.53), we have:
V1 jω .MVi
=−
Vg ( R + jω .L)V g

220
Vi ( R + jω .L)V1
or =− … (7.57)
Vg jω .MVg
From equations (7.56) and (7.57), we have:
( R + jω .L)V1 µ.( R + jω .L)
=
jω .MV g  1 
jω .C.rd  R + j (ω .L − )  + ( R + j ω .L )
 ωC 
jω .Mµ .V g
or V1 =
 1 
jω .C.rd  R + j (ω .L − )  + ( R + jω .L)
 ωC 
jω .Mµ .V g
or V1 = … (7.58)
1
j (ω .C.rd R + ω .L) − rd ω .C (ω .L − )+ R
ω .C
The equation (7.58) will be real if:
− rd ω 2 C.L + rd + R = 0
 R
or ω 2 C.L = 1 + 
 rd 
1  R
or ω2 = 1 + 
LC  rd 
1
1  R 2
or ω= 1 +  … (7.59)
LC  rd 
1
If the resonant frequency of the tank circuit is defined as ω 0 = , then for
LC
rd >> R the equation (7.59) can be written as:
 R   R 
ω = ω 0 1 +  f = f 0 1 +
or 
 2rd   2rd 
 R 
So the frequency of this oscillator is greater by the factor 1 +  than the
 2 rd 

resonant frequency.
At the frequency of oscillations equation (7.58) becomes:
V1 ω .Mµ
=
Vg ω .C.rd R + ω .L
V1
The factor = 1 when
Vg
Mµ = C.rd R + L
C.rd R + L
or M =
µ

221
L CR
or M− = where µ = rd .g m .
µ gm
CRµ
So gm = … (7.60)
µ.M − L
The equation (7.60) gives the value of gm for sustained oscillations. If this value
CRµ
less than , the circuit will not oscillate.
µ .M − L
7.7 TUNED COLLECTOR OSCILLATOR
Figure 7.22 shows the circuit diagram of a tuned collector oscillator, which is
analogous to the tuned drain FET oscillator. In this circuit too primary winding of
inductance L of a transformer and a capacitor form the tuned circuit. The tuned circuit is
connected to the collector of the transistor. The secondary winding of the transformer is
connected to the base of the transistor which provides a phase shift of 180o. The transistor
also provides a phase shift of 180o. Thus there will be the total phase shift of 360o. The
resistances R1, R2 and RE provide the necessary biasing to the transistor and C2 and CE are
used as the bye pass capacitors. Here M is mutual inductance of the coils.

Fig. 7.22
To calculate the frequency and the condition of oscillations, let us draw the
equivalent circuit of the oscillator by replacing the h-parameter model of the transistor as
shown in figure 7.23.

Fig. 7.23

222
In this circuit the resistors R1, R2 and RE and the capacitors C2 and CE play no
role in the a.c. operation so may be treated at short circuited. Here R is the resistance of
the coil L.
The voltage V0 is given by (ref. fig.7.23):
V0 = − I ( R + jω .L) … (7.61)
The voltage V f b across the secondary coil of the transformer (known as feedback
voltage) is given by:
V f b = jω .IM … (7.62)
The feedback factor β is obtained as:
Vf j ω .M
β = b =− … (7.63)
V0 ( R + j ω .L )
The voltage gain of the circuit without feedback is given by:
− h fe Z L
A= … (7.64)
hie + (hie hoe − h fe hre ) Z L
Where ZL is the load impedance of the output circuit, which is taken as the
1
parallel combination of ( R + jω .L) and . It is given by:
jω .C
1
( R + jω .L)
jω .C
ZL =
1
R + jω .L +
jω .C
 ( R + jω .L) 
=   … (7.65)
 ( R + jω .L) jω .C + 1 
The condition for sustained oscillations is :
Aβ = 1 … (7.66)
From the equations (7.63) to (7.66), we have:
 ( R + jω .L) 
 h fe 
 jω .M  ( R + jω .L ) jω .C + 1  =1
 
 ( R + j ω .L ) 
 h + (h h − h h ) ( R + jω .L ) 
 ie 
( R + jω .L ) jω .C + 1 
ie oe fe re

 h fe jω .M 
or   =1
 {( R + jω .L ) jω .C + 1}h + (h h − h h )( R + jω .L) 
 ie ie oe fe re 
or { }
h fe jω .M = jω .CR − ω 2 LC + 1 hie + (hie hoe − h fe hre )( R + jω .L) … (7.67)
Comparing the imaginary parts, we get:
h fe M = CRhie + (hie hoe − h fe hre ) L
or h fe M + h fe hre − hie hoe L − CRhie = 0 … (7.68)
Comparing the imaginary parts in equation (7.67), we get:

223
{1 − ω LC + h R}h − h h
2
oe ie fe re R=0
or {1 − ω LC}h = h h R − h
2
ie fe re oe ieh R
R (h h − h h )
or {1 − ω 2
LC } = −
h
oe ie fe re

ie

1  R(hoe hie − h fe hre ) 


or ω= 1 + 
LC  h ie 
1 R(hoe hie − h fe hre ) 
f = 1 +  … (7.69)
2π LC  hie 
This is the expression of frequency of oscillations of this oscillator. It may be
noted from this expression that usually (hoe hie − h fe hre ) and the resistance R are very
small. So the frequency of oscillations of the oscillator will be very nearly equal to the
resonant frequency of the tank circuit.
The frequency of oscillations is, therefore, given by:
1
f0 = … (7.70)
2π LC
From equation (7.68), it is obtained:
(hie hoe − h fe hre ) L + CRhie
M = … (7.71)
h fe
This is the minimum value of the mutual inductance between the primary and the
secondary of the transformer, required for the sustained oscillations in this oscillator.
7.8 GENERAL FORM OF RESONANT CIRCUIT OSCILLATORS
Many resonant circuits have been discussed in this chapter. There two more
important oscillators namely Hartley and Colpitts oscillators which may be explained if
we analyze the general form of the resonant circuit oscillators. Such a general form is
shown in figure 7.24. In the analysis of this general form an active device which has

Fig. 7.24

224
infinite input resistance such as an field effect transistor or an operational amplifier is
considered. In this circuit the feedback elements are the impedances Z1, Z2 and Z3.
The gain of the amplifier in the open loop condition is given by:
AZ
A=− v L … (7.72)
R0 + Z L
where ZL is the load impedance, which is the parallel combination of Z 2 and
( Z1 + Z 3 ) . The load impedance is therefore given by:
Z 2 ( Z1 + Z 3 )
Z L = Z 2 ( Z1 + Z 3 ) = … (7.73)
Z1 + Z 2 + Z 3
From equations (7.72) and (7.73), we have:
Z (Z + Z 3 )
Av 2 1
Z1 + Z 2 + Z 3
A=−
Z (Z + Z 3 )
R0 + 2 1
Z1 + Z 2 + Z 3
Av Z 2 ( Z 1 + Z 3 )
=− … (7.74)
R0 ( Z 1 + Z 2 + Z 3 ) + Z 2 ( Z 1 + Z 3 )
The feed back factor β is given by:
Z1
β =− … (7.75)
Z1 + Z 3
The condition for oscillation is given by:
Aβ = −1 … (7.76)
So by putting the values of A and β from equations (7.74) and (7.75)
respectively in equation (7.76), it is obtained as:
 Av Z 2 ( Z 1 + Z 3 )   Z1 
 .  = −1
 R0 ( Z 1 + Z 2 + Z 3 ) + Z 2 ( Z 1 + Z 3 )   Z 1 + Z 3 
 Av Z1 Z 2 
  = −1 … (7.77)
 R0 ( Z 1 + Z 2 + Z 3 ) + Z 2 ( Z 1 + Z 3 ) 
If the impedances are considered as pure reactances (inductive or capacitive), then
Z 1 = jX 1 Z 2 = jX 2 Z 3 = jX 3 .
The reactance X may be ( jω .L ) or (1 jω .C ) .
The equation (7.77) will be reduced to:
 − Av X 1 X 2 
  = −1 … (7.78)
 jR0 ( X 1 + X 2 + X 3 ) − X 2 ( X 1 + X 3 ) 
Comparing the real and imaginary parts of the equation (7.78), we get the
conditions of oscillations.
So (X1 + X 2 + X 3 ) = 0 … (7.79)
 Av X 1 
and   = −1 …(7.80)
X
 1 + X 3 

225
 X + X3 
or Av = − 1 
 X1 
Put ( X 1 + X 3 ) = − X 2 from equation (7.79), we have:
X 
Av =  2  … (7.81)
 X1 
The equation (7.79) gives the frequency of oscillation and equation (7.80) gives
the gain required for oscillations. It is concluded from the equations (7.79) and (7.81) that
the reactances X1 and X2 must of same sign and type and X3 must be of opposite sign.
If X1 and X2 are considered as capacitive reactances and X3 as the inductive
reactance, the oscillator circuit is called as colpitt’s oscillator. If on the other hand X1 and
X2 are considered as inductive reactances and X3 as the capacitive reactance, the circuit is
called as Hartley oscillator.
The transistorized Hartley and Colpitt’s oscillator circuits are also possible to
design. The qualitative analyses of such circuits are possible by considering the
generalized equations. However, the detailed analysis of the transistorized Hartley and
Colpitt’s oscillator circuits will be more difficult. These circuits will be discussed in the
following sections.
Example 7.6 Consider the general form of Colpitt’s oscillator as shown in figure 7.24.
1 1
if Z 1 = , Z2 = and Z 3 = r3 + jω .L ; where r3 is the series resistance with
jω .C1 jω .C 2
the inductance L. Find the expression of frequency of oscillation and minimum gain
required for the oscillations.
Solution. The general expression for Aβ is given by equation (7.77), which is
reproduced here:
 Av Z 1 Z 2 
  = −1
R (
 0 1 Z + Z 2 + Z 3 ) + Z 2 ( Z 1 + Z )
3 

Av
or = −1
 1 1 Z3 Z3 
 R0 ( + + ) +1+ 
 Z 2 Z1 Z 2 Z1 Z 1 
1 1
Put Z1 = , Z2 = and Z 3 = r3 + jω .L in this equation we get:
jω .C1 jω .C 2
Av
= −1
( )
R0 ( jω .C 2 + jω .C1 − ω C1C 2 (r3 + jω .L) + 1 + jω .C1 (r3 + jω .L)
2

Av
= −1 … (7.82)
( )
or
jω . R0 (C 2 + C1 ) − ω R0 C1C 2 r3 L + C1 r3 + 1 − ω 2 R0 C1C 2 r3 − ω 2 C1 L
2

Comparing the imaginary parts in this equation it is given as:


( )
R0 (C 2 + C1 ) − ω 2 R0 C1C 2 r3 L + C1 r3 = 0
or ω R0 C1C 2 r3 L = (R0 (C 2 + C1 ) + C1 r3 )
2

226
(R0 (C 2 + C1 ) + C1r3 )
or ω2 =
R0 C1C 2 r3 L
1 1 1 r 
or ω2 =  + + 3 
L  C1 C 2 R0 C 2 
1 1 1 r 
or ω 2 =  + (1 + 3 ) 
L  C1 C 2 R0 
1  1 1 r 
or ω=  + (1 + 3 ) 
L  C1 C 2 R0 
r3
This is the expression for frequency of oscillations. If << 1 , then we have:
R0
1  1 1 
ω=  +  … (7.83)
L  C1 C 2 
Comparing the real parts of the equation (7.82), we have minimum gain as:
Av min = −1 + ω 2 (R0 C1C 2 r3 + C1 L ) … (7.84)
From equations (7.83) and (7.84), we get:
1 1 1 
Av min = −1 +  + (R0 C1C 2 r3 + C1 L )
L  C1 C 2 
R0 C1C 2 r3 R0 C1C 2 r3 C1 L C1 L
or = −1 + + + +
C1 L C2 L C1 L C 2 L
C C + C2
or = 1 + R0 r3 1 … (7.85)
C2 L
This is the expression for the minimum gain required for oscillations.

7.9 TRANSISTOR HARTLEY OSCILLATOR

Figure 7.25 shows the circuit diagram of Hartley oscillator using transistor as the
active element. In this circuit the resistances R1, R2 and RE and the capacitance CE are
used to bias the transistor T1. These elements have no role to play in the a. c. analysis of
the circuit. The tank circuit and the feedback network comprises inductances L1, L2 and
capacitance C. The capacitor C” blocks the d. c. and allows only the a. c. signal to pass
through the collector to tank circuit. A radio frequency choke (RFC coil) is connected
between the collector and the d. c. supply. It is used to prevent the a. c. signal from
reaching the d. c. supply.
A total phase difference of 360 o is introduced in the circuit. The 180 o phase
shift is provided by the transistor and the other 180 o phase difference is provided by the
tank circuit. The coils L1 is inductively coupled with the coil L2 and the combination of
two will form an autotransformer.

227
Fig. 7.25
Now the circuit will be analysed for the purpose of getting the expression for the
frequency of oscillations and the condition required for the sustained oscillations. For this
purpose approximate h-parameter model of the transistor is considered. The equivalent
circuit of the oscillator is shown in figure 7.26.

Fig. 7.26
From this circuit the inductance L1 is in parallel with hie. The impedance Z’ of this
parallel combination is given by:
h . jω .L1
Z ' = ie …(7.86)
hie + jω .L1
The load impedance between the terminals 2 and 3 will be parallel combination of
the inductance L2 and the series combination of Z’ and the reactance of the capacitance C.
The load impedance is therefore given by:
1
(Z ' + ) jω .L2
jω .C
ZL =
1
Z' + + jω .L2
jω .C

228
( jω .CZ ' + 1) jω .L2
= … (8.87)
jω .CZ ' + 1 − ω 2 CL2
The output voltage across the series combination of Z’ and the capacitance is
given by:
1
V0 = − I 1 ( Z ' + )
jω .C
 1 + jω .CZ ' 
= − I1   … (7.88)
 jω .C 
The feedback voltage to the input terminals is given by:
V fb = − I 1 Z ' … (7.89)
The feedback factor can be calculated as:
V fb Z'
β= =
V0  1 + jω .CZ ' 
 
 jω .C 
 Z ' jω .C 
=  
' 
… (7.90)
 1 + jω .CZ 
The condition of oscillations is given by:
Aβ = 1
The voltage gain A without feedback is given by:
h fe  h fe  ( jω .CZ ' + 1) jω .L2 
A=− .Z L =  −   … (7.91)
 hie  jω .CZ + 1 − ω CL2 
' 2
hie
From equations (7.91) and (7.92), we have:
 h fe  ( jω .CZ ' + 1) jω .L2  Z ' jω .C 
or Aβ =  −    =1
' 
h
 ie  jω .CZ '
+ 1 − ω 2
CL 2  1 + jω .CZ 
 h fe  ω 2 L2 Z ' C 
or    = 1 … (7.92)
 hie  jω .CZ + 1 − ω CL2 
' 2

Put the value of Z’ from equation (7.86) in equation (7.92), we have:


 h . jω .L1 
 ω 2 L2 C ie 
 h fe  hie + jω .L1  =1
 
 h . j ω . L 
 hie  jω .C ie 1
+ 1 − ω 2 CL2 
 hie + jω .L1 
 h fe  jω 3 L1 L2 Chie 
or    =1
h h + j ω . L − ω 2
CL h − ω 2
L Ch − jω 3
L L C 
 ie  ie 1 2 ie 1 ie 1 2 
 jω L1 L2 Ch fe
3

or   =1
 h + jω .L − ω CL h − ω L Ch − jω L L C 
2 2 3
 ie 1 2 ie 1 ie 1 2 
Comparing the real parts, we get:
ω 2 CL2 hie + ω 2 L1Chie = hie

229
or ω 2 ( L1 + L2 )C = 1
1
or ω2 =
( L1 + L2 )C
1
or ω= … (7.93)
( L1 + L2 )C
This is the expression for frequency of oscillation of this oscillator.
Comparing the imaginary parts, we have:
ω 3 L1 L2 Ch fe = ω .L1 − ω 3 L1 L2 C
or ω 2 L2 Ch fe = 1 − ω 2 L2 C … (7.94)
From equations (7.93) and (7.94), we have:
L2
(1 + h fe ) = 1
( L1 + L2 )
L
or h fe = 1 … (7.95)
L2
This is the condition for sustained oscillation in Hartley oscillator i.e. the hfe of
the transistor should not be less than this value.
So we have considered the mutual inductance M of the coils. If inductance L1 is
replaced by L1 + M and inductance L2 by L2 + M and calculations are repeated in the
similar fashion the expression of frequency of oscillation will be given by:
1
ω=
( L1 + L2 + 2 M )C
The condition for sustained oscillations will be given by:
L +M
h fe = 1
L2 + M
7.10 TRANSISTOR COLPITT’S OSCILLATOR
Colpitts oscillator is basically the same as Hartley oscillator with the difference

Fig. 7.27

230
that the tap position is between the two capacitors instead of between two inductances.
There is an inductance across the two capacitors as shown in figure 7.27. The operation
of this circuit is the same as that of Hartley oscillator.
Now the circuit will be analysed in the similar way as for the Hartley oscillator
for which the equivalent circuit is drawn as shown in figure 7.28.

Fig. 7.28

From this circuit the capacitor C1 is in parallel with hie. The impedance Z’ of this
parallel combination is given by:
1
hie .
jω .C1
Z'=
1
hie +
jω .C1
hie
= … (7.96)
1 + jω .C1 hie
The load impedance between the terminals 2 and 3 will be parallel combination of
the capacitance C2 and the series combination of Z’ and the reactance of the inductance L.
The load impedance is therefore given by:
1
( Z ' + jω .L)
jω .C 2
ZL =
1
Z' + + jω .L
jω .C 2
( Z ' + jω .L)
= … (7.97)
jω .C2 Z ' + 1 − ω 2 LC2
The output voltage across the series combination of Z’ and the inductance L is
given by:
V0 = − I 1 ( Z ' + jω .L )
The feedback voltage to the input terminals is given by:
V fb = − I 1 Z '
The feedback factor can be calculated as:
V Z'
β = fb = ' … (7.98)
V0 ( Z + jω .L)

231
The condition of oscillations is given by:
Aβ = 1 … (7.99)
The voltage gain A without feedback is given by:
h fe  h fe  ( Z ' + jω .L) 
A=− .Z L =  −   … (7.100)
 hie  jω .C 2 Z + 1 − ω LC 2 
' 2
hie
From the equations (7.98) to (7.100), we have:
 h fe  ( Z ' + j ω .L )  Z' 
Aβ =  −  

  = 1
 hie  jω .C 2 Z + 1 − ω LC 2  ( Z + jω .L) 
' 2 '

 h fe  Z' 
or    = 1 … (7.101)
 hie  jω .C 2 Z + 1 − ω LC 2 
' 2

Put the value of Z’ from equation (7.9 6) in equation (7.101), we have:


 hie 
 
 fe 
h 1 + jω .C1 hie  =1
 
 hie 
 hie  jω .C + 1 − ω 2C2 L 
1 + jω .C1 hie
2
 
 h fe 
or   = 1
 1 + jω .C 2 hie + jω .C1 hie − ω LC 2 − jω C1C 2 Lhie
2 3

Comparing the imaginary parts, we get:
ω .C 2 hie + ω .C1 hie = ω 3 C1C 2 Lhie
or C 2 + C1 = ω 2 C1C 2 L
C + C2
or ω2 = 1
C1C 2 L
1
or ω= … (7.102)
 CC 
L 1 2 
 C1 + C 2 
This is the expression for frequency of oscillation of this oscillator.
Comparing the imaginary parts, we have:
1 − ω 2 LC 2 = h fe … (7.103)
From equations (7.10 2) and (7.103), we have
C + C2
1− 1 LC 2 = h fe :
C1C 2 L
C + C2
or 1− 1 = h fe
C1
C
or h fe = 2 … (104)
C1

232
This is the condition for sustained oscillation in Colpitt’s oscillator i.e. the hfe of
the transistor should not be less than this value.

7.11 CRYSTAL OSCILLATOR


Some crystals such as quartz or tourmaline etc. are used in crystal oscillators. Out
of these crystals, the quartz crystals are most commonly used for this purpose. The quartz
crystal oscillator produces oscillations with high stability as quartz crystals show almost
zero temperature coefficient of frequency. The quartz crystal oscillators are used for the
measurement of time with high degree of precision. Quartz watches and clocks are
commercially available which utilize the quartz crystal oscillators.
The quartz crystals are found in hexagonal form with pointed ends as shown in
figure 7.29(a). The line joining the pointed ends of the crystal is called the Z-axis or
optical axis. This axis used in finding the optical rotation in polarization of light. There
are other two sets of axes. One set of axes are the three lines (axes) passing through its
opposite corners. These axes are called X– axes or electrical axes. The other set of axes
are the three lines (axes) passing through the middle terminals of its faces. These axes are
called Y – axes or mechanical axes. Figure 7.29(b) illustrates the X-axes and Y- axes.

(a) (b)
Fig. 7.29
The crystal is cut into very thin slices and then carefully ground to desired
resonant frequency. The orientation of the slice, with reference to the crystal axes
illustrates the properties of the crystal. The crystal is cut at proper orientation with the
axes so that it show almost temperature coefficient of frequency. The resonant frequency
of crystal is inversely proportional to its thickness. The resonant frequency of the crystal
is given by:
N
f =
t

233
where N is crystal constant which depend on its cut and t is the thickness of the
quartz. Commercial quarts crystals are available for the frequency range of a few KHz to
MHz. The Qs are in the range of several thousands.
The quartz crystals exhibit piezoelectric effect. This effect refers to the crystal for
its ability to transform mechanical deformation into electrical charges and vice-versa.
Hence if the quartz crystal is compressed, it develops a voltage and similarly, if a voltage
is applied across it, a change in mechanical dimensions will result. Hence if the crystal is
properly mounted, deformations take place within the crystal, electromechanical system
is formed which will vibrate when properly excited.

(a) (b)

(c) Fig. 7.30


The crystal is mounted horizontally by clamping between two metal plates or by
two electrodes on its side faces. The symbolical representation of the quartz crystal is
shown in figure 7.30(a). The electrical equivalent circuit of the quartz crystal is shown in
figure 7.30(b), which consists of series LS CS RS circuit and a parallel capacitance Cp
arises due to metal plates or electrodes of the crystal. Two types of resonance may occur
in the quartz crystal; one is known as series resonance and the other is known as parallel
resonance. In other words the quartz crystal can oscillate at either of two frequencies,
series or parallel resonance frequencies. When the series resonance occurs inductive
reactance of LS equals the capacitive reactance of the reactance CS; and the impedance of
the crystal becomes equal to the resistance RS, which is quite low. The parallel resonance
occurs at slightly higher frequency than the series resonance frequency fS. At this

234
resonance, the LCR series becomes inductive which resonates with CP. It gives rise the
parallel resonance frequency fP and the impedance of the crystal becomes maximum at
this frequency as shown in figure 7.30(c).
Now we shall find the expressions of two resonance frequencies and the
impedances of the crystal at these two frequencies by consider the electrical equivalent
circuit of the crystal. .
The impedance of the quartz crystal (ref. fig.7.30 b) is given by:
1 1
= jω .C P +
Z  1 
 RS + jω .LS + 
 jω .C S 

jω .C S
= jω .C P +
((1 − ω LS C S ) + jω .C S RS
2
)
jω .C S ((1 − ω 2 LS C S ) − jω .C S RS )
= jω .C P +
((1 − ω 2 LS C S ) 2 + ω 2C S2 RS2 )
jω .C S (1 − ω 2 LS C S ) + ω 2 .C S2 RS
= jω .C P +
((1 − ω 2 LS C S ) 2 + ω 2C S2 RS2 )
ω 2 .C S2 R S jω .C S (1 − ω 2 LS C S )
= + ω +
((1 − ω 2 LS C S ) 2 + ω 2 C S2 RS2 ) ((1 − ω 2 LS C S ) 2 + ω 2 C S2 RS2 )
j .C P

… (7.105)
The resonant frequencies are obtained by putting the imaginary part to zero, as:
ω .C S (1 − ω 2 LS C S )
ω .C P + =0
((1 − ω 2 LS C S ) 2 + ω 2C S2 RS2 )
or ((1 − ω 2
)
LS C S ) 2 + ω 2 C S2 RS2 C P + C S (1 − ω 2 LS C S ) = 0
CS L C2
or ω 4 L2S C S2 − 2ω 2 LS C S + 1 + ω 2 C S2 RS2 + −ω 2 S S = 0
CP CP
 LS C S2   C S 
or ω L C + ω  (−2 LS C S ) + C S RS −
4 2 2 2 2 2
 + 1 + =0
C P   C P 
S S

ω2  L C2  1  C 
or ω 4 + 2 2  (−2 LS C S ) + C S2 RS2 − S S  + 2 2 1 + S  = 0
LS C S  C P  LS C S  C P 
ω2  C R2 C  1  C 
or ω4 +  − 2 + S S − S  + 2 2 1 + S  = 0
 
LS C S  LS C P  LS C S  C P 
C S RS2 C S RS
For the quartz crystal the quantity = << 1 , because the time constant
LS  LS 
 
 RS 
 LS 
  is very much larger than the time constant CS RS .
 RS 

235
ω2  C  1  C 
So ω4 −  2 + S  + 2 2 1 + S  = 0 … (7.106)
LS C S  C P  LS C S  C P 
This is a quadratic equation which can be solved for ω 2 as:
2
1  C  1  C  4  CS 
ω =
2
 2 + S  ±  2 + S  − 2 2 1 + 
LS C S  CP  LS C S2
2
 CP  LS C S  CP 
2
1 1 1 4 1  CS  4 C 4 4 C
or = + ± 2 2
+ 2 2   − 2 2 S − 2 2 − 2 2 S
L S C S 2 LS C P 2 LS C S LS C S  CP  LS C S C P L S C S LS C S C P
1 1 1 1
or = + ±
LS C S 2 LS C P 2 LS C P2
2

1 1 1 1
or = + ± … (1.07)
L S C S 2 LS C P 2 L S C P
Taking the negative sign in this equation, we get the series resonant frequency ω S as:
1 1 1
ω S2 = or ωS = or fS = … (7.108)
LS C S LS C S 2π LS C S
Taking the positive sign in equation (7.107), we get the parallel resonant frequency ω P
as:
1 1
ω P2 = +
LS C S L S C P
1  1 1 
or ω P2 =  + 
LS  CS CP 
1 1
or ω P2 = or ωP =
 C C   C C 
LS  S P  LS  S P 
 CS + CP   CS + CP 
1
or fP = … (7.109)
 CS CP 
2π LS  
 CS + CP 
To find the impedance of the crystal we consider the real part of equation (7.105) as:

Z=
((1 − ω 2 LS C S ) 2 + ω 2C S2 RS2 ) … (7.110)
ω 2 .C S2 RS
The impedance Z S of the crystal at the series resonance frequency may be obtained by
1
putting ω S2 = in equation (7.110) as:
LS C S
ω 2 C S2 RS2
ZS = = RS … (7.111)
ω 2 .C S2 RS
This impedance is equal to the resistance RS which a very small quantity for a quartz.

236
Similarly, the impedance Z P of the crystal at the parallel resonance frequency may be
1
obtained by putting ω P2 = in equation (7.110) as:
 CS CP 
LS  
 CS + CP 
(1 − ω 2 LS C S ) 2
Z P = RS +
ω 2 .C S2 RS
2
 CS + CP 
1 − LS C S 
LS C S C P
or Z P = RS +  
 CS + CP 2 
 C S RS 
 LS C S C P 
2
 C 
1 − 1 − S 
CP 
or Z P = RS + 
 CS + CP 
 C S RS 
 LS C P 
2
 CS 
 
 C P 
or Z P = RS +
 CS + CP 
 C S RS 
 LS C P 
  LS  C S  
    
 R C 
or Z P = RS 1 +  S  P   … (7.112)
 (C S + C P )RS 
 
 
So the impedance at the parallel resonance frequency is a very large quantity.
ω L
The quality factor Q = S S of the quartz crystal is very large quantity as RS is
RS
very small.
The ratio of parallel to series resonance frequency is given by:
1/ 2
1  1 1 
 + 
ωP LS  C S C P 
=
ωS 1
LS C S
1/ 2
1  CS 
1 + 
C S  C P 
or =
1
CS

237
1/ 2
 C 
or = 1 + S 
 CP 
ω P  1 CS 
or ≡ 1 + 
ω S  2 C P 
Several oscillator circuits incorporating crystal are used. In such circuits the
crystal is used to replace the entire tank circuit, or one of the reactances of the tank
circuit. The Pierce crystal oscillator is used which is basically a Colpitts’ oscillator in
which the inductor is replaced by crystal as shown in figure 7.31.

Fig. 7.31
In this circuit both the capacitors C1 and C2 are very much larger than CP, so the
resonant frequency is almost dependent on the value of CP. The rest of the circuit
elements perform their usual work.
Example 7.7 If the resistance RS of the equivalent circuit of quartz crystal (fig. 7.30b) is
negligibly small than the impedance of the crystal will be reactive. Show that the
reactance of the quartz crystal is given by:
 j  ω 2 − ω S2 
jX =  −  2 
2 
 ω .C P  ω − ω P 
where ω S and ω P are the series and parallel resonance frequencies respectively which
1 1  1 1 
are given by ω S2 = and ω P2 =  + .
LS C S LS  C S C P 
Solution. If the resistance of the quartz crystal is negligibly small than the reactance of
the quartz crystal is given by:

238
 1  − j 
j  ω .LS −  
 ω .C S  ω .C P 
jX =
 1 j 
j  ω .LS − − 
 ω .C S ω .C P 
 2 1 
 ω − 
 −j   LS C S 
=  
 ω .C P   ω 2 − 1 − 1 

 LS C S LS C P
 
 2 1 
 ω − 
 −j   LS C S 
=  
 ω .C P   ω 2 − 1 ( 1 + 1 ) 
 LS C S C P 

 j  ω 2 − ω S2 
=  −  2 
 Proved.
 ω .C P  ω − ω P
2

PROBLEMS

1. Discuss the Berkhausen criterion in order to get the sustained oscillation in an


oscillator circuit.
2. What type of feedback used for getting the sustained oscillations in an oscillator
circuit? Is any input signal necessary to get an output from an oscillator? If not,
how do the oscillations starts?
3. What is an oscillator circuit? What is the condition for the circuit to oscillate?
Mention the different classes of oscillators.
4. Explain, how can a negative resistance introduced in a circuit using operational
amplifier.
5. Draw the circuit of an R C phase shift oscillator and explain its operation. Find an
expression for the frequency of oscillations and the condition for sustained
oscillations.
6. Discuss R C phase shift oscillator using field effect transistor. Find the expression
for the frequency of oscillations. Also show that the minimum gain of the
amplifier required for the circuit to oscillate should not be less than 29.
7. Explain the transistor RC phase shift oscillator. Find the expression for frequency
of oscillations of this oscillator. Find the minimum value of hfe of the transistor
required for oscillations.
8. Can RC phase shift oscillator circuit be designed with operational amplifier?
Draw and explain such circuit.
9. Sketch the circuit of Wein-bridge oscillator. Explain the principle of its operation
and find an expression for the frequency of oscillations. Also show that the
minimum gain of the amplifier used in the oscillator should be more than 3 for the
oscillations in the circuit.

239
10. Find the expression for the frequency of oscillations and the condition for getting
the sustained oscillations in a tuned collector oscillator. What is the minimum
value of Mutual inductance required for sustained oscillations?
11. Discuss the principle and operation of tuned drain oscillator circuit. Find the
expression for minimum value of trans-conductance gm required for the FET used
in the circuit.
12. Sketch the topology for a generalized resonant-circuit oscillator, using the
impedances Z1, Z2 and Z3. At what frequency the circuit will oscillate? Under
what conditions does the generalized circuit will work as Colpitts’ oscillator?
13. Using the topology for a generalized resonant-circuit oscillator containing three
impedances Z1, Z2 and Z3. Find the conditions for the circuit to oscillate. Under
what conditions does the generalized circuit will work as Hartley oscillator?
14. Describe the operation of a Hartley oscillator circuit.
15. Draw the circuit of Colpitts’ oscillator and explain its operation. Find the
expression of frequency of oscillations.
16. Discuss the transistorized Hartley oscillator. Find the expression for frequency of
oscillations neglecting the mutual inductance of the coil. Find also the minimum
hfe of the transistor required for the circuit to oscillate.
17. Discuss the transistorized Colpitts’ oscillator. Find the expression for frequency
of oscillations and the minimum hfe of the transistor required for the circuit to
oscillate.
18. Draw the electrical equivalent circuit of the quartz crystal. What is piezoelectric
effect? Find the expressions for the resonant frequencies in the two modes of
vibrations. Also find the ratio of the parallel to series resonant frequencies.
19. Draw the circuit of a crystal oscillator. What are advantages of this oscillator over
an LC oscillator?
20. What is piezoelectric effect? Find the expressions for the series and parallel
resonant frequencies of a quartz crystal; also find the impedances of the crystal at
these two resonant frequencies.
V f'
21. Show that the ratio for the three stage RC phase shifting network shown
V0

Fig. 7.32
in figure 7.32 is given by:
V f' 1
=
V0 1 − 5α − 6 jα + jα 3
2

, where α = (1 ω .C.R ) .
1
and frequency of oscillations is given by: f =
2π 6 RC

240
V f'
22. Show that the ratio for the two stage RC phase shifting network shown in
V0
figure 7.33 is given by:
V f' 1
=
V0 (3 + j (ω .CR − (1 ω .CR ) )
1
and frequency of oscillations is given by: f = .
2π RC

Fig. 7.33
23. What should be the value of the capacitance C of the RC network of a Wein
bridge oscillator to generate a sinusoidal of 1 KHz frequency? The value of the
resistance used in the network is 15 KΩ. (Ans.: 0.001 µf)
24. If R = 12 KΩ and C = 0.01 µf in the Wein bridge oscillator circuit, then calculate
the frequency of oscillations. (Ans.: 1.33 KHz)
25. A quartz crystal has the following parameters LS = 4 H, CS = 0.05 pf, RS = 2 KΩ
and CP = 10 pf. Find the series and parallel resonant frequencies of the crystal.
Find also the Q of the crystal.
(Ans.: fS = 353.86 KHz, fP = 357.14 KHz and Q = 4443.7)
26. If for a quartz crystal CS = 0.06 pf and CP = 12 pf, by what percent is the parallel
resonant frequency greater than the series resonant frequency. (Ans.: 0.25%)
27. Find the frequency of oscillations of a Hartley oscillator (figure 7.25 in the text) if
L1 = 100 µH and L2 = 1 mH, M = 20 µH and C = 20 pf. (Ans.: 1.05 MHz)
28. The tuned collector circuit consists a tuned circuit. If the inductance of the tuned
circuit is 1.2 mH, the resistance of the coil is 10 Ω and the capacitance of 100 pf.
Calculate (i) the frequency of oscillations and (ii) the minimum value of mutual
inductance between the collector and the base coil required for sustained
oscillations. Given the CE h-parameters of the transistor used: hie = 2600Ω ,
h fe = 100 , hre = 0.62 x10 −4 and . (Ans.: 460 KHz and 0.1 µH)

__________

241
8
Multivibrators
Multivibrators are basically the relaxation oscillators. It is a regenerative circuit
consisting of two active devices coupled together. In these circuits at a time only one
device conducts while the other remains in cutoff. There are three basic kinds of
multivibrators namely Bistable, Monostable and Astable multivibrators. In this chapter
detailed discussion on these multivibrators with their uses will be made. In addition some
more relaxation oscillator circuits including the Schmitt trigger and timer circuit will also
be discussed.
8.1 BISTABLE MULTIVIBRATOR
The bistable multivibrator as the name indicates has two stable states and the
circuit can be in one of the two stable states. When the circuit is one of the two stable
states, it will continue to be in that state till it is changed by the external excitation or
external triggering circuit. So after application of the external triggering pulse, there will
a transition from one stable state to other. The bistable multivibrators are also known as
flip-flops, Eccles-Jordan circuit, Scale of 2, Toggle circuits or Binary. The bistable
multivibrator finds applications in digital circuits for counting and storing the digital
information. These circuits can also be used for generation and processing of pulse type
waveforms.
Figure 8.1 shows the schematic diagram of a bistable multivibrator, in which two

Fig. 8.1
inverters are connected back to back to provide the positive feedback in the circuit. The
inverters are basically two common emitter transistor amplifiers. The resistor values in
this circuit are so chosen that the saturation is ensured when the transistor is turned on.
That is the transistor is conducting means it is said to be on or in saturation. So in this
multivibrator when one transistor T1 is in cut-off, the collector voltage (VC1) of this
transistor will be high. This collector voltage is connected to the base of the other
transistor T2 and this voltage is sufficient to take the transistor T2 into saturation. So the
transistor T1 will be off and T2 will be on, his is one stable state of the multivibrator. The
circuit will remain in this stable stage indefinitely till it is forced to change the state by
the external triggering pulse. The second stable state will be that the transistor T1 is on
and T2 is off.
The two transistors will never be in the conductive (active) region. Consider that
both the transistors are conducting and are in the active region and if the collector voltage
of either of the transistor, says VC1 of T1 increases due to some reason. This will result an
increase in the base current of transistor T2 making the collector voltage VC2 to fall. This
will then reduce the base current of T1 which then causes a further increase in VC1. The
regenerative feedback will then lead the transistor T1 is in cut-off and the transistor T2 is
in on. Similarly, on the other hand if VC1 of T1 decreases due to some reason, then this
will result a decrease in the base current of transistor T2 making the collector voltage VC2
to increase. This will then increase the base current of T1 which then causes a further
reduction in VC1. This will finally lead the transistor T1 to on position and the transistor T2
to off.
To analyze the circuit let us consider that the transistor T1 is off and transistor T2
is in saturation. The equivalent circuit for this case which shows the collector of transistor
T2 is given in figure 8.2. The collector voltage of transistor T2 is VCE2(Sat) and the base
voltage of this transistor will be VBE2(Sat).

Fig. 8.2
The base voltage VB1 of transistor T1 is obtained by applying the superposition
theorem as:
 RB 2   R1 
VB1 = −VBB   + VCE 2 ( Sat )   … (8.1)
 R1 + RB 2   R1 + RB 2 

243
The transistor T1 to be in the cutoff, the base voltage of this transistor should be
less than the base emitter cut-off voltage (VBE1,Cutoff) of transistor T1.
i.e. V B 1 << V BE 1 , Cutoff
The current I1 flowing through the collector resistance RC2 is given by:
V − VCE 2( Sat )
I1 = CC … (8.2)
RC 2
Similarly, the current I2 flowing through RB2 is given by:
V + VCE 2( Sat )
I 2 = BB … (8.3)
R1 + RB 2
The collector current of transistor T2 is, therefore, given by:
I C 2 = I1 − I 2 … (8.4)
The minimum value of base required to bring the transistor T2 into saturation is:
I
I B 2,min = C 2 … (8.5)
h fe
The equivalent circuit for this case that the transistor T1 is off and T2 is on
showing the base of transistor T2 is given in figure 8.3.

Fig. 8.3
From this figure the current I3 flowing through the resistance RB1 is given by:
VCC − VB 2 ( Sat )
I3 = … (8.6)
RC1 + R2
Similarly the current I4 flowing through the resistance R2 is given by:
VBB + V B 2 ( Sat )
I4 = … (8.7)
R2
Further I 3 = I 4 + I B2 … (8.8)
The base current of transistor T2 is, therefore, given by:
I B2 = I 3 − I 4 … (8.9)

244
In this circuit the resistance RB1 also acts as the load resistance to the OFF
transistor. Thus the value of RB1 must be large enough as compared with the collector
resistance RC1. But for regeneration to exist the value of RB1 must be less than hfeRC.
i.e. RB1 << hfe.RC1 … (8.10)
Further for the transistor to remain in saturation the condition given in equation
(8.5) may be written as:
I
I B2 > C 2
h fe
V CC − V B 2( Sat ) V BB + V B 2 ( Sat )  1 V CC − V CE 2 ( Sat ) V BB + V CE 2 ( Sat ) 
 −  >>  − 
 R C1 + R 2 R2  h fe  RC 2 R1 + R B 2 
…(8.11)
The collector voltage VC1 of the off transistor is given by:
VC1 = V BE 2 ( Sat ) + R B1 I 3
 VCC − VB 2( Sat ) 
= VBE 2( Sat ) + R B1  
 RC 1 + R 2 
 VCC RB1 + V B 2 ( Sat ) RC1 
=   … (8.12)
 R C1 + R 2 
The collector will swing from VC1 to VCE2(Sat) given by:
Collector swing = VC1 − VCE 2( Sat )
 VCC R B1 + VB 2( Sat ) RC1 
=   − VCE 2 ( Sat ) …(8.13)
 RC1 + R2 
From the equation (8.13), one can find the swing at the collector of either
transistor if the resistance values connected to other transistor is same.
For practical purposes the coupling resistances RB1 and RB2 are shunted with two
capacitors C1' and C 2' respectively as shown in figure 8.4. These two shunt

Fig. 8.4

245
capacitances reduce the transition time of the bistable multivibrator, which is defined as
the time interval for the transfer of conduction from one transistor to other. The
capacitors C1' and C 2' are also called the communicating capacitors.
The bistable multivibrator can also be designed with fixed bias or self bias using
only one supply as shown in figure 8.5. In this circuit the self bias is provided using a
common emitter resistance RE.

Fig. 8.5
8.2 TRIGGERING METHODS OF BISTABLE MULTIVIBRATOR
As discussed above, bistable multivibrator is to be triggered by a narrow pulse or
step voltage from stable state to other stable state. The triggering are basically are of two
types:
(1) Asymmetrical Triggering
(2) Symmetrical Triggering

8.2.1 Asymmetrical Triggering


In this method of triggering a trigger pulse of short duration is applied for the
transition of the multivibrator only in one direction. However, a separate trigger pulse is
applied from a separate source at a different place to trigger the multivibrator to other
direction. The different methods of this unsymmetrical mode of triggering will now be
discussed.

Triggering by a positive pulse to the base of transistor:

In this method of triggering a positive pulse of short duration is applied through a


capacitor C to the base of the transistor which is in saturation. The schematic diagram of
such triggering method is shown in figure 8.6. At the leading edge of the trigger pulse the
capacitor C will starts charging through the resistance RS of the source. When the voltage
across C becomes equal to the pulse amplitude, the capacitor will act as short circuit and
at the trailing edge of the pulse, negative voltage appears at the base of the ON transistor
and the bistable multivibrator triggers. It may be noted that the triggering in this occurs at
the trailing edge of the pulse.

246
Fig. 8.6
Triggering by a negative pulse to the collector of transistor:
In this method of triggering a negative going pulse is applied to the collector of
the transistor which is in cutoff. The circuit arrangement to this method is shown in figure
8.7. When a negative going pulse is applied to the collector of OFF transistor, then this
pulse goes to the base of the ON transistor through the communicating capacitor. The
triggering will, therefore, occur at the leading edge of the pulse itself.

Fig. 8.7
Another method of triggering by a positive pulse:
The triggering can also be done through the additional transistors. The transistors
T3 and T4 are connected in parallel with the transistors T1 and T2 respectively with their
collectors tight together and the emitters of are also connected together as shown in figure
8.8. The triggering pulse may be applied to the base of either transistor T3 and T4 through
the resistance RB. In the stable state of multivibrator one of the transistors T1 and T2 will
be OFF and the other will be ON. The triggering pulse is applied to the base of the shunt

247
transistor (T3 or T4) corresponding to the off transistor (T1 or T2). Assume that the
transistor T1 is OFF and T2 is ON. When a positive pulse is applied to the base of the
transistor T3, then this transistor conducts and its collector goes to low which triggers the
multivibrator to the other state.

Fig. 8.8

Triggering by a negative pulse through a diode:


Figure 8.9 shows another method of asymmetrical triggering with separate source.
The negative going triggering pulse is applied to the collector of OFF transistor through

Fig. 8.9

its corresponding diode and the capacitor. Let us assume that the transistor T1 is ON and
T2 is OFF. In this condition the diode will be in reverse bias by the voltage drop across the
resistance RC1. The triggering pulse will not be transmitted to the base of the other
transistor unless the pulse is negative and its amplitude is greater than the voltage across
the resistance RC1. If the transistor T1 is OFF, the voltage drop across the diode D1 will be

248
zero and a negative going pulse will be transmitted to the base of other transistor T2 and
thus triggers the multivibrator. The resistor R3 and R4 act to discharge the capacitors C1
and C2 between the trigger pulses.
8.2.2 Symmetrical Triggering
In symmetrical triggering to bistable multivibrator, triggering pulse from a single
source is applied to the circuit. In this case each successive triggering pulse causes the
transition from one state to other.
Symmetrical triggering by negative pulse to the collectors through the diode:
Figure 8.10 shows the circuit arrangement for such symmetrical triggering. Let us
assume that the transistor T1 is ON and transistor T2 is OFF. In this condition the collector
voltage of transistor T1 will be low due to which the diode D1 will be in reverse bias and
it will not transmit the negative trigger pulse. But the diode D2 will be in forward bias and
thus transmit the negative trigger pulse to the base of transistor T1 through RB2 and C 2'
combination and transistor T1 will be ON and T2 will be OFF. In this condition the
negative trigger pulse will be transmitted to the base of the transistor T2 as the diode D1
will be in the forward bias. The diodes D1 and D2 are known as steering diodes. If the
triggering rate is high the diode D3 helps in removing the charges accumulated on the
capacitors C1' or C 2' as diode D3 will in reverse bias during the trigger pulse and it will
conduct after the pulse.

Fig. 8.10

Symmetrical triggering by positive pulse to the collectors through the additional


transistor amplifiers:
In this symmetrical triggering method two additional transistors T3 and T4 are
connected in parallel with the transistors T1 and T2 respectively as shown in figure 8.11.
When a positive pulse is applied through the capacitor C to the bases of transistors T3 and
T4, both the transistors conduct and the triggering pulse gets transmitted through RB1 or
RB2 depending upon the corresponding transistor T1 or T2 is OFF.

249
Fig. 8.11
Example 8.1. The bistable multivibrator shown in figure 8.11(a) has the following
circuit parameters:
VCC = 15V, VBB = 5 V, RC1 = RC2 = 1.2KΩ, RB1 = RB2 = 5KΩ, R1 = R2 = 12 KΩ
and hfe of the transistors is 50.
Verify that one transistor is in saturation and other is in cut-off.

Fig. 8.11(a)
Solution. Consider that the transistor T1 is OFF and T2 is ON, then the current I1 flowing
through the collector resistance RC2 is given by (assume VCE(Sat) = 0.2 for silicon transistor
ref. figure 8.2):
V − VCE 2( Sat )
I1 = CC
RC 2
15 − 0.2
= mA = 7.33mA
1.2
The current I2 flowing through RB2 is given by:

250
V BB + VCE 2( Sat )
I2 =
R1 + R B 2
5 + 0.2
= mA = 0.31mA
12 + 5
The collector current of transistor T2 is, therefore, given by:
I C 2 = I 1 − I 2 = 7.33 − 0.31 = 7.02mA
The current I3 flowing through the resistance RB1 is given by (assume VB(Sat) =
0.8V):
VCC − VB 2 ( Sat )
I3 =
RC1 + R2
15 − 0.8
= mA = 1.08mA
1.2 + 12
The current I4 flowing through the resistance R2 is given by:
VBB + V B 2 ( Sat )
I4 =
R2
5 + 0.8
= mA = 0.48mA
12
The base current of transistor T2 is, therefore, given by:
I B 2 = I 3 − I 4 = 1.08 − 0.48 = 0.6mA
The condition that the transistor T2 to remain in saturation is:
I
I B2 > C 2
h fe
7.02
0.6mA > mA
50
0.6mA > 0.1404mA
Hence the condition that one transistor is ON and other transistor is OFF, is
verified.
8.3 MONOSTABLE MULTIVIBRATOR
The Monostable multivibrator circuit has one stable state and one meta-stable or
quasi-stable state. The circuit will remain to be in the stable state and after the application
of trigger pulse the transition from the stable state to quasi-stable state will take place.
The circuit will remain in the quasi-state for some time (fixed time delay) and will then
return back to the original stable state. Monostable multivibrator is also called one shot,
or single shot multivibrator.
Monostable multivibrator designed with the transistors as active devices, are
classified into the following categories:
1. Collector Coupled Monostable Multivibrator
2. Emitter Coupled Monostable Multivibrator
8.3.1 Collector Coupled Monostable Multivibrator
Figure 8.12 shows the circuit diagram of collector coupled monostable
multivibrator which is similar to that of bistable multivibrator except that one of the
resistances in the feedback path has been replaced by a capacitance C and also the base of

251
the transistor T2 is connected to the positive supply voltage through a resistance R. The
base of the transistor T1 is connected to – VBB.

Fig. 8.12
Since the base of the transistor T2 is connected to the positive supply through the
resistance R, so this transistor will saturate. The collector voltage VC2 of T2 will be low
(VCE(Sat)), due to which the transistor T1 will be in cut-off. Thus T1 is OFF and T2 is ON, is
the stable state of the circuit. In this steady state no current will flow through the
capacitor C. Now when a negative trigger pulse is applied to the collector of transistor T1,
it reaches the base of the transistor T2 through the capacitor C. This cuts off the transistor
T2 and transistor T1 goes into saturation. The voltage VC1 will be low ( ≈ VCE (Sat ) ) and VC2
will be high ( ≈ VCC ). This is not a stable state. The negative change in the collector
voltage of T1 will be transmitted to the base of T2 through the capacitor C. Now the
capacitor C will starts charging through the resistance R; as the collector end of C is low
and the other end of C is connected to VCC through R. The base voltage of T2, therefore,
rises exponentially. As soon as the base voltage of T2 becomes equal to VBE(Sat), the
transistor T2 becomes ON and the circuit return to its original state i.e. T1 OFF and T2 ON.
The time delay after which the circuit returns to its stable state will depend on the
charging time of the capacitor C, i.e. it will depend on RC time constant. Now we shall
calculate this time delay.
The voltage waveforms of the monostable multivibrator at different points are
shown in figure 8.13. From this figure it is clear that the stable state of the circuit is
transistor T2 ON and T1 OFF i.e. VC 2 ≈ VCE ( Sat ) and VC1 ≈ VCC . Due to which VB2 is equal to
VBE(Sat). Now when the trigger pulse is applied, the voltage VB2 becomes negative and
goes to – VCC. The voltage VC2 becomes high (VCC) and VC1 goes low (VCE(Sat)). The
voltage VB2 starts charging exponentially, and as soon as VB2 becomes equal to VBE(Sat),
the circuit returns to its stable state. The time duration for which the collector voltage of
T2 is high after the application of trigger pulse will be fixed for the given circuit
parameters. Thus this circuit can be used to get standardized pulse for each trigger pulse.

252
Fig. 8.13
Calculation of time duration of quasi-stable state:
It is well known that the transistor T1 is OFF and T2 is ON for the stable state of the
multivibrator. The base current IB2 of the transistor T2 is given by:
VCC − VBE ( Sat )
I B2 = … (8.14)
R
Transistor T2 to be in the saturation h fe I B 2 should be greater than maximum
VCC
collector current I C max . The maximum value of collector current will be .
RC 2
VCC
So h fe I B 2 > I C max = … (8.15)
RC 2
By the application of trigger pulse, the transistor T1 becomes ON. The collector
voltage VC1 falls from VCC to VCE(Sat).
The base voltage will also fall by the same amount,
i.e. VBE2 falls from VBE (Sat ) to V BE ( Sat ) − (V CC − V CE ( Sat ) )
= V BE ( Sat ) − VCC + VCE ( Sat )
The base emitter voltage of transistor T2 will now be
VBE = −VCC + VBE ( Sat ) + VCE ( Sat ) … (8.16)
This voltage is also connected to the base end of the capacitor C (as shown in
figure 8.14). This capacitor will also start charging from VBE to VCC
The voltage across the capacitor is approximately equal to VBE2 which is given by:

253
Fig 8.14

VBE 2 = VCC − VCC e −t RC + (− VCC + VBE ( Sat ) + VCE ( Sat ) ).e −t RC … (8.17)
Let RC = τ
So VBE2 = VCC + (− 2VCC +VBE(Sat) +VCE(Sat) ).e−t τ … (8.18)
Let at t = T (pulse width), VBE2 becomes equal to VBE(Sat).
So { } ( )
VBE ( Sat ) − VCC = − 2VCC + VBE ( Sat ) + VCE ( Sat ) .e −T τ … (8.19)
 2VCC − VBE( Sat) − VCE( Sat) 
or eT τ =  
 V − V 
 CC BE( Sat ) 
T  2VCC − VBE ( Sat ) − VCE ( Sat ) 
or = ln 
τ  V − V 
 CC BE ( Sat ) 
 2VCC − VBE ( Sat ) − VCE ( Sat ) 
or T = τ ln  … (8.20)
 V − V 
 CC BE ( Sat ) 
This is the expression for time duration of quasi-stable state of the multivibrator.
If VBE (Sat ) and VCE (Sat ) are neglected then this expression may be approximated as:
T = τ ln(2)
T = RC ln (2 ) = 0 . 69 RC … (8.21)
The time interval T is called the delay time, the gate time, pulse width or pulse
duration. This delay may be varied by varying the time constant RC.
Example 8.2. Consider the monostable multivibrator shown in figure 8.12 having the
following parameters:
VCC = 15V, RC1 = RC2 = 4.7 KΩ, R = RB2 = 33KΩ, C = 0.1µf, R1 = 1KΩ and VBB = – 5V.
Calculate the pulse width if VBE(Sat) = 0.8 V, VCE(Sat)=0.2 V for the transistor.
Solution. The expression of pulse is given by:
 2VCC − V BE ( Sat ) − VCE ( Sat ) 
T = RC ln 
 V − V 
 CC BE ( Sat ) 
 2 x 15 − 0 .8 − 0.2 
= 33x10 3 x0.1x10 −6 ln 
 15 − 0.8 
 29 
= 3.3x10 −3 ln  = 3.3 x10 ln 2.04
−3

 14.2 
= 3.3x10 ln 2.04 = 3.3x10 −3 x0.714
−3

= 2.36m sec

254
8.3.2 Emitter Coupled Monostable Multivibrator

An alternative form of monostable multivibrator is the emitter coupled


monostable multivibrator as shown in figure 8.15. In this circuit coupling from the
collector of transistor T2 is removed and instead a feedback has been provided through
the common emitter resistance RE. The negative supply is, therefore, not needed. The
signal at the collector of transistor T2 is not directly involved in the regenerative loop.
Hence this collector makes an ideal point to take output waveforms.
In the stable state, transistor T2 is in saturation and transistor T1 is OFF. On the
application of negative trigger pulse at the collector of transistor T1 through a capacitor
C2, the transistor T2 goes into active region thereby reducing the voltage VE across the
common emitter resistance RE. The base emitter voltage of transistor T1 will therefore go
on increasing which will force the transistor T1 to conduct. This is regenerative process
with both the transistors operating in the active region; it will ultimately force the
transistor T1 in the ON state (saturation). This state is not the stable state rather it is a
quasi-stable state and finally the circuit will reach to its initial stable state. The collector
end of Capacitor C is approximately at zero potential and the other end is at the base
voltage of transistor T2 which is equal to VBE(Cutoff). Now the capacitor C will start
charging through the resistance R and the base voltage of the transistor T2 will increase
and thus another regenerative feedback will take place and finally the T2 becomes ON and
T1 OFF.

Fig. 8.15

The voltage waveforms of this emitter coupled monostable multivibrator are


shown in figure 8.16.

255
Fig. 8.16

8.4 ASTABLE MULTIVIBRATOR

The astable multivibrator is very commonly used to generate square wave. It is also

Fig. 8.17

known as free running multivibrator. This circuit does not have any stable state. It
continuously moves from one state to other and never stays in the stable state. The
typical circuit diagram of this multivibrator is shown in figure 8.17. The operation of this
circuit can be explained as follows:

256
Fig. 8.18
Suppose at time t1, the transistor 1 has just switched from OFF state to ON state,
the collector voltage VC1 will fall from VCC to VCE(Sat). This change in collector voltage of
transistor 1 gets transmitted to the base of transistor 2 through the coupling capacitor C1.
The transistor 2 thus goes into cut-off. The collector end of the capacitor C1 is at VCE(Sat)
and the other end of this capacitor is connected to the base of the transistor 2 which is at
(–VCC) voltage. Now this capacitor starts charging through the resistance R1 to +VCC
voltage (the total charging voltage is +2VCC). The base voltage VB2 of transistor 2 rises
from –VCC to +VCC. As soon as this base voltage VB2 becomes equal to VBE(Sat) the
transistor 2 goes into saturation. Now the transistor 2 changes from OFF state to ON state,
so the collector voltage VC2 of the transistor 2 changes from VCC to VCE(Sat). This change
will be transmitted to the base of the transistor 1 through the capacitor C2. The same
operation thus happens with the base of the transistor 1, giving the continuous oscillations
as shown in figure 8.18. The wave forms at the base of the transistors 1 and 2 are also
shown in this figure.
The period of oscillations or the frequency of oscillations can also be calculated
as given below:
When the transistor 1 changes the state from OFF to ON, the transistor 2 goes in to
cutoff and voltage at base of the transistor 2 will be low. The capacitor C1 starts charging
to VCC through the resistance R1.

257
The voltage across the capacitor is equal to VBE2 which is given by:
V BE 2 = V CC − V CC e − t R1C1 + (− V CC + V BE ( Sat ) + V CE ( Sat ) ).e − t R1C1 … (8.22)
Let R1C1 = τ 1
So VBE2 = VCC + (− 2VCC +VBE(Sat) +VCE(Sat) ).e−t τ1 … (8.23)
Let at t = T 1 (pulse width), VBE2 becomes equal to VBE(Sat).
So {V BE ( Sat ) − V CC } = (− 2V CC + V BE ( Sat ) + V CE ( Sat ) ).e −T1 τ1
… (8.24)
 2VCC − VBE( Sat) − VCE( Sat) 
or eT1 τ1 =  
 V − V 
 CC BE( Sat ) 
T1  2VCC − VBE ( Sat ) − VCE ( Sat ) 
or = ln 
τ1  V − V 
 CC BE ( Sat ) 
 2VCC − VBE ( Sat ) − VCE ( Sat ) 
T1 = τ 1 ln 
or  VCC − VBE ( Sat )  … (8.25)
 
Similarly, when the transistor 2 changes the state from off to on, the time period
T2 may be calculated and it is given by:
 2VCC − VBE ( Sat ) − VCE ( Sat ) 
T2 = τ 2 ln  … (8.26)
 V − V 
 CC BE ( Sat ) 
where τ 2 = R2 C 2
The total time period is given by:

 2VCC − V BE ( Sat ) − VCE ( Sat )   2V − V BE ( Sat ) − VCE ( Sat ) 


T = T1 + T2 = τ 1 ln  + τ 2 ln CC 
 V − V   V − V 
 CC BE ( Sat )   CC BE ( Sat ) 
 2VCC − V BE ( Sat ) − VCE ( Sat ) 
= (τ 1 + τ 2 ) ln  … (8.27)
 V − V 
 CC BE ( Sat ) 
If VCE(Sat) and VBE(Sat) are negligibly small, this equation reduces to:
T = (τ 1 + τ 2 ) ln(2)
Further, if τ 1 = τ 2 = RC , the total time period is given by:
T = 2 RC ln(2) = 1.38 RC … (8.28)
And the frequency of oscillation is given by:
1 1
f = = … (8.29)
2 RC ln(2) 1.38RC
This is the expression for frequency of oscillation of this square wave generated
by the astable multivibrator.
Example 8.3 In the astable multivibrator circuit shown in figure 8.17, calculate the
frequency of oscillations if the circuit parameters are as given below:
VCC =+ 12 V, R1 = R2 = R = 47 KΩ, RC1 = RC2 = 10 KΩ and C1 = C2 = C = 0.01 µf.
For the transistor VBE(Sat) = 0.8 V, VCE(Sat)=0.2 V.

258
Solution. The time period for the oscillations is given by:
 2VCC − V BE ( Sat ) − VCE ( Sat ) 
T = 2 RC ln 
 V − V 
 CC BE ( Sat ) 
 2 x12 − 0.8 − 0.2 
= 2 x 47 x10 3 x 0.01x10 − 6 ln 
 12 − 0.8 
 23 
= 0.94 x10 −3 ln −3
 = 0.94 x10 ln(2.05)
 11 .2 
−3
= 0.94 x10 x 0.72 = 0.6768x10-3 Sec
The frequency of oscillations is given by:
1 1
f = = x10 3
T 0.6768
= 1.48KHz
8.5 COMPARATOR
A comparator is circuit which compares the input voltage with a known voltage
known as reference voltage or threshold voltage. The operational amplifier with open
loop mode may be used as a comparator. The comparator circuit is shown in figure 8.19,
in which the input voltage Vi to be compared with threshold voltage VT is applied to the
non-inverting input of an operational amplifier. Since the operational amplifier is used in
open loop mode so the output voltage will either be Vmax or – Vmax depending on the
terminal voltage V of the operational amplifier. If the input voltage Vi applied to the non-
inverting input is slightly greater than the reference voltage VT then the terminal voltage
of the operational amplifier will be a small positive voltage. This corresponds to an
output Vmax as V0 = AV where A is the open loop gain of the amplifier which is infinitely
large for an ideal operational amplifier; so output saturates. If on the other hand input
voltage Vi is slightly less than the threshold voltage VT, then the terminal voltage V will a
small negative voltage and output will saturate to – Vmax. The transfer characteristic of an
ideal comparator is shown in figure 9.19(b), in which there is a discontinuity when the
dV0
input voltage is equal to the threshold voltage. In other words, the incremental gain
dVi

(a) (b)

259
(c) Fig. 8.19
will tend to infinity. The transfer characteristic of practical comparator using the practical
operational amplifier will be as shown in figure 8.19(c). There is a region W known as
window of the comparator, where the amplifier does not produce the saturated output. In
this region the comparator is not suitable in illustrating if the input voltage is less than or
greater than the threshold or reference voltage VT. For the good comparator the width of
the window should be as small as possible. This width is controlled by the open loop gain
of the operational amplifier.
If the sinusoidal signal is applied to the non-inverting terminal of the operational
amplifier, then the output will be a square wave as shown in figure 8.20. When the input
is less than VT the output is – Vmax and when it is greater than VT the output is +Vmax.

Fig. 8.20

If the reference voltage is set to zero in the comparator circuit, then the circuit is
called as the zero crossing detector. The output of this circuit will be square wave if the
input is either sinusoidal or triangular wave. Figure 8.21 (a) shows the circuit of zero
crossing detector and input output waveforms are shown in figure 8.21(b). This circuit is
also called as square wave generator.

260
(a) (b)
Fig. 8.21
Although an operational amplifier can be used as the comparator, but the
operational amplifier of high slew rate is good for its use as a comparator. The slew rate
is the maximum rate of change of output voltage with time. The output will therefore
swing instantaneously from one saturation level to other corresponding to the input
signal. Specially designed comparators ICs are now available such as µA 710, LM 339
etc.

8.6 SCHMITT TRIGGER


Consider the circuit shown in figure 8.22(a), in which the input voltage Vi is
applied to the inverting input and a feedback arrangement is made using the resistances
R1 and R2. In this circuit there is positive feedback. Assume that the loop gain is greater
than unity. Due to regeneration in the circuit the output will saturate giving the output
either +Vmax or –Vmax. If +Vmax is the output then +βVmax will be the threshold voltage and
the input voltage Vi will be compared by this threshold voltage; and if on the other hand
–Vmax is the output voltage then the threshold voltage will be –βVmax, now the input
voltage will be compared by this threshold voltage. The β is the feedback factor. So there
will be two threshold voltages +Vmax known as the upper (or higher) threshold voltage
and the other as lower threshold voltage –Vmax.
Suppose the low negative voltage, the output will be small positive voltage and
due to regeneration the output saturates and gives an output +Vmax and the threshold
voltage (higher) will be given by:
R2
VTH = Vmax = β .Vmax … (8.30)
R1 + R2
where β is the feedback factor given by:
R2
β= … (8.31)
R1 + R2

261
(a)

Fig. 8.22

Now the input will be compared by this threshold voltage. If the input is increased
the output will be +Vmax, till input is less than this threshold voltage. If the input is
increased beyond +βVmax , the output saturates to –Vmax. This variation is illustrated in
figure 8.22(b). The threshold voltage (lower) will now be given by:
R2
VTL = − Vmax = − β .Vmax … (8.32)
R1 + R2
If the input is decrease the output will be –Vmax, till input is greater than this
threshold voltage. If the input is decreased beyond –βVmax , the output saturates to +Vmax.
This variation is illustrated in figure 8.22(c).
The transfer characteristic of this circuit is like the hysteresis curve as shown in
figure 8.22(d). The difference VD between the threshold voltages is given by:
 R2   R2 
VD = VTH − VTL =  Vmax  −  − Vmax 
 R1 + R2   R1 + R2 

262
 2 R2 
=  Vmax  … (8.33)
 R1 + R2 
This difference may be changed by changing the values of resistances R1 and R2.
This circuit is known as Schmitt trigger circuit. It converts the sinusoidal signal of
frequency f to symmetrical square wave as shown in figure 8.23.

Fig. 8.23
Example 8.4. The Schmitt trigger circuit of figure 8.22(a) has the following parameters:
R1 = 200 KΩ, R2 = 100 and Vi is the sinusoidal wave of 1.5 V (pp). The saturation
voltage for the operational amplifier is ± 15 V. Determine the lower and upper threshold
voltages of the Schmitt trigger circuit.
Solution. The upper threshold voltage is given by:
R2
VTH = Vmax
R1 + R2
100
= x15
(200 x10 3 + 100)
= 7.5mV
The lower threshold voltage is given by:
R2
VTL = − Vmax
R1 + R2
100
=− x15 = −7.5mV
(200 x10 3 + 100)
8.7 ASTABLE MULTIVIBRATOR USING AN OPERATIONAL AMPLIFIER
The circuit diagram of astable or free running multivibrator using an operational
amplifier is shown in figure 8.24. It is also called square wave generator. The operational
amplifier used in this circuit operates in the saturation region. So the output may either be
+Vmax or –Vmax. The feedback voltage VT also known as the threshold voltage is applied to
the non-inverting input of the operational amplifier. It may be given by:
R2
VT = ± Vmax = ± β .Vmax … (8.34)
R1 + R2

263
where β is the feedback factor given by:
R2
β= … (8.35)
R1 + R2

Fig. 8.24
The output voltage is also fed back to the inverting terminal through the RC
combination. Whenever input at the inverting terminal becomes greater than the threshold
voltage VT, switching action takes place giving the square wave output.

Fig. 8.25

Consider for instance the output is at +Vmax. The non-inverting terminal is at


+βVmax. The capacitor C now starts charging through the resistance R and thus the voltage
across the capacitor increases and as soon as this voltage exceeds +βVmax, the threshold
voltage at the non-inverting terminal, the output changes the state from +Vmax to –Vmax. At
this instant the voltage at the capacitor will be +βVmax. Now the capacitor C starts

264
discharging through the resistance R and thus when this voltage more negative than
–βVmax, the output changes the state and gets the previous state. This way cycle repeats
and output will be the square wave. The waveforms of this circuit at the output, non-
inverting and inverting terminals are shown in figure 8.25.
The frequency of the square wave generated in this circuit will now be calculated.
Let us assume initially output voltage is +Vmax, and voltage at the inverting input is
–βVmax (this is the initial voltage at the capacitor). The voltage at the non-inverting
terminal is +βVmax. The capacitor will now start charging through the resistance R to
+Vmax. The voltage VC across the capacitor is then given by:
 (−
t
)  ( − RCt ) 
 − β .Vmax  e

VC = Vmax 1 − e RC   

   
t
(−
= Vmax − Vmax (1 + β )e
)
RC
… (8.36)
At time t = T1 , the voltage across the capacitor reaches to +βVmax.
T1
(−
β .Vmax = Vmax − Vmax (1 + β )e
)
RC
So
T1
(−
Vmax (1 + β )e = Vmax (1 − β )
)
RC
or
1+ β 
T
( 1 )
or e RC
=  
1− β 
1+ β 
or T1 = RC ln  … (8.37)
1− β 
Now the output voltage will be –Vmax, and voltage at the inverting input is +βVmax
(this is the initial voltage at the capacitor). The voltage at the non-inverting terminal is
–βVmax. The capacitor will now start discharging through the resistance R to –Vmax. The
voltage VC across the capacitor is then given by:
 (−
t
)  (− t ) 
VC = −Vmax 1 − e RC  + β .Vmax  e RC 
   
t
(−
= −Vmax + Vmax (1 + β )e
)
RC
… (8.38)
At time t = T2 , the voltage across the capacitor reaches to –βVmax.
T2
(−
− β .Vmax = −Vmax + Vmax (1 + β )e
)
RC
So
1+ β 
T2
( )
or e RC
=  
1− β 
1+ β 
or T2 = RC ln  … (8.39)
1− β 
The total time T will now be given by ( using equations 8.38 to 8.39):
1+ β 
T = T1 + T2 = 2 RC ln  … (8.40)
1− β 

265
Put the value of feedback factor β from (8.35) in this equation (8.40), we get:
 2R 
T = 2 RC ln1 + 2  … (8.40)
 R1 
The frequency of oscillations will then be given by:
1 1
f = = … (8.41)
T  2 R2 
2 RC ln1 + 
 R1 
It is clear from this equation that the frequency of oscillation depends only on the
external components.

Example 8.5 The astable multivibrator shown in figure 8.24 has the following
parameters: R1 = 100 Ω, R2 = 100KΩ, R = 10KΩ and C = 0.01 µf.
Find the frequency of oscillations of this multivibrator.

Solution. The frequency of oscillation for this case is given by:


1
f =
 2R 
2 RC ln1 + 2 
 R1 
1
=
 2 x100 x10 3 
2 x10 4 x0.01x10 −6 ln1 + 
 100 
5000 5000
= =
ln(2001) 7.6
= 658Hz

8.8 MONOSTABLE MULTIVIBRATOR USING AN OPERATIONAL


AMPLIFIER

Monostable multivibrator can be designed using the operational amplifier. Such a


circuit is shown in figure 8.26. As it is well known that the monostable multivibrator has
one stable state and a quasi stable state and when a trigger pulse is applied the circuit
moves from the stable state to the quasi stable state and after some time it return back to
the original stable state. In the stable state of the circuit the amplifier gets saturated and
the output will be +Vmax. In this condition the inverting terminal of the amplifier will be
clamped at 0.7V by the diode D1. The non-inverting terminal will be at VT = +βVmax
potential, which is supposed to be greater than 0.7V. So the voltage V between the
terminals of the operational amplifier will negative, giving the saturated output (+Vmax).
The β is the feedback factor given by:
R2
β= … (8.42)
R1 + R2

266
Fig. 8.26
The combination of capacitor C1 and resistor R3 form a differentiator circuit.
When a negative going pulse is applied to the capacitor C1, a negative impulse signal is
formed across the resistor R3 which is applied to the non-inverting of the amplifier
through the diode D2.This diode also avoids any positive spikes to go to the non-inverting
terminal. The value of resistance R3 is chosen to be greater than R2 to eliminate the
loading. Due to the negative impulse, the voltage at the non-inverting terminal of the
amplifier goes down to even less than 0.7V. The terminal voltage V of the amplifier
becomes positive which switches the output from +Vmax to –Vmax. The diode D1 will now
be in the reverse bias and the capacitor C will starts charging to –Vmax through the
resistance R. The voltage at the non-inverting terminal of the amplifier will be at –βVmax.
Now as soon as the voltage at the capacitor C becomes more negative than –βVmax, the
operational amplifier goes back to the original stable state giving the output voltage
+Vmax. The waveforms at various points of the monostable multivibrator are shown in
figure 8.27.
The time duration for which the circuit remains in the quasi – stable state, known
as pulse width will now be calculated.
During the stable state of this circuit, the voltage at the capacitor C is 0.7V (it is
initial voltage of the capacitor). After the application of trigger pulse, the output goes to
–Vmax. The capacitor C will start charging to –Vmax voltage through the resistance R. So
the capacitor voltage VC is given by:
 (−
t
)  (− t ) 
VC = −Vmax 1 − e RC  + VD  e RC  … (8.43)
   
where VD = 0.7V , the forward voltage drop of the diode D1 (or the initial
voltage of the capacitor).

267
Fig. 8.27

At time t = T1 , the capacitor voltage becomes –βVmax, so from equation 8.43 we


get:
 (−
T
)  ( − RC
T
)
− β .Vmax 
= −Vmax 1 − e RC 
 + V D

 e 

   
T
(−
(1 − β )V max = (V max + V D )e
)
RC
or
 V D  ( − RC )
T
or (1 − β ) =  1 +  e
 V max 
 V 
T
 1 + D 
V max 
e RC = 
( )
or
(1 − β )
 V 
 1 + D 
V max 
or T = RC ln  … (4.44)
(1 − β )
This is the expression of pulse width during which the circuit remains in the
quasi-stable state. For the monostable operation, the width of the trigger pulse should be
less than T.
If VD << Vmax , then we have:
1
T = RC ln … (4.45)
(1 − β )
From equations (4.42) and (4.45), we obtain:

268
 R 
T = RC ln  1 + 1  … (4.46)
 R2 
If R1 = R2 , then T = RC ln( 2 ) = 0 . 69 RC
8.9 TRIANGULAR WAVEFORM GENERATOR
Figure 8.28 shows a very simple circuit for generating the triangular waveforms.
It consists of a comparator and an integrator circuit. The output of the integrator is
applied to the non-inverting terminal of the first operational amplifier through the
resistance R2. This connection produces two threshold voltages for the comparator,
giving square waves at its output of amplitude of ± Vmax . The square waves applied to the
inverting terminal of the second operational amplifier used as integrator finally produces
the triangular waveform.

Fig. 8.28
To understand the operation of this circuit consider that initially the output of the
comparator is + Vmax corresponding to which integrator gives the negative going output.
Thus one end of the potential divider comprising R1 and R2 is at + Vmax and the other end
is at the negative going ramp. The voltage VP at the point P will be given by:
 R2 
VP = −Vr +  [Vmax − (−Vr )]
R
 1 + R 2 

 R2 
= −Vr +  [Vmax + Vr )] … (8.47)
 R1 + R2 
where Vr is the ramp voltage generated at the output of integrator.
As the negative going ramp attains such a value so that the voltage at the point P
becomes slightly less than zero, the output of first operational amplifier changes the state
from + Vmax to − Vmax . So let us assume that at time t = t1 , the voltage VP is zero as:
 R2 
0 = −Vr +  [Vmax + Vr )]
 R1 + R2 

 R2   R2 
Vr 1 −  =  Vmax
 R1 + R2   R1 + R2 

269
Vr R1 = R2Vmax
R2
− Vr = − Vmax … (8.48)
R1
Now at the output of the integrator we get the positive going ramp and as soon as
this ramp attains such a value so that the voltage at the point P becomes slightly greater
than zero, the output of first operational amplifier changes the state from − Vmax to
+ Vmax . So let us assume that at time t = t 2 , the voltage VP is zero and similarly we get:
R2
Vr = Vmax … (8.49)
R1
Thus peak to peak output amplitude of the triangular wave is:
2 R2
V0 ( pp) = Vmax … (8.50)
R1
The time for the integrator output to swing from − Vr to + Vr is (T 2 ) . This time
can be calculated from the integrator equation given by:
T 2
1
RC ∫0
V0 ( pp) = − Vi dt

where Vi = −Vmax .
T 2

∫ (− V )dt
1
So V0 ( pp) = − max
RC 0

Vmax  T 
=   … (8.51)
RC  2 
 V ( pp) 
or T = 2 RC  0  … (8.52)
 Vmax 
Put the value of V0 ( pp) from equation (8.50) in equation (8.52), we have
4 RCR2
T=
R1
The frequency of oscillations is given by:
1 R1
f = = … (8.53)
T 4 RCR2
The waveform of this circuit is shown in figure (8.29).

270
Fig. 8.29

Another method of producing triangular waveforms is shown in figure 8.30, in


which square waves are generated by an astable multivibrator rather than the comparator
circuit as discussed above. The first operational amplifier is the astable multivibrator and
the second circuit forms a practical integrator.

Fig. 8.30
8.10 TIMER IC 555
The timer IC 555 is a most popular and commonly used monolithic IC. It was first
introduced by Segnetics and can be used to provide many important applications
including the introduction of an accurate time delay ranging from microseconds to hours.
It can be wired both in both monostable and astable modes. This IC 555 is reliable, easy
to use and economical having good temperature stability; it can be operated on +5 to
+18V d. c. supply.
Figures 8.31(a) and (b) show the pin diagram and inside simplified functional
diagram of this IC respectively. It is available both in TO-99 can and 8-pin DIP. The 8
pin diagram is shown in figure 8.31(a). It can be noted from the functional block diagram
(ref. figure 8.31b) that there are three equal resistances of 5KΩ each forming an internal

271
2
potential divider arrangement. It provides (+ VCC ) to the inverting terminal of first
3
operational amplifier, being used as the comparator; the voltage + VCC is the supply

Fig. 8.31(a)

Fig. 8.31(b)
voltage. This pin is known as control input as it contains the control voltage. The control
input (pin 5) is not used in most of its applications. The inverting terminal (pin 6) of the
first operational amplifier is known as threshold terminal. Whenever the threshold
voltage becomes slightly greater than the control voltage, this operational amplifier gives
high output which sets the RS flip-flop. The non-inverting terminal of the second
1
operational is kept at (+ VCC ) potential by the internal potential divider. However, the
3
inverting terminal (pin 2) of this operational amplifier is known as the trigger pin,

272
1
whenever the trigger input is slightly less than (+ VCC ) , the operational amplifier gives
3
the high output which resets the flip-flop.
The collector of the transistor in the internal diagram is known as the discharge
terminal (pin 7), which is normally connected externally to the timing capacitor. The
output of the flip-flop will force the transistor to be either in cutoff or saturation. When
the transistor saturates it discharges the timing capacitor and when it is in cutoff it
charges the capacitor. The Q terminal of the flip-flop is used as the output (pin 3). There
is an external pin provided known as reset terminal (pin 4), which when connected to
ground terminal it inhibits the IC. Normally it is connected to the supply voltage.
Now we shall discuss some of its important applications.
8.10.1 Monostable Operation
Figures 8.32 (a) shows the monostable operation of 555 timer in the form of
functional block diagram. Figure 8.32(b) shows its pin connection. The waveforms for
this mode of operation are shown in figure 8.32(c).

(a) (b)

(c) Fig. 8.32

273
The working of the timer IC 555 as the monostable operation can be understood
by referring to these figures. A low going trigger signal is applied to the trigger input
1
(pin 2) of the IC. When the trigger input is slightly less than (+ VCC ) , the second
3
operational amplifier gives high output and resets the RS flip-flop. The Q output of the
flip-flop will be low and it takes the discharge transistor into cutoff, which allows the
capacitor to start charging. The voltage across the capacitor increases and as soon as this
voltage (it is also the threshold voltage at the non-inverting terminal of the first
2
operational amplifier) becomes greater than (+ VCC ) , the output of first operational
3
amplifier goes high and sets the flip-flop. Now as the flip-flop is set, the discharge
transistor saturates which quickly discharges the capacitor C. The waveforms shown in
figure 8.32 (c) clearly verify the operation.
The pulse width for the output to remain high will be equal to the time taken to
2
reach the capacitor voltage to (+ VCC ) . The pulse width may be calculated as follows:
3
The capacitor C charges to + VCC voltage through the resistance R, so the
capacitor voltage VC is given by:
 −
t


VC = VCC 1 − e RC 
… (8.54)

 
2
At time t = T (pulse width), the capacitor voltage VC becomes equal to (+ VCC ) ,
3
2  −
T

so V CC = V CC  1 − e RC  … (8.55)
3  
T
− 2 1
or e RC = 1 − =
3 3
T
or e RC = 3
or T = RC ln(3) = 1.1RC … (8.56)
This is the expression for pulse width for the monostable operation and it clearly
indicates that this pulse width in independent of the supply voltage.
8.10.2 Astable Operation
Figures 8.33 (a) shows the astable operation of 555 timer in the form of functional
block diagram. Figure 8.33 (b) shows its pin connection. The waveforms for this mode of
operation are shown in figure 8.33 (c).
If we compare the circuits of astable operation with the circuit for monostable
operation, we seen a resistance R2 is connected between the pin 6 and 7 in the circuit of
astable operation. In this operation the trigger pin is also connected to pin 6 (threshold
terminal). So when the transistor is in cutoff the capacitor C charges to the voltage VCC
through the resistances R1 and R2. Similarly, when the transistor is in saturation the
capacitor C discharges through only the resistance R2.
The working of the timer IC 555 as the astable operation can be understood by
referring to figures 8.33 (a to c). Let us assume that initially the flip-flop is reset and

274
output Q is low due to which the discharge transistor is in cutoff. So the capacitor C starts
charging to +VCC through the resistance ( R1 + R2 ) . The capacitor voltage (threshold
2
voltage) thus increases and as soon as the capacitor voltage just exceeds (+ VCC ) , the
3
first operational amplifier gives high output which set the flip-flop and Q becomes. The
transistor saturates and the pin 7 becomes nearly at the ground potential. Now the
capacitor C starts discharging through the resistance R2. The capacitor voltage goes
1
down and as soon as it becomes less than (+ VCC ) the second operational amplifier gives
3
the high output forcing the flip-flop to reset. Thus the cycle repeats and waveforms are
given in figure 8.33(c).

(a) (b)

(c) Fig. 8.33

The output of this operation is rectangular wave which is not symmetrical; the
high state lasts longer than the low state, as the charging timing constant ( R1 + R2 )C is

275
larger than the discharging time constant R2 C . We may now calculate the frequency of
oscillation of the rectangular wave from the timings of high and low state.
The capacitor C charges to + VCC voltage through the resistance ( R1 + R2 ) , so the
capacitor voltage VC is given by:
 −
t


VC = VCC 1 − e ( R1 + R2 ) C 
… (8.57)
 
 
2
At time t = T1 , the capacitor voltage VC becomes equal to (+ VCC ) ,
3
2  −
T1

so V CC = V CC  1 − e ( R1 + R 2 ) C  … (8.58)
3  
 
or T1 = RC ln(3) = 1.09( R1 + R2 )C … (8.59)
1
The time T2 charge the capacitor from 0 to (+ VCC ) is obtained as:
3
1  −
T2

V CC = V CC  1 − e ( R1 + R 2 ) C  … (8.60)
3  
 
3
T2 = ( R1 + R2 )C ln( ) = 0.405( R1 + R2 )C … (8.61)
2
1 2
So the time to charge the capacitor from (+ VCC ) to (+ VCC ) can be obtained by
3 3
subtracting equation (8.61) from (8.59) and this will the time duration for which the
output will high. This time Thigh is given by:
Thigh = T1 − T2
= 1.09( R1 + R2 )C − 0.405( R1 + R2 )C
= 0.69( R1 + R2 )C … (8.62)
2
The low output is obtained when the capacitor discharges from (+ VCC ) to
3
1
(+ VCC ) through the resistance R2. Let Tlow is time for this charging period, which is
3
given by:

Tlow = R2 C ln(2) = 0.69 R2 C … (8.63)


Therefore, total time is given by:
T = Thigh + Tlow
= 0.69( R1 + R2 )C + 0.69 R2 C
= 0.69( R1 + 2 R2 )C … (8.64)
So the frequency of oscillations is given by:

276
1 1 1.44
f = = = … (8.65)
T 0.69( R1 + 2 R2 )C ( R1 + 2 R2 )C
Due to the asymmetry in the output wave, the duty cycle is defined as:
W
D = x100% … (8.66)
T
where W is the time during which the wave is high and T is the total time of the
wave. So put the value of W = Thigh from equation 8.62 and the value of total time T from
equation (8.64) in equation (8.66) we get:
0.69( R1 + R2 )C
D= x100%
0.69( R1 + 2 R2 )C
( R1 + R2 )
= x100% … (8.67)
( R1 + 2 R2 )
If R1 is much smaller than R2, the duty cycle approaches to 50%. The value of R1
should not be kept very much smaller otherwise internal discharge transistor will large
amount of collector current when it will be in the saturation region, which lead the
damage of the transistor consequently the timer IC.
8.10.3 Saw tooth Generator
The timer IC 555 can be wired for the generation of saw tooth wave. Such a
circuit is shown in figure 8.34(a). In this circuit the capacitor C is charged with a constant
current source. The constant current source is designed using a PNP transistor.

(a)

(b) Fig. 8.34

277
The circuit is otherwise in the monostable operation. When low going trigger
pulse is applied to the trigger input, the capacitor charges linearly with constant current
source. Therefore, the voltage across the capacitor will be a linear ramp shown in figure
8.34(b).
8.10.4 Voltage Controlled Oscillator
Figure 8.35(a) shows the circuit diagram of voltage controlled oscillator using the
timer IC 555. In this circuit an external potential dividing arrangement is used to have the
control terminal (pin 5) at desired voltage. This voltage overrides the voltage at the
control pin generated by the internal potential dividing arrangement. So by the external
potentiometer the control voltage at the control pin may be changed. The rest of the
circuit is the sane as that of astable operation. The voltage across the capacitor will
depend on the control voltage, whose waveform is shown in figure 8.35(b).

(a) (b)
Fig. 8.35

PROBLEMS

1. What is multivibrator? Draw the circuit diagram of a bistable multivibrator and


explain its operation.
2. What is difference between an oscillator and multivibrator? Draw the circuit of
bistable multivibrator and find the expression for collector swing of one transistor
used in the multivibrator.
3. Show that for the bistable multivibrator one transistor remains in the saturation and
other transistor in cutoff.
4. Discuss various methods of triggering of bistable multivibrator.
5. Discuss various symmetrical methods of triggering of bistable multivibrator.
6. What is a monostable multivibrator? Discuss the operation of collector coupled
monostable multivibrator.
7. Draw the circuit diagram of collector coupled monostable multivibrator and find the
expression for the time duration for the quasi-state of the multivibrator.
8. Discuss the operation of emitter coupled monostable multivibrator.
9. Draw the circuit diagram of an astable multivibrator and explain its operation.

278
10. Draw the circuit diagram of an astable multivibrator and find the expression for the
frequency of oscillations.
11. How can an operation amplifier be used as a comparator? What do you understand
by peak detector circuit?
12. What is Schmitt trigger circuit? How can an operational amplifier be used as
Schmitt trigger?
13. Draw the circuit of astable multivibrator using an operational amplifier. Explain its
operation.
14. Draw the circuit diagram of an astable multivibrator using operational amplifier.
Find the expression for its frequency of oscillations.
15. Draw the circuit of monostable multivibrator using an operational amplifier.
Explain its operation and find the expression for the pulse width.
16. How can triangular waveforms be generated using operational amplifier? Find the
frequency of oscillation of the triangular waves generated.
17. What is timer circuit? Draw and explain the functional block diagram of the timer
IC 555.
18. Discuss the use of IC 555 for monostable operation. Find also the expression for its
pulse width.
19. Discuss the use of IC 555 for astable operation. Find also the expression for its
frequency of oscillations.
20. Explain how timer IC 555 can be used as voltage controlled oscillator and saw tooth
wave generator.
21. The bistable multivibrator shown in figure 8.11(a) has the following circuit
parameters:
VCC = 15V, VBB = 5 V, RC1 = RC2 =2.2KΩ, R1 = R2 = 12 KΩ and hfe of the transistors
is 50.
Find the maximum value of the resistance RB to ensure saturation. (Ans.: 110 KΩ)
22. Consider the monostable multivibrator shown in figure 8.12 having the following
parameters: VCC = 12V, RC1 = RC2 = 3.3 KΩ, R = RB2 = 10KΩ, C = 0.01µf, R1 =
1KΩ and VBB = – 5V. Calculate the pulse width by neglecting VBE(Sat) and VCE(Sat)
for the transistor. (Ans.: 69 µSec.)
23. In the astable multivibrator circuit shown in figure 8.17, calculate the frequency of
oscillations if the circuit parameters are as given below:
VCC = + 15 V, R1 = R2 = R = 100 KΩ, RC1 = RC2 = 12 KΩ and C1 = C2 = C =
0.001 µf. Neglect VBE(Sat) and VCE(Sat). (Ans.: 1.45MHz)
24. The Schmitt trigger circuit of figure 8.22(a) has the following parameters:
R1 = 100 KΩ, R2 = 100 and Vi is the sinusoidal wave of 1.2 V (pp). The saturation
voltage for the operational amplifier is ± 12 V. Determine the lower and upper
threshold voltages of the Schmitt trigger circuit. (Ans.: ± 12mV )

__________

279
9
Active Filters
The electronic signals generally contain unwanted components called as noise.
The elimination of noise and the extraction of signal of the desired frequency can be done
with the help of frequency selective network called the filters. The filters are designed
using some of the passive components e.g. resistance, capacitance and inductors. Since
these filters contain passive components so these filters are called passive filters. The
filters which contain active device in addition to the passive components are called the
active filters. The operational amplifiers are used as the active devices in the active
filters. The active filters have the high input impedance and very low output impedance
and provide high gain. In this chapter the details of the design of active filters will be
discussed. These filters include first and second order low and high pass filters; band pass
and band elimination filters etc.
9.1 ACTIVE FILTERS
The active filters have an operational amplifier as the active device and the passive
network mainly the resistance and capacitance network as the frequency selective circuit.
Basically, the signal of specified band of frequencies is passed through the filters and the
signals of frequencies outside this band are attenuated or blocked by the filters. Because
of the use of the operational amplifiers in the active filters, it offers very high input
impedance and very low output impedance so there will be no problem of loading. The
large value of resistors can be used in the design of these filters because of the high input
impedance of the operational amplifiers. This will reduce the size and cost of the
capacitors. In the active filters the high frequency is limited to the gain band width
product and slew rate of the operational amplifiers.
The active filters are used almost in all the fields of electronic and communication
such as Radio, Television, Telephone and space satellites etc.
The most commonly used filters are:
(i) Low-pass Filter
(ii) High-pass Filter
(iii) Band-pass Filter
(iv) Band-rejection Filter
The frequency responses of these filters are shown in figure 9.1, in which the
dashed curves show the ideal response of these filter while the solid curves show the
response of practical filters. Butterworth, Chebysev and Cauer filters are most commonly
used practical filters but because of having good amplitude response near zero frequency,
the Butterworth is most popular filter. The Butterworth filter has a flat pass-band as well
as the stop-band, hence it is also known as the flat-flat filter. We shall now discuss the
details of the Butterworth low and high pass filters in the following sections.

Fig. 9.1
9.2 FIRST ORDER LOW PASS FILTER
Figure 9.2(a) shows the first order Butterworth low pass filter, comprising an RC
network for filtering and an operational amplifier used in non-inverting configuration for
amplification. The gain of the amplifier is decided by the resistances R1 and Rf.

(a) (b)
Fig. 9.2
The voltage V1 at the non-inverting terminal of the operational amplifier is given
by:
 1 j ωC 
V1 = Vi  
 R +1 j ωC 

281
 1 
= Vi   … (9.1)
 1 + j ω CR 
The output voltage is given by:
 Rf 
V0 = 1 + V1 … (9.2)
 R 1 
From equations (9.1) and (9.2), we have:
 R f  Vi 
V0 = 1 +  
 R1  1 + j ω CR 
V0  Af 
or =  
Vi  1 + j ω CR 
V0
where is the gain of the filter which is a function of frequency and
Vi
 Rf 
A f = 1 +  , is the gain of the amplifier.
 R1 
Put ω = 2 π f , we get:
V0  Af 
=   … (9.3)
Vi  1 + j ( f f H ) 
1
where f H = , is the high cutoff frequency of the low pass filter.
2 π RC
The magnitude of the gain of the filter is given by:
V0  Af 

= … (9.4)
Vi  1 + ( f f H ) 2 
 
and the phase angle φ is given by:
 f 
φ = − tan −1   … (9.5)
 fH 
If the magnitude of the gain of the filter is plotted as a function of frequency, we
get the response as shown in figure 9.2(b).
From this graph it is clear that when the input is of very low frequency ( f < f H ),
the magnitude of the gain of the filter is:
V0
≈ Af ,
Vi
it is constant till ( f < f H ) and A f is called as the pass band gain.
Further if the frequency of the input signal is equal to the cut-off frequency
( f = f H ), the magnitude of the gain of the filter is given by:
V0  A f 
=  = 0.707 A f
Vi  2 

282
i.e. at the cutoff frequency the magnitude of the gain of the filter becomes 0.707
times the pass band gain. In other words at the cutoff frequency the gain is decreased by
3db. So the cutoff frequency is also known as –3db point.
Finally, if the input signal is of very high frequency (say f > f H ), the magnitude
of gain of the filter becomes very low and is given by:
V0
< Af
Vi
Thus the low pass filter has a constant gain A f for the signal whose frequency is
lying between 0 to high cutoff frequency f H . At the frequency where the gain of the filter
reduces to 0.7.07 times the pass band gain A f is called the high cutoff frequency f H .
When the frequency of the signal increases beyond the high cutoff frequency, then the
gain of the filter reduces at a constant rate.
If the frequency is increased by 10 times beyond cutoff frequency than the
magnitude of the gain of the filter is also reduced by ten times i.e. the gain decreases
20db (= 20 log 10) each time the frequency is increased by 10 times. Similarly, if the
frequency is increased by 2 times beyond cutoff frequency than the magnitude of the gain
of the filter is also reduced by two times i.e. the gain decreases 6db (20 log 2 = 20x0.3)
each time the frequency is doubled. From the above discussion it is clear that the filter
allows low frequency signal (less than cutoff frequency) to pass through it and the signal
is attenuated at a rate –20db/decade or –6db/octave (octave means the frequency is
increased by two times) beyond the cutoff frequency.
9.3 SECOND ORDER LOW PASS FILTER
The second order Butterworth low pass filter can be obtained by using additional
RC network to the fist order low pass filter, as shown in figure 9.3(a).

(a) (b)
Fig. 9.3
The circuit will be analysed and the expression for cutoff frequency and the gain
of the filter will now be calculated.
Applying the KCL to the node V1 we have:
I1 = I 2 + I 3 … (9.6)
Vi − V1 V1 − V0 V1 − V2
= + … (9.7)
R3 1 j ω C3 R2

283
The operational amplifier is assumed to be ideal, so the current flowing through
the non-inverting terminal of the operational amplifier will be zero due to its infinite
input resistance. The voltage V2 may also be written as:
V1
V2 = (1 j ω C 2 )
R2 + 1 j ω C 2
V1
=
1 + j ω C 2 R2

or V1 = (1 + j ω C 2 R2 ).V2 … (9.8)
Put the value of V1 from equation (9.8) to equation (9.7), we get:
Vi − (1 + j ω C 2 R2 ).V2 (1 + j ω C 2 R2 ).V2 − V0 (1 + j ω C 2 R2 ).V2 − V2
= + … (9.9)
R3 1 j ω C3 R2
Vi (1 + j ω C 2 R2 ).V2 (1 + j ω C 2 R2 ).V2 − V2
or − = j ω C 3 (1 + j ω C 2 R2 ).V2 − j ω C 3V0 +
R3 R3 R2 R2
  1  1  Vi
V2  (1 + j ω C 2 R2 ) j ω C 3 +
1
or + − = + j ω C 3V0
  R2 R3  R2  R3
or V2 ((1 + j ω C 2 R2 ){ j ω C 3 R3 R2 + R2 + R3 } − R3 ) = Vi R2 + j ω C 3 R2 R3V0
 Vi R2 + j ω C 3 R2 R3V0 
or V2 =   … (9.10)
 (1 + j ω C 2 R2 ){ j ω C 3 R3 R2 + R2 + R3 } − R3 
The output voltage of this filter is also given by:
 Rf 
V0 = 1 + .V2
 R1 
V0
or V2 = … (9.11)
Af
where Af the gain of the amplifier, which is given by:
 Rf 
A f = 1 +  … (9.12)
 R 1 
From equations (9.10) and (9.11), we have:
V0  Vi R2 + j ω C 3 R2 R3V0 
=  
A f  (1 + j ω C 2 R2 ){ j ω C 3 R3 R2 + R2 + R3 } − R3 
 A f (Vi R2 + j ω C 3 R2 R3V0 ) 
or V0 =   … (9.13)
 (1 + j ω C 2 R2 ){
. j ω C 3 R3 R2 + R2 + R3 } − R3 
 j ω C 3 R2 R3 A f   A f Vi R2 
V0 1 −  =  
 (1 + j ω C R
2 2 ){
. j ω C R R
3 3 2 + R 2 + R 3 } − R3   (1 + j ω C R
2 2 ){
. j ω C R R
3 3 2 + R 2 + R3 } − R3 

V0 ((1 + j ω C 2 R2 ){
. j ω C3 R3 R2 + R2 + R3 } − R3 − j ω C3 R2 R3 A f ) = A f Vi R2
( )
V0 j ω C3 R3 R2 + R2 + R3 − ω 2 C 2 C3 R22 R3 + jωC 2 R22 + jωC 2 R2 R3 − R3 − j ω C3 R2 R3 A f = A f Vi R2
or ( )
V0 j ω C3 R3 + 1 − ω C 2 C 3 R2 R3 + jωC 2 R2 + jωC 2 R3 − j ω C3 R3 A f = A f Vi
2

284
V0  Af 

or = … (9.14)
Vi  1 − C 2 C3 R2 R3ω 2 + j ω C 3 R3 + C 2 R2 + C 2 R3 − C 3 R3 A f 

If R2 = R3 = R and C 2 = C 3 = C , then the equation (9.14) reduces to:
V0  Af 

= …(9.15)
Vi  1 − ω 2 R 2 C 2 + j ω(3 − A f ) RC 
If the gain of the amplifier is chosen to be 3 then equation (9.15) becomes:
V0  Af 
=  2 2 2 2 

Vi  1 + j ω R C 
V0 Af
=
Vi  ω 
4

1 +  
ωH 
1
where ω H = is the high cutoff frequency for the second order low pass filter.
RC
V0 Af
Also = … (9.16)
Vi  f 
4

1 +  
 fH 
1
and fH = … (9.18)
2 π RC
The frequency response of this filter is shown in figure 9.3(b). This frequency
response is similar to the first order low pass filter but the signal gets attenuated at a rate
–40db/decade beyond the cutoff frequency. If the frequency is increased by 10 times
beyond cutoff frequency than the magnitude of the gain of the filter reduced by hundred
times i.e. the gain decreases 40db (= 20 log 100) each time the frequency is increased by
10 times.
9.4 FIRST ORDER HIGH PASS FILTER
Figure 9.4 (a) shows the first order Butterworth high pass filter. It contains an RC
network for filtering and an operational amplifier for amplification. The gain of the
amplifier is decided by the resistances R1 and Rf.

(a) (b) Fig. 9.4

285
The circuit for the first order high pass filter may now be analysed by calculating
the cutoff frequency and drawing the frequency response curve. The voltage V1 at the
non-inverting terminal of the operational amplifier is given by:
 R 
V1 = Vi  
 R +1 j ωC 
 j ω CR 
= Vi   … (9.19)
 1 + j ω CR 
The output voltage is given by:
 Rf 
V0 = 1 + V1 … (9.20)
 R1 
From equations (9.19) and (9.20), we have:
 R f  j ω CR 
V0 = Vi 1 +  
 R1  1 + j ω CR 
V0  A f ( j ω CR ) 
or = 
Vi  1 + j ω CR 
V0
where is the gain of the filter which is a function of frequency; and
Vi
 Rf 
A f = 1 +  , is the gain of the amplifier.
 R1 
Put ω = 2 π f , we get:
V0  j ( f fL ) 
= A f   … (9.21)
Vi 1 + j ( f fL ) 
1
where f L = , is the low cutoff frequency of the high pass filter.
2 π RC
The magnitude of the gain of the filter is given by:
V0  A f ( f f L ) 
= … (9.22)
Vi  1 + ( f f L ) 2 
 
If the magnitude of the gain of the filter is plotted as a function of frequency, we
get the response as shown in figure 9.4(b).
From this graph it is clear that when the input is of very low frequency ( f < f L ),
the magnitude of the gain of the filter is small enough and it increases (at a rate of
20db/decade) till the frequency equals to the cutoff frequency. At the cutoff frequency the
gain becomes equal to A f is called as the pass band gain. This filter therefore allows
passing the signal of high frequency (greater than the cutoff frequency).
Further if the frequency of the input signal is equal to the cut-off frequency
( f = f L ), the magnitude of the gain of the filter is given by:
V0  A f 
=  = 0.707 A f …(9.23)
Vi  2 

286
i.e. at the cutoff frequency the magnitude of the gain of the filter becomes 0.707
times the pass band gain. So the cutoff frequency is also known as –3db point.
9.5 SECOND ORDER HIGH PASS FILTER
The second order Butterworth high pass filter can be obtained by using additional
RC network to the fist order high pass filter, as shown in figure 9.5 (a). For simplicity,
consider C 3 = C 2 = C and R3 = R2 = R .

(a) (b)
Fig. 9.5
The circuit will be analysed and the expression for cutoff frequency and the gain
of the filter will now be calculated.
Applying the KCL to the node V1 we have:
I1 = I 2 + I 3 … (9.24)
Vi − V1 V − V0 V − V2
= 1 + 1
(1 j ω C ) R (1 j ω C )
V − V0
j ω C (Vi − V1 ) = 1 + j ω C (V1 − V2 ) … (9.25)
R
The operational amplifier is assumed to be ideal, so the current flowing through
the non-inverting terminal of the operational amplifier will be zero due to its infinite
input resistance. The voltage V2 may also be written as:
V1 R
V2 =
R +1 j ωC
V ( j ω CR)
= 1
1 + j ω CR
or V1 =
(1 + j ω CR ) .V … (9.26)
2
j ω CR
Put the value of V1 from equation (9.26) to equation (9.25), we get:

 1 + j ω CR  1  1 + j ω CR   1 + j ω CR 
j ω C Vi − .V2  =  .V2 − V0  + j ω C  .V2 − V2 
 j ω CR  R  j ω CR   j ω CR 
 1 + j ω CR 1 + j ω CR  V
V2  j ω C − 2 − 2 
 = − 0 − j ω CVi
 R j ω CR  R

287
 3 1  V
or V2  j ω C − − 2 j ω C −  = − 0 − j ω CVi
2 
 R j ω CR  R
 3 1  V
or V2  − − j ω C − 2 
 = − 0 − j ω CVi … (9.27)
 R j ω CR  R
The output voltage of this filter is also given by:
 Rf 
V0 = 1 + .V2
 R1 
V0
or V2 = … (9.28)
Af
where Af the gain of the amplifier, which is given by:
 Rf 
A f = 1 + 
 R 1 

From equations (9.27) and (9.28), we have:


V0  3 1 Af 
 − − j ω C − +  = − j ω CVi
Af  R j ω CR 2
R 
V0  1 1 
 j ω C + 2
+ (3 − A f )  = j ω CVi
Af  j ω CR R 
 
 
V0  Af j ω C 
or =
Vi  1 1 
 j ωC + + (3 − A f ) 
 j ω CR 2 R 
 
 
V0  Af 
or = … (9.29)
Vi  1 1 
1 − 2 2 2 + (3 − A f ) 
 ω C R jωCR 
If the gain of the amplifier is chosen to be 3 then equation (9.29) becomes:
 
V0  Af 

=
Vi  1 
1 − 2 2 2 
 ω C R 
V0 Af
=
Vi ω 
4

1+  L 
ω 
1
where ω L = is the low cutoff frequency for the second order high pass filter.
RC

288
V0 Af
Also = … (9.30)
Vi f 
4

1 +  L 
 f 
1
and fL = … (9.31)
2 π RC
The frequency response of this filter is shown in figure 9.5 (b). This frequency
response is similar to the first order high pass filter but the magnitude of the gain of the
filter increases (at a rate of 40db/decade) till the signal frequency is equal to the cutoff
frequency. At the cutoff frequency the gain becomes equal to unity.
9.6 HIGHER ORDER FILTERS
The first order and second order low and high pass filters have been discussed in
the forgoing sections. The higher order filters may also be designed using first and
second order filters. For example, to design third order low pass filter, the first order low
pass filter and second order low pass filters may be connected in cascade or series;
however, the fourth order low pass filter may designed connecting two second order low
pass filters in cascade. Similarly, first order high pass filter and second order high pass
filter when connected in tandem form the third order high pass filter; two second order
high pass filters may be connected in cascade to form a fourth order high pass filter. The
further higher order filters may also be designed in the similar fashion. The purpose of
using the higher order active filters is that the stop band response of the filter approached
to its ideal stop band characteristics and overall gain of the filter will be the product of
the individual filters.
Figure 9.6 shows a third order low pass filter in which the cascade connections of
a first order low pass filter and a second order low pass filter are made. It is well known
that the stop band gain decreases at a rate of 20db/decade in the first order low pass filter
and in the second order low pass filter the stop band gain decreases at a rate of
40db/decade, so for the third order low pass filter the stop band gain decreases at a rate of
60db/decade. The overall gain of this filter will be the product of the individual filter,
which may be given by:
2
 Rf 
A f = 1 + 
 R1 

Fig. 9.6

289
The fourth order low pass filter is shown in figure 9.7, which is designed
connecting two low pass filters in cascade. The stop band gain of this filter will decrease
at a rate 80db/decade.

Fig. 9.7
The frequency response of both the third order low pass filter and fourth order
low pass filter is the same except the decrement in the pass band gain is different (figure
9.8). The high cutoff frequency of both the third and fourth order low pass filters is the
same, if the resistances and the capacitances of the filter sections are equal. It is given by:
1
fH =
2 π RC

Fig. 9.8
9.7 BAND PASS FILTERS
The band pass filter allows the signal to pass through the filter whose frequency
lies in the particular band of frequencies i.e. it has the pass band gain between the two
cutoff frequencies f H (high cutoff frequency) and f L (low cutoff frequency). The high
cutoff frequency is always greater than the low cutoff frequency. The difference of these
two cutoff frequencies is known as the band width (BW). The signal, whose frequency
lies outside the band width of the band pass filter, gets attenuated. The average of the
two cutoff frequencies is known as the central frequency f 0 .
The quality factor Q, which is figure of merit of band pass filter, is defined as:
f0 f
Q= = 0 … (9.32)
f H − f L BW

290
The band pass filters may be classified into the following two categories as per
their quality factor Q.
(i) Wide band pass filter (Q<10)
(ii) Narrow band pass filter (Q>10)
9.7.1 Wide Band Pass Filter
A wide band pass filter is shown in figure 9.9, which is formed simply by
connected a high pass filter and a low pass filter in cascade. If both the high pass and low
pass filters are of first order, then the band pass filter will be of first order and the pass
band gain will decrease at a rate of (– 20db/decade).

Fig. 9.9
The magnitude of the gain of the high pass filter of figure 9.9 is given by:
V01  A f ( f f L ) 
= … (9.33)
Vi  1 + ( f f )2 
 L 
1
where fL =
2 π R2 C 2
 Rf 
and A f = 1 + 
 R1 
The magnitude of the gain of the low pass filter of figure 9.9 is given by:
V0  Af 
=  … (9.34)
V01  1 + ( f f ) 2 
 H 
1
where fH =
2 π R3 C 3
The magnitude of the gain of this wide band pass filter (overall) is obtained from
equations (9.33) and (9.34). It is obtained by multiplying two gains.
V0 V V  Af  A f ( f f L ) 
= 0 . 01 =   
Vi V01 Vi  1 + ( f f ) 2  1 + ( f f ) 2 
 H  L 

291
 A 2f ( f f L ) 
=  … (9.35)
 ( H )(
 1 + ( f f )2 1 + ( f f )2 
L ) 
The frequency response curve of the filter is shown in figure 9.10, in which the
pass gain decreases at a rate of 20db/decade of either side of the cutoff frequencies.

Fig. 9.10
The second order wide band pass filter can also be designed by connecting the
second order high pass filter and second order low pass filter in cascade. The pass band
gain in this case will decrease at a rate of 40db/decade of either side of the cutoff
frequencies.
9.7.2 Narrow Band Pass Filter
The narrow band pass filter is shown in figure 9.11, in which one operational
amplifier in the inverting configuration is used. There are two feedback path in this filter
hence it is also called the multiple feedback filter. The important parameters in the band
pass filter are the central frequency f 0 , band width (BW) and the gain of the amplifier.

Fig. 9.11
The circuit of figure 9.11 will now be analyzed for the purpose of calculating the
gain of the amplifier, central frequency and the band width.
Applying the KCL to the node 1, we have:
V1 − Vi V1 V −V V −V
+ + 1 2 + 1 0 =0 … (9.36)
R1 R2 (1 / j ω C1 ) (1 / j ω C2 )
Assuming that the operational amplifier behaves like an ideal operational
amplifier, so the node 2 will at the virtual ground ( V2 = 0 ). The equation (9.36) becomes:

292
V1 − Vi V1
+ + j ω C1V1 + j ω C 2 (V1 − V0 ) = 0
R1 R2
 1 1  V
or V1  + + j ω C1 + j ω C 2  = j ω C 2V0 + i … (9.37)
 R1 R2  R1
Applying the KCL to the node2, we have:
V1 − V0
=
(1 / j ω C1 ) R3
as no current flows to the input terminals of the operational amplifier.
V0
or V1 = − … (9.38)
j ω C1 R3
Put the value of V1 from equation (9.38) in equation (9.37), we get:
V0  1 1  V
−  + + j ω C1 + j ω C 2 + j 2 ω 2 C1C 2 R3  = i
j ω C1 R3
 R1 R2  R1
V0 − j ω C1 R3
or =
Vi  1 1 
R1  + + j ω C1 + j ω C 2 + j 2 ω 2 C1C 2 R3 
 R1 R2 
V0 (− 1 / R1 )
or = … (9.39)
Vi  1 1 1 1 C2 
 ( + )+ + + j ω C 2 
 j ω C1 R3 R1 R2 R3 C1 R3 
The frequency of resonance or the central frequency f 0 is obtained by putting the
imaginary parts of this equation to zero as:
1 1 1
ω C2 = ( + )
ω C1 R3 R1 R2
1  1 1 
or ω2 =  + 
C1C 2 R3 R
 1 R 2 

1  1 1 
or ω0 =  + 
C1C 2 R3  R1 R2 
1 1 1 1 
f0 =  +  … (9.40)
2 π C1C2 R3  R1 R2 
V
At the central frequency the gain 0 of the filter is given by:
Vi
V0 R
=− 3 … (9.41)
Vi 2R1
The Q factor at resonance is given by:
Q = ω 0 RC eq

293
C1C 2
In this circuit R = R3 and C eq = , so the Q will be given by:
C1 + C 2
ω RCC 2 π f 0 R3C1C 2
Q= 0 3 1 2 = … (9.42)
(C1 + C 2 ) (C1 + C 2 )
The band width is given by:
f (C1 + C 2 )
BW = 0 = … (9.43)
Q 2 π R3C1C 2
For C1 = C 2 = C , equations (9.40) and (9.43) become:
1 1  1 1 
f0 =  +  … (.44)
2πC R3  R1 R2 
f 1
BW = 0 = … (9.45)
Q π R3C
The proper selection of the circuit parameters will help in getting the required
central frequency and the Q factor. The frequency of this narrow band pass filter is shown
in figure 9.12, the higher Q may be chosen for the sharper filter.

Fig. 9.12

9.8 BAND REJECTION FILTER S


The band rejection filters allow the signal to pass through the filter whose
frequency lies beyond the particular band of frequencies i.e. the particular band of
frequencies is eliminated or stopped to pass through these filters. Hence these filters are
also called as the Band Stop or Band Elimination filters.
Similar to band pass filters, the band rejection filters may be classified into the
following two categories as per their quality factor Q.
(iii) Wide band rejection filters (Q<10)
(iv) Narrow band rejection filters (Q>10)
9.8.1 Wide Band Rejection Filter
The wide band rejection filter can be designed using a first order low pass filter
and a first order high pass filter and a summing amplifier as shown in figure 9.13. The
frequency response of this filter is shown in figure 9.14. The high cutoff frequency for
low pass filter may be chosen by considering the proper values of the resistance R and
capacitance C; and the proper value of low frequency cutoff frequency for high pass filter

294
may be taken by considering R’ and C’. The pass band gain for both high pass filter and
R
low pass may be taken equal. The ratio 3 will decide the gain of summing amplifier.
R2

Fig. 9.13

Fig. 9.14
9.8.2 Narrow Band Rejection Filter
The narrow band rejection filter is also called the notch filter and commonly used
for the rejection of a single frequency. The notch filter is shown in figure 9.15, which
contains twin-T network. The twin-T network is a passive network having two T-
networks in parallel (shown by dotted lines); one T network consists of two capacitors
and a resistor and the other T network consists of two resistors and a capacitor. Two unity
gain buffer amplifiers are also used.
Now we shall calculate the notch frequency, bandwidth and the Q factor for this
case.

295
Fig. 9.15
Applying the KCL to the node 1, we have:
V1 − Vi V − V0 2(V1 − β V0 )
+ 1 + =0
(1 / j ω C ) (1 / j ω C ) R
2(V1 − β V0 )
or j ω C (V1 − Vi ) + j ω C (V1 − V0 ) + =0
R
 2β   1
or j ω CVi +  j ω C + V0 = 2 j ω C + V1 … (9.46)
 R   R
A fraction β of the output voltage is applied to the non-inverting input of the
second unity gain buffer amplifier and is known as the feedback factor given by:
R1
β=
R1 + R2
Applying the KCL to the node 2, we have:
V2 − Vi V2 − V0 (V2 − β V0 )
+ + =0
R R (1 / 2 j ω C )
Vi  1 1 
or +  2 β j ω C + V0 = 2 + j ω C V2 … (9.47)
R  R R 
Now applying the KCL to the node A, we get:
V1 − V0 V − V0
+ 2 =0
(1 / j ω C ) R
V 1 
or j ω CV1 + 2 =  + j ω C V0
R R 
1 
 + j ω C V0 − j ω CV1
V2 =  
R
or … (9.48)
(1 / R )
From equations (9.48) and (9.47), we have:
1 
 + j ω C V0 − j ω CV1
Vi  1 1  R
+  2 β j ω C + V0 = 2 + j ω C   
R  R R  (1 / R)

296
1  1 2β j ωC 1  
2
1 
or V +  + − 2 + j ω C  V0 = −2 j ω C  + j ω C V1
R 2 i  2
R R    R 
R
1  1 2β j ωC 1  
2

Vi +  + − 2 + j ω C  V0
R2  R2 R R  
or V1 =  … (9.49)
1 
− 2 j ω C + j ω C 
R 
Rewriting the equation (9.46), we obtain:
 2β 
j ω CVi +  j ω C + V0
V1 =  R 
… (9.50)
 1
2 j ω C + 
 R
Equating equations (9.49) and (9.50), we have:
1  1 2β j ωC 1  
2

Vi +  + − 2  + j ω C  V0  2β 
 R2  j ω CVi +  j ω C + V0
R2  R  R   =  R 
1   1
− 2 j ω C + j ω C  2 j ω C + 
R   R
1  1 2β j ωC 1  
2

V +  + − 2  + j ω C  V0
R2
i  R2 R R  
  2β 
or = j ω CVi +  j ω C + V0
− j ωC  R 
 1 2β j ωC 1  
2
 2β 
− 2 + j ω C  V0 = −( j ω C ) Vi − ( j ω C ) j ω C +
1 
V + +
2
or
R V0
 
2 i 2
R  R R  R 
 2

or  − ( j ω C )2 − 2 β ( j ω C ) − 1 − 2 β j ω C − 2 1 + j ω C  V0 = 1 Vi + ( j ω C )2 Vi
 R R 2
R R   R2

 1   1 2
 R 2 + ( j ω C ) + R (1 − β) V0 =  R 2 + ( j ω C ) Vi
2 4 j ωC
or
   
The voltage gain of this notch filter is, therefore, given by:
 1 2
 2
+ ( j ωC) 
V0
= R 
Vi  1 
 R 2 + ( j ω C ) + R (1 − β) 
2 4 j ω C

 1 2
 2 2
+ ( j ω) 
or
V0
= R C 
Vi  1 
 R 2 C 2 + ( j ω ) + RC (1 − β) 
2 4jω

297
or
V0
= 2
(
ω 2 − ω 02 ) … (9.51)
Vi ω − ω 02 − 4 j ωω 0 (1 − β)
1
where ω0 =
RC
1
or f0 = … (9.52)
2 π RC
The gain of the filter becomes zero for ω = ω 0 and approaches unity for
ω << ω 0 and for ω >> ω 0 . The high frequency response will however be limited by the
high frequency response of the operational amplifier.
The frequency response of the notch filter is shown in figure 9.16.

Fig. 9.16
1
At 3db point the magnitude of the gain of the filter should be equal to .
2
i.e. (ω 2
)
− ω 02 = ±4 ωω 0 (1 − β)
2
ω ω
or 2
−1± 4(1 − β) = 0 … (9.53)
ω0 ω0
ω
This equation may be solved for as:
ω0
ω − 4(1 − β) ± 16(1 − β ) + 4
2
=
ω0 2
ω
= −2(1 − β) ± 1 + 4(1 − β) 2 … (9.54)
ω0
It will have two frequencies, the higher cutoff frequency f H and lower cutoff
frequency f L given by:
(
f H = f 0 1 + 4(1 − β) 2 + 2(1 − β) ) … (9.55)
and fL = f ( 1 + 4(1 − β)
0
2
− 2(1 − β) ) … 99.56)
The band width is given by:
BW = f H − f L = 4 f 0 (1 − β) … (9.57)

298
The Q factor is also given by:
f 1
Q= 0 = … (9.58)
BW 4(1 − β)
If β is taken to be unity, the Q factor becomes very large and the band width will
be zero. It will then reject the signal of particular frequency.

Example 9.1. Design a first order low pass filter having the high cutoff frequency of 1.5
KHz with pass band gain of 2. Use C = 0.01µF.
Solution. The high cutoff frequency for the first order low pass filter is given by:
1
fH =
2 π RC
It is given f H = 10 KHz , C = 0.01µ F
1
R=
2 x3.14 x1.5 x10 3 x0.01x10 −6
10 8
= = 10.6 KΩ
9420
The gain of the amplifier is to be kept as 2 so the resistance R f = R1 = 10 KΩ (say). The
required circuit is, therefore, given as shown in figure 9.17.

Fig. 9.17

Example 9.2. Design a second order low pass filter having the high cutoff frequency of
2 KHz with pass band gain of 2. Use C =0.0047µF.
Solution. If R2 = R3 = R and C 2 = C 3 = C , the high cutoff frequency for the second
order low pass filter is given by (ref. fig. 9.3):
1
fH =
2 π RC
1
R=
2 x 3.14 x 2 x10 x 0 .0047 x10 − 6
3

10 9
= = 16.9 KΩ
59032
The gain of the amplifier is to be kept as 2 so the resistance
R f = R1 = 10 KΩ (say). The required circuit is, therefore, given as shown in figure 9.18.

299
FIG. 9.18

PROBLEMS
1. Define an active filter. How it differ from the passive filter? How filters are
classified?
2. Discuss Butterworth first order active low pass filter. Find the expression for the
magnitude of the gain and the high cutoff frequency of this filter. Draw its
frequency response curve also.
3. Discuss Butterworth second order active low pass filter. What is the advantage of
second order low pass filter over the first order low pass filter?
4. Draw the schematic diagram of second active order low pass filter. Find the
expression for the magnitude of the gain and the high cutoff frequency of this
filter. Draw its frequency response curve also.
5. Discuss Butterworth first order active high pass filter. Find the expression for the
magnitude of the gain and the low cutoff frequency of this filter. Draw its
frequency response curve also.
6. Discuss Butterworth second order active high pass filter. Find the expression for
the magnitude of the gain and the low cutoff frequency of this filter. Draw its
frequency response curve also.
7. What is the advantage of designing the higher order active filters? Discuss the
design of third order active low pass filter.
8. Explain the design of fourth order active low pass filter and discuss its frequency
response curve also.
9. Discuss the design of third order active high pass filter and its frequency response
curve.
10. Discuss the design of fourth order active high pass filter and its frequency
response curve.
11. What is the difference between pass band and band rejection filters? Define the
terms band width, central frequency and the Q-factor of these filters. How the
band pass are filters classified according the Q-factor?
12. Discuss wide band pass active filter with its frequency response curve. Find the
magnitude of the gain of this filter.
13. Explain narrow band pass active filter using an operational amplifier in inverting
configuration. Find the expression for central frequency, band width and the Q-
factor for this filter.
14. Discuss wide band rejection active filter with its frequency response curve.

300
15. What is a notch filter? Draw the schematic diagram of a notch filter using a twin-
T network. Find the expression for lower and higher cutoff frequencies, band
width and the Q-factor for this filter.
16. Design a first order active low pass filter having the high cutoff frequency of
2KHz and pass band gain of 2.
17. Design a first order active high pass filter having the low cutoff frequency of 2
KHZ and pass band gain of 2.
18. Design a second order active high pass filter having the low cutoff frequency of 2
KHZ and pass band gain of 2.
19. Design a fourth order active low pass filter having the high cutoff frequency of 1
KHZ and pass band gain of 2.
20. Design a second order low pass active filter for a cutoff frequency of 1.5 KHz and
pass band gain of 1.6.

_________

301
10
Bridge Circuits
A bridge circuits are used for the measurement of electrical quantities such as
resistances, Capacitances and inductances. Two types of bridges are commonly used for
such measurements the D. C. bridges and A. C. bridges. Wheatstone bridge, the basic
D.C. bridge having four arms, is used for the measurement of resistance. In this chapter
both types of bridges will be discussed, these include Kelvin bridge, Maxwell bridge,
Hay bridge, Schering bridge and Wein bridge.
10.1 WHEATSTONE BRIDGE
The schematic diagram of a Wheatstone bridge is shown in figure 10.1, which
consists of four arms having the resistances R1, R2, R3 and R4, a voltage source E
connected between the nodes A and B; and a sensitive galvanometer G connected
between C and D. The galvanometer is used for the null detection i.e. when the bridge is
balanced no current flows through the galvanometer and its needle rests in the mid
position (zero is at the center of the scale of the galvanometer). In this condition the
potential at the points C and D are equal.

Fig. 10.1
The arms R1 and R2 of this bridge are known as the ratio arms, the arm R3 is
known as the standard arm and the arm R4 is known as the unknown arm. This bridge is
most commonly used for the measurement of unknown resistance. The resistance, whose
value is to be measured, is to be connected in the unknown arm. The resistance of the
standard arm is varied for the null detection. When the potential E is applied across the
points A and B, the current drawn from the source will be divided into two arms at point
A, i.e. I1 and I2. When the bridge is balanced the no current flows through the
galvanometer and the potential at the points C and D will be equal.
In this condition E AC = E AD
or I 1 R1 = I 2 R2 … (10.1)
The current flowing through the R1 and R3 arms will be equal if the current
flowing through the galvanometer is zero. This leads to:
E
I1 = I 3 = … (10.2)
R1 + R3
E
Similarly, I2 = I4 = … (10.3)
R2 + R4
From equations (10.1) through (10.3), we have:
E x R1 E x R2
=
R1 + R3 R2 + R4
or R1 x( R2 + R4 ) = R2 x( R1 + R3 )
or R1 R2 + R1 R4 = R2 R1 + R2 R3
or R1 R4 = R2 R3
It indicates that multiplications of resistances of opposite arms are equal.
RR
R4 = 2 3 … (10.4)
R1
This is the condition for the bridge to be balanced. From this equation it is clear
the resistor value of R4 can be determined in terms of three resistances having known
values. The resistance R4 may be replaced with Rx, as the unknown resistance which
follows:
RR
Rx = 2 3 … (10.5)
R1
10.1.1 Thevenin’s Equivalent Wheatstone Bridge
When the bridge is not balance there will be the deflection in the galvanometer
whose value will depend on the sensitivity of the galvanometer. The sensitivity of the
galvanometer is the deflection per unit current and is expressed in mm/µA. If the
sensitivity is more, the deflection in the galvanometer will be more for the same amount
of current. For the proper null detection of the Wheatstone bridge, the galvanometer
whose sensitivity is sufficiently large should be used.
To find the current through the galvanometer in the unbalance condition, the
Thevenin’s equivalent of the bridge as seen by the galvanometer is drawn. The
Thevenin’s voltage is open circuit voltage across the points C and D, when the
galvanometer is removed from the CD branch. For the calculation of the open circuit
voltage consider an unbalanced Wheatstone bridge shown in figure 10.2
With reference to this figure, the voltages in the CB and DB branches are given
E x R3 E x R4
by: ECB = E DB =
R1 + R3 R 2 + R4

303
Fig. 10.2
Thevenin’s voltage is the voltage across the point C and D which is the difference
of voltages in the CB and DB branches.
i.e. ETh = ECD = E DB − ECB = ECB − E DB
E x R4 E x R3
= −
R2 + R4 R1 + R3
 R4 R3 
or ETh = E  −  … (10.6)
 R2 + R4 R1 + R3 
Thevenin’s resistance of this circuit will be resistance in the CD branch which
will be obtained by replacing the voltage source E by its internal resistance (or source
resistance) RS as shown in figure 10.3. Normally, the source resistance RS is assumed to
be very small so the Thevenin’s resistance may be calculated by short circuiting the
branch AB ( RS = 0 ).

Fig. 10.3 Fig. 10.4


The Thevenin’s resistance RTh is, therefore, given by:
 RR R R 
RTh =  1 3 + 2 4  … (10.7)
 R1 + R3 R2 + R4 
The Thevenin’s equivalent of the Wheatstone bridge circuit is therefore shown in
figure 10.4. The Thevenin’s voltage ETh and Thevenin’s resistance RTh are given in
equations 10.6 and 10.7 respectively.
If a galvanometer, whose resistance (internal) is Rg, is connected across the
terminal CD, then the galvanometer current Ig is given by:

304
ECD
Ig = … (10.8)
RTh + R g
10.1.2 Slightly Unbalance Wheatstone Bridge
The approximate expressions for Thevenin’s voltage and current can easily be
obtained if the bridge is slightly unbalanced. The slightly unbalance bridge means that the
unknown arm slightly differs (not more than 5%) from the other three equal arms as
shown in figure 10.5.

Fig. 10.5 Fig. 10.6


With reference to this figure, the voltages in the CB and DB branches are given
by:
ExR E E ( R + ∆r ) E ( R + ∆r )
ECB = = E DB = =
R+R 2 R + ( R + ∆r ) (2 R + ∆r )
Thevenin’s voltage which is the difference of voltages in the CB and DB branches
is given by:
 E ( R + ∆r ) 1 
ETh = ECD = ECB − E DB = E  − 
 (2 R + ∆r ) 2 
 2( R + ∆r ) − (2 R + ∆r ) 
= E  
 2( 2 R + ∆r ) 
 2 R + 2∆r − 2 R − ∆r 
= E  
 2(2 R + ∆r ) 
 ∆r 
= E 
 4 R + 2∆r 
If ∆r is very small say less than 5%, then ∆r in the denominator can be
neglected. It will, however, not introduce much error. The approximate Thevenin’s
voltage will, therefore, be given by:
 ∆r 
ETh = E   … (10.9)
 4R 
The Thevenin’s resistance be given by:

305
 RR R ( R + ∆r ) 
RTh =  + 
 R + R R + R + ∆r 
 R R ( R + ∆r ) 
= + 
2 2 R + ∆r 
R R
= + = R … (10.10)
2 2
The equivalent circuit is shown in figure 10.6. This approximation is quite
accurate if the difference in the unknown branch is less than 5%.
10.1.3 Sources of Errors in Wheatstone Bridge
The Wheatstone bridge is widely used for the measurement of resistance, but for
very low value of resistances (less than 1 Ω) this bridge has the limitations due to the
following reasons:
(i) If the galvanometer is not of very high sensitivity, then the deflection in the
galvanometer will not be sufficiently visible for the measurement of low
value of resistances. Therefore, it will not be possible to detect the null point
very accurately; this becomes the source of error particularly when the
resistance to be measured is of very low value.
(ii) There is a possibility of change in resistance values of the bridge arms due
to heating effect ( I 2 R ) of current through the resistance. The excessive
current due to heating effect may change the measuring resistance. This will
affect the measurement and will introduce error for the low value of
measuring resistance. The excessive current may even permanently change
the resistance values.
(iii) Thermal e.m.fs., in the bridge and galvanometer circuits, caused due to
dissimilar metal contacts will also introduce an error in the measurement of
low value of resistance.
(iv) The other measurement errors in the Wheatstone bridge are due to the
resistance of leads and contacts in the bridge and galvanometer circuits.
These errors play a role in the measurement of very low resistance values.
10.2 KELVIN BRIDGE
As discussed above the Wheatstone bridge is not suitable for the measurement of
very low resistance values because of the comparable values of resistance of leads and
contacts in the bridge and galvanometer circuits. A modified form of Wheatstone bridge
is used for the measurement of resistance of very low values (less than even 1 Ω). It is
known as the Kelvin bridge.
Consider the bridge circuit shown in figure 10.7 in which Ry is resistance of the
connecting lead from R2 to RX (unknown resistance). The galvanometer can either be
connected to point A or to point B. The resistance Ry of the connecting lead gets added to
the resistance R2 if the galvanometer is connected to the point B for null detection i.e. it
results the measurement of RX a lower value than the actual. On the contrary Ry gets
added to the unknown resistance RX if the galvanometer is connected to the point A, thus
it gives the measurement of RX a higher value than the actual.

306
Let the galvanometer is connected at the point C in between the points A and B
for the proper null detection. The point C is chosen such that the ratio of the resistance

Fig. 10.7
from points B to C and that from the points A to C equals the ratio of resistances R1 and
R3.
R BC R3
i.e. = … (10.11)
R AC R1
The balance equation for the bridge yields:
R
R X + R BC = 3 ( R2 + R AC ) … (10.12)
R1
But we have:
R AC + R BC = R y … (10.13)
R BC R
or +1 = 3 +1
R AC R1
RBC + R AC R3 + R1
or =
R AC R1
Ry R + R1
or = 3
R AC R1
R y R1
or R AC = … (10.14)
R1 + R3
From equations (10.13) and (10.14), we get:
R y R1
RBC = R y − R AC = R y −
R1 + R3
R3 R y + R1 R y − R y R1
or RBC =
R1 + R3
R3 R y
= … (10.15)
R1 + R3

307
Substituting the values of RAC and RBC from equations (10.14) and (10.15)
respectively in equation (10.12), we obtain:
R3 R y R R y R1
RX + = 3 ( R2 + )
R1 + R3 R1 R1 + R3
R3 R y R R R y R3
or RX + = 2 3+
R1 + R3 R1 R1 + R3
R R
or RX = 2 3 … (10.16)
R1
This is the usual balance equation of Wheatstone bridge. It clearly indicates that
the effect of resistance of the connecting leads is eliminated if the galvanometer is
connected at the point C somewhere in between the points A and B. It is, however,
necessary that the ratio of RBC and RAC should be equal to the ratio of R3 and R1 .
This principle becomes the basis for the construction of Kelvin double bridge
popularly known as Kelvin bridge. The schematic diagram of Kelvin double bridge is
shown in figure 10.8, which basically consists of two sets of ratio arms. In this case the
ratio of resistances m and n is equal to the ratio of resistances R3 and R1 .

Fig. 10.8
With reference to the figure 10.8, the null point is obtained when the potentials at
the points O and C are equal. This leads:
E PO = E PAC …. (10.17)
ER1
But E PO = … (10.18)
R1 + R3
 ( m + n) R y 
and E = I  R2 + R X +  … (10.19)
 m + n + Ry 
 
From equations (10.17) and (10.19), we get:

308
R1  (m + n) R y 
E PO = I  R2 + R X +  … (10.20)
R1 + R3  m + n + Ry 
 
Also:
 n (m + n) R y 
E PAC = I  R2 + 
 ( m + n ) m + n + R 
 y 

 nR y 
= I  R2 +  … (10.21)
 m + n + R 
 y 
From equations (10.17), (10.20) and (10.21), we have:
R1  (m + n) R y   nR y 
I  R2 + R X +  = I  R2 + 
R1 + R3  m + n + R y  
 m + n + R 
y 

 (m + n) R y  R1 + R3  nR y 
or  R2 + R X + =  R2 + 
 m + n + R  R  m + n + R 
 y  1  y 
 (m + n) R y   R3  nR y 
or  R2 + R X +  = 1 +  R2 + 
 m + n + R   R  m + n + R 
 y   1  y 

 mR y nR y   nR y  R3  nR y 
or  R2 + R X + +  =  R2 + +  R2 + 
 m + n + R y m + n + R y   m + n + R y  R1  m + n + Ry 
 
mR y R R nR y
or RX + = 3 R2 + 3
m + n + R y R1 R1 m + n + R y
R3 R nR y mR y
or RX = R2 + 3 −
R1 R1 m + n + R y m + n + R y
R3 nR y  R3 m 
or RX = R2 +  −  … (10.22)
R1 m + n + Ry  R1 n 
R3 m
It is assumed that =
R1 n
The equation (10.22) becomes:
R
RX = 3 R2 … (10.23)
R1
This is the usual balance equation of Kelvin bridge. It clearly indicates that the
effect of resistance of the connecting leads is eliminated if the ratios of the resistances of
the two sets of ratio arms are equal. This bridge can typically measure the low resistance
to approximately 1 Ω to as low as 0.00001Ω.
10.2.1 Practical Kelvin Double Bridge
The schematic diagram of commercially available Kelvin double bridge is shown
in figure 10.9. The commercial Kelvin bridge is capable of measuring resistances ranging
between 10 Ω to 0.00001 Ω. Since very low resistance value can be measured with this
bridge, so the lead resistance and the contact resistance may create a serious problem.
The special design of the bridge will reduce this effect. It consists of standard resistor in

309
nine steps of 0.001 Ω each and a calibrated maganin bar of 0.0011 Ω with a sliding
contact. When both the switches are in ON position, the suitable value of standard resistor
is selected. In this condition the voltage drop between the ratio arm connection points is
changed, but the total resistance around the battery circuit is unchanged. The contact
R
resistance effect is negligible and the ratio 3 is selected such that a relatively large part
R1
of the standard resistance is used and hence RX is determined to the largest possible
number of significant figures. It, therefore, increases the measurement accuracy.

Fig. 10.9

10.3 A C BRIDGES
Figure 10.10 shows the basic diagram of an a. c. bridge. This bridge is similar to
d. c. bridge, with the difference that the bridge arms are impedances. The bridge is
excited by an a. c. source rather than d. c. Further for null detection a detector circuit such
as headphones is used in place of galvanometer.

310
Fig. 10.10
One can find the condition for the a.c. bridge to be balance as:
Z1Z 4 = Z 2 Z 3
Z2Z3
or Z4 = … (10.24)
Z1
where Z1, Z2, Z3 and Z4 are the impedances of the bridge arms. The impedances
are the complex quantities that possess the phase angle also. The impedance Z can be
written in the form Z∠ θ , where Z is the magnitude of the impedance Z and angle θ is the
phase angle of the impedance. The equation (10.24) can thus be written in the complex
form as:
( Z1∠ θ 1 )( Z 4 ∠ θ 4 ) = ( Z 2 ∠ θ 2 )( Z 3 ∠ θ 3 ) … (10.25)
Equation (10.25) can be written in the form:
Z 1 Z 4 ∠ (θ 1 + θ 4 ) = Z 2 Z 3 ∠ (θ 2 + θ 3 ) … (10.26)
as in the multiplication of complex quantities the magnitudes are multiplied and
the phase angles are added.
The equation (10.27) shows that two balance conditions must simultaneously be
satisfied.
The first condition is that the multiplications of magnitudes of impedances
opposite arms must be equal.
i.e. Z1 Z 4 = Z 2 Z 3 … (10.27)
The second condition is that the phase angle of of the impedances of the opposite
arms must be equal.
i.e. ∠ θ1 + ∠ θ 4 = ∠ θ 2 + ∠ θ 3 … (10.28)

10.4 MAXWELL BRIDGE


Maxwell bridge is used to measure an unknown inductance in terms of a known
capacitor. The schematic diagram of a Maxwell bridge is shown in figure 10.11. One of
the ratio arms has the parallel combination of a resistance R1 and a capacitor C1. The
expression for the unknown inductance LX in terms of the other bridge parameters can
easily be obtained. The resistance RX is the leakage resistance of the inductance LX.

311
Fig. 10.11

The balance equation can be written as:


Z1Z X = Z 2 Z 3
The expression for the impedance of the unknown arm is given by:
Z Z
Z X = 2 3 = Z 2 Z 3Y1 … (10.29)
Z1
where Y1 is the admittance of the impedance Z1, which is given by:
1
Y1 = + j ω C1
R1
The other bridge parameters are given by:
Z 2 = R2
Z 3 = R3
Z X = RX + j ω LX
The equation (10.29) becomes:
 1 
R X + j ω L X = R2 R3  + j ω C1 
 R1 
R R
or R X + j ω L X = 2 3 + j ω C1 R2 R3
R1
Comparing the real and imaginary parts, we obtain:
R R
RX = 2 3 … (10.30)
R1
and L X = C1 R2 R3 … (10.31)
This gives the expression for the unknown inductance in terms of the other bridge
parameter. It is also clear from this expression that the measurement is independent of the
frequency of the excitation signal. The resistor can directly be calibrated to read the value
of the unknown inductance.

312
The Maxwell bridge is limited to the measurement of inductance of the coils of
medium quality factor Q. The Q of the coils should be in between 1 and 10. The Q of the
coil is defined as:
ω LX ω C1 R2 R3 R1
Q= =
RX R2 R3
= ω R1C1 … (10.32)
The phase angle of high Q coils will be nearly equal to +90 o (as RX should be
small) i.e. ∠ θ 4 = 90o . For the bridge to be balance the second condition should also be
satisfies; the sum of phase angles of opposite arms should be equal.
i.e. ∠ θ1 + ∠ θ 4 = ∠ θ 2 + ∠ θ 3
The phase angles ∠ θ 2 + ∠ θ 3 = 0 , as R2 and R3 are purely resistive. The angle
∠ θ 3 should therefore be − 90o . This is possible if the impedance Z1 is purely capacitive
or R1 is infinity large. It is very impractical to have excessively large value of R1.
Further, this bridge is also unsuited for the coils of very low Q (less than 1). The
Q values of this magnitude occur in inductive resistors, or in an R.F. coils if measured at
low frequencies. The difficulty in measurement occurs on account of labour involved in
obtaining the balance point. It is due to the fact that the adjustment for the inductive
balance by R3 upsets the resistive balance by R1. It is sometimes difficult to get the
balance point for very low Q coils. For medium Q coils, the resistance effect is more
prominent, so the balance point is reached after a few adjustments.
10.5 HAY BRIDGE
The Hay bridge is particularly useful for the measurement of inductance of high Q
coils. The schematic diagram of the Hay bridge is shown in figure 10.12. This bridge uses
a resistance R1 in series with the standard capacitor C1 unlike the Maxwell bridge which
uses a resistance R1 in parallel with the capacitor C1.

Fig. 10.12
The balance equation can be written as:
Z1Z X = Z 2 Z 3
The expression for the impedance of the unknown arm is given by:

313
Z2Z3
ZX = … (10.33)
Z1
 1 
where Z1 =  R1 + 
 j ω C1 
Z 2 = R2
Z 3 = R3
Z X = R X + j ω LX
Putting the values of bridge parameters in the balance equation (10.33), we get:
 1 
 R1 + (R X + j ω L X ) = R2 R3
 j ω C1 
LX RX
or R1 R X + + + j ω L X R1 = R2 R3
C1 j ω C1
Equating the real and imaginary parts, we obtain:
L
R1 R X + X = R2 R3 … (10.34)
C1
RX
and = ω L X R1 … (10.35)
ω C1
Equation (10.35) can be rewritten as:
R X = ω 2 L X C1 R1 … (10.36)
Putting the value of R X from equation (10.36) in equation (10.32), it can be
solved for the inductance LX and resistance RX as:
R1 (ω 2 L X C1 R1 ) + X = R2 R3
L
C1

or ( ) L
ω 2 L X C1 R12 + X = R2 R3
C1
or ω 2 L X C12 R12 + L X = R2 R3
 R2 R3 C1 
or L X =  2 2 
 … (10.37)
 1 + ω C1 R1 
2

 R2 R3 C1 
and R X = ω 2 C1 R1  
2 2 
 1 + ω C1 R1 
2

 ω 2 C12 R1 R2 R3 
=  2 2 
 … (10.38)
 1 + ω 2
C R
1 1 

The expressions for the unknown inductance LX and resistance RX contain the
frequency term ω. Therefore, it is evident that the frequency of the supply source to the
bridge must be accurately known. This is, however, not true when the inductance of high
Q coil is measured.
The Q of the coil is given by:

314
ω LX
Q= … (10.39)
RX
The phase angle of the impedance ZX is given by:
ω LX
tanθ X =
RX
which is positive (inductive).
ω LX
So tanθ X = =Q … (10.40)
RX
The phase angle of the impedance Z1 is given by:
1
tanθ1 = … (10.41)
ω C1 R1
which is negative (capacitive).
But according to the balance condition the sum of phase angles of opposite arms
should be equal.
i.e. ∠ θ1 + ∠ θ X = ∠ θ 2 + ∠ θ 3
The phase angles ∠ θ 2 + ∠ θ 3 = 0 , as R2 and R3 are purely resistive.
So tanθ1 = tanθ X (as θ1 is negative and θ X is positive).
1
This implies: Q= … (10.42)
ω C1 R1
From equations (10.37) and (10.42), we get:
 R RC 
L X =  2 3 1 2  … (10.43)
 1 + (1 Q) 
For a value of Q greater than 10, the term (1 Q) 2 will be less than 1 1000 which
can be neglected. Therefore, equation (10.43) reduces to:
L X = R2 R3C1 … (10.44)
This equation is the same as for a Maxwell bridge. It is thus concluded that the
Hay bridge is suitable for the measurement of inductance of high Q coils (greater than
10).
10.6 SCHERING BRIDGE
The schematic diagram of the Schering bridge is shown in figure 10.13. It is an
important a.c. bridge used for the precise measurement of the capacity of the capacitors.
This bridge is also useful for the measurement of the insulating properties of the
capacitors. One of the ratio arms has the parallel combination of resistance a R1 and a
capacitance C1. The standard arm has a standard capacitance C3. The capacitor C3 is a
high quality mica capacitor for the measurement of the capacity of the capacitor and it
usually an air capacitor (having very stable value and a very small electric field) for the
insulation measurement.

315
Fig. 10.13
The balance equation for this Schering bridge can be written as:
Z1Z X = Z 2 Z 3
The expression for the impedance of the unknown arm is given by:
Z Z
Z X = 2 3 = Z 2 Z 3Y1 … (10.45)
Z1
where Y1 is the admittance of the impedance Z1, which is given by:
1
Y1 = + j ω C1
R1
The other bridge parameters are given by:
Z 2 = R2
1
Z3 =
j ω C3
1
Z X = RX +
j ωCX
Putting the values of the circuit parameters in equation (10.45), we have:
1 1  1 
RX + = R2  + j ω C1 
j ωCX j ω C 3  R1 
1 1 R2 R2 C1
or RX + = +
j ωCX j ω C 3 R1 C3
Equating the real and imaginary parts, we obtain:
RC
RX = 2 1 … (10.46)
C3
C R
and CX = 3 1 … (10.47)
R2

316
These are the two balance equations and C1 and R2 are chosen as the variable
elements. Since R1 and C3 are fixed in equation (10.47), the dial of the resistor R2 may be
calibrated to read directly the capacity of the unknown capacitor CX.
The dissipation factor D of the unknown arm (series RC circuit) is given by:
RX
D= = ω C X RX … (10.48)
1 ωCX
The dissipation factor tells us something about the quality of a capacitor and by
putting the values of RX and CX from equations (10.46) and (10.47), we have:
C R RC
D=ω 3 1 2 1
R2 C 3
= ω C1 R1 … (10.49)
From this equation it is clear that for fixed frequency of the applied signal, the
dial of the capacitor C1 can be calibrated to read directly the dissipation factor.
It should however be understood that the calibration for dissipation factor holds
good for one particular frequency, but may be used at another frequency if correction is
made by multiplying by the ratio of frequencies.
10.7 WIEN BRIDGE
The another a.c. bridge known as the Wien bridge is shown in figure 10.14, which
consists a series RC combination in one arm and a parallel RC combination in the
adjoining arm. Basically it is used for the measurement of frequency of the applied
signal. It can also be used for the measurement of an unknown capacitor with great
accuracy.

Fig. 10.14
The balance equation of this bridge can be written as:
Z1Z 4 = Z 2 Z 3
It can also be written as:
ZZ
Z 2 = 1 4 = Z1 Z 4Y3 … (10.50)
Z3
where Y3 is the admittance of the impedance Z3, which is given by:

317
1
Y3 = + j ω C3
R3
The other bridge parameters are given by:
1
Z 1 = R1 +
j ω C1
Z 2 = R2
Putting the values of the circuit parameters in equation (10. 50), we have:
 1  1 
R2 = R4  + j ω C 3  R1 + 
 R3  j ω C1 
R1 R4 R4 C R
or R2 = + j ω C 3 R1 R4 + + 3 4
R3 j ω C1 R3 C1
Equating real and imaginary parts we get:
R2 R1 C3
= + … (10.51)
R4 R3 C1
R4
and ω C3 R1 R4 = … (10.52)
ω C1 R3
ω 2 C 3C1 R3 R1 R4 = R4
1
ω2 =
C1C 3 R1 R3
1
ω=
C1C 3 R1 R3
1
f = … (10.53)
2 π C1C3 R1 R3
In most Wien bridges, the components are so chosen that
R1 = R3 = R (Variable resistances R1 and R3 may be mechanically
ganged to have both these resistances equal) and C1 = C 3 = C (fixed values)
The equations (10.51) and (10.53) become:
R2
=2
R4
1
and f =
2 π RC
As long as C1 and C3 are fixed capacitors having capacity equal in magnitude and
R2 = 2R4 , this bridge may be used as the frequency determining device. In this condition
the bridge may be balanced by a single control, the coupling point of the resistances R1
and R3. This control may directly be calibrated in terms of frequency f. This bridge is
suitable for measurement of frequencies from 100 Hz to 100 KHz with an accuracy
ranging from 0.1% to 0.5%. The Wien bridge also finds application in audio and high
frequency oscillators as the frequency determining device.

318
Unless the waveform of the applied signal is sinusoidal, the bridge is very
difficult to be balanced because it is sensitive to the frequency of the applied signal.
10.8 WAGNER GROUND CONNECTION
In a.c. bridges the stray capacitances exists between the various bridge elements
and between the bridge elements and the ground. These capacitances affect the accuracy

Fig. 10.15
of bridge measurements particularly at high frequencies or when small capacitors or large
inductors are measured. An effective way of controlling these stray capacitances is by
shielding properly the bridge elements. This method does not eliminate the capacitance,
but makes it constant in value which can easily be compensated.
Another method of eliminating the effect of stray capacitances to a greater extent
in the a.c. bridges is the Wagner ground or earth connection. Figure 10.15 shows the
Wagner ground connection to a general form of the bridge network, in which Z1, Z2, Z3
and Z4 are the elements of the four arms of a bridge. The impedances Z5 and Z6 are the
two variable impedances of the Wagner ground branch. The center point of this branch is
grounded. The capacitors C1, C2, C3 and C4 are the stray capacitors appearing at the
junctions of the bridge arms and the ground. The following procedure is used for
eliminating the effect of stray capacitance in the bridge circuits.
The switch S is thrown to position 1, and bridge is balanced by adjusting the
impedances Z2 and Z4. The presence of the stray earth capacitors will prevent in obtaining
the true balance, but a point of minimum sound in the headphone is obtained. The
headphone is used as the detector in the bridge circuit.
After this adjustment for getting the minimum sound, the switch is thrown to
position 2 so that the headphone is connected to the B point and earth. The impedances Z5
and Z6 of the Wagner ground branch are then adjusted for the minimum sound. Now
when the switch S is reconnected to the position 1, the balance point will be disturbed
and the impedances Z2 and Z4 are adjusted for the minimum sound again. This procedure
is repeated till the null point is obtained with switch on both the positions of the switch.
All the three points’ B, D and E are at the ground potential. In this condition no current

319
flows in the capacitors C2 and C4, and since C1 and C3 are in shunt with the elements of
the Wagner ground branch, these capacitor are eliminated from the bridge network.
Example 10.1. The d.c. Wheatstone bridge(fig. 10.16) has the following parameters:
R1 = 2 KΩ R2 = 4 KΩ
R3 = 8 KΩ R4 = 8.5 KΩ
E = 5 volts with zero internal resistance
Galvanometer resistance Rg = 300 Ω
Calculate the galvanometer current. Also find the deflection in the galvanometer
due to unbalance of the bridge if the current sensitivity is 0.1 mm / µA.

Fig. 10.16
Solution. Thevenin’s voltage ETh is given by the difference of voltages in the CB and
DB branches.
ETh = ECD = E DB − ECB = ECB − E DB
 R3 R4 
= E  − 
R
 1 + R 3 R 2 + R 4 

 8 8.5   8 8.5 
= 5 −  = 5 − 
 2 + 8 4 + 8.5   10 12.5 
= 5(0.8 − 0.68) = 0.6 V
Thevenin’s equivalent resistance RTh is given by:
 RR R R 
RTh =  1 3 + 2 4 
 R1 + R3 R2 + R4 
 2 x 8 4 x 8.5 
= +  = 1.6 + 2.72
 2 + 8 4 + 8.5 
= 4.32 K Ω
Galvanometer current is given by:
ETh
Ig =
RTh + R g
0.6 0.6
= =
4.32 K + 0.3K 4.62 K

320
= 0.1299mA
Galvanometer deflection d is given by:
d = 129.9 µ A x 0.1mm / µ A
= 12.99mm
Example 10.2. The four impedances of an a.c. bridge (figure 10.17) have the following
parameters:
Z 1 = 200 Ω ∠ 50 o
Z 2 = 100 Ω ∠ 40 o
Z 3 = 400 Ω ∠ − 30 o

Z 4 = 200 Ω ∠ 30 o
Find whether the bridge is balanced or not.

Fig. 10.17
Solution. The first condition for a.c. bridge is given by:
Z1 . Z 4 = Z 2 . Z 3
Z1 . Z 4 = 200 x 200 = 40 KΩ
Z 2 . Z 3 = 100 x 400 = 40 KΩ
The first condition is satisfied.
The second balance condition is given by:
∠ θ1 + ∠ θ 4 = ∠ θ 2 + ∠ θ 3
∠ θ1 + ∠ θ 4 = ∠50 o + ∠30o = ∠80o
∠ θ 2 + ∠ θ 3 = ∠40 o + ∠ − 30 o = ∠10 o
The phase equation is not satisfied. So the bridge is not balance.

Example 10.3. An a.c. bridge shown in figure 10.18 is excited by sinusoidal signal of
1KHz. The impedance Z1 is a pure capacitance of 0.2µF, Z2 is a pure resistance of 500Ω,
Z3 is the parallel combination of a 300Ω resistance and a 0.1µF capacitor. Find the
magnitude and phase of the unknown impedance Z4 , which is a series combination of
resistance and capacitance or inductance.

321
Fig. 10.18
1 1
Solution. Z1 = =
2 π fC 2 x 3.14 x 1000 x 0.2 x 10 − 6
= 796.18Ω
Z 1 = 796.18∠(−90 o )
Z 2 = 500 Ω ∠ 0 o
1
Rx
jω C R
Z3 = =
R +
1 1 + jω CR
jω C
R 300
= =
1 + jω CR 1 + j x 2 x 3 . 14 x 0 . 1 x 10 − 6 x 300
300
=
1 + jx 2 x 3 . 14 x 100 x 0 . 1 x 10 − 6 x 300
300
=
1 + j 0 . 1884
300 (1 − j 0 . 1884 )
=
(1 + j 0 . 1884 )(1 − j 0 . 1884 )
300 (1 − j 0 . 1884 )
=
1 + ( 0 . 1884 ) 2
= 290 (1 − j 0 . 1884 )
= 290 − j 54 . 58

( ) 
= ( 290 ) 2 + ( 54 . 58 ) 2 . − tan −1 (

54 . 58 
290 
)

= 295 .1∠ ( − 10 .7 o )

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Now Z4 =
Z2Z3
=
[ ][ ]
500∠(0 o ) 295.1∠(−10.7 o )
Z1 796.18∠(−90 o )
500 x 295.1
= ∠(0 o ) − ∠(10.7 o ) + ∠(90o )
796.18
= 185.32∠79.3o
Since the phase angle is positive so it indicates that the impedance is the series
combination of resistance R4 and inductance L4. The magnitude of the resistance R4 and
inductance L4 may be calculated as given below:
R42 + (2 π fL4 ) 2 = 185.32
2 π fL4
= tan(79.3 o ) = 5.29
R4
2 π fL4 = 5.29 R4
R4 1 + (5.29) 2 = 185.32
185.32
R4 = = 34.45Ω
5.38
5.29 x 34.45
L4 =
2 x 3.14 x 1000
= 29mH
Example 10.4. The circuit parameters of Kelvin’s bridge shown in figure 10.19 are as
follows: R1 = 10Ω R2 = 100Ω
R AC = 1000Ω RBC = 10Ω
Find the value of unknown resistance R X .

Fig. 10.19
Solution. The value of unknown resistance R X is given by:
R R
RX = 2 3
R1
The ratio of R3 and R1 is also given by:

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R3 RBC
=
R1 R AC
R3 10
= = 0.01
R1 1000
R X = 0.01x100 = 1Ω
Example 10.5. The circuit parameters of Maxwell bridge (fig. 10.20) for the
measurement of inductance of the coil are given as:
R1 = 500 KΩ R2 = 6.90 KΩ
R3 = 100 KΩ C1 = 0.22 µ F
Find the series equivalent ( R X and L X ) of the unknown impedance.

Fig. 10.20
Solution. The value of RX is given by:
R R
RX = 2 3
R1
6.9 Kx100 K
= = 1.38KΩ
500 K
The value of LX is given by:
L X = C1 R2 R3
= 0.022 x10 −6 x 6.9 x10 3 x100 x10 3
= 15.18H

Example 10.6. The circuit parameters of Wien bridge (fig. 10.21) are given as follows:
Impedance Z1 is the series combination of resistance R1 and a 2 µ F capacitor.
Impedance Z2 is a pure resistance of 1000Ω.
Impedance Z3 is the parallel combination of a resistance of 200Ω and a capacitor
of 1 µ F .
Impedance Z4 is also a pure resistance of 400Ω.
Determine the value of resistance R1 and the frequency at which the bridge will
oscillate.

324
Fig. 10.21
Solution. The balance condition of this bridge is given by:
R2 R1 C 3
= +
R4 R3 C1
R C 
or R1 =  2 − 3  R3
 R4 C1 
 1000 1 
= − 200
 400 2 
= 400Ω
The frequency of oscillations at which the bridge will be balance is given by:
1
f =
2 π C1C3 R1 R3
1
=
2 x3.14 2 x10 −6 x1x10 −6 x 400 x 200
10 4
=
2 x3.14 x 4
= 398Hz
PROBLEMS

1. Describe the operation of d.c. Wheatstone bridge. Find the condition for the
bridge to be balanced.
2. Draw the Thevenin’s equivalent of the d.c. Wheatstone bridge and find the
expression of the galvanometer current.
3. Find the approximate expression for the Thevenin’s voltage and resistance if the
d.c. bridge is slightly unbalance (less than 5%).
4. Find the condition for the d.c. Wheatstone bridge to be balanced. Describe the
possible sources of errors in the Wheatstone bridge.

325
5. The d.c. Wheatstone bridge is not suitable for the measurement of unknown
resistance (less than 1Ω). Comment on this statement and give reason in support
of your answer.
6. Describe the operation of Kelvin bridge. Also find the condition of the bridge to
be balanced.
7. Describe the operation of Kelvin double bridge. Find the condition of this bridge
to be balanced. What are the advantages of this Kelvin double bridge over the
conventional d.c. Wheatstone bridge?
8. Discuss the principle of operation of Kelvin double bridge. Also explain the
practical Kelvin double bridge.
9. Explain the operation of a simple a.c. bridge. What are the two conditions for the
a.c. bridge to be balanced?
10. Find the two conditions for an a.c. bridge to be balanced. Will the bridge be
balanced, if only one condition is satisfied?
11. Draw the circuit of Maxwell bridge and explain how this bridge is used for the
measurement of unknown inductance.
12. Describe the operation of Maxwell bridge. Show that this bridge is used for the
measurement of inductance of low Q coil.
13. Describe the operation of Hay bridge. Show that this bridge is used for the
measurement of inductance of high Q coil.
14. Discuss the operation of Schering bridge which is used for the measurement of
the capacity of an unknown capacitor.
15. How does the basic circuit of Kelvin bridge differ from that of ordinary
Wheatstone bridge.
16. What is the use of Wien bridge? Discuss its operation.
17. Explain the operation of Wien bridge. Find out the expression of frequency of
oscillations at which the bridge will be balanced.
18. What is the use of Wagner ground (earth) connection? Give the details of the
Wagner ground connections.
19. What arrangement is generally used in a.c. bridge to eliminate the effect of stray
capacitances? Discuss its detail.
20. Find the resistance of the unknown arm RX of a Wheatstone bridge (figure 10.22),
if the values of other arms of the bridge are:
(i) R1 = 4 KΩ R 2 = 2 KΩ R3 = 100Ω
(ii) R1 = 3KΩ R2 = 12 KΩ R3 = 50Ω
(iii) R1 = 300Ω R 2 = 3 KΩ R3 = 1KΩ
(iv) R1 = 20 KΩ R2 = 200 KΩ R3 = 12Ω
(Ans.: (i) 50Ω, (ii) 200Ω, (iii) 10KΩ and (iv) 120 Ω )
21. The bridge parameters of unbalanced Wheatstone bridge (figure 10.22) are given
below:
R1 = 100Ω R2 = 200Ω R3 = 1000Ω R4 = 2010Ω
Calculate (i) the galvanometer current if the galvanometer resistance is 20Ω.
(ii) the deflection in the galvanometer if its sensitivity of the
galvanometer is 2mm/ µ A.
(Ans.:8.54µA, 17mm.)

326
Fig. 10.22 Fig. 10.23
22. An a.c. Wheatstone bridge (figure 10.23) has the following parameters, show if
the bridge is balanced.
(i) Z 1 = 50Ω∠ − 40 o Z 2 = 100Ω∠0 o Z 3 = 500Ω∠ − 30 o Z 4 = 1000Ω∠30 o
(ii) Z 1 = 100Ω∠60 o Z 2 = 250Ω∠0 o Z 3 = 400Ω∠40 o Z 4 = 1000Ω∠ − 30 o
(iii) Z 1 = 1000Ω∠30 o Z 2 = 2500Ω∠20 o Z 3 = 40Ω∠40 o Z 4 = 4000Ω∠30 o
(Ans.: Balanced, not balanced, not balanced)
24. An a.c. (figure 10.23) has the following parameters:
(i) Z 1 = 200Ω∠40 o Z 2 = 500Ω∠0 o Z 3 = 800Ω∠10 o
Find the value of the unknown arm.
(Ans.: Z 4 = 2000Ω∠ − 25 o )
25. An a.c. (figure 10.23) is excited with a sinusoidal signal of 1KHz frequency. The
bridge parameters are given below:
The impedance Z1 is the parallel combination of resistance 1000Ω with 0.5 µF
capacitor, impedance Z2 is the series combination of resistance 1000Ω with 0.5 µF
capacitor, impedance Z3 is the series combination of resistance 200Ω with an
inductance of 30 mH.
Find the value of unknown arm Z4.
(Ans.: 80Ω∠ − 110 )
26. The circuit parameters of Kelvin’s bridge shown in figure 10.19 are as follows:
R1 = 100Ω R2 = 10Ω
R AC = 10000Ω RBC = 100Ω
Find the value of unknown resistance R X .
(Ans.: 0.1Ω)
27. The circuit parameters of Maxwell bridge (fig. 10.20) for the measurement of
inductance of the coil are given as:
R1 = 10 KΩ R2 = 1.5 KΩ

327
R3 = 1.5 KΩ C1 = 0.5 µ F
Find the series equivalent ( R X and L X ) of the unknown impedance.
(Ans.: R X = 225Ω and L X = 1.125H )
28. The circuit parameters of Wien bridge (fig. 10.21) are given as follows:
Impedance Z1 is the series combination of resistance R1 and a 0.2 µ F capacitor,
Impedance Z2 is a pure resistance of 2000Ω, Impedance Z3 is the parallel
combination of a resistance of 100Ω and a capacitor of 0.5 µ F and Impedance Z4
is also a pure resistance of 100Ω.
Determine the value of resistance R1 and the frequency at which the bridge will
oscillate.
(Ans.: 1.75KΩ, 1.2KHz)

_________

328
11
Switching Devices
and Circuits
In this chapter the construction and working of some important switching devices
such as Unijunction Transistors (UJT’s), Silicon Controlled rectifiers (SCR’s), Diacs,
Triacs and Silicon Controlled Switches (SCS) with their applications will be discussed.
The working of these devices depends on the phenomenon of avalanche breakdown. So
these devices are also called the breakdown devices.
11.1 UNIJUNCTION TRANSISTOR
The unijunction transistor (UJT) is three-terminal Silicon device which has only
one P-N junction. Figure 11.1(a) shows the physical structure of the unijunction
transistor. It consists of lightly doped (high resistance) N-type silicon bar which form the
base of the device. The impurity of P-type material is diffused into the base producing a

(a) (b)
Fig. 11.1
single P-N junction which behaves like a diode. Two ohmic (non-rectifying) contacts are
formed on the N-type bar. These two contacts on the N-type base are known as Base 1
(B1) and Base 2 (B2). The B2 is nearer to the P-N junction and B1 is slightly far from the
junction. The P-Type (aluminum) forms the emitter E. This device has three terminals
emitter E, base B2 and base B1; and a junction hence the name unijunction transistor. Its
characteristics are very different from the conventional two-junction bipolar transistor. It
is not an amplifying device. It exhibit negative resistance in the characteristics hence it is
useful in generating the oscillations. The unijunction transistor can also be used as a pulse
generator with the trigger or control signal applied at the emitter. The symbolic
representation of the unijunction transistor is shown in figure 11.1 (b). The emitter
terminal (E) is shown at an angle to the vertical and the arrow to the emitter indicates the
direction of the conventional emitter current when UJT is in the conducting state.
The equivalent circuit of the unijunction transistor is shown in figure 11.2(a). The
diode D1 is formed by P-N junction inside UJT. The interbase resistance RBB of UJT is
the base resistance between the terminals B1 and B2 when IE = 0. This resistance RBB is,
therefore, divided into two parts RB2 and RB1 at the cathode point A of the diode. So when
IE = 0, RBB is given by:
RBB = RB1 + RB 2 … (11.1)
It may further be noted that the point A is such that RB1 > RB 2 . Usually
RB1 = 0.6 R BB .
Now if the voltage VBB is applied to the terminal B2 with respect to terminal B1 the
voltage VB1 across RB1 (or at the cathode point) is given by:
R B1
V B1 = VBB
R B1 + R B 2
= ηVBB … (11.2)
The factor η is called the intrinsic stand off ratio of the device and is given by:
RB1
η=
R B1 + R B 2
The intrinsic stand off ratio is the property f the UJT and is always less than unity
usually its value lies in between 0.5 to 0.85.

(a) (b)
Fig. 11.2
The working of the working of unijunction transistor may now be explained as
follows:
After the application of the voltage VBB at the point B2, the voltage VB1 across the
resistance RB1 will reverse bias the diode D1. The total reverse voltage VP is given by:

330
VP = V B1 + VD
= ηVBB + VD … (11.3)
where VD is the barrier voltage of the diode and its value is 0.7V for Si.
This reverse voltage VP is called the peak point voltage. When the applied emitter
voltage VE is greater than the peak point voltage VP , the diode D1 fires and the emitter
current IE flows. The region from VE = 0 to VE = VP is called the cutoff region. When VE
exceeds the peak point voltage, the holes from P-type emitter are injected into the N-type
base. These holes will now move towards the terminal B1, because B1 is more negative
than the terminal B2. So the base region between the point A and B1 has the excess holes.
In order to keep the charge neutrality, free electrons will also diffuse towards this
terminal B1. There will, therefore, be an increase in charge carriers in this base region
between the point A and the terminal B1. Due to this increase in the charge carriers the
resistance RB1 will decrease. Due to decrease in RB1, η as well as VB1 decreases. This
decrease in VB1 causes more emitter current to flow which causes further reduction in RB1,
η and VB1. This is the regenerative process. So as IE increases, VB1 as well as VE
( VE = V B1 + V D ) decreases. The decrease in the emitter voltage due to the increase in
emitter current produces negative resistance. The V-I characteristic curve of UJT is given
in figure 11.2(b). From this curve it is clear that the negative resistance region extends to
the valley point where VE = Vγ . Beyond this valley point IE increases with VE. This is the
saturation region which exhibits a positive resistance in the characteristic.
The unijunction transistor can be triggered to conduction if a suitable positive
pulse is applied to its emitter. It can, however, be brought back to cutoff if a negative
pulse is applied to the emitter.
11.2 UNIJUNCTION TRANSISTOR RELAXATION OSCILLATOR
The use of unijunction transistor is the relaxation oscillator. The basic circuit
diagram of UJT relaxation oscillator is shown in figure 11.3 which consists of a UJT, a

Fig. 11.3
resistance R and a capacitance C. The operation of this circuit is explained as given
below:

331
When power is switched on to the circuit, the capacitor C starts charging
exponentially through the resistance R and as soon as the emitter voltage reaches the peak
point voltage VP of UJT, the emitter becomes forward biased. The emitter current flows
due to the conduction of the diode of UJT. The UJT is said to have fired. The resistance
RB1 drops to a very low value accompanied by a heavy flow of emitter current. The
capacitor C will now start discharging through the emitter and low RB1. The UJT then
goes to cutoff region. The capacitor C again starts charging through R and the cycle
repeats. If the output is taken across the capacitor C we get the saw tooth wave as shown
in figure 11.3.
If two resistances R1 and R2 are introduced at the base B1 and B2 respectively as
shown in figure 11.4, the spike waveforms are obtained at the two bases. When UJT fires,
there is sudden increase in the emitter current through R1. This increase in the current
through R1 is the positive going spikes. At the same time there is fall of voltage VEB1 due
to which the current through R2 increases thus generating negative going spike at the base
B1. These spikes are shown in the figure 11.4. The frequency of the waveforms can be
changed by applying different values of the capacitor.

Fig. 11.4
The frequency of oscillations f of this UJT relaxation oscillator depends on the
time constant RC and on the characteristic of the transistor. For the value of R1 less than
100 Ω , the period of oscillations T is given by:
 1 
T = RC ln  … (11.4)
1− η 
And frequency of oscillations is given by:
1 1
f = = … (11.5)
T  1 
RC ln 
1− η 
where η is the intrinsic stand off ratio.
11.3 SILICON CONTROLLED RECTIFIER
The Silicon Controlled Rectifier is a four layer switching device and is also an
important member of thyristor family. This device was first introduced by Bell Telephone

332
Laboratories in 1956. It finds many applications in relay controls, time delay circuits,
phase controls, inverters and battery chargers etc. Figure 11.5 shows the physical
structure and symbolic representation of the device. The silicon controlled rectifier (SCR)
is a four-layer PNPN solid state rectifier which has three electrodes: an anode, a cathode
and a gate. The gate serves as a control element. When the anode is kept at a positive
potential with respect to cathode junctions J1 and J2 will be in forward bias and the
junction J3 will be in reverse bias and thus no current flows through the device and it is
said to be in the off state. The current will, however, flow through the device if the
positive gate potential is applied. In this condition SCR is said to be in the ON state. If on
the other hand the anode is kept at the negative potential with respect to cathode, SCR
will not conduct as the junctions J1 and J2 will be in reverse bias.

(a) (b)
Fig. 11.5
The basic operation of SCR can also be described by splitting physical structure
of SCR into two three-layer transistor structures as shown in figure 11.6(a). This structure
is the equivalent of two complementary transistors as shown in figure 11.6(b). When the

(a) (b)
Fig. 11.6
anode is at the positive potential with respect to cathode, the collector of transistor T1
drives the base of the transistor T2 and the collector of T2 drives the base of T1. As long as
the base emitter junction of T2 is in cutoff, the two transistors will be in the blocking
state. If a small forward current is produced in the base emitter junction of T2, the
transistor will conduct and the collector current of transistor T2 will flow into the base of

333
transistor T1. The transistor T1 thus conducts. The conduction of transistor T2 will
increase due to the flow of collector current of T1 into base of T2. This positive feedback
loop will cause a rapid increase in the conduction between anode and cathode. As long as
voltage is applied between the anode and cathode, the complementary pair of transistor
will continue to conduct. Once the SCR is in saturation, the gate voltage can be removed.
Hence turning on the SCR can be achieved by a short duration gate pulse. The conduction
of the device can be stopped only by removing the anode voltage or by reversing the
anode voltage.
The V-I characteristic curve of SCR is shown in figure 11.7. In this figure when
the anode is positive with respect to cathode the characteristic is known as forward
characteristic. In the forward direction, if the anode voltage is increased from zero with
no gate current, then below the break-over voltage (VB0), the SCR will not be conducting.
It is said to be holding the forward blocking state. As soon as the anode voltage becomes
equal to the break-over voltage, the voltage across SCR suddenly drops as shown by
dotted lines and SCR is said to be conducting. If proper gate current is made to flow, the
SCR will conduct at much smaller voltage. From this figure it is clear that the break-over
voltage can be controlled by increasing the gate current.
Similarly, in the reverse direction when anode is negative with respect to cathode,
SCR does not conduct and voltage across SCR will be nearly equal to applied reverse
voltage. If the reverse voltage is increased than at some voltage, the breakdown occurs
and SCR starts conducting heavily in the reverse direction. The voltage at which the
breakdown occurs in the reverse direction is known as the reverse breakdown voltage.

Fig. 11.7
Now important term related to SCR are defined as follows:
Breakover voltage: The breakover voltage (VB0) of SCR is defined as the minimum
forward voltage at which it is turned ON provided the gate is open or no current is flowing
through the gate. The SCRs of different breakover voltages are commercially available.
The supply voltage of SCR should be less than the breakover voltage (VB0), otherwise
SCR will conduct even at a very small gate current.
Peak reverse voltage (PVR): It is the maximum reverse voltage that can be applied
across SCR without conducting in the reverse direction. The PVR of SCRs is specified by
the manufacturers. If the applied reverse voltage is exceeded than the PVR rating of SCR,
than there may be avalanche breakdown and SCR will be damage.

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Holding current (IH): It is the maximum anode current at which SCR is turned OFF
from ON condition, provided the gate is open. As discussed above, once the SCR is on it
will continue to remain in the conducting state even if the gate voltage is removed. The
only way to turn off SCR is to reduce the supply voltage to almost zero. At this potential
the internal transistor comes out of saturation region and opens the SCR. In this condition
the anode current is very small and is known as holding current. Thus the SCR will be
turned off if the anode current is less than its holding current.
Forward current rating: It is the maximum anode current that can pass through the SCR
without destruction. If the anode current exceeds the specified forward current rating then
the SCR will be damaged due to the excessive heating at the junctions. The forward
current rating is specified by the manufacturers. The forward current rating of the
commercially available SCRs ranges from about 30A to 100A.
11.4 HALF WAVE SERIES STATIC SWITCH
There is variety of applications of SCR’s. A few applications are being discussed
here. Figure 11.8(a) shows the use of SCR as half wave series static switch. The a.c.
signal is applied XY input terminals of the circuit. When the switch S is open then no

(a) (b)
Fig. 11.8
current flows through the load resistance RL as the gate current is zero and the SCR will
be in cutoff region. The switch S is an electromagnetic, electrical or mechanical switch.
When the switch S is closed as shown in figure 11.8(b), during the positive half cycle of
the input wave the gate of the SCR will be at the positive potential and sufficient gate
current flows. The SCR is, therefore, turned ON and the voltage drop across SCR will be
very low. The gate current will be greatly reduced. During the negative half cycle of the
input wave will be turned off as the anode will be at negative potential with respect to
cathode. The reversal of gate current is prevented using the diode D. The waveforms for
the load current or load voltage are also shown in figure 11.8(b), which are the half wave
rectified signal.
11.5 PHASE CONTROL CIRCUIT
As discussed above the half wave rectified output can be obtained by using SCR
circuit. By varying the gate triggering current the phase angle can be controlled, which is
illustrated in figure 11.9(a). This circuit is similar to the circuit discussed for getting the
half wave rectified output. In this circuit a variable resistance R is used. The combination
of resistances R and R1 will limit the gate current during the positive portion of the input

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signal. If R is set to its maximum value, the gate current will not be sufficient to turn-on
the SCR. As R is decreased from the maximum, the gate current can make the SCR to
turn-on somewhere in between 0 to 90o. If on the other hand R is low, the SCR will
trigger almost immediately at the start of the positive half cycle of the input signal. So by
adjusting the value of resistance R, the conduction angle between 0 to 900 can be
obtained as shown in figure 11.9(b).

(a) (b)
Fig. 11.9
11.6 SCR HALF WAVE RECTIFIER
On the principle of varying the conduction angle, SCRs can be used for getting
the half wave rectified output. Figure 11.10 shows the half wave rectifier circuit using
SCR. The a.c. signal E to be rectified is applied across an SCR through a load resistance
RL. The gate is connected to the positive supply through a variable resistance r. This
variable resistance will control the gate current and the conduction angle can be varied. It
is assumed that the peak reverse voltage of SCR is greater than peak inverse voltage of
the a.c. signal, so that the avalanche breakdown will not occur during the negative half
cycle of the a.c. supply.

Fig. 11.10

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The working of this circuit can be explained as follows:
During the positive half cycle of the input a.c. signal E, the anode of the SCR is
positive with respect to the cathode, it will start conducting when the gate current is made
to flow. The gate current flows due to the d.c. source and a variable resistance r. This
variable resistance r can vary the conduction angle θ C . At the particular conduction angle
θ C the SCR may conduct. So the current in the load resistance flows for less than half of
the cycle i.e. for θ C to180o the current flows in the load resistance and not from 0 to 180o
as flows in the usual half wave rectifier circuit. The present circuit therefore controls the
power in the load resistance.
During the negative half cycle of the input a.c. signal the SCR will not conduct
even if the proper gate current flows.
The input output wave forms are shown in figure 11.10(b).
Let E = Em Sin θ is the input signal applied across the SCR, where E m is the peak
value of the input signal. The average output voltage E av (across the load resistance) will
be given by:
π
1
2 π θ∫C
E av = E m sin θ .d θ

Em
= (Cos θ C − Cos π )

E
= m (1 + Cos θ C ) … (11.1)

The average current flowing through the load is given by:
E Em
I av = av = (1 + Cos θ C ) … (11.2)
RL 2 π RL
It is clear from this equation that if θ C = 0 o , the average output current will be
same as for normal half wave rectifier i.e.
I av =
Em
2 π RL
( ) E
1 + Cos 0 o = m
π RL
If θ C = 90 o then I av will be given by:

I av =
Em
(
2 π RL
1 + Cos90 o = ) Em
2 π RL
From the above discussion it may be noted that the average current will decrease
with the increase of θ C .
11.7 SCR FULL WAVE RECTIFIER
The use SCR as full wave rectifier is illustrated in figure 11.11. The working of
this circuit is similar to that of SCR half wave rectifier. During the positive half cycle of
the input signal first SCR (S1) will conduct as per its gate current; the second SCR (S2)
will not conduct through this half cycle. During the negative half cycle the second SCR

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(S2) will conduct and the first SCR (S1) will not conduct. The wave form across the load
resistance is shown in figure 11.11(b).

(a)

(b)
Fig. 11.11
The average output voltage E av (across the load resistance) for this case is
given by:
π
1
E av =
π ∫E
θC
m sin θ .d θ

Em
= (Cos θ C − Cos π )
π
E
= m (1 + Cos θ C ) … (11.3)
π
The average current flowing through the load is given by:
E E
I av = av = m (1 + Cos θ C ) … (11.4)
RL π RL
It is clear from the equations (11.3) and (11.4) that the average voltage or the
average current in the load resistance is double to that of the half wave rectifier for the
same firing angle. It is because of the rectification of negative half cycle also.

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11.8 SILICON CONTROLLED SWITCH
The silicon controlled switch (SCS) is a four layer PNPN and four-terminal
device. The four terminals of the device are anode (A), cathode (K), anode gate (G1) and
cathode gate (G2). The structural diagram of SCS is shown in figure 11.12(a) and its
symbolic representation in figure 11.12(b). The SCS is similar to SCR with the

(a) (b)
Fig. 11.12
difference that it has an additional gate terminal i.e it has two gates and one nearer to the
anode is called as anode gate and the other gate being nearer to the cathode is known as
cathode gate. Both the gates can be used to turn-ON or turn-OFF the device. When a
negative pulse is applied to the anode gate (G1) the device will be turned on; and to
switch off the device a positive pulse is needed at the anode gate. Similarly, positive
pulse at the cathode gate (G2) will switch on the device and the negative pulse at this gate
will switch off the device.

Fig. 11.13
The operation of this device can now be understood by considering its two
complementary transistor equivalent circuit shown in figure 11.13. When a negative
pulse is applied at the anode gate G1, emitter base junction of the transistor T1 will be in
forward bias which turns it ON. The heavy current IC1 will flow through the base of the
transistor T2 and will also turn it ON. There will be regenerative action and SCS will be in
the ON state. A positive pulse at the anode gate G1 will reverse bias the emitter base
junction of the transistor T1 resulting off this transistor and the current IC1 will also be
almost zero and transistor T2 will be off. Thus the device is open or off. Similarly the

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device can also be switched off or on by applying the proper pulse at the cathode gate G2.
The V-I characteristic of SCS is same as that of SCR. The SCS has much reduced turn-
OFF time.
The SCS finds applications in counters, registers, timing circuits, pulse
generators, voltage sensors and oscillators etc.
A simple application of the use of SCS is illustrated in figure 11.14. It is an alarm
system with any number of inputs situated at various stations. In the figure only three
inputs are shown. The inputs are connected to cathode gates of different SCSs. To these
inputs transducers capable of giving positive signal can be connected. Whenever any of
the transducer gives the positive signal to any of the input the corresponding SCS will be
ON and the relay will be energized to produce the sound in the alarm. The outputs are the
indicating lights which will indicate the location of the input.

Fig. 11.14
11.9 THE TRIAC
The triac is a three terminal semiconductor device used for controlling current in
either direction. Figure 11.15 shows the schematic symbol for the triac. The symbol looks
like two SCRs in parallel (opposite direction) with one trigger or gate terminal. The
mains or power terminals are designated as MT1 and MT2. When the voltage on the MT2
is positive with regard to MT1 and a positive gate voltage is applied, the left SCR
conducts. When the voltage is reversed and a negative voltage is applied to the gate, the
right SCR conducts. Minimum holding current, IH, must be maintained in order to keep a
triac conducting. A triac operates in the same way as the SCR; however, it operates in
both forward and reverse directions.

Fig. 11.15

340
The triac is a five layer N1-P1-N2-P2-N3 device as shown in figure 11.16(a), which
may be considered to consist of an N1-P1-N2-P2 section in parallel with a P1-N2-P2-N3
section, as illustrated in figure 11.16(b). An additional N region serves as the control gate.
The TRIAC is therefore a double ended SCR.
The break-over voltage is usually high. When a positive voltage is applied to MT2
with respect to the terminal MT1, positive gate voltage will turn ON the triac. Similarly,
when MT2 is at a negative potential with respect to the terminal MT1, a negative gate
voltage will turn ON the device.

(a) (b)
Fig. 11.16
To get a quick understanding of its operation refer to its characteristic curve
shown in figure 11.17 and compare this to the SCR characteristic curve. It can be
triggered into conduction by either a PLUS (+) or MINUS (-) gate signal.

Fig. 11.17
11.10 THE DIAC
The DIAC is like a triac without gate terminal, so it is a two terminal device. As
gate is not provided, it triggers only at a constant voltage known as breakover voltage

341
(VB0) in either direction. Figure 11.18 shows the symbol of the DIAC which shows that it

Fig. 11.18
is combination of two SCRs connected in reverse parallel. The two terminals of the diac
are termed as anode 1 and anode 2 as either of these two terminals may be connected to
the positive or negative supply.

Fig. 11.19
The basic structure of the DIAC is shown in figure 11.19 and it’s V-I characteristic
curve is shown in figure 11.20. When anode 1 is positive with respect to anode 2, then the
conduction takes place due to breakover of P1N2P2N3 section. Similar action takes place
in P2N2P1N1 section when the polarity is reversed.
The characteristic curve of the DIAC clearly indicates that the device has the
symmetrical bidirectional switching action. Due to this feature, the DIACs are frequently
used as triggering devices in triac phase control circuits.

Fig. 11.20
11.11 DIMMER CIRCUIT
The use of diac and triac for controlling the a.c. power into the load resistance is
shown in figure 11.21(a). This circuit called the light dimmer circuit consists of a triac, a
diac and an RC combination. As is well known the triac can conduct in both the

342
directions if the appropriate triggering pulse is applied to its gate. The triggering pulse is
applied through the diac. The variable resistance R in the RC combination is used to vary
the conduction angle θ C . When the power to the load is switched on, the capacitor C
starts charging through the variable resistance R during the positive half cycle of the input
wave and as soon as the voltage across the capacitor C becomes equal to the breakover
voltage of the diac a sharp high current trigger pulse is applied to the gate of the triac.
The triac now conducts and the load current flows through the load. A similar operation
repeats for the next half cycle. So for half cycle (positive or negative) of the input wave
the current in the load resistance flows for some portion (at some conduction angle θ C ) as
shown in figure 11.21(b). The power to the load may thus be increased or decreased by
varying the resistance R.

(a) (b)
Fig. 11.21
The circuit of figure 11.21(a) may however produce transient surges due to fast
switching action of the triac which cause the electrical line disturbances. In order to
prevent these disturbances, a line filter consisting of inductance L and capacitor C2 is
incorporated as shown in figure 11.22. A series combination of capacitor C1 and
resistance R1 is used to prevent the triac when the inductive load is applied. This circuit
now-a-days very commonly used as the fan regulator.

Fig. 11.22
Another circuit for solid state variac is shown in figure 11.23, which utilizes triac
and Unijunction transistor in addition to few more components. When the triac is not
conducting the bridge circuit converts the a.c to d.c. and the zener diode gives the
constant voltage to the unijunction transistor. The capacitor C also charges through the
resistance R. At certain emitter voltage, the UJT fires; this gives the positive spikes at the
input of pulse transformer. These spikes applied to the gate of the triac forces it to

343
conduct and load current flows through the load. The power can however, be controlled
by varying the variable resistance R.

Fig. 11.23
PROBLEMS
1. Describe the construction and working of unijunction transistor.
2. What is relaxation oscillator? How can a unijunction transistor be used as a
relaxation oscillator? Give the expression of its frequency of oscillations.
3. How can a unijunction transistor (UJT) be used to produce saw tooth wave?
4. Discuss the behaviour of Silicon Controlled Rectifier (SCR) using two-transistor
equivalent circuit.
5. What is Silicon Controlled Rectifier (SCR)? Draw its V-I characteristics and
explain the working of SCR. How can SCR be used as a half wave series static
switch?
6. Discuss the working of SCR and explain the following terms related to SCR:
(i) Breakover voltage (ii) Peak reverse voltage
(iii) Holding current (iv) Forward current rating
7. What is Silicon Controlled Rectifier (SCR)? How is SCR triggered? Discuss the
use of SCR as a phase control circuit.
8. Discuss the use of SCR for the half wave rectifier circuit. Find the expression of
average load current in the circuit.
9. Discuss the use of SCRs for the full wave rectifier circuit. Find the expression of
average load current in the circuit.
10. Discuss the behaviour of Silicon Controlled Switch (SCS). How can SCS be
triggered ON or OFF?
11. What is Silicon Controlled Switch (SCS)? Discuss the application of SCS as an
alarm system.
12. Discuss the behaviour and V-I characteristic of a Triac.
13. Draw the circuit of light dimmer and explain its working.
14. Discuss the use of Triac and UJT in power controller circuit.
15. Write short note on the following:
1. SCR
2. SCS
3. Diac
4. Triac
________

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