‘ i 4 PB-ADC3 User’s Manual Preface PB-ADC3 Optoisolated Analog to Digital Piggyback for VMOD-2 and IMOD Manual Order Nr. 14279 User’s Manual Issue 3 Unpacking and Special Handling Instructions ‘This PepCard product is carefully designed for a long and fautt-free life; nonetheless its life expectancy can be drastically reduced by improper treatment during unpacking and installation. Observe standard anti-static precautions when changing piggybacks, ROM deviees, jumper settings, etc. If the product contains batteries for RTC or memory back-up, ensure that the board is not placed on conductive surfaces, including ant static plastics or sponges. These can cause shorts and damage tothe batteries or tracks on the bosrd. ‘When installing the board, switch off the power mains to the chassis, Do not disconnect the mains as the ground. connection prevents the chassis from static voltages, which can damage the board as itis inserted. Furthermore, do not exceed the specified operational temperature ranges of the board version ordered, Ifbatteies are present, their temperature restrictions must be taken into account. Keep all ofthe original packaging material for future storage or warranty shipments. It is necessary to store or ship the board, re-pack it as it was originally packed. Fast, 1996 ‘©1996 PEP Modular Computer Page o-1Preface PB-ADC3 User’s Manual Revision HistoRY PB-ADC3 User's Manui Issue Brief Description of Changes PCB Index Date of Issue i First Issue 2-01 January, 1994, 2 ‘Simall conections throughout manual 2-01 February. 1994 200 ‘Corrections to Chapter 4 2-01 March, 1994 3 ‘Cliange to specifications (overvoltage protection) and 0B Tuly, 1996 board index 3 inserted ‘This document contains proprietary information of PEP Modular Computers. It may not be copied or ransinitied by any means, passed to others, or stored in any retrieval system or media, without the prior consent of PEP Modular Computers or its authorized agents. ‘The information in this document is, to the best of our knowledge, entirely correct, However, PI Computers cannot accept liability for any inaccuracies, or the consequences thereof, nor for an the use or application of any circuit, product, or example shown in this document. fodular ty arising from PEP Modular Computers reserve the right o change, modify, or improve this document or the product described herein, as seen fit by PEP Modular Computers without further notice. Pageod ‘© 1996 PEP Modular Computers Tul 31, 1956PB-ADC3 User's Manual Preface PEP Modular Computers® Two Year Limited Warranty We grant the original purchaser of PEP products the following hardware and system warranty. No other wascanties that may be granted or implied by anyone on behalf of PEP are vatid unless the consumer has the express written consent of PEP Modular Computers. PEP Modular Computers warrants theit own products (excluding software) to be fee from defects in workmanship ‘and materials for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor extendible to cover any other consumers or long term storage of the product. ‘This warranty does not cover products which have been modified, altered, or repaited by any other party than PEP Modular Computers or their authorized agents. Furthermore, any product which has been, or is suspected of being damaged as a result of negligence, misuse, incorrect handling, servicing or maintenance; or has been damaged as a result of excessive current/voltage or temaperatute; or has had its serial number(s), any other markings, or parts thereof altered, defaced, or removed will also be excluded from this waranty A customer who has not excluded his eligibility for this warranty may, in the event of any claim, return the product at the earliest possible convenience, together with a copy of the original proof of purchase, a full description of the application it is used on, and a description of the defect; tothe original place of purchase. Pack the product in such a way as to ensure safe transportation (we recommend the original packing materials), whereby PEP undertakes to repair or replace any part, assembly or sub-assembly at our discretion; or, to refund the original cost of purchase, if appropriate, In the event of repair, refund, or replacement of any part, the ownership of the removed or replaced parts reverts to PEP Modular Computers, and the remaining part of the original guarantee, ot any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee are considered gestures of goodwill, and will be defined in the "Repair Report” retumed from PEP with the repaired or replaced iter, Other than the repair, replacement, or refund specified above, PEP Modular Computers will not accept any liability for any further claims which result directly or indirectly from any warranty claim. We specifically exclude any claim for amage to any system or process in which the product was employed, or any loss incurred as a result of the product not functioning at any given time. The extent of PEP Modular Computers liability to the customer shall not be greater than the original purchase price ofthe item for which any claim exists. PEP Modular Computers makes no warranty or representation, either express or implied, with respect to its products, reliability, fitness, quality, marketability or ability to fulfill any particular application or purpose. As a result, the products are sold "as is,” and the responsibility to ensure their suitability for any given task remains the purchaser's In no event witi PEP be liable for direct, indirect, or consequential damages resulting from the use of our hardware or software products, or documentation; even if we were advised of the possibility of such claims prior to the purchase of, or 0 Ideal Curve GaIN=t F800 “The slope of the curve is measured in the form of the Gain Error for both the $ volt and 10 volt range and stored in the EEPROM. In onder to calculate the corrected value, the offset is frst subtracted from the actual value and then the slope is multiplied with the correction factor, as shown below. Corrected Value = (Actual Value - Offset Value) *(1 + 2) * ILSB where: = Gain Error/ (Full Range - Gain Error) (S¥ Unipolar) ISB =2.44mV (SV Bipolar) (OV Unipolar) .88mV (OV Bipolar) (20mA Unipolar) T6LA (20mA Bipolar) Page 24 © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User Manual Issue 2 Chapter 2 Functional Description 2.3 Logic Interface The logic imerface, together with both shift registers, form the serial interface to the LTC1290 and the EEPROM. The shift register frequency is set to {MHz for both registers. The data transfer is made up of 16 shifts for the LTC1290 and 25 shifts for the EEPROM. ‘As well as serial interface tasks, the status rogister is also realized using the PAL logic. Its tasks include the EOC (End Of Conversion) timing and interrupt handling. Another important task performed by the logic interface is the generation of an ID byte, This built-in test feature allows an interrogation of the VMOD-2/IMOD, supplying an ID for each of the fitted piggybacks. If ths is integrated into the application software, it can be used to check that any piven tasks are valid for the fited pigayback. Ofsets $7F (for location A) and SFF (for location B), allow a software check of which piggybacks are fitted. ‘The PB-ADC3 has a "SEB" Byte. Other ID Bytes are: SEE PB-BIT BITBUS communications controtler SEF PB-DIO4 Digital VO piggyback (high voltage) $rO PB-CNT Counter pigavback SFI PB-DAC2 Dio A converter piggyback SEA PB-DAC3 D to A output piggyback $F2 PBDIO Digital VO piggyback SF PB-DINS Digital input piggyback 3F4 PB-ADC2 A to D converter piggyback SEB PB-ADC3 ‘A to D input piggyback SPS PR-CIOR Counter/V/0 pigayback 3F7 PR-SIO4 ‘Quad serial piggyback RS232 387 PB-SIOSA Quad serial piggyback RS42/RS485 SF8 PBDOUT 12 channel high voltage digital output SED PB-DOUT2 16 channel high voltage digital ouput SF9 PB-DIN2 Digital input piggyback SFB PB-DIO-2 Digital VO piggyback SFC PB-REL Relay pigeyback seD PB-DIOS Digital VO piggyback SFE PB-STP Stepper motor controller piggyback Feb 16, 1994 © 1994 PEP Modular Computers Page 2-5Chapter 2 Functional Description PB-ADC3 User’s Manual Issue 2 This page has been intentionally left blank Page 2-6 “© 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 3. CONFIGURATION Chapter 3 Configuration 3 ‘The PB-ADC3 has 8 pairs of solder jumpers on the solder side of the board, one pair for each channel. These allow the ‘voltage distributor to be set for full or half operation. The 3-pad solder jumper, BSI sets the offset voltage forall inputs Go be used only in Unipolar Mode). Figure 3.0.0.1: PB-ADC3 Jumper Layout (Solder Side) Table 3.0.0.2: Voltage Version: eo | c ee ee ee PB-ADC3 Default Jumper Settings Channel Taniper | Default Setting [Function =a] 0 BPO, BNO, open (0-10V and OV put 1 ‘BPI BML open (0-10V and #10V input 2 1BP2, BM2 open (0-10V and #10V input 3 BPS, BM3 ‘open (0-10V and #10V input 4 BPS. BMA, open (0-10V and =10V input 3 ‘BPS_BMS open (0-10V and =10V input 6 'BP6_BM6 ‘pen (0-10V and =10V input 7 BP? BMT. open (0-10V and +10V input BSE 13 [No additional offset on all inputs Current Version: Channel Tamper fault _Seiting [Function 0 BPO, BMO a [0-20mA input T BPL_BMI set [0-20mA input 2 BP2, BM set [0-20mA input 3 1BP3, BM3 set [20m input 4 BPA BM set [0-20 input 3 BPS, BMS set [20m input 6 ‘BPG. BMG set [0-20m input 7 BP7_BM? set [0-20mA input BSL 13 ‘No additional ofset on all inputs Feb 16, 1954 © 1984 PEP Modular Compaters Page 31Chapter 3 Configuration PB-ADC3 User’s Manual Issue 2 Default settings are shown in italic in the following sections 3.1 Jumpers BP7-BP0, BM7-BMO: Input Selection Voltage Version: [okamne—[ Jumper] Sertiag | Fanetton 0 BPOBMO—] — open] O-10V and 2I0V par wr | osvendasy 7 BEL EMI] open] -0-10¥ and 2107 pat se | osvandssv Z BPE DME | open 0-100 and #100 pat se | 0svaasv 5 BPS BNE | open] 0-10V and 2100 Tapa mt | 0svandssv 7 BREEN] — open] 0-10V and 3107 pat (ae BES BMS open] 0-10V and 3107 pat tt __ | osvenssv 3 RG BM [open | 0-10¥ and 100 par su | 0Vanlasv 7 BP BMT —|— open [0-10 and 107 a s__| osvamissy Current Version: ‘Only one jumper setting is available for the current input version of the PB-ADC3, Channel Jumper, Setting | Function o BPO, BMO, Set 0-20mA input 1 ‘BP1, BMI ser (0-20mA input 2 ‘BP2, BM2, Set (0-20mA input 3 1BP3, BM3 se (0-20mA input 4 BP4, BM4 r set 0-20mA input 3 ‘BPS, BMS, set (0-20mA input 6 BPS, BM6 set 0-20mA input 7 ‘BPT, BM7, ser (0-20mA input Pages ‘1954 PEP Modular Computers Feb 16, 1998PB-ADC3 User’s Manual Issue 2 Chapter 3 Configuration 3.2 Jumper BS1: Offset Voltage Selection ‘This jumper can be configured to set a voltage offset, approx 7.SmV, on all channels. This jumper is used for both voltage and current versions of the PB-ADC3. Voltage and Current Versions: Jumper Setting | Function BSI 13, Offset GV on all puts 2 ‘Offset approx. 7.SmV on all inputs ‘The real measured value of the offset is stored in the EEPROM, For more details on offet voltage selection, please refer to section 2.1 in this manual 3.3. VMOD-2/AMOD Jumper Configuration In order for the PB-ADC3 to be put into use on either the VMOD-2 or IMOD boards, the IRQ and Base Address jumper setlings on these boards must be correctly configured, For more details on these jumper configurations, please refer to the VMOD-2 or IMOD user manuals. Feb 16, 1994 © 1994 PEP Modular Computers Pages3Chapter 3 Configuration PB-ADC3 User's Manual Issue 2 ‘This page has been intentionally left blank Paget (©1994 PEP Modular Computers Feb 16, 1958PB-ADC3 User's Manual Issue 2 Chapter 4 Programming rl 4, PROGRAMMING The base address of the PB-ADCS in the upper pigayback position (location A) is the same as that set for the VMOD- 2/AMOD used (default: $87FE2400/$F70000), whereas the base address in the lower piggyback position (location B) is 4580 of that set for the VMOD-2/IMOD (dofault: $87FE2480/SF 70080), 4.1 PB-ADC3 Address Map Aauress | WyteTWord | Rend Wee | Fanetion BASEYSOO[ Wad ‘ReadWrie | ADC communications repiser BASE:S10_| Woo Read Wie | EEPROM commuticaionsregiot BASES§20|- Wad Write EEPROM programming retister BASES31 | Bye Reail Wiz | Stas register BASE:S7E | Bye Real Dreger 4.11 ADC Communications Register ($00) ‘his register isthe serial interface register for data wansfer to and from the LTC converter chip. The next conversion of the selected channel is started with a word write access to this register. The channel number, the bipolar of unipolar selection and the data output format of the converted value all have to be set (5 214 id ie et to io 7 Oto deo @2i io) BASE+$00 not used | data format [mode] ‘channel Register Description Name Value Description data format] %110 16-bit, LSB first Other mode bits 7-5 of the LTC1290 must not be used on the PB-ADC3, mode a Bipolar bit 1 Unipolar channel eit Channel 0 bits 3-0 %1101 Channel 1 011i Channel 2 0101 Channel 3 1011 Channel 4 61001 Channel $ ‘0011 Channel 6 0001 Channel 7 GeRest Notallowed not used Tor 0 bits 15-8 Feb 16, 1954 © 1994 PEP Modular Computers Page #1Chapter 4 Programming _ PB-ADC3 User’s Manual Issue 2 ‘With each 16 bit data transmission to the LTC converter a 16 bit data word is retumed from the previous conversion. This means that a new conversion has to be staried in order to get out the actual result A: Read Out of One Channel Figure 4.1.1 First > Start Conversion Start Channel n |<_—_—. Start Conversion Channel m Read Conversion Channel n Example best.b 92, BASE+$31 oc? bne.s wait move.w #5CF, BASE+$00 convert channel 0, bipolar wake2: best.b #2, BASES $31 OC? bne.s £2 move.w #59, BASE+S00 convert channel 5, bipolar waitd: beet .b #2, BASE+S32. BOC? bne.s wait? move.w BASE+$00,d0 get channel 0 conversion result Paseo? © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Chapter 4 Programming 4.1.2 EEPROM Communications Register ($10) ‘This register handles the data exchange with the EEPROM. This requires a ‘WORD’ write and read access. Before reading « particular address in the EEPROM, a read command fas to be written tothe required address on this register. Write (Two Cases): 1) Write for EN/DIS protection command eee 14s) 12) 1 10) Ge Bee, 6) 6 dees 2. ie. 0) BASE+S10 ‘command hot used 2) Write for readout command 15 14 139 «12 «1 «6100 9 8 7 6 5 4 8 2 1 BASE:$i0[__ command ‘address not used Register Description Name Value, Description: ‘command | %10011 Disable program protection bits 15-11 | %10000 Enable program protection bits 15-13 | 110 Read stored data address "These bits can ofly be Interpreted with aread bits 12-7 command 0-63, ‘Address 0-63 (de) not used] Free bits 10.0 bits 6-0 Read: After a read command, it can be determined using the stats bit EOC, when the expected data can be read (WORD) ee tae le; fale fl 100) 6) 7, Ge 4) a 2 0) BASE+$10 read data Mar 3, 1994 © 1994 PEP Modular Computers Page a3Chapter 4 Programmin; Example 1 wait #2, BASE+$31 wait #3C000, BASE+$10 wait2: #2, BASE+$31 wait2 BASE+510,.40 ‘Adress offset! -> read command = $CO80 ‘Address offet 63> read command = $DF80 Example 2 wait btst.b #2, BASE+$31 bne.s wait, move.w #$9800,BASB+$10 wait2: btst.b #2, BAS#+§31 bne.s wait? move.w . #$2000, BASH+$20 PB-ADC3 User’s Manual Issue 2 oc? read command for EPROM address offset 0 BoC? get EEPROM read result BoC? set SEPROM in programming mode oc? set EEPROM in protected mode Page 4 ‘© 1994 PEP Modular Computers ‘Mar 3, 1994PB-ADC3 User's 413 Manual Issue 2 Chapter 4 Programming EEPROM Programming Register ($20) ‘This register is used for data exchange inthe progranuning mode. This requires two consecutive word write accesses to the register. The first access sends the write command and the address that isto be overwritten, First value write: 16 14 18 12 «1 «1 9 8 7 6 5 4 3 24 0 BASE+s20[ command address not used Register Description Name Value Description: ‘command #101 ‘Write the following data bits 15-13, ‘address oe “akress 010 63 (dee) bits 12.7 ‘not used Free bits 6-0 Second value write: After a write command, it must be determined using the status bit EOS, when the next write access can take place Nop 4 2 Oe 6 6 ee 8 2 io BASE+$20: write data ‘After the data has been transferred, the start ofthe program can be determined with the status register's EOC flag. The PB-ADC3/EEPROM can only be accessed again after the EOC flag has reverted to O and a programming time of atleast Sms has passed. Example wait: btst.b #2, BASE+$31 EO: bres wait, move.w #$B000,BASE+$20 write command to first user location wait2: best.b #2, BASE+$31 EK bne.s — wait2 move.w #81234, BASE+$20 program $1234 wait3: best-b #4, BASE+$31 EOS? bne.s waits then wait at least Sms Mar, 1594 ‘© 1594 PEP Modular Computers PagesChapter 4 Programming PB-ADC3 User's Manual Issue 2 Note Due to the fact that the EEPROM contains calibration data programmed by PEP, it is not recommended that data be writen to the EEPROM, even in free locations. 4.14 Status Register ($31) “The status register an be read and written 1o in byte access. This returns four pieces of information; EOC/EOS (End Of Conversion/End Of Shift) INT and TNTENA. 7 6 5 4 3 2 1 ° BASEs$31 not used EOCIEOS| INT _| INTENA Register Description Name ‘Value | Description Aecess ot used 1 | Basic setting bits 7-3 EOC/EOS © | Endof conversion (default) End of shift default) | *Read only bit 2 1__| Conversion active Shift busy INT 0 | PB-ADC3 IRQ line active "Read only bit L 1__| NoPB-ADC3 IRQ INTENA 0 | RRQ disabled ReallWrite bit 1__| mG enabied “ * a write access to this bit has no influence Interrupt Handling ‘The interrupt is activated as soon as “I” is set on the INTENA bit or, in other words, if the EOC flag is routine staris immediately. the IRQ If conversion was stated immediately before setting an INTENA bit, the EOC flag will already be “1” and the first IRQ will ocour after the end of the BOC. ‘Taking away an JNT'signal a the end of an IRQ routine is possible by starting the next conversion or INTENA bit clear. Note Ie using interrupts, the IRQ vector is set on the VMOD-2 or IMOD, 4.1.5 ID Register ($7 ‘This register contains the ID byte, allowing automatic recognition ofthe piggyback fitted to the VMOD-2 or IMOD. This feature is particulary useful ina system with several piggybacks fitted. The ID byt is read using a byte read access. PB-ADC3 ID byte =SEB For more information on the ID byte, please see the ID Byte section in the Functional Description chapter. Pogeae © 1994 PEP Modular Computers Mar3, 1994PB-ADC3 User’s Manual Issue 2 42 Analog In order to calculate the accurate result from the actual value, the following formula is used (see also the Functional Input Correction Description chapter in this manual): Chapter 4 Programming Corrected Value = (Actual Value - Offset Value) * (1 + €) * ILSB where: = Gain Error/ (Full Range - Gain Error) ‘The values of the above parameters are extracted from the EEPROM (described in the next Section) and are shown in the following Tables for the available voltage and current ranges. Table 4.2.0.1: SV Range Parameters \ Conversion | Parameter | Unipolar [Bipolar ‘Actual Value [0 - SFRF $800 - 0-507 ‘Ofiset Value —| Offset EEPROM Offset EEPROM /2 LSB SV 7/4096 = 122m TOV 74096 = 2.44mV € ‘SV range gain error / (GV range gain error / (SEFF- 5V range gain error) (SFEF - 5V range gain error))/2 Table 4.2.0.2: 10V Range Parameters | Conversion ' Parameter —| Unipolar Bipot ‘Actual Value —[0 = SERF F800 - 0- S07, ' ‘Offset Value | Offset BEFROM ‘Offeet EEPROM /2 | TSB IOV /4096 = 24am 20V 71096 = 48m i © TOV range pun ero ‘GOV range gun eror 7 (SFFF -10V range gain ero) (SPFF - 10V range gain enon I Table 4.2.0.3: 20mA Range Parameters } Conversion: | Parameter | Unipolar Bipolar | ‘Actual Value 0 - SEF SP800 - 0- STF, ‘Offset Value | Offset EEPROM ‘Offset EEPROM 12 LSB 2OmA / 4096 = 4.88nA 40mA 14096 = 9:76 WA € 20mA range gain error / (QOmA range gain eror / {SFFF - 20mA range gain error) (SFFF - 20mA range gain error)V/2 See Appendix A.2 for a programming example using optimized INTEGER ARITHMETIC. Feb 16, 1994 ‘© 1994 PEP Modular Computers ts Jumper BSI default seChapter 4 Programming 4.3 EEPROM Data Structure ‘The EEPROM 93C46 provides a 64-word address, word access, permanently programmable memory. The address assignments to the individual analog outpots are shown below. Note thatthe address counter of the Table is word. PB-ADC3 User's Manual Issue 2 orientated Address 15 14 19 120 «1110 8 eG fs $0 ‘additional offset for unipolar mode channel offset st 10V range gain error (reserved) ‘BV range (20mA range) gain error $2 ‘additional offset for unipolar mode ‘channel offset $3 40V range gain error (reserved) ‘BV range (20mA range} gain error se ‘additional offset for unipolar mode. channel offset SF 10V range gain error (reserved) ‘BV range (20mA range) gain error $10 7 user $F "Read command for accessing an EEPROM address: EEPROM Read Command = $C000 + (Address <<7): channel 0 channel 1 channel 7 Page 4-8 © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Chapter 4 Programming EEPROM Description Tame Value] Bescripiton ‘additional | Typ. 6 | A byte value of the offset whon offset voliage s selected offset for on jumper BSI (position 1-2); unipolar measured in 5V unipolar range mode Example bits 15.8 $06 = 6LSB: (TSB =1.22mV) ‘channel OJ Channet 0 bits 7-4 1 | Channel 1 2 | Channel 2 3 | Chanel 4 | Channel 5 | Channel 6 | Channet 6 1__| Channel 7 offset Typ. 0 | A signed nibble vas of te ofset when the alciional bis 3-0 ‘offset voliage isnot selected on jumper B51 (position 1- 3); unipolar measured in SV range Example $0= OLSB; (1188 = 1.22nV) TOV range | Typ $10 | A byte value for the gain difference ofthe full voliage gain error value; unipolar measured. Not signticant forthe 20mA, bits 15.8 input version. Example Contents = $11 -> At $FFF- $11 = SFEE fullwoltage for unipolar voltage measurement 10V - 1LSB ‘BV range | Typ. $20 | A byte value forthe gain ciferense of the full volage, or gain error current, value; unipolar measured its 7-0 Example Contents = $23 -> At SFFF - $23 = SFDC fall voltage for unipolar voltage measurement SV - 1LSB (foc unipolar measurement ofthe curent 20mA - ILSB) wer 48 words fee for user-specific data. bits 15-0, Note |Care must be taken when editing the EEPROM. PEP accepts no responsibility forthe erasure of [calibration data. Feb 16, 1994 © 1994 PEP Modular Computers Page #3Chapter 4 Programming PB-ADC3 User's Manual Issue 2 This page has been intentionally let blank Page 410 © 1994 PEP Modular Computers Feb 16, 1998PB-ADC3 User’s Manual Issue 2 Chapter 5 Pinouts -_ ea) 5. PINoUTS ‘The PB-ADC3 has three sets of connectors. ST100 is the rearmost row of 15 pins directly next to ST101 with 30 pins. ‘ALthe front end of the piggyback there is ST102 with 26 pins 5.1 Main Board Figure 5.1.0.1: Board Connector Overview Pint Pit sTi00 Pints S11 ST100 Connector ‘The ST100 connector is fitted into the socket row BUOA or BUOB on the IMOD and VMOD-2, depending if there is one ‘or two pigaybacks to be fited. Fin # Signal ‘GND. NIC NIC NG NC. Wwsi* IDs IDié DB D2 m1 Dit 2 DIO 3 1Doo 14 Dos 15 GND) Active Signal Low Feb 16, 1994 ‘©1994 PEP Modular Computers Page 51Chapter 5 Pinouts PB-ADC3 User’s Manual Issue 2 S12 ST101 Connector ‘The ST101 connector is fited into the socket row BULA or BULB on the IMOD and VMOD-2 (depending if there is one cr two piggybacks to be fitted) to the VMEbus interface logic. (Ping Signal Pint_|_Sigaat i ‘GND, 2 VCC. 3 NIC. 4 NIC 3 RAW 6 CLE 7 RESET 3 UDTACKY 3 INTA® 10 cst it INT™ 12 NIG B D7 1s so 15 D6 16 NC 7 TDs 18 TAS, 19 1D 20 TAS 21 13 2. TA 23 12 24 NC 25 TDL 26 NIC 27 100, 28. NIC 29) GND, 30 WCC * Active Signal Low 5.3. STL02 Connector ‘The ST102 connector is fitted into the socket row BU2A or BU2B on the IMOD and VMOD-2 (depending if there is one ‘or two piggybacks to be fitted), directly to half of the 50-way VMOD-2 front panel connector, and ultimately to the ‘user's external interfaces. Page 52 © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 5.2. VMOD-2/IMOD Front Panel Figure 5.2.0.1: VMOD-2/IMOD Front Panel Even Pins Pinso —__| Pin2 (dd Pins | _ pinag Pint Chapter 5 Pinouts Piggyback A gna Fin AG) aw 6 GND. a7 ‘GND. AIG) BIG AN) 43 Q ‘GND a1 GND) ABCs) 39 BQ Ade) 37 BAC ‘GND, 35 GND, 36 ASG) 33 BS) 32 AGC) 31 Bo) 30 ‘GND, 29 GND 28 AIG) 27 BIC) Ext Ri Piggyback B in F Pin Signal 24 23 0 2 ‘GND 21 GND) 20 v BIC) 18 +) a7 A 16, ‘GND. 15 GND) is FICS 13 BAC) 2 Ad) O 10. ‘GND ND) 3 ASCH) 6 AGC) B60) 4 ‘GND GND) 2 ATG) Feb 16, 1994 © 1994 PEP Moduler Computers Page 53Chapter 5 Pinouts PB-ADC3 User's Manual Issue 2 ‘The relevant half of the VMOD-2 and IMOD front pane! 50-way connector (pins 1..24 for lower position and pins 27.50 for upper) assumes the relationship of PB-ADC3 signals and its ST1O2. An optional 50-way header behind the front panel connector has an identical pin-out to the front panel connector. [tis provided for applications where the flat band cable isto be routed internally, or where an alternative front panel isto be fitted and used. In some cases, cables can be touted through the systemss interior i. tothe back panel (from this optional connector) and some from the external connector on the front panel. In doing so take care not to exceed the fan out ability of the piggyback’s driver circuits, Note With systems that have more than one of this type of connector or which use several VMOD-2 or [IMODs with various piggybacks, itis advisable to put a drop of paint on the back of the mating. {connector and on the front pane! of the VMOD-2 or IMOD, for correct connection. The connector splits virtually in half (pins 1-24 and 27-$0) for connection to the rear piggyback location, Pages © 1994 PEP Modular Computers Feb 16, 1958PB-ADC3 User’s Manual Issue 2 Chapter 5 Pinouts 5.3. VMOD-2D Front Panel Figure 5.3, YMOD-2D Front Panel | Pina7 t Pina Pin34 vwop-20] L@_| Piggyback A Fin # Signal 50 AO) 49 ‘GND TANG 48 Ach BY, a7 GND. i) 46 AAG) BAC) 45 ‘GND ASG 44 AGC) BOL) a3 ‘GND. ATG) (Tr ee GND [oT Ft Reset Vee] Piggyback B Prt a 40, 39 38 37 36 35 34 Feb 16, 1994 ‘© 1954 PEP Modular Computers Page 55Chapter 5 Pinouts PB-ADC3 User’s Manual Issue 2 5.4 VMOD-2 / VMOD-2D Pinout Relationship Piggyback A Signal | VMOD-2 | VMOD-20 | Signal | VMOD-2 | VMOD-2D Pin # Pin # Pin # in # HOG) 50 50 BOQ) Ec) 17 ‘GND a8 33 GND) 47 9 AIG) 46, 16 BIO) 45 32 AZ) 4 48 BG) 43 13 ‘GND 2 3 GND) 41 47 AS) 40. 14 BQ 30 30 ASG) 38, 46 Bac) 37 3 ‘GND 36 29 GND) 35 45 ASCs) 34 12 BS) 33 28 AGS) 32 44 BEC) 31 it ‘GND 30. 27 GND) Fa a ATG) 28. 10, BI) 27 26 ‘Signal VMOD-2_|-VMOD-20 | Signal VMOD-2_| VMOD-2D Pin Pin # Pin # Pin # Ext, Reset GND 26 2 xt Reset Vee 25 9 Piggyback B Signal | VMOD-2_] VMOD-2D | Signal | VMOD-2_] VMOD-2D Pin # Pin # Pin # Pin # ADC) 24 25, 2 at ‘GND, 22 8 21 24 ALG) 20 40 19 7 7 ADC) 1B 23 7 39 ‘GND, 16. 6 15 22 ABH) 4 38 3B 3 AMCe) 12 21 i 37 GND. 10. 4 20 ASH 8 36 3 AGC) 6 19 35 ‘GND 4 2 18 ATG) 2 34 i Page 56 © 1594 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Chapter 6 Installation 6 6. INSTALLATION 6.1 VMEbus Connection Caution! Before installing or removing any VMEbus boards, always tur off the power to the bus and any ‘external peripherals. Inserting or removing. modules, while the power is on, could result in damage to the VME module or herals interface. Please refer to VMOD-2/IMOD user's manual for details on installing or removing. Figure 6.1.0.1: The VMEbus Backplane CRON Bas TACK For Slot | CPU board used as system controller, remove BG3* and IACK* Jumpers For empty siots or non-daisy-chained ‘VME carts, close all jumpers For anlary CPU boards (rom slot 210») Ismay So ante SESSA RE pe For VME cards with daisy-chain interrupt logic on-board, remove IACK® jumper eg VMOD-2 + PB-ADC3 Feb 16, 1954 © 1994 PEP Modular Computers Page G1Chapter 6 Installation PB-ADC3 User’s Manual Issue 2 6.2 Installing the PB-ADC3 ‘The PB-ADC3 may be plugged into any free piggyback position (A or B) on the VMOD-2 or IMOD. Please ensure the correct location before fitting. Note |, One connector on the PB-ADC3 has fewer pins than the other. I2. ST101 has two-rows which are to ft the front two-rows of the VMOD-2 amd IMOD three-row interface socket. Take care to ensue that the piggyback isin its correct position, Optional ‘on-board O-way Header be vMoD-2's VMEbus Connector (96-Way ) 87102 Short puloi tong Connector ae : Connector (26-Way) (30-Way) Mechanical fastening and support is provided by the two interface connectors. In addition, the piggyback can be attached to the motherboard by screws and stand-off pillars atthe front end of the piggyback, and atthe corresponding location on the VMOD-2 and IMOD at the two hotes provided for this purpose. Page 62 © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User's Manual Issue 2 Chapter 6 Installation 6.3 General Notes for Using the System Having designed a system, when: is necessary to keep it in good working order. The three biggest risks to the system occur + Connecting peripherals, disk-drives, printers, terminals and external power sources; + Adding or changing modules, address settings and locations, ete; + Becoming complacent and not referring to the manuals when altering or adding modules. ‘These risks can be reduced by: + Checking the electrical compatibility ofall devices tobe connected: ‘+ Ensuring that they are powered from the same mains supply branch (phase) and grounded to the same reference point; + Shutting down all power before making or breaking any connections to modules or attachments to the system, including power to the peripherals; + Observing sensible static protection procedures before handling any modules, piggybacks or memory IC's; + Keeping all manuals available by the system and refer to them when requ Some tps are PEPCards arc not over sensitive to stati, but itis generally advisable o observe normal antisatic procedures When configuring the module it should not be taken out ofthe orginal packing unless necessary. The clear packs can be pene nh jumpers set, pigaytcks ded, wibou removing card This reves gave sotg of any ‘When inserting modules into a system, the power should be turned off and the mains lead not removed! The ground wire prevents the rack floating with dangerous static voltages, which could destroy circuits on the module being inserted ‘The front panel of the module and the shell of the connector should be touched to any part of the rack before fitting, This discharges any static from the user. ‘Modules should not be pulled straight out ofa rack and the back of the front panel checked to see if there are cables to ‘unplug. (uch asthe VSBC-1's40-pin parallel on-board headers). Any leads shouldbe disconnected from a module before "unscrewing the front panel and removing from the rack. It should be ensured that, when fitted, these cables have enough play to allow the modules to be removed far enough i detach these cables. Modules should be put into the rack before connecting any font-panel connectors ‘The "puied” jumpers shouldbe parked on to one of the pins they would normally bridge, so they can be quickly replaced. Ie should be remembered to check the mains inpot voltage selector switch before installing or using eny PSUL Arecond should be kept of settings and a copy forwarded with any board returned to PEP for failure analysis. Feb 16, 1994 © 1994 PEP Modular Computers Page 63Chapter 6 Installation PB-ADC3 User’s Manual Issue 2 This page has been intentionally left blank Page 6-4 © 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Appendix A Complex Examples ra APPENDIX A. COMPLEX EXAMPLES A.l Read Channels ‘The following program is for « continuous read of all 8 channels Al C-Progeam Listing #include finclude nelude #include [Medan eatenennaneneanmentane * Address Offset Table ent aiennernneeeaa iene #define UTC #derine EEPROM #define EEP_PROC #define STATUS Weezine ID [tttenenenetesees * definitions seeseuvetennensen) ¥define READY #éefine PBADC3_ID fdefine UNI 7 fdefine BrP define LsB define LSBBip define LSBLOvBip define LSBSVBip LsB10vUn: LSBSVUni, static unsigned char *babas: static unsigned short *wabase=0x87fe2400; (0x00 >>1 /* word read/write */ f pel} /* word read/write */ (0x20 >>2 /* word write */ x34 7* byte read/write */ OxTE /* byte read */ oxfa /* STATUS register READY check */ OxEB /* PB-ADC3 identification byte */ ox19 /* to add to code-word for unipolar conversion 0x00 /* to add to code-word for bipolar conversion */ 0.00122 0.00244 LSBBip*2 LSBBip usBuni*2 ESBUni 0x87f62400; /* default base address of vwoD-2 */ Feb 16, 1994 © 1994 PEP Modular Computers Page ATAppendix A Complex Examples PB-ADC3 User’s Manual Issue 2 short Channel{ J oxcf + Bip, /* channel 0 */ Oxed + Bip, /* channel 1 */ oxe7 + Bip, /* channel 2 */ Oxe5 + Bip, /* channel 3 */ oxeb + Bip, /* channel 4 */ oxcd + Bip, /* channel 5 */ 0x3 + Bip, /* channel 6 */ Oxel + Bip, /* channel 7 */ Oxct + Bip /* again channel 0 for the read out loop */ h float chan_LsB[ LSBi0VBip, /* channel 0 LSB definition */ LS810VBip, /* channel 1 LSB definition */ LSB10VBip, 7* channel 2 LSB definition */ LSB10VBip, /* channel 3 LSB definition */ LSB10VBip, 7* channel 4 LSB definition */ LSBLOVBip, 7* channel 5 LSB definition */ LsB10VBip, /* channel 6 LSB definition */ LSB1OVBip, 7* channel 7 LSB definition */ ESBLOVBip ¢* channel 0 LSB definition */ = PB-ADC3 Functions —* seanneuasentneneeuenen/ ADC_eheck() i For (count=0;count<100; count ++) ‘ status=* (babase+STATUS) ; /* check if BOC or shift is ready */ if ((status&Oxff) ==READY) > 3 ADC_convert (channel ,mode} short channel; 7* Channel number 0-7 */ char mode; /* Unipolar = 'U'; Bipolar = '°B'; */ c short adcconv; adeconv=code [channel] ; Af (mode=='U') adeconveadecony|Ox2 ADC_eheck(); * (ad¢_wabase+LTC) sadccony; Page AD © 1954 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Appendix A Complex Examples [ettneeneeeaees * Main Program * pevecvevenesiney, short value, bipvalue,univalue; Af (* (babase+ID) !=PBADC3_ID) /* PB-ADC3 ID Check */ printf (*\nError: Wrong PB-ADC3 ID found! Correct one is SEB!\: print£(* Read: $8x\n\n",*(babase+1D)); exit (0); ush (stdout) ; printf ("Select HEX/Voltage? (H/V): "); fi scant chr = toupper (chr); while for (n=0jn=0)print£(*+82.5£V", voltage); eloe printf (*#2.5£%v", voltage) ; Af (ne?) printe(* "); break; ANN); printf (*\nGood bye! Please try aga: break; ) printf(\n"); /* program end */ Feb 16, 1954 ‘© 1594 PEP Modular Computers Page ASAppendix A Complex Examples A.L2 Assembler Program PB-ADC3 User's Manual Issue 2 * endless loop example for read out channel 0 BASE equ $£02400 base address VMoD2 default ure equ $00 LTC communication register STATUS equ $31 status register offset CHAN = equ Sct channel 0 bipolar conversion code start: empi-b #$fa, BASESSTATUS ft register ready 7 bne.s start no, wait move.w ‘CHANO, BASELTC rt first conversion channel 0 eoc: cmpi.b #$fa,PASBYSTATUS end of conversion ? ne eoc no, wait loop: move.w ACHANO, BASEVLTC cart next conversion channel 0 data: empi-b #$fa,BASE+STATUS end of conversion and previous data ready? bne.s gata no, wait move.w BASEVLTC,d0 get previous conversion result bra.s loop loop back to next conversion + end of file Page Ad ‘© 1954 PEP Modular Computers Feb 16, 1994PB-ADC3 User's Manual Issue 2 Appendix A Complex Examples A.2. Converted Data Correction ‘define FOCLRFADY OxFA_—/* STATUS register ready check */ define NOT_E0C ox04 /* STATUS register ready check */ #define EEWRITE_CMD xA000 /* Command to write a value to an address */ #define xc00d /* Command to read a value from an address */ Faerine 0x9800/* Command to read a value from an address */ EE DISA_CMD 0x8000 /* Command to read a value from an address */ STATUS_BOC 0x4 /* BOC bit O=finished 1=conversion */ STATUSLINT 0x2 ‘Pending Interrupt bit O-active isinactive */ STATUS_INTENA 0x1 /* Interrupt enabled b: lisabled 1-enabled */ DISABLE Oxi /* Disable Interrupts */ csuer 19 /* Shift to get higher accuraccy */ UNIPOLAR oxt9 BIPOLAR x00 SINGLE_ENDED —OxC0 J” special register of piggy back ... */ define PB_ID (base) 0) 40x7£}) /* piggy back id adrs */ /* .., and its possible correct contains */ ‘define ID_ADC3 ox /* register definitions */ ‘define ADC3_COMM{base) —__( (INT16*) ((base)+0x00)) /* communication reg */ define ADC3_EZE_COMM(base) ((UINT16*) ({base)+(0xi0>>1))) /* EEPROM comm reg */ #define ADC3_BE_PROG(base) ((UINT16*} ({base)+(0x20>>1))) /* EEPROM program reg */ define ADC3_STATUS(base) ((UINTE*) ((base)+0x31)) /* Status Register */ typedef stru /* Calibration Data structure */ € UINTE extoffeets INTE channel UINTS stdoffsets UINT2 caliblo UINTa calibs; CALIB_DATA; typedef struct (* ape3_pEV */ 4 DEV_HDR ioDews int chan; /* channel number */ BOOL created; (7 true if this device has really been created */ UINTLS *pb_base; /* base address of the piggy back */ SEMID login; /* login flag */ BOOL calibration; —/* correct converted data with calibration (Gefault true) */ BOOL —offaettype; /* correct converted data with offeet (default false) */ BOOL —_voltagel0; /* What voltage is set (default 10 v) */ CALIB_DATA calibData[8];/* calibration data copy */ INT32 calArrBil0V(8]; /* calibration data for channels */ INT32 calarrUni10V(8]; /* calibration data for channele */ mnT32 calarrsisvi8]; /* calibration data for channels */ myr32_ calarruni5v(8]; /* calibration data for channels */ INT16 offArrBil0v(@]; /* calibration data for channels */ Feb 16, 1994 © 1994 PEP Modular Computers Page ASAppendix A Complex Examples PB-ADC3 User’s Manual Issue 2 1ov(8]; /* calibration data for channels */ INTI6 offArrti INTI6 offArrBiSV(8]; —/* calibration data for channels */ INTI6 offArrUnisV[8]; /* calibration data for channels */ } ADC3_DEN LOCAL ADC3_DEV adc3Dv [] = /* device descriptors */ i /* WMOD_O PBA */ ({QNULL}), 0, FALSE, (UINTLE *) (ADR_VMOD_0+ADR_PB_A), FALSE, TRUE, TRUE, TRUE}, 7* vwoD_0 PRB Y/ {{(NULE)}, 1, FALSE, (GINTI6 *) (ADR_VMOD_O+ADR_PR_B), FALSE, TRUE, TRUE, TRUE}, /* VMOD_L PBA */ {{(NULL}}, 2, FALSE, (UINTI6 *) (ADR_VMOD_1+ADR_PRLA), FALSE, TRUE, TRU! TRUE}, + VMOD_L PBB */ {(OWULL}}, 3, FALSE, TRUE}, (oInTié +ADR_PB_B), FALSE, TRUE, TRUE /* VMOD_2 PBLA */ {{(NULLD], 4) FALSE, (UINT26 *) (ADR_VMOD_2+ADR_PBLA}, TRUE}, TRUE, TRUE, s+ VMOD_2 PBB */ {((NULL}}, 9, FALSE, (UINTL6 *) (ADR_VMOD_2+8DR_PBLB}, FALSE, TRUE, TRUE, TRUE}, J+ vYoD_3 PBA */ {{INULL]}, 6, FALSE, (UINTI6 +) (ADR_VMOD_3+ADR_PBLA), FALSE, TRUE, TRUE, TRUE), (+ ywon_3 PBB */ (OONULL)}, 7, FALSE, (UINTLS *) (ADR_VMOD_3+ADR_PB_B), FAL: TRUE}, TRUE, TRUE, /* VMOD_A PBA */ {{{NULL}), 8, FALSE, (UINTL6 *) (ADRVMOD_4+ADR_PBLA), FALSE, TRUE, TRUE, /* vuoD_4 (C{NULL)}, 9, FALSE, (UINT16 *) (ADR_vwOD_4+ADR_PS_B), TRUE), ‘TRUE, 7+ VMoD_S PBA */ (((NULL}), 10, FALSE, (UINTIG *) (ADR_VMOD_S+ADR_PB_A), FALSE, TRUE, TRUE, TRUE), 7+ yMOD_S PBB */ ({(NOLL)}, 11, FALSE, (UINTLE *) (ADR_VMOD_5+ADR_PB_B), FALSE, TRUE, TRUE, TRUE) Page AS ‘© 1994 PEP Modular Computers Feb 16, 1994PB-ADC3 User’s Manual Issue 2 Appendix A Complex Examples eeTETTLeSTTECeLTETECeTteet est tereecerec erst tcecer cet eetet eT ewer eeeereewery’ * eerromRead - read deta from FEPROM at specified address LOCAL STATUS eePromRead(base, address, ve UINTIS *base; DINTIS address; DINTIE *value; G STATUS status; *(APC3_BR_COMY (base)} = {(UINT16) 3E_READ_CND) | (address<<7); ade3check (base) + fvalue = *(ADC3_2 com (base); status = ade3Check (base) ; wait Or return (status); ) EEE ERE EEO HORI U HO ESU HORA UR Uae anne eR * gotEBdata - copy default EEPROM data into RAM * worD 0 | * WoRD 1 | cal. Data 10V | cal. Data SV | a7 Offset Ichannellstd.or£} es ta (base, data) LOCAL STATUS get UINTI6 base; CALTS_DATA datal]; ADUS atatue; UINTIS value: for (chans0; chan<®; chan++) ‘ if ((status = eePromRead (base, chan*2, ivalue}) return (status); Gata{chan] .ext0ffset = value >> 8; data[chan] .std0ffset = value & Ox0F; data(chan].channel = (value & OxF0) >> 4; ox) if ((status = eePromRead (base, chant2+1, &value)) return (status); data[chan].calibi0 = value >> 8; Gataichan].calib5 = value & OxFF; ) ox) return (OX); 3 Feb 16, 1984 © 1594 PEP Modular Computers PagoA7Appendix A Complex Examples PB-ADC3 User’s Manual Issue 2 with calibration date * correct - corrects converted dat ” LOCAL INTI6 correct (pAdc3Dv, value, polarity, channel) ADC3_DEV *pade3Dv; HNTI6 value; UINTS polarity: UINTS channel; ‘ if (pAde3Dv->calibration) if (pAde3Dv-svoltagel9) if (polarity == UNIPOLAR) return ((INTI6) ( (INT32) ( ( (INT32) value << C_SHIFT) + value * pAde3Dv->calArrtni10V[channel]) >> C_SHIFT) - pAdo3Dv->of fArrtini1ov{channel}} © return (CINTI6) ( (TNT32) ( ( (INT32) value << C_SHIFT) + value * pAdc3Dv->calArrBil0V[channel]} >> C_SHIPT) - padc3Dv->of fArrBi10V [channel] ); a else if (polarity ©= UNIPOLAR) return ({INTI6) ( (INT32) ( ( (INT32) value << C_SHIPT) + value * pAde3Dv-scalArrUni$v(channel]) >> C_SHIFT) - pAdc3Dv->0f fArrUni Sv(channel]); return ((INTL6) ( (INT32) { ( (INT32) value << C_SHIPT) value * pAde3Dv->calArrBiSV(channel]} >> C_SHIFT) ~ pAde3v-s0f farrsiSv(channel}} else return (value); ? t > setarrays - set calibration arrays from calibration date ” LOCAL STATUS setArrays (pAdc3Dv) ADC3_DEV *pade3Dv; ( INTI6 chan; INF32 value; INT@ offset; Page AS © 1994 PEP Modular Computers Feb 16, 1954PB-ADC3 User’s Manual Issue 2 Appendix A Complex Examples for (cha: chan++) value = (INT32) pAde3Dv->calibpata [chan] .calibl0; pAdc3Dv->calArzUnii0V [chan] = (2932) ({value << C_SHIPT) / ((INTL6) Ox0FFF - (INTI6)value)); pAdc3Dv->calArrBi10V [chan] PAdc3Dv->calarrUni10V [chan] + pAdc3Dv->calArrni10v [ch value = (INT32) pade3nv->calibData [chan] .calibs pade3py->calArrunisv [chan] INT32) ({value << C_SHIFT) / ((INTL6) OxOFPF - pAdc3Dv->calArzBiSV [chan] pAdC3Dv->calArrUniSV [chan] + pAdc3Dv->calArrUniSV [chan]; 7 hanes. nds INT16) value) }s Af (pAdc3Dv-soffsetType} offset - phdc3Dv->calibData [chan] .stdoffset offset = pAdc3Dv->calibbata [chan] -extoz Eset pAde3Dv-soffArrUniSV [chan] = offset; PAdc3Dv->offArrBi5V [chan] = (offset + 1) >> 1; ¢* round (x/2) */ PAdc3Dv->offArrUnil0V [chan] = (offset + 1) >> 1; /# round (x/2) */ pAdc3Dv-soffArrBii0V [chan] = (offset + 2) >> 2; /* round (x/4) */ ) return (OK); } main 0) ¢ ADC3_DEV *pade3Dv; int i; INT16 “buffer, buf[10), value, address; UINT@ chan, channel; GINTIE mode; UINT32 repeater; pAde3Dv = gade3Dv[0] /* copy default EEPROM data into RAM */ Af (getERdata (ade3Dv [channel] .pb_base, sadc3Dv[0] .calibnata) return (ERROR) buffer = but; chan = 0; channel = channels {chan}; mode = (JINTI6) (UNIPOLAR | channel); repeater = 10; Feb 16, 1994 © 1994 PEP Modular Computers Page ADAppendix A Complex Examples PB-ADC3 User’s Manual Issue 2 ; icsrepeater; i++) (* repeat + 1 conversions */ ( /* to get 10 values */ pAdc3Dv-spb_base, mode) ; value = adc3Read (pAde3Dv->pb_base) ; (value == (INT16) 0xF000) return (ERROR); ) Ybuffer++ = correct (pAdc3Dv, value, UNIPOLAR, ) else status = adc3Check (pAde3Dv->pb_base) : } Page Ao © 1994 PEP Modular Computers Feb 16, 1994Ics 1c54 €F ‘ Ri1]R27] R12]R28)R44| [Rea] '4HCT399] oc/oc 2630 ICS Ics2 Ics R13/R29/R45/[REi| 1 4|/R30[R46|(Rae) RiS|R31 R Ri6/R32| R17/R33/R49)(R65)| R18/R34/R5e/(Roa| LT1014 1c64 ST1e@, ST101 22v1e Ltc1298 2630 IC56 R19/R35} Ree] R36] R21/R37| Re2IR38} Ub B-Seite / B-side Rea|R39| Ic62 Re4lR4G| 2ev1e 1C53 re} Ics? 2632 1C6@ \7 TRABTRAS [RA4 [RASTRAZ TRAIT RAO LT 1014 ReS|Ra1: ReBLR42| ca7[caé [cas] cas] CA] Caz] Cai] CAO] REF 192 ORIGINAL ] >) PB- "ADC 3 [FED te [Pace 02.07 1996 j Modular Computer's |~—— Vor? Page4 anduog ze Tnpox | sz0 WNIDIHO L-Seite / L-side ER BE EERE Siig] 3/8/alz1a13/3]s]8131213) 3) BEELER EEEER Ge) oe er GB d Bisa , a & GE a) IC65 1064 Go C6. 74HCT299|~| 74HCT299 gf a | Cex) &ORIGINALWNIDIHO 7 = fe een