Computing Ds 4Gb DDR3L (A-Ver) Based VLP RDIMMs (Rev.1.1)

240pin DDR3L SDRAM VLP Registered DIMM
DDR3L SDRAM VLP

Registered DIMM
Based on 4Gb A-die
HMT451V7AFR8A
HMT41GV7AFR4A
HMT41GV7AFR8A
HMT82GV7AMR4A
HMTA4GV7AHR4A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.1 / Mar. 2014 1

Revision History
Revision No. History Draft Date Remark
1.0 Initial Release May.2013
1.1 module line-up arranged Mar.2014

(added 4Rx4, removed 4Rx8)
Rev. 1.1 / Mar. 2014 2

Description
SK hynix VLP (Very Low Profile) registered DDR3L SDRAM DIMMs (Registered Double Data Rate Synchro-
nous DRAM Dual In-Line Memory Modules) are low power, high-speed operation memory modules that use
DDR3L SDRAM devices. These Registered SDRAM DIMMs are intended for use as main memory when
installed in systems such as servers and workstations.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)

• VDDQ = 1.35V (1.283V to 1.45V)
• VDDSPD=3.0V to 3.6V
• Backward Compatible with 1.5V DDR3 Memory Module
• 8 internal banks
• Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
Ordering Information
# of
Part Number Density Organization Component Composition FDHS
ranks
HMT451V7AFR8A-H9/PB/RD 4GB 512Mx72 512Mx8(H5TC4G83AFR)*9 1 X
HMT41GV7AFR4A-H9/PB/RD 8GB 1Gx72 1Gx4(H5TC4G43AFR)*18 1 X
HMT41GV7AFR8A-H9/PB/RD 8GB 1Gx72 512Mx8(H5TC4G83AFR)*18 2 X
HMT82GV7AMR4A-G7/H9/PB 16GB 2Gx72 DDP 2Gx4(H5TC8G43AMR)*18 2 O
HMTA4GV7AHR4A-G7/H9 32GB 4Gx72 QDP 4Gx4(H5TCAG43AHR)*18 4 O
* In order to uninstall FDHS, please contact sales administrator
Rev. 1.1 / Mar. 2014 3

Key Parameters
CAS
tCK tRCD tRP tRAS tRC
MT/s Grade Latency CL-tRCD-tRP
(ns) (ns) (ns) (ns) (ns)
(tCK)
DDR3L-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7
13.5 13.5 49.5

DDR3L-1333 -H9 1.5 9 36 9-9-9
(13.125)* (13.125)* (49.125)*
13.75 13.75 48.75

DDR3L-1600 -PB 1.25 11 35 11-11-11
(13.125)* (13.125)* (48.125)*
13.91 13.91 47.91

DDR3L-1866 -Rd 1.07 13 34 13-13-13
(13.125)* (13.125)* (48.125)*
*SK hynix DRAM devices support optional downbinning to CL 11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [Mbps]
Grade Remark
CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13
-G7 800 1066 1066
-H9 800 1066 1066 1333 1333
-PB 800 1066 1066 1333 1333 1600
-RD 800 1066 1066 1333 1333 1600 1866
Address Table
4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 32GB(4Rx4)
Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms
Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15
Column Address A0-A9 A0-A9, A11 A0-A9 A0-A9, A11 A0-A9, A11
Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2
Page Size 1KB 1KB 1KB 1KB 1KB
Rev. 1.1 / Mar. 2014 4

Pin Descriptions
Num Num
Pin Name Description Pin Name Description
ber ber
CK0 Clock Input, positive line 1 ODT[1:0] On Die Termination Inputs 2
CK0 Clock Input, negative line 1 DQ[63:0] Data Input/Output 64
CK1 Clock Input, positive line 1 CB[7:0] Data check bits Input/Output 8
CK1 Clock Input, negative line 1 DQS[8:0] Data strobes 9
CKE[1:0] Clock Enables 2 DQS[8:0] Data strobes, negative line 9
DM[8:0]/
Data Masks / Data strobes,
RAS Row Address Strobe 1 DQS[17:9], 9
Termination data strobes
TDQS[17:9]
DQS[17:9], Data strobes, negative line,
CAS Column Address Strobe 1 9
TDQS[17:9] Termination data strobes
Reserved for optional hardware
WE Write Enable 1 EVENT 1
temperature sensing
Memory bus test tool (Not Con-
S[3:0] Chip Selects 4 TEST 1
nected and Not Usable on DIMMs)
A[9:0],A11,
Address Inputs 14 RESET Register and SDRAM control pin 1
A[15:13]
A10/AP Address Input/Autoprecharge 1 VDD Power Supply 22
A12/BC Address Input/Burst chop 1 VSS Ground 59
BA[2:0] SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1

Serial Presence Detect (SPD)
SCL 1 VREFCA Reference Voltage for CA 1
Clock Input
SDA SPD Data Input/Output 1 VTT Termination Voltage 4
SA[2:0] SPD Address Inputs 3 VDDSPD SPD Power 1

Parity bit for the Address and
Par_In 1
Control bus
Parity error found on the
Err_Out 1
Address and Control bus
Rev. 1.1 / Mar. 2014 5

Input/Output Functional Descriptions
Symbol Type Polarity Function
Positive Positive line of the differential pair of system clock inputs that drives input to the on-
CK0 IN
Line DIMM Clock Driver.
Negative Negative line of the differential pair of system clock inputs that drives the input to the
CK0 IN
Line on-DIMM Clock Driver.
Positive
CK1 IN Terminated but not used on RDIMMs.
Line
Negative
CK1 IN Terminated but not used on RDIMMs.
Line
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
Active buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
CKE[1:0] IN
High POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
Enables the command decoders for the associated rank of SDRAM when low and dis-
ables decoders when high. When decoders are disabled, new commands are ignored
Active and previous operations continue. Other combinations of these input signals perform
S[3:0] IN
Low unique functions, including disabling all outputs (except CKE and ODT) of the register(s)
on the DIMM or accessing internal control words in the register device(s). For modules
with two registers, S[3:2] operate similarly to S[1:0] for the second set of register out-
puts or register control words.
Active
ODT[1:0] IN On-Die Termination control signals
High
Active When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
RAS, CAS, WE IN
Low operation to be executed by the SDRAM.
VREFDQ Supply Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
VREFCA Supply
ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.

BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being
BA[2:0] IN —
applied. Bank address also determines mode register is to be accessed during an MRS
cycle.
Provided the row address for Active commands and the column address
and Auto Precharge bit for Read/Write commands to select one location out of the mem-
A[15:13, ory array in the respective bank. A10 is sampled during a Precharge command to deter-
12/BC,11, IN — mine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If
10/AP,[9:0] only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also pro-
vide the op-code during Mode Register Set commands.
DQ[63:0],
I/O — Data and Check Bit Input/Output pins
CB[7:0]
Active
DM[8:0] IN Masks write data when high, issued concurrently with input data.
High
VDD, VSS Supply Power and ground for the DDR SDRAM input buffers and core logic.
VTT Supply Termination Voltage for Address/Command/Control/Clock nets.
Rev. 1.1 / Mar. 2014 6

Symbol Type Polarity Function
Positive
DQS[17:0] I/O Positive line of the differential data strobe for input and output data.
Edge
Negative
DQS[17:0] I/O Negative line of the differential data strobe for input and output data.
Edge
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
TDQS[17:9] MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is
TDQS[17:9] OUT applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will
provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS
function via mode register A11=0 in MR1
These signals are tied at the system planar to either VSS or VDDSPD to configure the
SA[2:0] IN —
serial SPD EEPROM address range.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor
SDA I/O — must be connected from the SDA bus line to VDDSPD on the system planar to act as a
pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
SCL IN —
nected from the SCL bus time to VDDSPD on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing
OUT
device.The system should guarantee the electrical level requirement is met for the
EVENT (open Active Low
EVENT pin on TS/SPD part.
drain)
No pull-up resister is provided on DIMM.
VDDSPD Serial EEPROM positive power supply wired to a separate power pin at the connector
Supply
which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on
RESET IN
the DRAM.
Par_In IN Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even)
OUT Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out (open Err_Out bus line to VDD on the system planar to act as a pull up.
drain)
TEST Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 1.1 / Mar. 2014 7

Pin Assignments
Front Side Back Side Front Side Back Side
Pin # Pin # Pin # Pin #
(left 1–60) (right 121–180) (left 61–120) (right 181–240)
1 VREFDQ 121 VSS 61 A2 181 A1
2 VSS 122 DQ4 62 VDD 182 VDD
3 DQ0 123 DQ5 63 NC, CK1 183 VDD
4 DQ1 124 VSS 64 NC, CK1 184 CK0
DM0,DQS9,
5 VSS 125 65 VDD 185 CK0
TDQS9
NC,DQS9,
6 DQS0 126 66 VDD 186 VDD
TDQS9
7 DQS0 127 VSS 67 VREFCA 187 EVENT, NC
8 VSS 128 DQ6 68 Par_In, NC 188 A0
9 DQ2 129 DQ7 69 VDD 189 VDD
10 DQ3 130 VSS 70 A10 / AP 190 BA1
11 VSS 131 DQ12 71 BA0 191 VDD
12 DQ8 132 DQ13 72 VDD 192 RAS
13 DQ9 133 VSS 73 WE 193 S0
DM1,DQS10,
14 VSS 134 74 CAS 194 VDD
TDQS10
NC,DQS10,
15 DQS1 135 75 VDD 195 ODT0
TDQS10
16 DQS1 136 VSS 76 S1, NC 196 A13
17 VSS 137 DQ14 77 ODT1, NC 197 VDD
18 DQ10 138 DQ15 78 VDD 198 S3, NC
19 DQ11 139 VSS 79 S2, NC 199 VSS
20 VSS 140 DQ20 80 VSS 200 DQ36
21 DQ16 141 DQ21 81 DQ32 201 DQ37
22 DQ17 142 VSS 82 DQ33 202 VSS
DM2,DQS11, DM4,DQS13,
23 VSS 143 83 VSS 203
TDQS11 TDQS13
NC,DQS11, NC,DQS13,
24 DQS2 144 84 DQS4 204
TDQS11 TDQS13
25 DQS2 145 VSS 85 DQS4 205 VSS
26 VSS 146 DQ22 86 VSS 206 DQ38
27 DQ18 147 DQ23 87 DQ34 207 DQ39
28 DQ19 148 VSS 88 DQ35 208 VSS
29 VSS 149 DQ28 89 VSS 209 DQ44
30 DQ24 150 DQ29 90 DQ40 210 DQ45
31 DQ25 151 VSS 91 DQ41 211 VSS
NC = No Connect; RFU = Reserved Future Use
Rev. 1.1 / Mar. 2014 8

Front Side Back Side Front Side Back Side
Pin # Pin # Pin # Pin #
(left 1–60) (right 121–180) (left 61–120) (right 181–240)
DM3,DQS12, DM5,DQS14,
32 VSS 152 92 VSS 212
TDQS12 TDQS14
NC,DQS12, NC,DQS14,
33 DQS3 153 93 DQS5 213
TDQS12 TDQS14
34 DQS3 154 VSS 94 DQS5 214 VSS
35 VSS 155 DQ30 95 VSS 215 DQ46
36 DQ26 156 DQ31 96 DQ42 216 DQ47
37 DQ27 157 VSS 97 DQ43 217 VSS
38 VSS 158 CB4, NC 98 VSS 218 DQ52
39 CB0, NC 159 CB5, NC 99 DQ48 219 DQ53
40 CB1, NC 160 VSS 100 DQ49 220 VSS
NC,DM8,DQS17, DM6,DQS15,
41 VSS 161 101 VSS 221
TDQS17 TDQS15
NC,DQS17, NC,DQS15,
42 DQS8 162 102 DQS6 222
TDQS17 TDQS15
43 DQS8 163 VSS 103 DQS6 223 VSS
44 VSS 164 CB6, NC 104 VSS 224 DQ54
45 CB2, NC 165 CB7, NC 105 DQ50 225 DQ55
46 CB3, NC 166 VSS 106 DQ51 226 VSS
47 VSS 167 NC(TEST) 107 VSS 227 DQ60
48 VTT, NC 168 RESET 108 DQ56 228 DQ61
KEY KEY 109 DQ57 229 VSS
DM7,DQS16,
49 VTT, NC 169 CKE1, NC 110 VSS 230
TDQS16
NC,DQS16,
50 CKE0 170 VDD 111 DQS7 231
TDQS16
51 VDD 171 A15 112 DQS7 232 VSS
52 BA2 172 A14 113 VSS 233 DQ62
53 Err_Out, NC 173 VDD 114 DQ58 234 DQ63
54 VDD 174 A12 / BC 115 DQ59 235 VSS
55 A11 175 A9 116 VSS 236 VDDSPD
56 A7 176 VDD 117 SA0 237 SA1
57 VDD 177 A8 118 SCL 238 SDA
58 A5 178 A6 119 SA2 239 VSS
59 A4 179 VDD 120 VTT 240 VTT
60 VDD 180 A3
NC = No Connect; RFU = Reserved Future Use
Rev. 1.1 / Mar. 2014 9

Registering Clock Driver Specifications
Capacitance Values
Symbol Parameter Conditions Min Typ Max Unit
Input capacitance, Data inputs 1.5 - 2.5 pF

CI
Input capacitance, CK, CK, FBIN, FBIN
1.5 - 2.5 pF
(up to DDR3-1600)
Input capacitance, RESET, MIRROR,

CIR VI = VDD or GND; VDD = 1.5v - - 3 pF
QCSEN
Input & Output Timing Requirements
DDR3L-800
DDR3L-1600 DDR3L-1866
1066/1333
Symbol Parameter Conditions Unit
Min Max Min Max Min Max
Input clock fre- Application fre-

fclock 300 670 300 810 300 945 Mhz
quency quency
Input clock fre-

fTEST Test frequency 70 300 70 300 70 300 Mhz
quency
Input valid before

tSU Setup time 100 - 50 - 40 - ps
CK/CK
Input to remain
tH Hold time 175 - 125 - 75 - ps
valid after CK/CK
Propagation
tPDM delay, single-bit CK/CK to output 0.65 1.0 0.65 1.0 0.65 1.0 ns
switching
Output disable
Yn/Yn to output 0.5 + 0.5 + 0.5 +
tDIS time (1/2-Clock - - - ps
float tQSK1(min) tQSK1(min) tQSK1(min)
prelaunch)
Output enable
Output driving to 0.5 - 0.5 - 0.5 -
tEN time (1/2-Clock - - - ps
Yn/Yn tQSK1(max) tQSK1(max) tQSK1(max)
prelaunch)
Rev. 1.1 / Mar. 2014 10

On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal
sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
EVENT
SCL
SDA SA0
EVENT
SPD with SA1
SCL Integrated SA2
SA0 SDA TS
SA1
SA2
Temperature-to-Digital Conversion Performance
Parameter Condition Min Typ Max Unit
Active Range,
- ± 0.5 ± 1.0 °C
75°C < TA < 95°C
Temperature Sensor Accuracy (Grade B) Monitor Range,

- ± 1.0 ± 2.0 °C
40°C < TA < 125°C
-20°C < TA < 125°C - ± 2.0 ± 3.0 °C
Resolution 0.25 °C
Rev. 1.1 / Mar. 2014 11

Functional Block Diagram
4GB, 512Mx72 Module(1Rank of x8)
/BA[N:O]A
/BA[N:O]B
RCASA_n
RCASB_n
RRASA_n
RRASB_n
PCK0A_c
RWEA_n
PCK0B_c
RWEB_n
PCK0A_t
PCK0B_t
A[N:O]A
A[N:O]B
RODT0A
RODT0B
RCKE0A
RCKE0B
RS0A_n
RS0B_n
DQS8_t DQS_t ZQ DQS4_t DQS_t ZQ
DQS8_c DQS_c DQS4_c DQS_c
A[N:O]/BA[N:O]
A[O:N]/BA[O:N]
DM8/DQS17_t TDQS_t DM4/DQS13_t TDQS_t
DQS17_c TDQS_c D8 DQS13_c TDQS_c D4
CB[7:0] DQ [7:0] DQ[39:32] DQ [7:0]
RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
CK_n
CK_n
CS_n
CS_n
CK_t
CK_t
ODT
ODT
CKE
CKE
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]

DQ[31:24] DQ [7:0] DQ[47:40] DQ [7:0]
RAS_n
CAS_n
RAS_n
CAS_n
WE_n
WE_n
CK_n
CS_n
CK_n
CS_n
CK_t
CK_t
ODT
ODT
CKE
CKE

A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
DM2/DQS11_t TDQS_t DM6/DQS15-t TDQS_t

DQ[23:16] DQ [7:0] DQ[55:48] DQ [7:0]
RAS_n
CAS_n
RAS_n
CAS_n
WE_n
WE_n
CK_n
CK_n
CS_n
CS_n
CK_t
CK_t
ODT
ODT
CKE
CKE

VDDSPD SPD
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]

DQS10_c TDQS_c D1 DQS16_c TDQS_c D7 VDD D0–D8
DQ[15:8] DQ [7:0] DQ[63:56] DQ [7:0]
VTT
RAS_n
CAS_n
RAS_n
CAS_n
WE_n
WE_n
CK_n
CK_n
CS_n
CS_n
CK_t
CK_t
ODT
ODT
CKE
CKE
VREFCA D0–D8
VREFDQ D0–D8
Vtt
DQS0_t DQS_t ZQ
VSS D0–D8
DQS0_c DQS_c
A[N:O]/BA[N:O]
DM0/DQS9_t TDQS_t
DQS9_c TDQS_c D0
DQ[7:0] DQ [7:0] Note:
RAS_n
CAS_n
WE_n
1.DQ-to-I/O wiring may be changed within byte.

CK_n
CS_n
CK_t
ODT
CKE
2.ZQ resistors are 240 Ω ±1%.For all other resistor values refer to the
appropriate wiring diagram.
Vtt
S0_n RS0A_n → CS0_n: SDRAMs D[3:0], D8

S1_n RS0BCK_n → CS0_n: SDRAMs D[7:4]
BA[N:0]
1: RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8
2 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4]
A[N:0] R RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8
E RA[N:0]B → A[N:0]: SDRAMs D[7:4]
RAS_n RRASA_n → RAS_n: SDRAMs D[3:0], D8
G RRASB_n → RAS_n: SDRAMs D[7:4] VDDSPD VDDSPD SA0 SA0
CAS_n I RCASA_n → CAS_n: SDRAMs D[3:0], D8
EVENT EVENT SPD with SA1 SA1
S RCASB_n → CAS_n: SDRAMs D[7:4]
WE_n RWEA_n → WE_n: SDRAMs D[3:0], D8 SCL SCL Integrated SA2 SA2
T RWEB_n → WE_n: SDRAMs D[7:4] TS
CKE0 E RCKE0A → CKE0: SDRAMs D[3:0], D8 SDA SDA VSS VSS
R RCKE0B → CKE0: SDRAMs D[7:4]
ODT0 RODT0A → ODT0: SDRAMs D[3:0], D8
/ Plan to use SPD with Integrated TS of Class B and
RODT0B → ODT0: SDRAMs D[7:4]
CK0_t P PCK0A_t → CK_t: SDRAMs D[3:0], D8
might be changed on customer’s requests. For more
120 Ω
±1% L PCK0B_t → CK_t: SDRAMs D[7:4] details of SPD and Thermal sensor, please contact
CK0_c L PCK0A_c → CK_c: SDRAMs D[3:0], D8 local SK SK hynix sales representative
CK1_t 120 Ω PCK0B_c → CK_c: SDRAMs D[7:4]
±1%
CK1_c
PAR_IN OERR_n Err_Out_n
RESET_n RST_n
RST_n: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330 Ω resistor to ground
Rev. 1.1 / Mar. 2014 12

8GB, 1Gx72 Module(1Rank of x4) - page1
/BA[N:O]A
/BA[O:N]B
RCASA_n
RCASB_n
RRASA_n
RRASB_n
PCK0A_c
RWEA_n
RWEB_n
PCK0B_c
PCK0A_t
PCK0B_t
A[N:O]A
A[O:N]B
RODT0A
RODT0B
RCKE0A
RCKE0B
RS0A_n
RS0B_n
DQS8_t DQS_t ZQ DQS17_t DQS_t ZQ DQS4_t DQS_t ZQ DQS13_t DQS_t ZQ
DQS8_c DQS_c DQS17_c DQS_c DQS4_c DQS_c DQS13_c DQS_c
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM VSS DM VSS DM VSS DM
D8 D17 D4 D13
VSS
VSS
VSS
VSS
CB[3:0] DQ [3:0] CB[7:4] DQ [3:0] DQ[35:32] DQ [3:0] DQ[39:36] DQ [3:0]
RAS_n
RAS_n
RAS_n
RAS_n
CAS_n
CAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CS_n
CS_n
CK_c
CK_c
CK_c
CK_c
CK_t
CK_t
CK_t
CK_t
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D3 D12 D5 D14
VSS
VSS
VSS
VSS
DQ[27:24] DQ [3:0] DQ[31:28] DQ [3:0] DQ[43:40] DQ [3:0] DQ[47:44] DQ [3:0]
RAS_n
RAS_n
RAS_n
RAS_n
CAS_n
CAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CS_n
CS_n
CK_c
CK_c
CK_c
CK_c
CK_t
CK_t
CK_t
CK_t
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D2 D11 D6 D15
VSS
VSS
VSS
VSS
DQ[19:16] DQ [3:0] DQ23:20] DQ [3:0] DQ[51:48] DQ [3:0] DQ[55;52] DQ [3:0]
RAS_n
RAS_n
RAS_n
RAS_n
CAS_n
CAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CS_n
CS_n
CK_c
CK_c
CK_c
CK_c
CK_t
CK_t
CK_t
CK_t
ODT
ODT
ODT
ODT
CKE
CKE
CKE
CKE
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
D1 D10 D7 D16
VSS
VSS
VSS
VSS
DQ[11;8] DQ [3:0] DQ[15:12] DQ [3:0] DQ[59:56] DQ [3:0] DQ[63:60] DQ [3:0]
RAS_n
RAS_n
RAS_n
RAS_n
CAS_n
CAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CS_n
CS_n
CK_c
CK_c
CK_c
CK_c
CK_t
CK_t
CK_t
CK_t
ODT
ODT
ODT
ODT
CKE
CKE
CKE
ZQ ZQ CKE
DQS0_t DQS_t DQS9_t DQS_t Vtt
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
VSS DM VSS DM
D0 D9
VSS
VSS
DQ[3:0] DQ [3:0] DQ[7:4] DQ [3:0]

RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
CS_n
CS_n
CK_c
CK_c
CK_t
CK_t
ODT
ODT
CKE
CKE
Vtt
VDDSPD VDDSPD SA0 SA0

Plan to use SPD with Integrated TS of Class B and
EVENT EVENT SPD with SA1 SA1 might be changed on customer’s requests. For more
SCL SCL Integrated SA2 SA2 details of SPD and Thermal sensor, please contact
TS local SK SK hynix sales representative
SDA SDA VSS VSS
VDDSPD SPD
Note:
1. DQ-to-I/O wiring may be changed within a nibble. VDD D0–D17
2. Unless otherwise noted, resistor values are 15  5 %. VTT
3. See the wiring diagrams for all resistors associated with the com-
VREFCA D0–D17
mand, address and control bus.
4. ZQ resistors are 240  1 %. For all other resistor values refer to the VREFDQ D0–D17
appropriate wiring diagram. VSS D0–D17
Rev. 1.1 / Mar. 2014 13

8GB, 1Gx72 Module(1Rank of x4) - page2
S0_n RS0A_n → CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17

1:2 RS1A_n → CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35
S1_n RS0B_n → CS0B_n: SDRAMs D[7:4], D[16:13]
R RS1B_n → CS1B_n: SDRAMs D[25:22], D[34:31]
E
BA[2:0] RBA[2:0]A → BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
G RBA[2:0]B → BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
A[15:0] I RA[15:0]A → A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
S RA[15:0]B → A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RAS_n T RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
E
CAS_n RCASA_n → CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
R RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
WE_n / RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35
P RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
CKE[1:0] L RCKE0A → CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17
RCKE0B → CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35
L
ODT[1:0] RODT[1:0]A → ODT0: SDRAMs D[3:0], D8. D[12:9], D17
RODT[1:0]B → ODT0: SDRAMs D[21:18], D26, D[30:27], D35
CK0_t CK0A_t_R0 → CK-t: SDRAMs D[3:0], D8, D[21:18], D26

CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22]
120 Ω CK0A_t_R1 → CK-t: SDRAMs D[12:9], D17, D[30:27], D35
CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31]
CK0_c CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[21:18], D26
CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22]
CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35
CK1_t CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31]
120 Ω
CK1_c
PAR_IN Err_Out_n
RESET_n RST_n
RST_n: All SDRAMs
* S[3:2]_n are NC (Note: Otherwise stated differently all resistors values on this base are 22+-5%)
Rev. 1.1 / Mar. 2014 14

/BA[N:O]A
/BA[N:O]B
RCASA_n
RRASA_n
PCK0A_c
RWEA_n
PCK0A_t
A[N:O]A
A[N:O]B
PCK1A_c
RODT0A
PCK1A_t
RODT0B
RCKE0A
RODT1A
RCKE0B
RODT1B
RS0A_n
RCKE1A
RCKE1B
RS1A_c
RCASB
RRASB
PCK0B
PCK0B
RWEB
PCK1B
PCK1B
RS0B
RS1B
DQS8_t DQS_t DQS_t DQS4_t DQS_t DQS_t
DQS8_c DQS_c DQS_c DQS4_c DQS_c DQS_c
DM8/DQS17_t TDQS_t TDQS_t DM4/DQS13-t TDQS_t TDQS_t
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DQS17_c TDQS_c
DQ [7:0]
D8 TDQS_c
DQ [7:0]
D17 DQS13_c TDQS_c
DQ [7:0]
D4 TDQS_c
DQ [7:0]
D13
CB[7:0] DQ[39:32]
ZQ ZQ ZQ ZQ
RAS_n
RAS_n
CAS_n
CAS_n
RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CK_c
CK_c
CK_t
CK_t
CS_n
CS_n
CK_c
CK_c
ODT
ODT
CK_t
CK_t
CKE
ODT
CKE
ODT
CKE
CKE
DM3/DQS12_t TDQS_t TDQS_t DM5/DQS14_t TDQS_t TDQS_t
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DQS12_c
DQ[31:24]
TDQS_c
DQ [7:0]
D3 TDQS_c
DQ [7:0]
D12 DQS14_
DQ[47:40]
TDQS_c
DQ [7:0]
D5 TDQS_c
DQ [7:0]
D14
ZQ ZQ ZQ ZQ
RAS_n
RAS_n
CAS_n
CAS_n
RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CK_c
CK_c
CK_t
CK_t
CS_n
CS_n
CK_c
CK_c
ODT
ODT
CK_t
CK_t
CKE
CKE
ODT
ODT
CKE
CKE
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DQS11_c
DQ[23:16]
TDQS_c
DQ [7:0]
D2 TDQS_c
DQ [7:0]
D11 DQS15_c
DQ55:48]
TDQS_c
DQ [7:0]
D6 TDQS_c
DQ [7:0]
D15
ZQ ZQ ZQ ZQ
RAS_n
RAS_n
CAS_n
CAS_n
RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CK_c
CK_c
CK_t
CK_t
CS_n
CS_n
CK_c
CK_c
ODT
ODT
CK_t
CK_t
CKE
ODT
CKE
ODT
CKE
CKE
A[N:O]/BA[N:O]
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
A[O:N]/BA[N:O]
DQS10_c
DQ[15:8]
TDQS_c
DQ [7:0]
D1 TDQS_c
DQ [7:0]
D10 DQS16_c
DQ[63:56]
TDQS_c
DQ [7:0]
D7 TDQS_c
DQ [7:0]
D16
ZQ ZQ ZQ ZQ
RAS_n
RAS_n
CAS_n
CAS_n
RAS_n
RAS_n
CAS_n
CAS_n
WE_n
WE_n
WE_n
WE_n
CS_n
CS_n
CK_c
CK_c
CK_t
CK_t
CS_n
CS_n
CK_c
CK_c
ODT
ODT
CK_t
CK_t
CKE
ODT
CKE
ODT
CKE
CKE
DQS0_t DQS_t DQS_t Vtt

DQS0_c DQS_c DQS_c
DM0/DQS9_t TDQS_t TDQS_t
A[N:O]/BA[N:O]
A[N:O]/BA[N:O]
DQS9_c
DQ[7:0]
TDQS_c
DQ [7:0]
D0 TDQS_c
DQ [7:0]
D9
ZQ ZQ
RAS_n
CAS_n
RAS_n
CAS_n
WE_n
WE_n
CS_n
CK_c
CK_t
CS_n
CK_c
ODT
CK_t
CKE
ODT
CKE
VDDSPD VDDSPD SA0 SA0

EVENT_n EVENT SPD with SA1 SA1
Vtt SCL SCL Integrated SA2 SA2
TS
SDA SDA VSS VSS
Plan to use SPD with Integrated TS of Class B and

Note: might be changed on customer’s requests. For more
details of SPD and Thermal sensor, please contact
1. DQ-to-I/O wiring may be changed within a byte. local SK SK hynix sales representative
2. Unless otherwise noted, resistor values are 15 Ω ±5%.
3. ZQ resistors are 240 Ω ±1%. For all other resistor values
refer to the appropriate wiring diagram. VDDSPD Serial PD
4. See the wiring diagrams for all resistors associated with the VDD D0–D17
command, address and control bus. VTT D0–D17
VREFCA D0–D17
VREFDQ D0–D17
VSS D0–D17
Rev. 1.1 / Mar. 2014 15

S0_n RS0A_n → CS0_n: SDRAMs D[3:0], D8

1:2 RS0B_n → CS0_n: SDRAMs D[7:4]
S1_n
S[3:2] NC R
E
BA[N:0] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17
G RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]
A[N:0] I RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17
S RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13]
RAS_n T RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D17
RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13]
E
CAS_n RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D17
R RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13]
WE_n / RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D17
P RWEB_n → WE_n: SDRAMs D[7:4], D[16:13]
CKE0 L RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
L
CK0_t PCK0A_t → CK-t: SDRAMs D[3:0], D8

PCK0B_t → CK_t: SDRAMs D[7:4]
120 Ω
CK0_c PCK0A_c → CK_c: SDRAMs D[3:0], D8

PCK0B_c → CK_c: SDRAMs D[7:4]
CK1_t
120 Ω
CK1_c
PAR_IN Err_Out_n
RESET_n RST_n
RST_n: SDRAMs D[17:0]
Rev. 1.1 / Mar. 2014 16

VSS
RS0_n
RS1_n
DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS

DQS0_c DQS_c D0 DQS_c D18 DQS9_c DQS_c D9 DQS_c D27
DQ[3:0] DQ [3:0] DQ [3:0] DQ[7:4] DQ [3:0] DQ [3:0]

DQ[11:8] DQ [3:0] DQ [3:0] DQ[12:15] DQ [3:0] DQ [3:0]

DQ[16:19] DQ [3:0] DQ [3:0] DQ[20:23] DQ [3:0] DQ [3:0]

DQ[24:27] DQ [3:0] DQ [3:0] DQ[28:31] DQ [3:0] DQ [3:0]

DQ[32:35] DQ [3:0] DQ [3:0] DQ[36:39] DQ [3:0] DQ [3:0]

DQ[40:43] DQ [3:0] DQ [3:0] DQ[44:47] DQ [3:0] DQ [3:0]

DQ[48:51] DQ [3:0] DQ [3:0] DQ[52:55] DQ [3:0] DQ [3:0]

DQ[56:59] DQ [3:0] DQ [3:0] DQ[60:63] DQ [3:0] DQ [3:0]

CB[3:0] DQ [3:0] DQ [3:0] CB[7:4] DQ [3:0] DQ [3:0]
VDDSPD SPD
VDDSPD VDDSPD SA0 SA0 VDD D0–D17
EVENT EVENT SPD with SA1 SA1 VTT
SCL SCL Integrated SA2 SA2
TS VREFCA D0–D17
SDA SDA VSS VSS
VREFDQ D0–D17
Plan to use SPD with Integrated TS of Class B and might be VSS D0–D17
changed on customer’s requests. For more details of SPD and Ther-
mal sensor, please contact local SK SK hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 1.1 / Mar. 2014 17

S0_n RS0_n → CS1_n: SDRAMs D[17:9]

S1_n 1:2 RS1_n → CS0_n: SDRAMs D[8:0]
S2_n RS2_n → CS1_n: SDRAMs D[35:27]
S3_n R RS3_n → CS0_n: SDRAMs D[26:18]
BA[N:0] E RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
G RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
A[N:0] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
I RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
RAS_n S RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
T RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
CAS_n E RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
WE_n R RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
/ RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], U[25:22], U[34:31]
CKE0 P RCKE0A → CKE1: SDRAMs D[12:9], D17, D[30:27], D35
L RCKE0B → CKE1: SDRAMs D[16:13], D[34:31]
CKE1 RCKE1A → CKE0: SDRAMs D[3:0], D8, D[21:18], D26
L RCKE1B → CKE0: SDRAMs D[7:4], D[25:22]
CK0_t PCK0A_t → CK_t: SDRAMs D[3:0], D[12:8], D17
PCK0B_t → CK_t: SDRAMs D[7:4], D[16:13]
120 Ω PCK1A_t → CK_t: SDRAMs D[21:18], D[30:26], D35
PCK1B_t → CK_t: SDRAMs D[25:22], D[34:31]
CK0_c PCK0A_c → CK_c: SDRAMs D[3:0], D[12:8], D17
CK1_t PCK0B_c → CK_c: SDRAMs D[7:4], D[16:13]
120 Ω PCK1A_c → CK_c: SDRAMs D[21:18], D[30:26], D35
CK1_c PCK1B_c → CK_c: SDRAMs D[25:22], D[34:31]
PAR_IN Err_Out_n
RESET_n RST_n
RESET_n: SDRAMs D[35:0]
Rev. 1.1 / Mar. 2014 18

VSS
RS0_n
RS1_n
RS2_n
RS3_n
DQS0_t DQS_t DQS_t DQS_t DQS_t

DQS0_c DQS_c D0 DQS_c D18 DQS_c D36 DQS_c D54
DQ[3:0] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[11:8] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[19:16] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[27:24] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[35:32] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[43:40] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[51:48] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[59:56] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

CB[3:0] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]
Rev. 1.1 / Mar. 2014 19

VSS
RS0_n
RS1_n
RS2_n
RS3_n

DQ[7:4] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[15:12] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[23:20] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[31:28] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[39:36] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[47:44] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[55:21] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

DQ[63:60] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]

CB[7:4] DQ [3:0] DQ [3:0] DQ [3:0] DQ [3:0]
VDDSPD VDDSPD SA0 SA0 VDDSPD SPD

EVENT EVENT SPD with SA1 SA1 VDD D0–D71
SCL SCL Integrated SA2 SA2
TS VTT
SDA SDA VSS VSS
VREFCA D0–D71
Plan to use SPD with Integrated TS of Class B and might be VREFDQ D0–D71
changed on customer’s requests. For more details of SPD and VSS D0–D71
Thermal sensor, please contact local SK hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 1.1 / Mar. 2014 20

S[3:0]_n RS0A_n → CS0_n: SDRAMs D[17:0]

1:2 RS1A_n → CS1_n: SDRAMs D[18:35]
RS2A_n → CS2_n: SDRAMs D[36:53]
R RS3A_n → CS3_n: SDRAMs D[54:71]
BA[2:0] E RBA[2:0]A→ BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35, D[39:36], D44, D[48:45], D53, D[57:54], D62, D[66:63], D71
G RBA[2:0]B→ BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31], D[43:40], D[52:49], D[61:58], D[70:67]
A[15:0] RA[15:0]A→ A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35, D[39:36], D44, D[48:45], D53, D[57:54], D62, D[66:63], D71
I RA[15:0]B→ A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31], D[43:40], D[52:49], D[61:58], D[70:67]
RAS_n S RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35, D[39:36], D44, D[48:45], D53, D[57:54], D62, D[66:63], D71
T RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31], D[43:40], D[52:49], D[61:58], D[70:67]
CAS_n E RCASA_n →CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35, D[39:36], D44, D[48:45], D53, D[57:54], D62, D[66:63], D71
RCASB_n →CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31], D[43:40], D[52:49], D[61:58], D[70:67]
WE_n R RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35, D[39:36], D44, D[48:45], D53, D[57:54], D62, D[66:63], D71
/ RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31], D[43:40], D[52:49], D[61:58], D[70:67]
CKE[1:0] P RCKE0A→ CKE1: SDRAMs D[3:0], D8, D[12:9], D17, D[39:36], D44, D[48:45], D53
RCKE0B→ CKE1: SDRAMs D[7:4], D[16:13], D[43:40], D[52:49]
L
RCKE1A→ CKE0: SDRAMs D[21:18], D26, D[30:27], D35, D[57:54], D62, D[66:63], D71
L RCKE1B→ CKE0: SDRAMs D[25:22], D[34:31], D[61:58], D[70:67]
ODT[1:0] RODT[1:0]A → RODT[0]A ~> SDRAMs D[3:0], D8, D[12:9], D17 RODT[1]A ~> SDRAMs D[39:36], D44, D[48:45], D53
RODT[1:0]B → RODT[0]B ~> SDRAMs D[7:4], D[16:13] RODT[1]B ~> SDRAMs D[43:40], D[52:49]
CK0A_t_R0 → CK_t: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[39:36], D44, D[57:54], D62
CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22], D[43:40], D[61:58]
CK0_t CK0A_t_R1 → CK_t: SDRAMs D[12:9], D17, D[30:27], D35, D[48:45], D53, D[66:63], D71
CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31], D[52:49], D[70:67]
120 Ω
CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[39:36], D44, D[57:54], D62
CK0_c CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22], D[43:40], D[61:58]
CK1_t CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35, D[48:45], D53, D[66:63], D71
120 Ω CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31], D[52:49], D[70:67]
CK1_c
PAR_IN Err_Out_n
RESET_n RST_n
RESET_n: All SDRAMs
Rev. 1.1 / Mar. 2014 21

Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol Parameter Rating Units Notes

VDD Voltage on VDD pin relative to Vss - 0.4 V ~ 1.80 V V 1,3
VDDQ Voltage on VDDQ pin relative to Vss - 0.4 V ~ 1.80 V V 1,3
VIN, VOUT Voltage on any pin relative to Vss - 0.4 V ~ 1.80 V V 1
TSTG Storage Temperature -55 to +100 o
C 1, 2
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.

DRAM Component Operating Temperature Range
Temperature Range

Normal Operating Temperature Range 0 to 85 oC 1,2
TOPER
Extended Temperature Range 85 to 95 oC
1,3
Notes:
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For mea-
surement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. Dur-
ing operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85oC and 95oC
case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply:
a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It
is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability
b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b).
DDR3 SDRAMs support Extended Temperature Range and please refer to component datasheet and/or the
DIMM SPD for tFEFI requirements in the Extended Temperature Range.
Rev. 1.1 / Mar. 2014 22

AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions - DDR3L (1.35V) operation
Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.283 1.35 1.45 V 1,2,3,4
VDDQ Supply Voltage for Output 1.283 1.35 1.45 V 1,2,3,4
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ (t) over a
very long period of time (e.g., 1 sec).
2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3 operation (see Figure 0).
Recommended DC Operating Conditions - - DDR3 (1.5V) operation
Rating
Symbol Parameter Units Notes
Min. Typ. Max.
VDD Supply Voltage 1.425 1.5 1.575 V 1,2,3
VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2,3
Notes:
1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifications under the same speed timings as
defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and
VDDQ are changed for DDR3L operation (see Figure 0).
Rev. 1.1 / Mar. 2014 23

Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk
CK,CK#
Tmin = 10ns tCKSRX

VDD, VDDQ (DDR3)
VDD, VDDQ (DDR3L)
Tmin = 10ns Tmin = 200us
T = 500us
RESET#
CKE Tmin = 10ns VALID
tDLLK
tIS
tXPR tMRD tMRD tMRD tMOD tZQinit
COMMAND READ 1) MRS MRS MRS MRS ZQCL 1) VALID
BA READ MR2 MR3 MR1 MR0 VALID

tIS tIS
ODT READ Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID
RTT
NOTE 1: From time point “Td” until “Tk” NOP or DES commands must be applied
TIME BREAK DON’T CARE
between MRS and ZQCL commands.
Figure 0 - VDD/VDDQ Voltage Switch Between DDR3L and DDR3
Rev. 1.1 / Mar. 2014 24

AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and Address
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
Symbol Parameter Unit Notes
VIH.CA(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.CA(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.CA(AC160) AC input logic high Vref + 0.160 Note2 Vref + 0.160 Note2 - - V 1,2,5
VIL.CA(AC160) AC input logic low Note2 Vref - 0.160 Note2 Vref - 0.160 - - V 1,2,5
VIH.CA(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 Vref + 0.135 Note2 V 1,2,5
VIL.CA(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 Note2 Vref - 0.135 V 1,2,5
VIH.CA(AC125) AC Input logic high - - - - Vref + 0.125 Note2 V 1,2,5
VIL.CA(AC125) AC input logic low - - - - Note2 Vref - 0.125 V 1,2,5
Reference Voltage for
VRefCA(DC) 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3,4
ADD, CMD inputs
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 38.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than +/-1% VDD (for refer-
ence: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (see table above) operation only. If the device is operated at 1.5V (table "Single
Ended AC and DC Input Levels for DQ and DM" on page 26), the respective levels in JESD79-3 (VIH/L.CA(DC100),
VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) apply. The 1.5V levels (VIH/
L.CA(DC100), VIH/L.CA(AC175), VIH/L.CA(AC150), VIH/L.CA(AC135), VIH/L.CA(AC125) etc.) do not apply when
the device is operated in the 1.35 voltage range.
Rev. 1.1 / Mar. 2014 25

AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066s specified in table below.
DDR3 SDRAM will also support corresponding tDS values (Table 43 on page 117 and Table 50 in “DDR3L
Device Operation”) as well as derating tables Table 46 in “DDR3L Device Operation” depending on Vih/Vil
AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
VIH.DQ(DC90) DC input logic high Vref + 0.09 VDD Vref + 0.09 VDD Vref + 0.09 VDD V 1
VIL.DQ(DC90) DC input logic low VSS Vref - 0.09 VSS Vref - 0.09 VSS Vref - 0.09 V 1
VIH.DQ(AC160) AC input logic high Vref + 0.160 Note2 - - - - V 1, 2, 5
VIL.DQ(AC160) AC input logic low Note2 Vref - 0.160 - - - - V 1, 2, 5
VIH.DQ(AC135) AC Input logic high Vref + 0.135 Note2 Vref + 0.135 Note2 - - V 1, 2, 5
VIL.DQ(AC135) AC input logic low Note2 Vref - 0.135 Note2 Vref - 0.135 - - V 1, 2, 5
VIH.DQ(AC130) AC Input logic high - - - - Vref + 0.130 Note2 V 1, 2, 5
VIL.DQ(AC130) AC input logic low - - - - Note2 Vref - 0.130 V 1, 2, 5
Reference Voltage
VRefDQ(DC) 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4
for DQ, DM inputs
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 38.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference:
approx. +/- 13.5 mV). 4. For reference: approx. VDD/2 +/- 13.5 mV
4. For reference: approx. VDD/2 +/- 13.5 mV
5. These levels apply for 1.35 volt (table "Single Ended AC and DC Input Levels for Command and Address" on
page 25) operation only. If the device is operated at 1.5V (table above), the respective levels in JESD79-3 (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) apply. The 1.5V levels (VIH/
L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135) etc.) do not apply when the device is
operated in the 1.35 voltage range.
Rev. 1.1 / Mar. 2014 26

Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in
figure below. It shows a valid reference voltage VRef (t) as a function of time. (VRef stands for VRefCA and
VRefDQ likewise).
VRef (DC) is the linear average of VRef (t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 33. Further-
more VRef (t) may temporarily deviate from VRef (DC) by no more than +/- 1% VDD.
voltage
VDD
VRef(t)
VRef ac-noise
VRef(DC) VRef(DC)max
VDD/2
VRef(DC)min
VSS
time
Illustration of VRef(DC) tolerance and VRef ac-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are depen-
dent on VRef.
“VRef ” shall be understood as VRef(DC), as defined in figure above.
This clarifies that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VRef(DC) deviations from the optimum position within the data-eye of the input
signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VRefac-noise. Timing and voltage effects due to ac-noise on VRef up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
Rev. 1.1 / Mar. 2014 27

AC and DC Logic Input Levels for Differential Signals
Differential signal definition
tDVAC
VIL.DIFF.AC.MIN
Differential Input Voltage(i.e.DQS - DQS#, CK - CK#)
VIL.DIFF.MIN
0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Definition of differential ac-swing and “time above ac-level” tDVAC
Rev. 1.1 / Mar. 2014 28

Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
DDR3L-800, 1066, 1333, 1600, 1866
Min Max
VIHdiff Differential input high + 0.180 Note 3 V 1
VILdiff Differential input logic low Note 3 - 0.180 V 1
VIHdiff (ac) Differential input high ac 2 x (VIH (ac) - Vref) Note 3 V 2
VILdiff (ac) Differential input low ac Note 3 2 x (VIL (ac) - Vref) V 2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level
applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot.Refer to "Overshoot and Undershoot Specifications" on page 38.
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS

DDR3L-800/1066/1333/1600 DDR3L-1866
tDVAC [ps] tDVAC [ps] tDVAC [ps] tDVAC [ps] tDVAC [ps]
Slew Rate
@ |VIH/Ldiff @ |VIH/Ldiff @ |VIH/Ldiff @ |VIH/Ldiff @ |VIH/Ldiff
[V/ns]
(ac)| = 320mV (ac)| = 270mV (ac)| = 270mV (ac)| = 250mV (ac)| = 260mV
min max min max min max min max min max
> 4.0 189 - 201 - 163 - 168 - 176 -
4.0 189 - 201 - 163 - 168 - 176 -
3.0 162 - 179 - 140 - 147 - 154 -
2.0 109 - 134 95 105 111
1.8 91 - 119 - 80 - 91 - 97 -
1.6 69 - 100 - 62 - 74 - 78 -
1.4 40 - 76 - 37 - 52 - 56 -
1.2 note - 44 - 5 - 22 - 24 -
1.0 note - note - note - note - note -
< 1.0 note - note - note - note - note -
note : Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become
equal to or less than VIL(ac) level.
Rev. 1.1 / Mar. 2014 29

Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has
also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the single-
ended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ
time
Single-ended requirements for differential signals.

Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended compo-
nents of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the
transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended
components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing,
but adds a restriction on the common mode characteristics of these signals.
Rev. 1.1 / Mar. 2014 30

Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
DDR3L-800, 1066, 1333, 1600, 1866
Min Max
Single-ended high level for strobes (VDD / 2) + 0.175 Note 3 V 1,2
VSEH
Single-ended high level for Ck, CK (VDD /2) + 0.175 Note 3 V 1,2
Single-ended low level for strobes Note 3 (VDD / 2)- 0.175 V 1,2
VSEL
Single-ended low level for CK, CK Note 3 (VDD / 2) - 0.175 V 1,2
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac)
of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced
ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU
need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 38.
Rev. 1.1 / Mar. 2014 31

Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the
requirements in table below. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)

DDR3L-800, 1066, 1333, 1600, 1866
Min Max
Differential Input Cross Point Voltage -150 150 mV 2
VIX(CK)
relative to VDD/2 for CK, CK -175 175 mV 1
Differential Input Cross Point Voltage
VIX(DQS) -150 150 mV 2
relative to VDD/2 for DQS, DQS
Notes:
1. Extended range for VIX is only allowed for clock and if single-ended clock input signals CK and CK are monotonic
with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK -
CK is larger than 3 V/ns.
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL  25mV 
VSEH - ((VDD/2) + Vix (Max))  25mV
Rev. 1.1 / Mar. 2014 32

Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on “DDR3L Device Operation” for single-ended
slew rate definitions for address and command signals.

See 7.6 “Data Setup, Hold and Slew Rate Derating” on “DDR3L Device Operation” for single-ended slew
rate definition for data signals.
Slew Rate Definitions for Differential Input Signals

Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table
and figure below.
Differential Input Slew Rate Definition
Measured
Description Defined by
Min Max
Differential input slew rate for rising edge
VILdiffmax VIHdiffmin [VIHdiffmin-VILdiffmax] / DeltaTRdiff
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
VIHdiffmin VILdiffmax [VIHdiffmin-VILdiffmax] / DeltaTFdiff
(CK-CK and DQS-DQS)
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
Differential Input Voltage (i.e. DQS-DQS; CK-CK)
Delta
TRdiff
VIHdiffmin
VILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.1 / Mar. 2014 33

AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
DDR3L-800, 1066,
1333, 1600, 1866
VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V
VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V
VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V
VOH(AC) AC output high measurement level (for output SR) VTT + 0.1 x VDDQ V 1
VOL(AC) AC output low measurement level (for output SR) VTT - 0.1 x VDDQ V 1
Notes:
1. The swing of ±0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing with
a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ / 2.
Differential AC and DC Output Levels

Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
DDR3L-800, 1066,
1333, 1600, 1866
VOHdiff (AC) AC differential output high measurement level (for output SR) + 0.2 x VDDQ V 1
VOLdiff (AC) AC differential output low measurement level (for output SR) - 0.2 x VDDQ V 1
Notes:
1. The swing of ±0.2 x VDDQ is based on approximately 50% of the static differential output high or low swing with
a driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
Rev. 1.1 / Mar. 2014 34

Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals are shown in table and figure below.
Single-ended Output slew Rate Definition
Measured
From To
Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC)-VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC)-VOL(AC)] / DeltaTFse
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
Single Ended Output Voltage(l.e.DQ)
VOH(AC)
V∏
VOl(AC)
Delta TFse
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)

DDR3L-800 DDR3L-1066DDR3L-1333DDR3L-1600DDR3L-1866
Units
Parameter Symbol Min Max Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 1.75 51) 1.75 51) 1.75 51) 1.75 51) 1.75 51) V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from
low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular
maximum limite of 5 V/ns applies.
Rev. 1.1 / Mar. 2014 35

Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure
below.
Differential Output Slew Rate Definition
Measured
From To
Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTRdiff
Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) [VOHdiff (AC)-VOLdiff (AC)] / DeltaTFdiff
Notes:
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta
TRdiff
Differential Output Voltage(i.e. DQS-DQS)
VOHdiff(AC)
VOLdiff(AC)
Delta
TFdiff
Differential Output slew Rate Definition
Differential Output Slew Rate

DDR3L-800 DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Units
Parameter Symbol Min Max Min Max Min Max Min Max Min Max
Differential Output Slew Rate SRQdiff 3.5 12 3.5 12 3.5 12 3.5 12 3.5 12 V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
Rev. 1.1 / Mar. 2014 36

Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the
actual load presented by a production tester. System designers should use IBIS or other simulation tools to
correlate the timing reference load to a system environment. Manufacturers correlate to their production
test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
25 Ohm
CK, CK DQ
DUT VTT = VDDQ/2
DQS
DQS
Reference Load for AC Timing and Output Slew Rate
Rev. 1.1 / Mar. 2014 37

Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
DDR3 DDR3 DDR3 DDR3 DDR3
Parameter Units
L-800 L-1066 L-1333 L-1600 L-1866
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.67 0.5 0.4 0.33 0.28 V-ns
Maximum undershoot area below VSS (See Figure below) 0.67 0.5 0.4 0.33 0.28 V-ns
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDD
Volts
(V)
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Rev. 1.1 / Mar. 2014 38

Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
DDR3 DDR3 DDR3 DDR3 DDR3
Parameter Units
L-800 L-1066L-1333L-1600L-1866
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4 0.4 0.4 0.4 0.4 V
Maximum overshoot area above VDD (See Figure below) 0.25 0.19 0.15 0.13 0.11 V-ns
Maximum undershoot area below VSS (See Figure below) 0.25 0.19 0.15 0.13 0.11 V-ns
(CK, CK, DQ, DQS, DQS, DM)
See figure below for each parameter definition
Maximum Amplitude
Overshoot Area
VDDQ
Volts
(V)
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.1 / Mar. 2014 39

Refresh parameters by device density
Refresh parameters by device density
Parameter RTT_Nom Setting 512Mb 1Gb 2Gb 4Gb 8Gb Units Notes
REF command ACT or
tRFC 90 110 160 260 350 ns
REF command time
Average periodic 0 C  TCASE  85 C 7.8 7.8 7.8 7.8 7.8 us
tREFI
refresh interval 85 C  TCASE  95 C 3.9 3.9 3.9 3.9 3.9 us 1
Notes:
1. Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices
support the following options or requirements referred to in this materia.
Rev. 1.1 / Mar. 2014 40

Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3L-800 Speed Bins

For specific Notes See "Speed Bin Table Notes" on page 46.
Speed Bin DDR3L-800E

Unit Notes
CL - nRCD - nRP 6-6-6
Parameter Symbol min max
Internal read command to first data tAA 15 20 ns
ACT to internal read or write delay time tRCD 15 — ns
PRE command period tRP 15 — ns
ACT to ACT or REF command period tRC 52.5 — ns
ACT to PRE command period tRAS 37.5 9 * tREFI ns
CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3

Supported CL Settings 6 nCK
Supported CWL Settings 5 nCK
Rev. 1.1 / Mar. 2014 41

Speed Bin DDR3L-1066F

Unit Note
Internal read command to
tAA 13.125 20 ns
first data
ACT to internal read or

tRCD 13.125 — ns
write delay time
PRE command period tRP 13.125 — ns
ACT to ACT or REF

tRC 50.625 — ns
command period
ACT to PRE command

tRAS 37.5 9 * tREFI ns
period
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6
CL = 6
CWL = 6 tCK(AVG) Reserved ns 1,2,3,4
CWL = 5 tCK(AVG) Reserved ns 4
CL = 7
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,4
CL = 8
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3
Supported CL Settings 6, 7, 8 nCK
Supported CWL Settings 5, 6 nCK
Rev. 1.1 / Mar. 2014 42

Speed Bin DDR3L-1333H

Unit Note
Internal read 13.5
tAA 20 ns
command to first data (13.125)5,10
ACT to internal read or 13.5
tRCD — ns
write delay time (13.125)5,10
13.5
PRE command period tRP — ns
(13.125)5,10
ACT to ACT or REF 49.5
tRC — ns
command period (49.125)5,10
ACT to PRE command
tRAS 36 9 * tREFI ns
period
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7
CL = 6 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7
1.875 < 2.5
CL = 7 CWL = 6 tCK(AVG) ns 1,2,3,4,7
(Optional)5,10
CL = 8 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,7
CWL = 5, 6 tCK(AVG) Reserved ns 4
CL = 9
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4
CL = 10 1.5 <1.875 ns 1,2,3
CWL = 7 tCK(AVG)
(Optional) ns 5
Supported CL Settings 6, 7, 8, 9, 10 nCK
Supported CWL Settings 5, 6, 7 nCK
Rev. 1.1 / Mar. 2014 43

Speed Bin DDR3L-1600K

Unit Note
CL - nRCD - nRP 11-11-11
Internal read 13.75
tAA 20 ns
command to first data (13.125)5,10
tRCD — ns
13.75
(13.125)5,10
ACT to ACT or REF 48.75
tRC — ns
ACT to PRE command
period
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,8
1.875 < 2.5
CWL = 6 tCK(AVG) ns 1,2,3,4,8
CL = 7 (Optional)5,10
CWL = 7 tCK(AVG) Reserved ns 1,2,3,4,8
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,8
CL = 8
1.5 <1.875
CL = 9 CWL = 7 tCK(AVG) ns 1,2,3,4,8
(Optional)5,10
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,8
CWL = 5, 6,7 tCK(AVG) Reserved ns 4
CL = 11
CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3
Supported CL Settings 5, 6, 7, 8, 9, 10, 11 nCK
Supported CWL Settings 5, 6, 7, 8 nCK
Rev. 1.1 / Mar. 2014 44

Speed Bin DDR3L-1866M
Unit Note
CL - nRCD - nRP 13-13-13
Internal read command 13.91
tAA 20 ns
to first data (13.125)5,11
tRCD — ns
13.91
(13.125)5,11
ACT to PRE command
period
ACT to ACT or PRE 47.91
tRC - ns
CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,9
CWL = 7,8,9 tCK(AVG) Reserved ns 4
CL = 7 CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,4,9
CWL = 6 tCK(AVG) 1.875 < 2.5 ns 1,2,3,9
CL = 8
CWL = 8,9 tCK(AVG) Reserved ns 4
CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4,9
CL = 9
CL = 10 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,9
CL = 11 CWL = 8 tCK(AVG) 1.25 <1.5 ns 1,2,3,4,9
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 12
CWL = 5,6,7,8 tCK(AVG) Reserved ns 4
CL = 13
CWL = 9 tCK(AVG) 1.07 <1.25 ns 1, 2, 3
Supported CL Settings 6, 7, 8, 9, 10, 11, 13 nCK
Supported CWL Settings 5, 6, 7, 8, 9 nCK
Rev. 1.1 / Mar. 2014 45

Speed Bin Table Notes
Absolute Specification (TOPER; VDDQ = VDD = 1.35V +0.100/- 0.067 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When mak-
ing a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as require-
ments from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchro-
nized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should
use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculat-
ing CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a man-
datory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is
supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
10. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must
be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H
devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23)
also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125
ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
11. DDR3 SDRAM devices supporting optional down binning to CL=11, CL=9 and CL=7, tAA/tRCD/tRPmin
must be 13.125ns. SPD setting must be programed to match. For example, DDR3-1866 devices sup-
porting down binning to DDR3-1600 or DDR3-1333 or 1066 should program 13.125ns in SPD bytes for
tAAmin(byte 16), tRCDmin(byte 18) and tRPmin(byte 20) is programmed to 13.125ns, tRCmin(byte
21,23) also should be programmed accordingly. For example, 47.125ns (tRASmin + tRPmin = 34ns +
13.125ns)
Rev. 1.1 / Mar. 2014 46

Environmental Parameters
TOPR Operating temperature See Note 3
HOPR Operating humidity (relative) 10 to 90 % 1
TSTG Storage temperature -50 to +100 o 1

C
HSTG Storage humidity (without condensation) 5 to 95 % 1
PBAR Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2
Note:
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and
device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum
rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 1.1 / Mar. 2014 47

IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls
of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ cur-
rents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can
be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one
merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= VILAC(max).

• ”1” and “HIGH” is defined as VIN >= VIHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not lim-
ited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.1 / Mar. 2014 48

IDD IDDQ (optional)
VDD VDDQ
RESET
CK/CK
DDR3L
SDRAM
CKE DQS, DQS RTT = 25 Ohm
CS DQ, DM, VDDQ/2
RAS, CAS, WE TDQS, TDQS
A, BA
ODT
ZQ
VSS VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific IDDQ

memory channel Test Load
environment
Channel
IDDQ IDDQ
IO Power
Simulation Simulation
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 1.1 / Mar. 2014 49

Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3L-1066 DDR3L-1333 DDR3L-1600 DDR3L-1866
Symbol Unit
7-7-7 9-9-9 11-11-11 13-13-13
tCK 1.875 1.5 1.25 1.07 ns
CL 7 9 11 13 nCK
nRCD 7 9 11 13 nCK
nRC 27 33 39 45 nCK
nRAS 20 24 28 32 nCK
nRP 7 9 11 13 nCK
1KB page size 20 20 24 26 nCK
nFAW
nRRD
nRFC -512Mb 48 60 72 85 nCK
nRFC-1 Gb 59 74 88 103 nCK
nRFC- 2 Gb 86 107 128 150 nCK
nRFC- 4 Gb 139 174 208 243 nCK
nRFC- 8 Gb 187 234 280 328 nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions

Symbol Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT and
IDD0 PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8a); AL: 0; CS: High between ACT,
IDD1 RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM:
stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.1 / Mar. 2014 50

Symbol Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details:
see Table 5.
Precharge Standby ODT Current
IDD2NT Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank
IDD2P0
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buf-
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
IDD2P1
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
fer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0

Active Standby Current
IDD3N Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all
banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
IDD3P
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Rev. 1.1 / Mar. 2014 51

Symbol Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different
IDD4R
data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at 0; Pattern Details: see Table 7.

Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8a); AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different
IDD4W
data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 8.

Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8a); AL: 0; CS: High between REF; Command,
IDD5B Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registersb);
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale); CKE:
IDD6 Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer
and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL

Self-Refresh Current: Extended Temperature Range (optional)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extendede);
IDD6ET CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8a); AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID_LEVEL
Rev. 1.1 / Mar. 2014 52

Symbol Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8a),f); AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
IDD7 10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different address-
ing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B

b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.1 / Mar. 2014 53

Table 3 - IDD0 Measurement-Loop Patterna)
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1, 2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC+3, 4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
... repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary

1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead
a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Rev. 1.1 / Mar. 2014 54

Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1,2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRCD - 1, truncate if necessary
nRCD RD 0 1 0 1 0 0 00 0 0 0 0 00000000
... repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS PRE 0 0 1 0 0 0 00 0 0 0 0 -
... repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
1*nRC+1,2 D, D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
1*nRC+3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
... repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
1*nRC+nRCD RD 0 1 0 1 0 0 00 0 0 F 0 00110011
... repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
1*nRC+nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 -
... repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID_LEVEL.
Rev. 1.1 / Mar. 2014 55

Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High
1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead

toggling

Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)

Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 D 1 0 0 0 0 0 0 0 0 0 0 -
1 D 1 0 0 0 0 0 0 0 0 0 0 -
2 D 1 1 1 1 0 0 0 0 0 F 0 -
3 D 1 1 1 1 0 0 0 0 0 F 0 -
Static High
1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1

toggling

Rev. 1.1 / Mar. 2014 56

Table 7 - IDD4R and IDDQ4R Measurement-Loop Patterna)
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 RD 0 1 0 1 0 0 00 0 0 0 0 00000000
1 D 1 0 0 0 0 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 0 0 00 0 0 0 0 -
4 RD 0 1 0 1 0 0 00 0 0 F 0 00110011
5 D 1 0 0 0 0 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 0 0 00 0 0 F 0 -
toggling
1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1

b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Patterna)

Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
Datab)
CAS
CKE
WE
CS
0 0 WR 0 1 0 0 1 0 00 0 0 0 0 00000000
1 D 1 0 0 0 1 0 00 0 0 0 0 -
2,3 D,D 1 1 1 1 1 0 00 0 0 0 0 -
4 WR 0 1 0 0 1 0 00 0 0 F 0 00110011
5 D 1 0 0 0 1 0 00 0 0 F 0 -
Static High
6,7 D,D 1 1 1 1 1 0 00 0 0 F 0 -
toggling

a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.1 / Mar. 2014 57

Table 9 - IDD5B Measurement-Loop Patterna)
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
CAS
CKE
WE
Datab)
CS
0 0 REF 0 0 0 1 0 0 0 0 0 0 0 -
1 1.2 D, D 1 0 0 0 0 0 00 0 0 0 0 -
3,4 D, D 1 1 1 1 0 0 00 0 0 F 0 -
5...8 repeat cycles 1...4, but BA[2:0] = 1
Static High

toggling

2 33...nRFC-1 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
Rev. 1.1 / Mar. 2014 58

ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Command
Number
Sub-Loop
A[15:11]
BA[2:0]
A[9:7]
A[6:3]
CK, CK
A[2:0]
A[10]
Cycle
ODT
RAS
Datab)
CKE
CAS
WE
CS
0 0 ACT 0 0 1 1 0 0 00 0 0 0 0 -
1 RDA 0 1 0 1 0 0 00 1 0 0 0 00000000
2 D 1 0 0 0 0 0 00 0 0 0 0 -
... repeat above D Command until nRRD - 1
nRRD ACT 0 0 1 1 0 1 00 0 0 F 0 -
nRRD+1 RDA 0 1 0 1 0 1 00 1 0 F 0 00110011
1
nRRD+2 D 1 0 0 0 0 1 00 0 0 F 0 -
... repeat above D Command until 2* nRRD - 1
2 2*nRRD repeat Sub-Loop 0, but BA[2:0] = 2
3 3*nRRD repeat Sub-Loop 1, but BA[2:0] = 3
4*nRRD D 1 0 0 0 0 3 00 0 0 F 0 -
4
Assert and repeat above D Command until nFAW - 1, if necessary
5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4
6 nFAW+nRRD repeat Sub-Loop 1, but BA[2:0] = 5
7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6
8 nFAW+3*nRRD repeat Sub-Loop 1, but BA[2:0] = 7
nFAW+4*nRRD D 1 0 0 0 0 7 00 0 0 F 0 -
Static High
9
toggling
Assert and repeat above D Command until 2* nFAW - 1, if necessary

2*nFAW+0 ACT 0 0 1 1 0 0 00 0 0 F 0 -
2*nFAW+1 RDA 0 1 0 1 0 0 00 1 0 F 0 00110011
10
D 1 0 0 0 0 0 00 0 0 F 0 -
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD ACT 0 0 1 1 0 1 00 0 0 0 0 -
2*nFAW+nRRD+1 RDA 0 1 0 1 0 1 00 1 0 0 0 00000000
11
D 1 0 0 0 0 1 00 0 0 0 0 -
2&nFAW+nRRD+2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
D 1 0 0 0 0 3 00 0 0 0 0 -
14 2*nFAW+4*nRRD
15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4
16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5
D 1 0 0 0 0 7 00 0 0 0 0 -
19 3*nFAW+4*nRRD
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.1 / Mar. 2014 59

IDD Specifications (Tcase: 0 to 95oC)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power.
The actual measurements may vary according to DQ loading cap.
4GB, 512M x 72 R-DIMM: HMT451V7AFR8A

Symbol DDR3L 1333 DDR3L 1600 DDR3L 1866 Unit note
IDD0 1052 1061 1070 mA
IDD1 1115 1124 1133 mA
IDD2N 908 926 926 mA
IDD2NT 944 962 962 mA
IDD2P0 300 300 300 mA
IDD2P1 318 318 327 mA
IDD2Q 917 917 917 mA
IDD3N 989 998 1007 mA
IDD3P 381 390 390 mA
IDD4R 1439 1529 1619 mA
IDD4W 1484 1574 1664 mA
IDD5B 2564 2564 2564 mA
IDD6 336 336 336 mA
IDD6ET 372 372 372 mA
IDD7 1934 1979 2069 mA
8GB, 1G x 72 R-DIMM: HMT41GV7AFR4A

IDD0 1340 1358 1376 mA
IDD1 1466 1484 1502 mA
IDD2N 1052 1088 1088 mA
IDD2NT 1124 1160 1160 mA
IDD2P0 372 372 372 mA
IDD2P1 408 408 426 mA
IDD2Q 1070 1070 1070 mA
IDD3N 1214 1232 1250 mA
IDD3P 534 552 552 mA
IDD4R 2114 2294 2474 mA
IDD4W 2204 2384 2564 mA
IDD5B 4364 4364 4364 mA
IDD6 444 444 444 mA
IDD6ET 516 516 516 mA
IDD7 3104 3194 3374 mA
Rev. 1.1 / Mar. 2014 60

8GB, 1G x 72 R-DIMM: HMT41GV7AFR8A
IDD0 1196 1295 1313 mA
IDD1 1259 1358 1376 mA
IDD2N 1052 1088 1088 mA
IDD2NT 1124 1160 1160 mA
IDD2P0 372 372 372 mA
IDD2P1 408 408 426 mA
IDD2Q 1070 1070 1070 mA
IDD3N 1214 1232 1250 mA
IDD3P 534 552 552 mA
IDD4R 1583 1763 1862 mA
IDD4W 1628 1808 1907 mA
IDD5B 2708 2798 2807 mA
IDD6 444 444 444 mA
IDD6ET 516 516 516 mA
IDD7 2078 2213 2312 mA
16GB, 2G x 72 R-DIMM: HMT82GV7AMR4A

IDD0 1574 1628 1826 mA
IDD1 1700 1754 1952 mA
IDD2N 1304 1340 1412 mA
IDD2NT 1412 1484 1556 mA
IDD2P0 516 516 516 mA
IDD2P1 522 588 588 mA
IDD2Q 1340 1376 1376 mA
IDD3N 1628 1664 1700 mA
IDD3P 840 840 876 mA
IDD4R 2204 2402 2762 mA
IDD4W 2294 2492 2852 mA
IDD5B 1634 4652 4832 mA
IDD6 660 660 660 mA
IDD6ET 804 804 804 mA
IDD7 3014 3392 3662 mA
Rev. 1.1 / Mar. 2014 61

32GB, 4G x 72 R-DIMM: HMTA4GV7AHR4A
Symbol DDR3L 1066 DDR3L 1333 Unit note
IDD0 2114 2204 mA
IDD1 2240 2330 mA
IDD2N 1844 1916 mA
IDD2NT 2060 2204 mA
IDD2P0 804 804 mA
IDD2P1 876 948 mA
IDD2Q 1916 1988 mA
IDD3N 2492 2564 mA
IDD3P 1452 1452 mA
IDD4R 2744 2978 mA
IDD4W 2834 3068 mA
IDD5B 5174 5228 mA
IDD6 1092 1092 mA
IDD6ET 1380 1380 mA
IDD7 3554 3968 mA
Rev. 1.1 / Mar. 2014 62

Module Dimensions
512Mx72 - HMT451V7AFR8A
Front
2.10±0.15 14.90
Detail C 13.60
18.75±0.15
3±0.1
Clock Driver
Registering
15.80±0.1
3±0.1
1 120 8.00±0.1
2X3.0±0.10
5.175 47.00 71.00

Detail A Detail B
128.95
133.35
Back
SPD/TS
240 121
2x R0.75 Max
Side
Detail of Contacts B Detail of Contacts C 3.64mm max
Detail of Contacts A
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~0.1
1.00 1.50 ±0.10
5.00
1.27±010mm
max
Note:
1.  0.13 tolerance on all dimensions unless otherwise stated.
Units: millimeters
Rev. 1.1 / Mar. 2014 63

1Gx72 - HMT41GV7AFR4A
Front
2.10±0.15 14.90
Detail C 13.60
18.75±0.15
3±0.1
Clock Driver
Registering
15.80±0.1
3±0.1
1 120 8.00±0.1
2X3.0±0.10
5.175 47.00 71.00

Detail A Detail B
128.95
133.35
Back
SPD/TS
240 121
2x R0.75 Max
Side
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~0.1
1.00
1.50 ±0.10
5.00
1.27±010mm
max
Note:
Units: millimeters
Rev. 1.1 / Mar. 2014 64

1Gx72 - HMT41GV7AFR8A
Front
2.10±0.15 14.90
Detail C 13.60
18.75±0.15
3±0.1
Clock Driver
Registering
15.80±0.1
3±0.1
1 120 8.00±0.1
2X3.0±0.10
5.175 47.00 71.00

Detail A Detail B
128.95
133.35
Back
SPD/TS
240 121
2x R0.75 Max
Side
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~0.1
1.00
1.50 ±0.10
5.00
1.27±010mm
max
Note:
Units: millimeters
Rev. 1.1 / Mar. 2014 65

2Gx72 - HMT82GV7AMR4A
Front
2.10±0.15 14.90
Detail C 13.60
18.75±0.15
3±0.1
Clock Driver
Registering
15.80±0.1
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
3±0.1
1 120 8.00±0.1
2X3.0±0.10
5.175 47.00 71.00

Detail A Detail B
128.95
133.35
Back
SPD/TS
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
240 121
2x R0.75 Max
Side
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~0.1
1.00
1.50 ±0.10
5.00
1.27±010mm
max
Note:
Units: millimeters
Rev. 1.1 / Mar. 2014 66

2Gx72 - HMT82GV7AMR4A - Heat Spreader
Front
29 29
18.75±0.15
12.3 13.3
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
SPD/TS
1 120
127
Back
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
SPD/TS
240 121
Detail of Contacts A Detail of Contacts B Detail of Contacts C

Side
0.80± 0.05 7.65mm max
2.50
9.8
0.4
8.5
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~1.0
1.00
1.50 ±0.10
6.2mm
5.00
1.27±010mm
max
Note:
2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
Rev. 1.1 / Mar. 2014 67

4Gx72 - HMTA4GV7AHR4A
Front
2.10±0.15 14.90
Detail C 13.60
18.75±0.15
3±0.1
Clock Driver
Registering
15.80±0.1
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
3±0.1
1 120 8.00±0.1
2X3.0±0.10
5.175 47.00 71.00

Detail A Detail B
128.95
133.35
Back
SPD/TS
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
QDP
240 121
2x R0.75 Max
Side
0.80± 0.05
2.50
14.90
0.4
13.60
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~0.1
1.00
1.50 ±0.10
5.00
1.27±010mm
max
Note:
Units: millimeters
Rev. 1.1 / Mar. 2014 68

4Gx72 - HMTA4GV7AHR4A - Heat Spreader
Front
29 29
18.75±0.15
12.3 13.3
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
SPD/TS
1 120
127
Back
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
DDP
SPD/TS
240 121
Detail of Contacts A Detail of Contacts B Detail of Contacts C

Side
0.80± 0.05 7.85mm max
2.50
9.8
0.4
8.5
0.3 ±0.15
2.50±0.20
3.80
2.50±0.20
0.35
0.05
0.3~1.0
1.00
1.50 ±0.10 6.5mm
5.00
1.27±010mm
max
Note:
2.In order to uninstall FDHS, please contact sales administrator.
Units: millimeters
Rev. 1.1 / Mar. 2014 69

Computing Ds 4Gb DDR3L (A-Ver) Based VLP RDIMMs (Rev.1.1)

Transféré par

Informations du document

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Computing Ds 4Gb DDR3L (A-Ver) Based VLP RDIMMs (Rev.1.1)

Transféré par

Droits d'auteur :

Formats disponibles

240pin DDR3L SDRAM VLP Registered DIMM

DDR3L SDRAM VLP

Rev. 1.1 / Mar. 2014 1

Revision No. History Draft Date Remark

1.0 Initial Release May.2013

1.1 module line-up arranged Mar.2014

Rev. 1.1 / Mar. 2014 2

• Power Supply: VDD=1.35V (1.283V to 1.45V)

HMT451V7AFR8A-H9/PB/RD 4GB 512Mx72 512Mx8(H5TC4G83AFR)*9 1 X

HMT41GV7AFR4A-H9/PB/RD 8GB 1Gx72 1Gx4(H5TC4G43AFR)*18 1 X

HMT41GV7AFR8A-H9/PB/RD 8GB 1Gx72 512Mx8(H5TC4G83AFR)*18 2 X

HMT82GV7AMR4A-G7/H9/PB 16GB 2Gx72 DDP 2Gx4(H5TC8G43AMR)*18 2 O

HMTA4GV7AHR4A-G7/H9 32GB 4Gx72 QDP 4Gx4(H5TCAG43AHR)*18 4 O

* In order to uninstall FDHS, please contact sales administrator

Rev. 1.1 / Mar. 2014 3

DDR3L-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7

13.5 13.5 49.5

13.75 13.75 48.75

13.91 13.91 47.91

-G7 800 1066 1066

-H9 800 1066 1066 1333 1333

-PB 800 1066 1066 1333 1333 1600

-RD 800 1066 1066 1333 1333 1600 1866

4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 32GB(4Rx4)

Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms

Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15

Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2

Page Size 1KB 1KB 1KB 1KB 1KB

Rev. 1.1 / Mar. 2014 4

A12/BC Address Input/Burst chop 1 VSS Ground 59

BA[2:0] SDRAM Bank Addresses 3 VREFDQ Reference Voltage for DQ 1

SA[2:0] SPD Address Inputs 3 VDDSPD SPD Power 1

Rev. 1.1 / Mar. 2014 5

VREFDQ Supply Reference voltage for DQ0-DQ63 and CB0-CB7.

Selects which SDRAM bank of eight is activated.

VTT Supply Termination Voltage for Address/Command/Control/Clock nets.

Rev. 1.1 / Mar. 2014 6

Rev. 1.1 / Mar. 2014 7

NC = No Connect; RFU = Reserved Future Use

Rev. 1.1 / Mar. 2014 8

NC = No Connect; RFU = Reserved Future Use

Rev. 1.1 / Mar. 2014 9

Symbol Parameter Conditions Min Typ Max Unit

Input capacitance, Data inputs 1.5 - 2.5 pF

Input capacitance, RESET, MIRROR,

Input & Output Timing Requirements

Input clock fre- Application fre-

Input clock fre-

Input valid before

Rev. 1.1 / Mar. 2014 10

Connection of Thermal Sensor

Temperature-to-Digital Conversion Performance

Parameter Condition Min Typ Max Unit

Temperature Sensor Accuracy (Grade B) Monitor Range,

-20°C < TA < 125°C - ± 2.0 ± 3.0 °C

Rev. 1.1 / Mar. 2014 11

DM3/DQS12_t TDQS_t DM5/DQS14_t TDQS_t

DQS2_t DQS_t ZQ DQS6_t DQS_t ZQ

DM2/DQS11_t TDQS_t DM6/DQS15-t TDQS_t

DQS1_t DQS_t ZQ DQS7_t DQS_t ZQ

DM1/DQS10_t TDQS_t DM7/DQS16_t TDQS_t

1.DQ-to-I/O wiring may be changed within byte.

S0_n RS0A_n → CS0_n: SDRAMs D[3:0], D8