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QID UNIT QUESTION a b c d ANS

1 1 Which of the following operation is performed by micro-processor to i/o read i/o write memory write memory read a
get data from input device?
2 1 Which of the following operation is performed by micro-processor to i/o read i/o write memory write memory read c
write data into memory device?
3 1 Address lines of micro-processor are? Input lines output lines bi-directional none of the b
lines above
4 1 Data bus lines of micro-processor are? Input lines output lines bi-directional none of the c
lines above
5 1 8086 micro-processor is a? bit processor 16-bit processor 32-bit none of the b
processor above
6 1 Size 8of 8086 queue is? 4-bytes 6-bytes 8-bytes 16-bytes b
7 1 Most important advantage of segmentation scheme of 8086 is? It can access it can address its programs none of the c
more memory more i/o are re- above
locatable
8 1 Number of flags present in the flag register of 8086 micro-processor 3 5 6 9 d
is?
9 1 Number of memory locations that can be addressed by an 8086 64KB 1MB 16MB 16CB c
micro-processor is?
10 1 The size of a segment in 8086 is? 64KB 1MB 16MB 16GB a
11 1 The physical address of the memory location specified is 1000:1000H 10000H 11000 10100H 10001H b
is?
12 1 The physical address of the memory location containing the CS AND IP DS and DX SS and SP both a and c d
instruction code for next execution is stored in which one of the Register registers registers
following pair of registers?
13 1 If an I/O port is accessed via variable type addressing, the width of 8-bit 16-bit 20-bit none of the b
the port address is- above
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QID UNIT QUESTION a b c d ANS
14 1 If an I/O port is accessed via fixed type addressing, the width of the 8-bit 16-bit 20-bit none of above a
port address is-
15 1 The width of address bus of 8086 microprocessor is 8-bit 16-bit 19-bit 20-bit d
16 1 The width of data bus in 8086 microprocessor based system is 8-bit 16-bit 19-bit 20-bit b
17 1 The number of pins in 8086 microprocessor is 24 28 40 64 c
18 1 Which one of the following signals is activated by microprocessor ALE BHE INTA DEN b
when it is used D15-D8 lines for data transfer?
19 1 When the microprocessor uses D15-D8 data bus lines for data Low high may be low of none of above a
transfer, the signal level on A0 line should be high
20 1 If the signal level on M/IO pin is low, RD is high and WR pin is low, it memory read memory write i/o read i/o write d
means the microprocessor is performing operation
21 1 If the signal level on M/IO pin is high, RD is low and WR pin is high, it Memory read Memory write i/o read i/o write a
means the microprocessor is performing operation
22 1 Which one of the following pairs of signals is during DMA? INTR and INTA HOLD and HLDA DT/R and DEN RD and WR b
24 1 Which one of the following signals is used for interfacing slow CLK RESET READY none of above b
memory or I/O devices to the microprocessor?
25 1 Which one of the following signals is used for demultiplexing address READY ALE DT/R DEN b
and data bus signals?
26 1 Which one of the following signals indicates the direction of data DT/R DEN ALE M/IO b
flow on the data bus?
27 1 When an I/O port is accessed by its 8-bit I/O address the signal level Low on all 8 high on all 8 the level of high- a
on A15-A8 address lines would be lines lines A7-A0 impedance(float
lines(duplicat )
es)
28 1 How many input/output ports are possible in 8086 based system 256 512 32K 64K d
29 1 Which one of the following microprocessor multiplexes address and 8086 80286 80386 80486 a
data bus signals?
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QID UNIT QUESTION a b c d ANS
30 1 The function of BIU are It fetches It reads data It also writes All of these d
instruction from memory data from
from memory and ports memory and
ports
31 1 The function of EIU are It decodes the It executes the EU takes care All of these d
fetched decoded of performing
instructions. instructions. operations on
the data
32 1 _______ unit is called the external world interface of the processor BIU EU both a and b none of these a
33 1 _______ unit is called the execution heart of the processor. BIU EU both a and b none of these b
34 1 ______ unit takes care of all the address and data transfer on the EU BIU paging unit segmentation b
buses. unit
35 1 The BIU consists of ____. Segment Instruction Instruction All of these d
registers queue pointer
36 1 _____ unit takes care of performing operations on data. EU BIU both a and b none of these a
37 1 _____ unit works in synchronous with machine cycles. paging unit EU BIU all of these c
38 1 ______ unit works in synchronization with clock. segmentation paging bus interface Execution d
39 1 Segment registers in 8086 are ____. 16 bit 8 bit 32 bit 24 bit a
40 1 A segment is a logical unit of memory that may be upto _____ bytes 4 KB 1 MB 8 KB 64 KB d
long.
41 1 The segment can be _____ Adjacent overlapping disjoint all of these d
42 1 _____ provides a powerful memory management mechanism. Segmentation paging both a and b none of these c
43 1 _____ provide a way to easily implement object-oriented programs. Segments pages programs none of these a
44 1 ______ allows two processes to easily share data. Segments registers both a and b none of these a
45 1 _____ makes it possible to separate the memory areas for stack, Paging segmentation both a and b none of these b
code and data.
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46 1 The ____ pair gives the address of the next instruction to be CS:IP DS:IP ES:IP SS:BP a
executed in the program sequences.
47 1 The ____ pair gives the address of the top of the stack. SS:SP DS:IP ES:IP SS:BP d
48 1 The ____ pair gives the address of the top of the stack. CS:IP DS:IP ES:IP SS:BP d
49 1 ___ is used for random access of the stack. BP AX IP BX a
50 1 The ____ pair is used as source pointer for string instructions. DS:SI DS:EI both a and b none of these a
51 1 The ____ pair is used as destination pointer for string instructions ES:DI ES:SI both a and b none of these a
52 1 A flag is a _____. Flipflop register both(a) and(b) none of these c
53 1 Flag register cosists of ____ active flags out of sixteen. Nine six four two a
54 1 Setting ____ puts the processor into single step mode for debugging. Sign Flag(SF) Interrupt Direction Trap Flag(TF) d
Flag(IF) Flag(TF)
55 1 Trap flag used by debuggers for____. Single step Double stepping Both(a) None of these a
operation. and(b)
56 1 ____ bit is specifically for string instructions. Sign flag(SF) Interrupt Direction Trap flag(TF) c
flag(IF) flag(DF)
57 1 If DF=___, the string instruction will automatically I decrement the 1 0 2 3 a
pointer(s).
58 1 If DF=___, the string instruction will automatically increment the 0 1 2 3 a
pointer(s).
59 1 ____ flag is normally used to check for data transmission errors. Sign zero Parity all of these c
60 1 PF=____ low byte has an even parity. 1 0 2 3 a
61 1 PF=____ low byte has an odd parity. 1 0 2 3 b
62 2 The ______instruction of the 8086 can be used to do one of the 256 INTR INT N NMI all of these b
soft interrupts.
63 2 with the help of the ______we can call the routines from different hardware software error all of these b
programs in the system e.g BIOS. interrupt interrupt conditions
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QID UNIT QUESTION a b c d ANS
64 2 The 8086 can handle upto____different interrupt types. 128 256 512 1024 b
65 2 INT stands for_____. Input interrupt both a and b none of these b
66 2 A hardware interrupt is ______. Also called as Also called as An I/O A clock a
internal external interrupt. interrupt.
interrupt. interrupt.
67 2 Interrupts are classified as_____. Hardware Software Hardware None of these c
interrupts interrupts interrupts and
software
interrupts
68 2 what is meant by maskable interrupts? An interrupt An interrupt An interrupt An interrupt a
that can be that cannot be that can be that cannot be
turned off by turned off by turned off by turned off by
the the the system. the system.
programmer. programmer.
69 2 which interrupts are generally used for critical events such as power Maskable Non-Maskable Vectored None of the b
failure, emergency, shut off etc? interrupts interrupts interrupts above
70 2 In the interrupt instructions of the type INT n,the maximum value of 255 63 127 31 a
n is_____.
71 2 The registers which are pushed into the stack by the INT n CS IP Status register a and b d
instruction or hardware interrupts before entering into an ISR
are____.
72 2 After entering the ISR, the flags og 8086 which are cleared are_____. Trap IE DF CY a
73 2 If an ISR is to be executed after the execution of every instruction of enabled disabled ignored none of these c
a main program, the flag of 8086 which is to be set to be 1 is______.
74 2 When an interrupt occurs, the processor compleates the current microinstructio instruction it is macro it is subroutine it is b
_____before jumping to the interrupt service subroutine. n it is executing executing executing
executing
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QID UNIT QUESTION a b c d ANS
75 2 The value of the IP and CS registers corresponding to the interrupt n*0048 n*0004 both b and d n*0004+2 c
service routine(ISR) of the instruction INTo is obtained from the
location _______.
76 2 The mnemmic for the instruction which generates an interrupt if the INTO INT1 INT0 INT2 a
result of an arithmetic operation exceeds the capacity of the register
used for storing the result is
77 2 If an attempt is made to divide a number by 0 the INT n instruction is 0 1 3 4 a
executed where n is _______.
78 2 The interrupt which causes the ISR to be entered after the execution 0 1 3 4 b
of each instruction of main program is called type _______interrupt.
79 2 The ISR corresponding to the non-maskable interrupt can also be 1 2 3 4 b
executed using the INT n where n is _______.
80 2 The ISR corresponding to a breakpoint can be executed using the INT 0 1 2 3 d
n where n is _______.
81 2 In 8086 the following has the highest priority among all the NMI Division by zero TYPE 255 OVERFLOW b
interrupts.
82 2 the interrupt type which has highest priority for receiving service is INTR INTO INT n NMI d
_____.
83 2 The interrupt type which has lowest priority for receiving service is Divide error Single step NMI INTR b
_____.
84 2 8259 chip works as a _____. Interrupt Microprocessor Microcontroll Timer a
controller er device
85 2 The external asynchronous input applied to the microprocessor is Timer counter Stack interrupt d
termed as an_____.
86 2 In 8086 we have _____ sources of interrupt. 1 2 3 4 c
87 2 ________ are the interrupt sources of 8086. Hardware Software Error All of these d
interrupt interrupt conditions
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QID UNIT QUESTION a b c d ANS
88 2 If the physical pins are provided in the chip… Hardware Software Error All of these a
interrupt interrupt conditions
89 2 The 8086 _______has hardware interrupt pins. 1 2 3 4 b
90 2 ________ interrupt cannot disabled. INTR All of these INT N NMI c
91 2 _______interrupt can be enabled and disabled using the CLI and STI INTR All of these INT N NMI a
instruction.
92 2 The last instruction in a subroutine program should be… JMP RET IRET Any instruction b
93 2 The last instruction in a interrupt service subroutine should be JMP RET IRET Any instruction c
94 2 Which one of the following interrupt occurs if trap flag is set? Divide by zero Single step Non maskable break point b
interrupt
95 2 When an interrupt signal is applied to NMI input pin of 8086 type-0 type-1 type-2 type-3 c
microprocessor ,which one of the following interrupt type occurs?
96 2 Memory location holding address of interrupt service routine of the 0000h-00003h 00008h-0000Bh 0001OH- 00020h-00022h d
type -08H are, 00013H
97 2 Which of hardware interrupt can be disabled through instructions? NMI INTR ---- ---- b
98 2 How many hardware interrupt request can be prosessed by a signal 8 15 16 64 a
interrupt controller IC 8259A
99 2 Among the following interrupt which one takes top priority? divide by zero NMI INTR single step a
100 2 Among the following interrupt which one takes least priority? divide by zero NMI INTR single step d
101 2 DMA request is usually initiated by? Peripheral microprocessor memory none of the a
above
102 2 Which one of the following register of the interrupt controller ISR IRR IMR ---- b
8259A,register interrupt request
103 2 61) SF=____ indicates msb is negative. 0 1 2 3 b
104 2 SF=____ indicates msb is positive. 0 1 2 3 a
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105 2 ____ flag is used by decimal arithmetic instructions. a) Auxiliary carry flag sign flag all of these a
carry(AF)
106 2 AH and AL registers can be used as ____ bit operands. 8 2 4 6 a
107 2 AX and BX registers can be used as ____ bit operands. 16 32 64 8 a
108 2 AX,BX,CX and DX are called as____. General Special registers Index Scaled registers a
purpose registers
registers
109 2 BX is the _____ register. Pointer scale index base d
110 2 CX is the _____ register. Counter for General Count All of these d
shift and rotate purpose
111 2 ____ register is used for string and loop operation. CX BX AX DX a
112 2 _____ register used for variable shift and rotate. AX BX CX DX c
113 2 DX is the ____register. Data rotate count shift a
114 2 ALU of 8086 is _____ bits. 8 16 20 24 b
115 2 For 16 bit address accesses of I/O ports only ___ can be used as DX AX BX CX a
pointer.
116 2 _____ is used for sequential access of stack segment. BX SP CX BP b
117 2 SP always points to the ____ of stack. Top bottom both(a) and(b) none of them a
118 2 _____ register is mainly used during instructions like BX AX SP BP c
PUSH,POP,CALL,RETURN,etc.
119 2 ____ register is used for holding the offset of a data word in the data DI AX BX AX d
segment (DS).
120 2 _____ register is used for holding the 16 bit offset of a data word in DI AX BX CX a
the extra segment (ES).
121 2 In 8086, the segment can begin at any memory address that is 4 8 16 32 c
divisible by ____.
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122 3 Registers may be used as ________. source destination both a and b none of these c
operands operands
123 3 If the source operand is a part of the instruction instead of register Immediate Register Direct Based a
or memory, it is referred as addressing mode. addressing addressing addressing addressing
mode mode mode mode
124 3 In ________ the effective address is taken from the displacement Indexed Register Register Based c
field of the instruction. addressing addressing realative addressing
mode mode addressing mode
mode
125 3 In _________ a base or indexed register contains the operands direct based indexed indexed register indirect b
effective address. addressing addressing addressing addressing
mode mode mode mode
126 3 In________ mode the contents of a base register are added to relative based scaled mode indexed mode all of these a
displacement, in order to obtain the operands effective address. mode
127 3 In ________ addressing mod ,an indexed register’s contents are direct indirect index mode based mode c
added to a displacement to obtain the operand’s effective address. addressing addressing
mode mode
128 3 In ______ mode the contents of an indexed register are multiplied by Scaled index based mode Indexed mode direct a
a scaling factor of (1,2,4 or 8) which is then added to the mode with addressing
displacement factor to obtain the operands effective address. displacement mode
129 3 For INT instruction, port address is stored in _________. AX BX CX DX d
130 3 ______instruction loads pointer from memory to ES. LSS LES LDS LGS b
131 3 ______instruction loads pointer from memory to DS. LSS LES LDS LGS c
132 3 ______instruction loads pointer from memory to FS LSS LES LDS LFS d
133 3 Which of these are data allocation directives? DD DT DQ All of these d
above
134 3 Which of these are not data allocation directives? DD DQ DT .CODE d
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QID UNIT QUESTION a b c d ANS
135 3 Which of these are segment directives? ASSUME END SEGMENT ALL OF THE d
ABOVE
136 3 The ______ instruction exchanges the contents of a register with XLAT XCHG NOT CWD b
contents of another register or the contents of a register with
contents of memory location.
137 3 _________ cannot directly exchange the contents of two memory XCHG CALL MOV XLAT a
locations.
138 3 The__________ instruction is used to translate a byte from one code MOV CALL XLAT POP c
to another code.
139 3 The ________instruction is intended for use when the operand-size PUSH POP XLAT all of these d
is 16 bits.
140 3 The _________instruction copies a word/double word from stack POP LGS MOV JN a
segment in memory to a destination specified in the instruction.
141 3 DB directives defines items that are _________ in length. WORD DOUBLE WORD BYTE QUAD WORD c
142 3 DW directives defines items that are _________ in length. double word word byte quad word b
143 3 DT is used to defines item that are _________ long. 8 bytes 4 bytes 2 bytes 10 bytes d
144 3 DD directive defines item that are _________ in length. double word word byte quad word a
145 3 _______ indicates the end of the segment. ENDP ENDM ENDS none of these c
146 3 _________ instruction copies the contents of AH register to the SAHF LAHF CLI STD a
lower byte of flag register.
147 3 ___________ informs the assembler to determine the offset or OFFSET ENDP PTR SHORT a
displacement of a named data item
148 3 ___________ is the only language understood directly by the CPU in Machine assembly high level all of these a
our computers. language language language
149 3 Assembly language is a __________ representation of machine code. opcode algorithm mnemonic program c
150 3 The first part of an instruction which specifies the task to be opcode operand instruction fetch cycle a
performed by the computer is called ___________. cycle
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QID UNIT QUESTION a b c d ANS
151 3 The second part of the instruction is the data to be operated on, and opcode operand instruction fetch cycle b
it is called________. cycle
152 3 _______ stores the ASCII codes for the letter and numbers in the Editor Linker Assembler Loader a
successive RAM locations.
153 3 The source file has a _______ extension given to it. .COM .OBJ .ASM .EXE c
154 3 __________ is a program which translate the assembly language Editor Linker Assembler Loader c
mnemonics into corresponding into corresponding binary codes.
155 3 assemblers available for assembling the programs for PC are: Microsoft ASM-86 Borland turbo all of the above d
micro assembler(TA
assembler SM)
(MASM)
156 3 ____________ can be used to check and correct the program till al Editor Debuger Assembler Loder b
errors are corrected.
157 3 _______containes the binary codes of the program instructions and .COM .ASM .OBJ .EXE c
the information about the addresses of the instructions.
158 3 _______contains the assembly language statements,the binary .COM .LST .OBJ .EXE b
codes of each instruction and the offset of each instruction.
159 3 If we take a print of the _______file, syntax errors in the assembly .COM .LST .OBJ .EXE b
program can be observed.
160 3 errors indicated by the assembler should be modified using the Editor Linker Assembler Loader a
_______.
161 3 If there are no errors in the program __________file is generated by .COM .LST .OBJ .EXE c
the assembler.
162 3 _________ is a program which is used for joining many object files Editor Linker Assembler Loader b
into one large object file.
163 3 The linker produces a _________ file that contains the binary codes object list assembler link d
for all the combined modules.
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QID UNIT QUESTION a b c d ANS
164 3 The linker produces a _________ file that has addresses of all linked .COM .MAP .OBJ .EXE c
files.
165 3 ________ is a program that transfers the program to be executed Editor Linker Assembler Loader d
from the secondary memory into memory accessed by the
microprocessor.
166 3 ________is used to detect the source of program or script error ,by Editor Debugger Assembler Loader b
performing step by step execution of application code and viewing
the content of code variables.
167 3 The __________permits the change in register contents , memory Editor Debugger Assembler Loader b
location and return the program.
168 3 With the help of the _________we can stop the program execution Editor Debugger Assembler Loader b
after each instruction so that we can check or alter the memory and
register contents.
169 3 ____________ can be used to check and correct the program till al Editor Debugger Assembler Loader b
errors are corrected.
170 3 The ___________is used to test and debug the hardware and Editor emulator Assembler Loader b
software of an external system such as the microprocessor based
system.
171 3 _______ is a combination of hardware and software. Editor emulator Assembler Loader b
172 3 _________consists of a multi-wire cable that connects the host Editor emulator Assembler Loader b
system to the exeternal System.
173 3 A _______ specifies the operation to be executed. mnemonic algorithm a and b none of these a
174 3 Assembly language consists of _______ type of statements 1 2 3 4 b
175 3 Following are the assembly language statements Executable Assembler Syntax a and b d
statements directives statements
176 3 For physical address generation the contents of segment register are 4 bits right 2 bits right 4 bits left 2 bits left c
shifted by _____.
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177 3 ___________ are the statements that direct the assembler to do Executable Assembler Syntax a and b b
something. statements directives statements
178 3 _______ are effective only during the assembly of a program but Executable Assembler Syntax a and b b
they do not generate any code that is machine executable. statements directives statements
179 3 Which of these are simplified segment directives? .DATA .CODE .MODEL All of these d
180 3 Which of these are simplified segment directives? .STACK .CODE .MODEL All of these d
181 3 Which of these are simplified segment directives? .CONST .EQU .DB All of these a
182 3 Which of these are simplified segment directives? .EXIT .DW .DB All of these d
183 3 Which of these are data allocation directives? EQU DB DW All of these d
184 3 Which of these are data allocation directives? DD DQ DT All of these d
185 3 Which of these are segment directives? ASSUME END SEGMENT All of these d
186 3 Which of these are segment directives? GROUP END SEGMENT All of these d
187 3 Which of these NOT are segment directives? GROUP END .DATA ASSUME c
188 3 Which of these are macro directives? MACRO ENDM LOCAL All of these d
189 3 Which of these CODE label directives? ALIGN EVEN LABEL All of these d
190 1 8088 is a………..bit processor. 4-bit 8-bit 16-bit 32-bit b
191 1 …..number of conditional flags in 8086 flag register format. 3 6 9 11 b
192 1 Microprocessor is multipurpose ……. device programmable programmable logic none of the a
logic above
193 1 Microprocessor is ……..of the computer system heart hands brains none of the c
above
194 1 8085 is an …...bit processor. 4 16 8 64 c
195 1 8085 has …...bit accumulator 4 8 16 32 b
196 1 8085 can operate with ……..MHz clock frequency. 5 2 1 3 d
197 1 8086 requires a single ……... power supply. +5V -5V +12V -12V a
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QID UNIT QUESTION a b c d ANS
198 1 8086 has ……. address lines. 10 40 20 16 c
199 1 8086 provides …..., 16- bit register. 10 11 13 14 d
200 1 8088 instruction queue is………bytes. 2 4 6 8 b
201 1 EU and BIU work in parallel with the bus interface unit keeping ….. one two three four a
step ahead.
202 1 …..number of 8085 compatible flags 3 4 5 6 c
203 1 AD0 to AD14 of 8086 are ……lines input output both a and b none of the a
above
204 1 HOLD AND HLDA are………signals minimum maximum mode both a and b none of the a
mode above
205 1 QS0 AND QS1 are …….signals. minimum maximum mode both a and b none of the b
mode above
206 1 When MN/MX= 1 processor operates in ………... mode . minimum maximum both a and b none of the a
above
207 1 When MN/MX= 0 processor operates in ………... mode . minimum maximum both a and b none of the b
above
208 1 The offset address values are from………………. 0000 H to FFFF 00000 H to 00001 H to none of the a
H FFFFF H FFFF1 H above
209 1 the physical addresses range from ………….… 0000 H to FFFF 00000 H to 000001 H to none of the b
H FFFFF H FFFFF 1H above
210 2 Divide by zero interrupt is a…….. Type 1 Type 2 Type 3 Type 0 d
211 2 Single step interrupt is a ……. Type 4 Type 3 Type 1 Type 2 c
212 2 Non maskable interrupt (NMI ) is a……… Type 2 Type 1 Type 3 Type 4 a
214 2 Breakpoint interrupt is a ……… Type 3 Type 2 Type 4 Type 0 a
215 2 Overflow interrupt is a ……… Type 0 Type 1 Type 2 Type 4 d
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QID UNIT QUESTION a b c d ANS
216 2 A common application for the NMI input is to ………...data in the save critical delete critical both a and b none of the a
event of power failure . above
217 2 8259A is a……. Programmable Programmable both a and b none of the a
interrupt peripheral above
controller interface
218 2 Type 0 – Divide by 0 Trap flag single reserved for reserved for a
stepping NMI INT3 single byte
instruction
219 2 Type 1 – Divide by 0 Trap flag single reserved for reserved for b
stepping NMI INT3 single byte
instruction
220 2 Type 2 – Trap flag single reserved for reserved for reserved for b
stepping NMI INT3 single INTO instruction
byte
instruction
221 2 Intel has reserved …... locations for storing IVT . 2024 1024 2064 1016 b
222 2 For 8086 , IVT starts at ………… 0000:0FFF H 0000:00FF H 0000:0000 H 0000:000F H c
223 2 For 8086 , IVT ends at ……….. 0000:03FF H 0000:0FFF H 0000:F3FF H 0000:FF3FFH a
224 2 The IVT contains ……. of all interrupt types. CS & SP SS & SP SP & DS IP & CS d
225 2 To manipulate the ISR address , the type no. is multiplied by …... 2 4 6 8 b
226 3 Identify the addressing mode of following instruction : MOV AX , direct immediate rgister none of the b
0005H above
227 3 Identify the addressing mode of following instruction:MOV AX ,[ direct immediate register none of the a
5000H] above
228 3 Identify the addressing mode of following instruction:MOV AX ,BX direct indirect register indexed c
229 3 Identify the addressing mode of following instruction:MOV AX , [BX] Register direct immediate indexed a
indirect
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QID UNIT QUESTION a b c d ANS
230 3 Identify the addressing mode of following instruction:MOV AX , register register relative direct immediate b
50H[BX] indirect
231 3 Identify the addressing mode of following instruction:MOV AX , [SI] indexed direct immediate none of the a
above
232 3 Identify the addressing mode of following instruction:MOV AX , based indexed base indexed none of above c
[BX][SI]
233 3 Identify the addressing mode of following instruction:MOV AX , relative based relative based direct none of the a
50H[BX][SI] indexed above
234 3 VAL1 DB ? is a …… Uninitialized initialized ----- ----- a
235 3 VAL2 DB 32 is a…... Decimal binary constant hex Constant none of the a
Constant above
236 3 VAL3 DB 20H is a….. Hexadecimal decimal binaryConstan none of the a
Constant Constant t above
237 3 VAL4 DB 10 DUP(0) is a….. five 0’s Ten 0’s eight 0’s none of the b
above
238 3 MOV destination , source Copies word Exchanges Copies data none of the c
from source to source and from source above
stack . destination to destination
.
239 3 LEA register , source Copies 2 Copies 2 Loads none of the c
consecutive consecutive effective above
words from words from address of
memory to memory to source into
register and ES register and DS register .
240 3 LDS register ,memory Loads effective Copies 2 Copies 2 none of the b
address of consecutive consecutive above
source into words from words from
register . memory to
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QID UNIT QUESTION a b c d ANS
memory to register and
register and DS ES
241 3 LAHF Load AH from Store AH to Push flags to none of the a
lower byte of lower byte of stack above
flag flag register .
242 3 PUSHF Pop flags from Push flags to Store AH to none of the b
stack stack lower byte of above
flag register .