2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

Implementation of Low Delay Dual Chamber

Pacemaker Using Verilog

Sonali Ray
Electronics & Communication Engg. Dept.
MNNIT Allahabad Meenakshi Sharma
Prayagraj, India Electronics & Communication Engg. Dept.
sonalirai15@gmail.com MNNIT Allahabad
Prayagraj, India
Rohini Srivastava meenakshi.pulastya@gmail.com
Electronics & Communication Engg. Dept.
MNNIT Allahabad Nitin Sahai
Prayagraj, India Biomedical Engineering Department
rohini@mnnit.ac.in North East Hill University (NEHU)
Shillong, India
R.P. Tewari nsahai@nehu.ac.in
Applied Mechanics Dept.
MNNIT Allahabad Dinesh Bhatia
Prayagraj, India Biomedical Engineering Department
rptewari@mnnit.ac.in North East Hill University (NEHU)
Shillong, India
Basant Kumar bhatiadinesh@rediffmail.com
Electronics & Communication Engg. Dept.
MNNIT Allahabad
Prayagraj, India
singhbasant@mnnit.ac.in

heart rate below 60 beats per minute. Arrhythmia can cause

cardiac arrest and sudden death if not treated properly.
Abstract—This paper presents a hardware implementation of Therefore, for proper detection of arrhythmia, both the right
Dual Chamber Cardiac Pacemaker for different ranges of heart chambers: right atrium and right ventricles must be sensed and
beats with minimum delay. Proposed research work attempts to paced. For this purpose dual chamber pacemaker are used.
design and implement a low delay dual chamber demand
pacemaker. Pacemakers are used for life-threatening disease
such as arrhythmia. A minimum delay between sensing and
pacing is very crucial for maintaining the adequate heart rate.
Therefore the main motive of this work is to reduce the delay
between sensing and pacing of the pacemaker. The demand
pacemaker works in accordance with the heart rate of the patient
who is suffering from arrhythmia and its range may be different
for different patients. The range from 30 beats per minute (bpm)
to 70 beats per minute (bpm) has been taken for the proposed
work. The tool used for the proposed low delay dual chamber
pacemaker is Xilinx 14.7. The result shows that the proposed
work is better in terms of delay, computational complexity, and
cost.

Keywords—Dual chamber pacemaker, demand pacemaker

arrhythmia, Verilog.

I. INTRODUCTION
Fig. 1. AV delay. (a) and (c) Paced AV delay in a dual chamber pacing
The pacemakers are used for the patients who are suffering
mode. (b) and (d) Sensed AV delay in a triggered mode.
from bradycardia; a type of arrhythmia. Bradycardia is the

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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

The heart rate due to physiological contraction of atria and flowchart for the implementation of low delay dual chamber
ventricles, is detected synchronously by the electrodes of the pacemaker is shown in Fig.2. The work process, mentioned in
dual chamber pacemaker. Fig.1 shows the atrio-ventricular the flow chart is repeated for the different ranges of heart beat.
(AV) delay of the dual chamber pacemaker. Fig 1(a) and Fig Algorithm and the flow chart for the proposed work are shown
1(b) show the AV delay which is shorter than the intrinsic below:
conduction. The pacing stimulus is delivered by the pulse At negative edge of Clock A
generator of the pacemaker at the end of the AV delay. Fig 1(c) 1. Sense A → 1
and Fig 1 (d) represent a longer delay and before the end of the
delay, the intrinsic QRS is sensed and ventricular pacing is 2. Check if Beat A = 1
inhibited [1]. It can be seen from the Fig 1, if the delay of the 3. If Yes Pace A =0, else Pace A =1 and Sense
pacemaker increases, one QRS complex may skip to be paced. A →0
Thus, in this paper our motive is to reduce the delay between • At negative edge of Clock V
sensing and pacing of the right chambers of the heart. A person
with 72 beats per minute will have one ECG beat of 0.8 second 4. Sense V → 1
duration. A pacemaker, whether a single chamber or dual 5. Check if Beat V = 1
chamber, waits for 0.8 seconds and then sends a stimuli to the 6. If Yes Pace V =0, else Pace V =1 and Sense
heart if internal pacing is absent. In spite of the delay another V →0
important parameter of the pacemaker is the heart beat range.
This range defines the degree of the blockage of the heart: first • Clock V is delayed version of Clock A
degree, second degree and third degree (complete) heart block. Beat A and Pace A are low power signals compared
Among all of these three degrees of blocking, third degree is to Beat V and Pace
the most life threating blocking as in this none of the electrical
impulse reaches from SA node to AV node [2].
Clock goes from 1 ࡳ› 0
Roopa T.et.al.[3] presented a hardware implementation of
single and dual chamber pacemaker using Verilog on Xilinx
14.1. They have generated ECG on Modelsim and delivered
the delay between sensing and pacing of 3.842 ns for dual Sense=1
chamber pacemaker. But the simulation was performed for the
heart beat ranging from 35-125 bpm at the interval of 20 bpm.
In the proposed work we have taken the heart beat interval of
10 bpm. Omkar et.al. [4] presented a hardware implementation
of pacemaker for different modes, but they delivered much Beat=1 Pace=0
larger delay between sensing and pacing as compare to the
proposed work. The delay is a critical parameter in the design
of the pacemaker, as a larger delay may become one of the
causes for the patient’s death. Thus the algorithm designed in
the proposed work attempts to minimize the time consumption Pace=1

in the execution for the sensing and pacing. The proposed

scheme is performed on Inbuilt Simulator (ISIM), which is
having the advantage of cost reduction, as testing and
implementation are done at the same platform. Rest of the
paper is organized as follows: section II presents the proposed
methodology for the hardware implementation. Section III
presents the experimental results. Conclusion and future scope
for the proposed scheme are presented in section IV and V
respectively.
II. PROPOSED WORK
This section presents the design steps for the proposed dual
chamber demand pacemaker along with its flowchart. The four
steps are taken for the designing of the dual chamber
pacemaker: beat, clock, sense and pace. Beat is the heart beat
coming from the heart. Clock provides reference timing at
which to sense the deviation from regular heartbeat. Sense is
active for short duration at every negative edge of clock and the
pace is the output of the pacemaker when sense becomes active.
Clock is used for the detection of internal pacing whereas sense
is used as a controlling signal for the pacemaker. Design
Sense=0
Fig. 2. Flowchart for the proposed scheme
In this work we start the process with negative edge of the
clock, as negative going edge is more power saving than the
positive edge clock. The sensing is used to check the heart beat
range according to the clock. More deviation from the regular
heart beat (72 bpm) will require more frequent external pacing:
time interval between two external pacing will be less.
III. EXPERIMENTAL RESULTS
The proposed work is implemented for four different range
of heart beats: 30-40 bpm, 40-50 bpm, 50-60 bpm and 60-70
bpm by look-up tables (LUT) generated in Xilinx. The test
bench forms of the proposed work are shown in figures from
Fig.3. to Fig.6.

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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

Fig. 3 shows the simulation result for the heart beat range 30-
40 bpm, the atrial and pacing cycle duration is high for this
range. Fig 3 to Fig 6 show the beat range selected from one of
the (a,b,c,d) wave forms and pacing of atria/ ventricles
according to these beat ranges. The Register-Transfer-Level
(RTL) of the dual chamber demand pacemaker is shown in Fig.
7.

Fig. 3. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 30-40 bpm

Fig. 4. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 40-50 bpm

Fig. 7. RTL of Dual Chamber Demand Pacemaker

The device utilities describe the internal circuit details for

Fig. 5. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 50-60 bpm
the hardware design e.g. Look up Tables (LUTs), Flip flops
etc. Less percentage of device utility will result in compact and
economical hardware design. The selected device for the
proposed dual chamber demand pacemaker- Spartan 3E. The
proposed design have maximum frequency support up to 1
GHz. The detailed description of the experimental result is
shown in TABLE I.

TABLE I. EXPERIMENTAL RESULT DESCRIPTION

Number of Slices 2 out of 4656

Number of 4 Input LUTs 4 out of 9312

Number of Inputs outputs 7

Number of slice Flip flop 5out of 9312

Number of bonded Input Output Buffers 6 out of 232

Fig. 6. Sensing and pacing timing diagram of Dual Chamber Pacemaker for
heart beat range from 60-70 bpm

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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

The implementation was performed by generated LUTs of

The existing works [3],[4] have proposed dual chamber
pacemaker implementation using VHDL The delay in both the
existing works are much larger than the proposed work.
Comparison between the reported work and the proposed
work is shown in TABLE II.
Xilinx for different range of heart beats. The experiments
shows that the proposed technique is quite cost effective as the
testing and implementation is performed using single software.
The proposed work is also having the advantages of less power
consumption and computational complexity as shown in TABLE
II.

TABLE II. COMPARISON OF THE PROPOSED WORK WITH THE REPORTED V. FUTURE WORK
WORK [3] IN DEVICE UTILITY

Device Comparison with Reported work

Utilization
The proposed work will be tested by giving ECG signals as
Reported work[3] Proposed Work
input. This ECG signal as the input to the pacemaker can
No. of 1685 out of 2 out of
slices 1792
91%
4656
0.042% either be generated using VHDL or can be applied externally
No. of 4 to the pacemaker for obtaining more accurate results. Rate
3152 out of 4 out of 0.043%
input
3584
86%
9312 adaptive pacemaker can also be designed by incorporating
LUTs some modification in the proposed work. Further, hardware
No. of slice 29 out of 5 out of
flip flops 3584
0.81%
9312
0.053% implementation of the proposed design will be done using
No. of VIVADO and FPGA.
bonded
6 out of ACKNOWLEDGMENT
Input 31 out of 68 46% 2.58%
232
Output
Buffers This research work is the part of the funded project,
“Design of Neural Network based Pacemaker” sponsored by
the Department of Biotechnology, Govt. of India. The authors
are grateful to the funding agency.
As it can be seen from the TABLE II that the proposed work
performs much better than the reported work from all type of
design perspective. As the computational complexity is
REFERENCES
reduced, the power consumption will also reduce for the
[1] Malcolm Kirk (2006). Basic Principles of Pacing,(Ch.1) pg 1–28.:
proposed work. Comparison between delay in the reported Implantable Cardiac Pacemakers and Defibrillators; BMJ publishers.
work [3] and the proposed work is shown in TABLE III. [2] Mayo Clinic Staff. (2017). Bradycardia - Symptoms and causes - Mayo
Clinic. Retrieved from http://www.mayoclinic.org/diseases-
conditions/bradycardia/symptoms-causes/dxc-20321638
TABLE III. TIMING ANALYSIS FOR THE EARLIER WORK AND THE
[3] Roopa, T., Manjula, B. M., & Sharma, C. (2014). Implementation of a
PROPOSED WORK
Pacemaker for Biomedical Application, 3(6), 2780–2785.
Timing Analysis Reported Proposed [4] Dwivedi, O., & Srivastava, G. (2015). Design and Implementation of
Work[3] Work programmable Cardiac Pacemaker Using VHDL, 5(5), 155–158.
[5] The ECG of Cardiac Pacemakers, Basic and Bedside
Minimum period 3.842ns 3.157ns Electrocardiography, 1st Edition (2009) Chapter 26.
[6] Halperin, D. (2008). Pacemakers and Implantable Cardiac
Minimum input arrival time before 12.309ns 3.317ns De¿brillators_ Software Radio Attacks and Zero-Power Defenses.pdf.
clock IEEE Symposium on Security and Privacy, 1–14.
https://doi.org/10.1109/SP.2008.31
[7] Nancy, L. (2012). The Pacemaker Challengeௗ: Developing Certifiable
Minimum output required time after 15.225ns 4.532ns
Medical Devices Edited by, 4(2), 17–37.
clock https://doi.org/10.4230/DagRep.4.2.17
[8] Barker, C., Kwiatkowska, M., Mereacre, A., Paoletti, N., & Patan, A.
(2015). Hardware-in-the-loop simulation and energy optimization of
The results presented in Table 3 shows the difference between cardiac pacemakers, 7188–7191.
https://doi.org/10.1109/EMBC.2015.7320050
the delays of the reported work and the proposed work. The
average reduction in overall delay is about 54%. In the [9] Chede, S., & Kulat, K. (2008). Design overview of processor based
implantable pacemaker. Journal of Computers, 3(8), 49–57.
reported work [4] the variable delay for AV node was https://doi.org/10.4304/jcp.3.8.49-57
mentioned 180msec which is very much larger than the delay [10] Chen, G. M., Engineering, B., & Fellow, S. (2000). Model - Based
achieved in proposed work. Conformance Testing for Implantable Pacemakers.
[11] Khandpur, R. S. (2003). Automated drug delivery systems. Biomedical
IV. CONCLUSION Instrumentation.
A dual chamber pacemaker design was implemented on
Verilog. The delay in the proposed design was reduced to 54%.

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