2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
Performance Evaluation of Fixed-Point Array
Multipliers on Xilinx FPGAs
Burhan Khurshid Saniya Syed
Department of ECE, IUST Department of ECE, IUST
Awantipora (J&K), India Awantipora (J&K), India
burhan32.iust@gmail.com saniyawolf95@gmail.com
Junaid Peerzada Adnan Yaqoob
Department of ECE, IUST Department of ECE, IUST
Awantipora (J&K), India Awantipora (J&K), India
peerzada954@gmail.com adnanyaqoob@gmail.com
Abstract – Multiplication is one of the frequently used
arithmetic operation in digital signal processing. It forms the
core element in many complex operations like Filtering, Fast
Fourier Transforms, Convolution etc. Since these circuits
perform key operations in signal processing, their speed and
power optimization are crucial quality factors. Evidently,
fixed-point representation has gained a lot of importance when
hardware realization of multipliers is considered.
Traditionally, three implementation styles have been used viz.
bit-parallel, bit-serial and digit-serial. However, bit-parallel
systems are preferred in performance-critical applications
because of their ability to process multiple bits in parallel. This
work considers the implementation of two widely used fixed-
point bit-parallel multipliers on Xilinx Spartan-6 FPGAs.
These include parallel Ripple Carry Array multipliers and
parallel Carry Save Array multipliers. A distinguishing feature
of this work is that the realizations are carried out using LUT
instantiations. This is in contrast to previous realizations,
where inferential codes are used to represent the functionality
of the design and the synthesizer decides the mapping of the
coded functionality, thereby, resulting in sub-optimal
realizations. We have compared our realizations against some
conventional multiplier designs. Experimental analysis using
Xilinx Spartan-6 FPGA reveals that our approach results in a
substantial improvement in performance with a little runtime
overhead.
Keywords – DSP, FPGA, Array Multipliers, Fixed-point
Arithmetic, LUT
I. INTRODUCTION
Multiplication is one of the frequent and critical
arithmetic operations encountered in signal processing
applications. Fixed-point multipliers are the elements of
choice when design and implementation of high
performance digital signal processing (DSP) hardware is
concerned [1-3]. Performance versus accuracy trade-offs
often compel designers to use these multiplier circuits in
their realizations. Since these circuits form key elements in
DSP, their performance is crucial and will affect the overall
performance of the DSP system they are part of [4-7].
Hence, there is an immense need for low power and high
speed realization of these multipliers on different hardware
platforms.
A degenerate case of the floating-point is the fixed-point
representation. Such a representation has a fixed exponent
that cannot vary with time. Further, the use of barrel shifter
unit in the circuit realization is eliminated as no variable
alignment is required in addition and subtraction. Such a
representation is suitable for FPGA applications as it results
978-1-7281-1380-7/19/$31.00 ©2019 IEEE 171
Syed Mehtaab
Department of ECE, IUST
Awantipora (J&K), India
syedmehtaab123@gmail.com
in the conservation of resources and thereby limits the
critical path delays and power consumption. In floating
point notation, mantissa needs to be properly aligned before
a particular operation can be performed and this consumes
lot of hardware, leading to longer combinational paths and
more power dissipation.
Field programmable gate arrays (FPGAs) are often used
as co-processors to perform high speed tasks that cannot be
achieved using conventional processors. Advantages of
these platforms include ability to be re-programmed in the
field, post-production design verification, relatively lower
non-recurring engineering (NRE) costs, reconfigurable
design approach, high integration levels etc. [8-9]. FPGAs
are truly revolutionary in the sense that they can combine
the benefits of both hardware and software. The hardware
aspects of FPGAs provide designers with huge power,
resource, and speed benefits while the software aspects
enable an FPGA to be re-programmed in the field to realize
a wide range of logical functions. The hardware aspects of
FPGAs enable implementations that are distributed
spatially. Therefore, the resultant designs have the potential
to be hundreds of times faster than microprocessor-based
designs. However, unlike in Application Specific Integrated
Circuits (ASICs), these computations are programmed into
the chip, not permanently by the manufacturing process.
This means that an FPGA-based system can be programmed
and re-programmed many times. A single FPGA can replace
thousands of discrete components by incorporating millions
of logic gates in a single integrated circuit (IC) chip. Owing
to these advantages, FPGAs are fast moving from prototype
applications to low and medium volume productions [10-
12].
The rest of the paper is organized as follows. Section II
briefly discusses bit-parallel multipliers based on fixed-point
arithmetic. Section III and section IV discusses the
architecture of Ripple Carry and Carry Save based array
multipliers, respectively. Synthesis, implementation and
analysis is carried out in section V. Conclusions are drawn
in section VI and references are listed at the end.
II. PARALLEL MULTIPLIERS
Two widely used bit-parallel multipliers have been
considered in this work. These include multipliers based on
ripple carry logic (RCA multipliers) and carry save logic
(CSA multipliers). In each case, the multiplicand (P) and
multiplier (Q) vectors are represented in fixed-point 2’s
complement form. A typical representation of N-bit
operands would, therefore, be: [7]:
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

ܲ ൌ ‫݌‬ேିଵ Ǥ ‫݌‬ேିଶ Ǥ ‫݌‬ேିଷǥǥ ‫݌‬ଶǤ ‫݌‬ଵ Ǥ ‫݌‬଴ ሺ—Ž–‹’‹…ƒ†ሻ (1) 0 X3 Y0 0 X2 Y0 0 X1 Y0 0 X0 Y0

ܳ ൌ ‫ݍ‬ேିଵ Ǥ ‫ݍ‬ேିଶ Ǥ ‫ݍ‬ேିଷǥǥ ‫ݍ‬ଶǤ ‫ݍ‬ଵ Ǥ ‫ݍ‬଴ ሺ—Ž–‹’Ž‹‡”ሻ (2) FA FA FA FA 0

X3 Y1 X2 Y1 X1 Y1 X0 Y1

Magnitude wise these numbers occupy the range [í1, 1) and

is given by:
FA FA FA FA 0
ܲ ൌ െ‫݌‬ேିଵ ൅  σேିଵ
௜ୀଵ ‫݌‬ேିଵି௜ ʹ
ି௜
(3) X3 Y2 X2 Y2 X1 Y2 X0 Y2

ܳ ൌ െ‫ݍ‬ேିଵ ൅  σேିଵ

௜ୀଵ ‫ݍ‬ேିଵି௜ ʹ
ି௜
(4)
FA FA FA FA 0

The product Y = P×Q is given by: X3 Y3 X2 Y3 X1 Y3 X0 Y3

ܻ ൌ െ‫ݕ‬ଶேିଶ ൅  σଶேିଶ

௜ୀଵ ‫ݕ‬ଶேିଶି௜ ʹ
ି௜
(5)
FA FA FA FA Y3

And may be represented as:

ܻ ൌ ‫ݕ‬ଶேିଶ Ǥ ‫ݕ‬ଶேିଷ Ǥ ‫ݕ‬ଶேିସǥǥ ‫ݕ‬ଵ Ǥ ‫ݕ‬଴  (6) Z3 Z2 Z1 Z0

Fig. 1 Block schematic of multiplier based on ripple carry logic

Since constant word-length multiplication is considered, the
N-1 lower order bits in the product Y are truncated, and the
product is given by:
ܹൌ െ‫ݓ‬ேିଵ ൅  σேିଵ
௜ୀଵ ‫ݓ‬ேିଵି௜ ʹ
ି௜
(7)
The constant word length product W may be represented as:
ܹ ൌ ‫ݓ‬ேିଵ Ǥ ‫ݓ‬ேିଶ Ǥ ‫ݓ‬ேିଷǥǥ ‫ݓ‬ଶǤ ‫ݓ‬ଵ Ǥ ‫ݓ‬଴
The product W is used when a constant word-length
multiplier is considered and Y is used when a full precision
product is required. Out of the (2N-1)-bit product, the N
MSB bits of an N×N bit multiplication are retained. The
number will lie in the range of (-1, 1-2-N+1). 2’s
complement arithmetic has an advantage that a correct final
result is guaranteed irrespective of the overflow in the
intermediate stages. In other words, the final result is correct
if it is known to lie in the range [- (1-2-N+1), (1-2-N+1)].
III. RIPPLE CARRY ARRAY MULTIPLIER
RCA multiplier is based on the traditional ripple carry
logic. In each row, the generated carry from the previous
full adder (FA) block ripples to the next FA block in the
chain. The critical path of this multiplier, thus depends on
the length of the carry chain. This in turn depends on the
operand word-length N. A block level schematic of a 4-bit
RCA multiplier is shown in fig. 1. Based on this schematic
an N×N RCA multiplier will require N2 adder cells and N2
IV. CARRY SAVE ARRAY MULTIPLIER
The major drawback of RCA multiplier is that the carry-
chain has a large delay associated with it. This delay has a
linear dependency on the operand word-length. An alternate
approach is the carry save logic, where the rippling of the
carry within a row is avoided. Instead the carry generated by
each FA cell is saved and propagated to the next row. This
(8)
carry propagation from one row to the next makes the bit-
wise addition operation within a row independent, enabling
an increase in the speed of the overall multiplication
process. A block level schematic of a 4-bit CSA multiplier
is shown in fig. 2. An additional overhead in CSA multiplier
is the terminating vector merging adder (VMA). VMA
merges the partial vectors corresponding to sum and carry
and generates the final output. It is essentially a ripple carry
adder and incurs an additional hardware cost in a CSA
multiplier. An N×N CSA multiplier will require N2 adder
cells, N2 AND gates and additional overhead of VMA adder.
The critical path will have and additional VMA component.
The critical path for a pure combinational realization will be
given by:
‫ܲܥ‬ோ஼஺ ൌ ܶ௔ ൅ ܰǤ ܶ஺ ൅ ܶ௏ெ஺ (10)
Where TVMA is the delay associated with VMA.
0 X3 Y0 0 X2 Y0 0 X1 Y0 0 X0 Y0
FA FA FA FA

AND gates. The critical path for such a realization will X3 Y1 X2 Y1 X1 Y1 X0 Y1

include the delay associated with the first carry chain, plus
intermediate rows, plus final carry chain. The critical path FA FA FA FA
for a pure combinational realization will be given by: X3 Y2 X2 Y2 X1 Y2 X0 Y2

‫ܲܥ‬ோ஼஺ ൌ ܶ௔ ൅ ܰǤ ܶ஺ ൅ ሺܰ െ ʹሻǤ ܶ஺ ൅ ܰǤ ܶ஺
FA FA FA FA

X3 Y3 X2 Y3 X1 Y3 X0 Y3

ൌ ܶ௔ ൅ ሺ͵ܰ െ ʹሻǤ ܶ஺ (9)

Where Ta and TA is the delay associated with AND gate and FA FA FA FA Y3

an FA cell respectively.
VECTOR MERGING ADDER

Z3 Z2 Z1 Z0

Fig. 2 Block schematic of multiplier based on carry save logic

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 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
V. SYNTHESIS, IMPLENTATION AND ANALYSIS
The basic logic element in an FPGA is the look-up table
(LUT). The input bandwidth of an LUT varies from family
to family. This work considers FPGAs that have 6-input
LUTs as their basic logic element. Specifically, we have
considered Spartan-6 FPGAs from Xilinx. Each logic slice
in Spartan-6 has a general fabric of LUTs, carry-chains,
function generators etc. The LUTs have an input bandwidth
of six and can be used to implement a 6-input Boolean
function, or two 5-input Boolean functions. The former is a
single mode operation and the latter is a dual mode
operation. To enable a dual mode operation the logical
function should have shared variables.
Detailed implementation has been done by realizing
multiplier structures of varying input word-lengths. The
parameters used to specify the performance include
resources utilized, timing and power dissipation. Resources
include the number of LUTs and logic slices used. Timing
gives the notion of speed for a particular realization. In this
work, we have considered both combinational and pipelined
realizations of RCA and CSA multipliers. For
combinational realizations, timing analysis is mainly
concerned with the delay incurred along the critical path,
which is defined as the longest combinational path in a
circuit. For pipelined realizations, timing analysis is
concerned with the frequency at which the multipliers can
be clocked. Timing analysis may be done after synthesis or
after placement and route (PAR). However, post-synthesis
timing analysis is often vulnerable to changes, as the logic
has not yet been mapped on the LUTs. Therefore, post PAR
timing analysis has been done which is more accurate. Post
PAR timing analysis also enables the designer to capture a
realistic picture of the switching activity that is occurring
within a routed design. The same is used to assess the power
dissipation (dynamic) of an implemented design. Generally,
a value change dump (VCD) or a simulation activity
interchange format (SAIF) file captures the switching
activity of a design, which in combination with the design
netlist and power constraint file is used to generate a
detailed power report. Power dissipation involves both static
and dynamic components. While static power is device
specific, dynamic power depends on the complexity of the
routed design. The amount of mapped logic, clock
frequency, density of interconnects and the toggle rate of
signals along nodes are some of the factors that will affect
the reported power metrics from the synthesizer database.
Language based design entry is used by coding the
multiplier functionality in VHDL. However, unlike
traditional approaches, an instantiation based coding
strategy is followed. Conventional codes are inferential.
Inferential coding styles do not give the designer any control
over the placement and distribution of the logic to the
underlying FPGA fabric. The synthesizer infers the VHDL
code and distributes the logic to the underlying FPGA fabric
as per its internal strategies which are not known to the
designer. Although such codes are easy to write and have a
high degree of readability the resulting design suffers from
poor performance.
In this work, VHDL codes have been written following
an instantiation strategy. Such a strategy involves writing a
173
VHDL script that directly calls upon the target element, in
this case a 6-input LUT, and assigns some part of the
available logic to it. Instantiation increases the complexity
of the code, makes it time consuming and often refers the
code incomprehensible, but generally results in an improved
performance.
Xilinx ISE 14.1 has been used to carry out the synthesis,
simulation and implementation of different multiplier
structures. For power estimation, Xpower analyzer has been
used. The entire analysis has been done on a comparative
basis and some frequently used traditional multiplier designs
have been considered. Such an analysis gives a good
measure of the achievable performance speed-up in fixed-
point array multipliers based on our approach. Multiplier
realizations reported in [13-14] have been considered.
However, the multipliers in [13-14] have been implemented
using Virtex-5 FPGAs. Since our work focusses on Spartan-
6 FPGAs, the multiplier designs presented in [13-14] are re-
implemented using Spartan-6 FPGAs.
A. Resource Analysis
Table 1 provides a comparison of the different FPGA
resources utilized by different multiplier realizations
proposed in this work and those reported in [13-14]. The
analysis considers an input operand word-length of 16 bits.
It is observed that fixed-point array-multipliers show an
improved resource utilization when compared to traditional
realization. This is due to the fixed nature of the multipliers
that truncates the extra bits so that the input operands and
the final product has the same word length. Among different
multipliers, CSA based array multipliers show higher
resource utilization due to the additional terminating VMA
part. Among different implementation styles, pipelined
multipliers have higher resource utilization due to the
involvement of pipelined registers. Further analysis is
carried out by plotting the different utilized resources
against the input operand word-length. The results are
shown in fig. 3.
TABLE 1. RESOURCE UTILIZATION FOR DIFFERENT MULTIPLIER
REALIZATIONS
Multiplier Design No. of No. of
LUTs Slices
Carry Save Mult. (CSM) [13-14] 942 458
Carry Ripple Mult. (CRM) [13-14] 1062 527
Type-I Signed Booth Mult. (BSM-I) [13-14] 1142 567
Type-II Signed Booth Mult. (BSM-II) [13-14] 884 379
Type-III Signed Booth Mult. (BSM-III) [13-14] 1073 532
Comb. Ripple Carry Array (CRCAr) [this work] 764 325
Pip. Ripple Carry Array (PRCAr) [this work] 835 336
Comb. Carry Save Array (CCSAr) [this work] 857 432
Pip. Carry Save Array (PCSAr) [this work] 902 445
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)

2250 RESOURCE UTILIZATION 70

CRITICAL PATH
2000 CRCAr 60 CRCAr
CCSAr
1750 PRCAr CCSAr

DELAY (nS)
PCSAr 50 PRCAr
1500 PCSAr

LUTs
1250
40
1000
750 30
500
20
250
0 10
4 8 12 16 20 24 28 32
WORD LENGTH 0
0 4 8 12 16 20 24 28 32
WORD LENGTH
700 RESOURCE UTILIZATION
Fig. 4 Critical Path versus word length
OCCUPIED SLICES

600 CRCAr
CCSAr
PRCAr
500 PCSAr C. Power Analysis
400 Finally dynamic power dissipation of different
300 multiplier realizations is reported in table 3. The analysis is
200
done for maximum operating frequency and a fixed input
operand word-length of 16 bits. Fixed-point array
100
multipliers show a considerable reduction in dynamic power
0 dissipation when compared to traditional multipliers. This is
0 4 8 12 16 20 24 28 32
WORD LENGTH due to the reduction in logic that is achieved by truncating
extra bits in fixed-point multipliers. Among different
Fig. 3 Resource utilization versus word length. (a) LUTs (b) Slices multipliers, CSA based array multipliers shows higher
power dissipation because of the extra logic overhead in
B. Timing Analysis terms of VMA. Among different implementation styles,
For timing the critical path and maximum achievable pipelined multipliers have higher power dissipation due to
clock frequency of different multiplier realizations have the involvement of pipelined registers which consume extra
been considered and compared against those reported in [13- power. Further analysis is done by plotting dynamic power
14]. The results are shown in table 2. Again an input dissipation as a function of operand word-length. The results
operand word-length of 16 bits has been considered. It is are shown in fig. 5.
observed that fixed-point array-multipliers shows an
improved timing response when compared to traditional TABLE 3. DYNAMIC POWER ANALYSIS FOR DIFFERENT MULTIPLIER
realizations. Among different multipliers, CSA based array REALIZATIONS
multipliers shows reduced critical paths because it does not Multiplier Design Dynamic Power
involve the rippling of carry from one unit to another within (mW)
a row. Among different implementation styles, pipelined Carry Save Mult. (CSM) [13-14] 35.69
multipliers have reduced critical path due to the involvement
of pipelined registers which break the combinational path. Carry Ripple Mult. (CRM) [13-14] 67.13
Further analysis is done by plotting the measured critical Type-I Signed Booth Mult. (BSM-I) [13-14] 69.74
path against the input operand word-length. The results are Type-II Signed Booth Mult. (BSM-II) [13-14] 68.89
shown in fig. 4. Type-III Signed Booth Mult. (BSM-III) [13-14] 56.52
TABLE 2. CRITICAL PATH AND THROUGHPUT FOR DIFFERENT Comb. Ripple Carry Array (CRCAr) [this work] 23.91
MULTIPLIERS Pip. Ripple Carry Array (PRCAr) [this work] 29.43
Multiplier Design Crit. Op. Freq. Comb. Carry Save Array (CCSAr) [this work] 25.04
Path (nS) (MHz) Pip. Carry Save Array (PCSAr) [this work] 31.05
Carry Save Mult. (CSM) [13-14] 29.6078 356.21
Carry Ripple Mult. (CRM) [13-14] 46.30314 308.71
70
POWER DISSIPATION
DYNAMIC POWER (mW)

Type-I Signed Booth Mult. (BSM-I) [13- 50.75136 298.71

60
14] CRCAr
CCSAr
Type-II Signed Booth Mult. (BSM-II) [13- 30.81981 323.01 50 PRCAr
PCSAr
14]
40
Type-III Signed Booth Mult. (BSM-III) 30.5715 325
[13-14] 30

Comb. Ripple Carry Array (CRCAr) [this 28.853 578 20

work]
10
Pip. Ripple Carry Array (PRCAr) [this 7.667 578
work] 0

Comb. Carry Save Array (CCSAr) [this 19.941 578 0 5 10 15 20 25 30 35

work] WORD LENGTH
Pip. Carry Save Array (PCSAr) [this work] 3.641 578 Fig. 5 Dynamic Power versus word length

174
 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN)
VI. CONCLUSION
This work carried out the analysis of fixed-point bit
parallel array multipliers. Realizations based on ripple carry
logic and carry save logic were considered. Performance
comparisons, based on the data obtained from the
synthesizer database were found to be consistent with the
theoretical arguments. A distinguishing feature of this work
was the use of instantiation based coding style. A substantial
improvement in performance was observed using the
instantiation based coding. One important feature of array
multipliers is that they can be easily pipelined, thereby
resulting in extremely fast structures. The analysis done in
this work also highlights this feature of array multipliers.
One limitation with fixed-point representation, however is
that it may affect the accuracy of the final product. In this
work, it was assumed that the operands are normalized so
that their magnitude lies between 0 and 1, resulting in fairly
accurate results.
ACKNOWLEDGEMENTS
The authors would like to acknowledge the TEQIP-III
project team for their assistance and financial support during
the entire course of study.
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