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Wednesday, October 25, 2017 Followers

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ECO fixing order
Step
Name commands Fixing mechanisms Precendence rules Follow
s
Cell sizing Does not introduce new ming or
1Power recovery fix_eco_power
buffer removal DRV viola ons Blog Archive

Fix DRC and Cell sizing Alters setup and hold slacks as ►
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2 fix_eco_drc
noise viola ons buffer inser on needed ►
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Setup fixing honors DRC but alters ►
► November (11)
Fix ming Cell sizing
3 fix_eco_ ming hold slack if needed; Hold fixing ▼
viola ons buffer inser on ▼ October (18)
honors setup slack and DRC both.
clock phase meaning; related to
asyn/syn clocks de...
Does not introduce new ming or
Final leakage get_timing_path slack, startpt,
4 fix_eco_power vt swap DRC viola ons; doesn't change endpt
recovery
layout
What is CRP? Explian with
Cross talk taken into ac...

Posted by sureshkodam at 12:29 AM FLOW of STA run:

Labels: PD, STA, VLSI Can clock path be like this?


RC corners used for setup and
hold violations

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ECO fixing order
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