ESE 570 MOS INVERTERS

DYNAMIC CHARACTERISTICS

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 1

 Usually
Cdb >> Cgd & Csb >> Cgs

extrinsic
parasitic
caps

n = fan-out ≥ 1

# worst
Cload = C #
dbn
+ #C#
dbp
+#C#gdn
+#C# gdp
+# C int
+ nCgb ≈# C#
i≈i
dbn
#
+ C dbp + Cint + n Cgb case
Cgb = Cgbn+ Cgbp
Kenneth Intrinsic Parasitic
R. Laker, University Caps updated 26Feb15
of Pennsylvania, 2
 Cload ≈ Cdbn + Cdbp + Cint + nCgb where n = fan-out ≥ 1

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 3

VDD

0 t

VDD

V50% = VDD/2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 4
 VDD

VDD

V50% = VDD/2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 5
 VDD

V10% = 0.1 VDD

V90% = 0.9 VDD

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 6

 MOS Inverter Dynamic Performance
1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +
Cload, estimate (or determine) the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall.

2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter
schematic.

METHODS:
1. Average Current Model
8V HL 5V OH −V 50%p 6
>PHL ≈C load =C load
I avg , HL I avg , HL
2. Differential Equation Model
d V out d V out
i C =C load ⇒ ∫ dt=C load ∫
dt iC
where dt≈> PHL Assume
Vin ideal
3. 1st Order RC Delay Model
>PHL≈0.69 C load∗Rn
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 7
 CALCULATION OF PROPOGATION DELAY TIMES
VDD

C load 8V HL C load 5V DD−V DD /26 t

> PHL ≈ = =C load R eff , HL 0
I avg , HL I avg , HL
C load 8V LH C load 5V DD / 2−06 VDD
> PLH ≈ = =C load R eff , LH
I avg , LH I avg , LH
0 t

VDD VDD VDD VDD/2)]

0, 0 0, VDD/2)]

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 8

 CALCULATION OF RISE & FALL TIMES
VDD

(0.9VDD– 0.1VDD)

(0.9VDD– 0.1VDD) iC = iDP - iDn

VDD VDD 0.1VDD)]

0, 0, 0.9VDD)]
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 9
Calculating Propagation Delays By Solving
the Circuit Differential Equation

Let's assume Vin is an ideal step-input.

Two Cases
1. Vin abruptly rises => Vout falls => > PHL
2. Vin abruptly falls => Vout rises => > PLH

iDP - iDn

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 10

1) Vin – ABRUPTLY RISES CASE ->> PHL
Vin(t = t0) = 0 -> VDD
Vin(t < t0) = 0 and Vout (t < t0) = VDD

LIN V50% ≤ Vout < VDD - VT0n

i Dp≈0

V out =V DD −V T0n
V50%= VDD/2
d V out −d V out
C load ≈−i Dn ⇒ dt =C load 5 6
dt i Dn
t sat

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 11

 CMOS Static Inverter Characteristics Recall

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 12

1) Vin – ABRUPTLY RISES CASE ->> PHL
Vin(t = t0) = 0 -> VDD

V50%= VDD/2

d V out −d V out
C load ≈−i Dn ⇒ dt =C load 5 6 t sat
dt i Dn

t=t50% V out =0.5V DD −1

> pHL =∫t=t dt =C load ∫V
50
5 6dV out =C load Reff , HL
0 out =V DD i Dn
V DD−V T0n −1 0.5V −1
.=C load ∫V 6dV out 1C load ∫V −V 5
DD
5 6 dV out = t50% - t0
DD i Dn i Dn
DD T0n

tsat - t0 t50% - tsat

nMOS SAT nMOS LIN
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 13
 1) Vin – ABRUPTLY RISES CASE => > PHL cont.
t0 < t < tsat i = k n 5V −V 62 =−i
Dn in T0n C
2
kn 2 dV out
5V in −V T0n 6 =−C load
2 dt
VDD
for Vin = VDD and V DD −V T0n ≤ V out ≤ V DD
VDD
V50%= VDD/2 dV out −dV out
i Dn=−C load => dt =C load
dt i Dn
t sat
tt'1sat V DD −V T0n −1
∫t dt =C load ∫V
0 DD
5
i Dn
6dV out
tt1sat
'
−C load V DD −V T0n
∫t dt = k
0
∫V DD
dV out
n
5V DD −V T0n 62
2
' 2C load V T0n
t −t 0 =
1
sat 2
k n 5V DD −V T0n 6
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 14
1) Vin – ABRUPTLY RISES CASE => > PHL cont.
VDD tsat < t < t50%
kn
i Dn= [5V in −V T0n 6V out −V 2out ]=−i C
2
0 kn 2 dV out
[5V DD −V T0n 6V out −V out ]=−C load
2 dt
VDD
V50%= VDD/2 Vin = VDD and V out ≤ V DD −V T0n
t50% V50% −1
∫tt dt=C load ∫V
50p 50p
t sat 5 6dV out
i Dn
'
1 DD −V T0n
sat
VDD

0.5VDD -
tsat VDD VDD

- 0.5V
Vout = V
tsat 50% DD

VDD VDD V = VVDD- V

out DD
VT0n
T0n

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 15

1) Vin – ABRUPTLY RISES CASE => > PHL cont.

Vout = V50% = 0.5VDD

tsat
VDD VDD Vout = VVDDDD- VT0n

VDD VDD/2
VDD VDD/2

' 2 C load V T0n

tt −t 0 =
1
sat
k n 5V DD −V T0n 62
tsat tsat
VDD VDD/2
VDD VDD VDD/2
Rn
VDD
VDD VDD VDD/2

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 16

1) Vin – ABRUPTLY RISES CASE > PHL => cont.

VDD
VDD VDD VDD/2

VDD

Recall from static CMOS Inverter:

k n k 'n 5W / L6n =n 5W / L6n
k R= = ' =
k p k p 5W / L6 p = p 5W / L6 p

DESIGN: (1) Vth → kR; (2) τPHL → kn; (3) kR & kn → kp

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 17
 SOMETIMES USED APPROXIMATION FOR τPHL

tt=t
=t'50% −C load V out =0.5 V DD
> PHL=∫t=t dt≈ ∫V
1
dV out
0 kn out =V DD
5V DD −V T0n 62
2

2C load 50.5V DD 6
.≈
k n 5V DD −V T0n 62

C load V DD
> PHL≈ 2
≈ R n C load
k n 5V DD −V T0n 6
t sat
Δ is less than 10%
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 18
VDD = 5 V, VGSn = 5 V and VDSn ≥ 4V => iDn = iDnsat = 5mA

VDDV
V50% = 0.5 VDD = 2.5

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 19

Example 6.1 cont.

1 pF 2V 455−16V
.= −3
[ 1ln 5 −16]
0.625 x 10 A/V 55−16V 55−16V
2
5V

1 pF 2 16
.= −3
[ 1ln 5 −16]=0.52 ns
0.625 x 10 A/V 546 4 5

F F C /V
UNITS: = V= V =s
A/V A C /s

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 20

 COMPARISON WITH SOMETIMES USED
APPROXIMATION FOR τPHL

= 0.52 ns

Approximation for τPHL

C load V DD 1 x 10−12 F∗5V
> PHL≈ 2
= −2
=0.5 ns
k n 5V DD −V T0n 6 10 A 2
2
54 V 6
4V
2 i Dnsat 10 mA −3 2
where k n = 2
= 2
=0.625 x 10 A /V
5V DD−V T0n 6 54 V 6
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 21
 DD DD

DD DD

0.99 mA A
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 22
Example 6.2 cont.

-3
4.04 ns
0.99 x 10 A

DD
tsat
Vout = 4.0V
tsat -6.25 x 10 -10
s/V Vout |
Vout = 4.5V

tsat
0.31 ns
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 23
Example 6.2 cont.

0.31 ns

tsat
tsat
Vin = 5 V
0.5 V
tsat
0.5 V
Vin = 5 V

3.39 ns

tsat tsat 3.39 ns + 0.31 ns = 3.70 ns

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 24

2) Vin – ABRUPTLY FALLS CASE => > PLH
Vout (t < t0) = 0, Vin(t = t0) = VDD -> 0

SAT 0 < Vout ≤ - VT0p

LIN - VT0p < Vout ≤ VDD/2

VDD

V50%= VDD/2
i Dn≈0

tsat

d V out d V out
C load ≈i Dp ⇒ dt =C load 5 6
dt i Dp
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 25
 CMOS Static Inverter Characteristics Recall
VDD

i Dn≈0

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 26

2) Vin – ABRUPTLY FALLS CASE => > PLH
VDD

V50%= VDD/2

tsat
d V out d V out
C load ≈i Dp ⇒ dt =C load 5 6
dt i Dp
t=t 50p V out =V50% 1
> PLH =∫t=t dt=C load ∫V
50% 50p
5 6dV out =C load R eff , LH
0 out =0 i Dp
−V T0p 1 V50% 1
.=C load ∫0 6 dV out 1C load ∫−V 5
50p
5 6dV out = t - t
i Dp T0pi Dp 50% 0

tsat - t0 t50% - tsat

pMOS SAT pMOS LIN
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 27
2) Vin – ABRUPTLY FALLS CASE > PLH => cont.

VDD
VDD VDD VDD/2

.≈ R p C load
VDD
Recall from static CMOS Inverter:

k n k 'n 5W / L6n =n 5W / L6n

k R= = ' =
k p k p 5W / L6 p = p 5W / L6 p

DESIGN: (1) Vth → kR; (2) τPLH → kp; (3) kR & kp → kn

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 28

 SOMETIMES USED APPROXIMATION FOR τPLH

t =t sat C load V out =0.5 V DD

> PLH =∫t =t dt ≈ ∫ dV out
0 kp 2
V out =0
5V DD −∣V T0p∣6
2
2C load 50.5V DD 6
.≈ 2
V50%= VDD/2
k p 5V DD −∣V T0p∣6

C load V DD
> PLH ≈ 2
≈ R p C load
tsat k p 5V DD −∣V T0p∣6

Δ is less than 10%

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 29
Inverter Dynamic Performance – Quick Review
1. ANALYSIS (OR SIMULATION): For a given MOS inverter schematic +
Cload, estimate (or determine) the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall.

2. DESIGN: For given specs for the propagation delays τPHL and/or τPLH,
OR the rise/fall times τrise and/or τfall + Cload, determine the MOS inverter
schematic.

METHODS:
1. Average Current Model
8V HL 5V OH −V 50%p 6
>PHL ≈C load =C load
I avg , HL I avg , HL
2. Differential Equation Model
d V out d V out
i C =C load ⇒ ∫ dt=C load ∫
dt iC
st
Assume
3. 1 Order RC Delay Model Vin ideal
>PHL ≈0.69 C load ∗R n

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 30

Quick Review τPLH & τPHL Differential Equation Model

CONDITIONS for Balanced CMOS Propagation Delays, i.e.

W =n W
=> 5 L 6 = = 5 L 6
p p n

i.e. Symmetrical Inverter

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 31
 µp

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 32

 27

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 33

ALTERNATIVE APPROXIMATE DELAY DESIGN FORMULAS
Using the approximate delay formulas on slides 18 and 29:
C load V DD Wn
> PHL≈ 2
≈ R n C load k n ==n C ox
k n 5V DD −V T0n 6 Ln

Wn C load V DD
≈
L n >PHL =n C ox 5V DD −V T0n 62

C load V DD Wp
> PLH ≈ ≈ R p C load k p == p C ox
2 Lp
k p 5V DD −∣V T0p∣6

Wp C load V DD
≈
L p > PLH = p C ox 5V DD −∣V T0p∣62

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 34

 VDD

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 35

Example 6.3 cont. t 5V out =1V 6 V out =1V
dV out
∫ dt=−C load ∫ i 5lin6
t 5V =4 V 6
out
Dn
V out =4V

8.11

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 36

Example 6.3 cont.

8.11 Wn = 8.11 (1 µm) = 8.11 µm

8.11 µm = 10.81 µm

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 37

 µp

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 38

 Design for Propagation Delays Using More
Realistic Model for Cload
Cload i≈i Cdbn + Cdbp + Cint + Cgb

(Wn, Wp).

Cload i≈i Cdbn(Wn) + Cdbp(Wp) + Cint + Cgb

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 39

Design for Propagation Delays Using More Realistic Model for Cload cont.

Cdbn (Wn) = [Wn (Y + xj)] Cj0n Keqn + (Wn + 2Y) Cjswn Keqn(sw)
Cdbp (Wp) = [Wp (Y + xj)] Cj0p Keqp + (Wp + 2Y) Cjswp Keqp(sw)
Cload = α0 + αnWn + αpWp
α0 = 2YCjswnKeqn + 2YCjswpKeqp + Cint + Cgb
αn = (Y + xj)Cj0nKeqn + CjswnKeqn
αp = (Y + xj)Cj0pKeqp + CjswpKeqp
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 40
Design for Propagation Delays Using More Realistic Model for Cload cont.

µp

= α0 + (αn + (Wp/Wn) αp)Wn

C load C load
> PHL =7 n and > PLH =7 p
Wn Wp
where
Cload = α0 + αnWn + αpWp

Γn and ΓP are set largely by process parameters and V DD.

const.

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 41

 C load C load
> PHL=7 n > PLH =7 p
Wn Wp

Cload = α0 + αnWn + αpWp Cload = α0 + αnWn + αpWp

Multiply and divide αpWp by Wn Multiply and divide αnWn by Wp

Cload = α0 + αnWn + (αpWp/Wn)Wn Cload = α0 + (αnWn/Wp)Wp + αpWp

= α0 + [αn + αpR]Wn = α0 + [αn/R + αp]Wp

1 =p W p
where R = Wp/Wn = constant (Recall: V th ⇒ = when Lp=Ln)
k R =n W n

α0 + [αn + αpR]Wn α0 + [αn/R + αp]Wp

τPHL ? Γn τPLH ? Γp
Wn Wp

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 42

Design for Propagation Delays Using More Realistic Model for Cload
cont.
α0 + [αn + αpR]Wn α0 + [αn/R + αp]Wp
τPHL ? Γn τPLH ? Γp
Wn Wp
where R = aspect ratio = Wp/Wn
Hence increasing Wn and Wp will have diminishing influence on τPHL and
τPLH as they become large, i.e.

> Limit = limit τPHL = Γn [αn + αp R]

PHL
Wn → large absolute
R = constant minimum
delays
> Limit
PLH
= limit τPLH = Γp [αn/R + αp]
Wp → large
R = constant α0 = f(Cint, Cgb).

P avg ≈C load V 2DD f

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 43
 Design for Propagation Delays Using More Realistic Model for Cload cont.

> Limit = limit τPHL = Γn [αn + αp R]

PHL
Wn → large absolute
R = constant minimum
delays
> Limit
PLH
= limit τPLH = Γp [αn/R + αp]
Wp → large
R = constant

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 44

Design for Propagation Delays Using More Realistic Model for Cload cont.
1.6
1.4 VDD = 3.3 V
1.2 External load cap = 100 fF
1.0 R = Wp/Wn = 2.75
τPHL (ns)
0.8 Ln = Lp = 0.8 µm
0.6
0.4
0.2
0.0
0 5 10 15 20 25
nMOS Channel Width Wn (µm)
Area x τPHLProduct (norm)

5.0

4.5

4.0
3.5
3.0 minimum
2.5
2.0
0 4 8 12 16 20
nMOS Channel Width Wn (µm)
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 45
 Taking Into Account Non-Ideal Input Waveform
ideal Vin
non-ideal Vin
Vout to ideal Vin
Vout to non-ideal Vin

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 46

 st
1 Order RC DELAY MODELS
Equivalent circuits used for MOS transistors
● Ideal switch + “effective” ON resistance + load capacitance.
● Unit nMOS has “effective” ON resistance Rn= Run/κn & capacitance Cd.
● Unit pMOS has “effective” ON resistance Rp = Rup/κp & capacitance κpCd;
where transistor scale factors κn ≥ 1 and κp ≥ 1, i.e. Wn = κnWun, Wp = κpWup
● Cgb = Cg and Cdb = Csb = Cd for the unit n,pMOS transistors and scale with κn, κp.

NMOS and pMOS transistor at minimum gate length (L)

● Capacitance directly proportional to gate width (W)
● Conductance directly proportional to gate width (W)
● Resistance is inversely proportional to gate width (W)

Example
Unit
Transistors

Example Unit Dimensions: L un=Lup =2< ; W un =W up =4 <

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 47
 st
1 Order RC – Elmore Delay Model
Step Source VDD
> PLH 1
0 0 t
> PLH > PLH
Rn or Rp
V 1 506=0 V1(t) −t / R p C load
V 1 5t6=V DD 51−e 6
V1(0) Cload V DD
Step Source > PHL V50%
50p = =V DD 51−e
−> / R PLH nu C load
6
> PHL 1 2
0 0 t −> / R C V DD −V50%
50p 1
e PLH p
=
load
=
V DD 2
V 1 506=V DD
> PLH =ln 526C load R p =0.69C load R p (0 -> 50%)

NOTE > D =R p C load (0 -> 63%) = 1 time constant

V 1 506=V DD
ALSO > PHL =ln 526C load R n=0.69 C load R n

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 48

 nMOS 1st Order RC Delay Model – Equiv. Rn
ASSUME: bulk and s at GND

κnCd
Rn = Run/κn
κn ON/
OFF
κnCg
κnCd

Where Wn = κnWun
κn ≥ 1, usually κn = 1
C load V DD
Recall: > PHL≈ 2
≈0.69 R n C load
k n 5V DD −V T0n 6

V DD L un
R n=R un≈ 2 iff κn = 1
0.69 =n C ox W un 5V DD−V T0n 6

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 49

 pMOS 1st Order RC Delay Model – Equiv. Rp
ASSUME: bulk and s at VDD
s
κpCd
Rp = Rup/κp
κp ON/
OFF
κpCg
κpCd
Where Wp = κpWup
d
κp ≥ 1, usually κp = µn/µp
usually κn = 1

C load V DD
Recall: > PHL≈ 2
≈0.69 R p C load
k p 5V DD −V T0p 6

R up V DD Lup
R p= ≈
; p 0.69 = p C ox ; p W up 5V DD−∣V T0p∣62
Where, recall Lup = Lun and Wup = Wun
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 50
 pMOS 1st Order RC Delay Model – Equiv. Rp → Rn
ASSUME: bulk and s at VDD
s
κpCd
Rp = Rup/κp
W p =n W n
ON/
5 6= 5 6
κp Lp = p Ln
OFF
κpCg L un=Lup
κpCd
Where Wp = κpWup W un =W up
d
κp ≥ 1, usually κp = µn/µp
usually κn = 1
V DD Lup V DD Lun
R p≈ 2 R n≈ 2
0.69= p C ox W p 5V DD−∣V T0p∣6 0.69 =n C ox W un 5V DD−V T0n 6
R up V DD L up
R p= ≈
;p =n 2
0.69 = p C ox W up 5V DD −∣V T0p∣6
=p
.=R n Iff |VT0p| = VT0n SYMMETRIC INVERTER
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 51
 st
1 Order Delay Model - τPHL
Estimating τPHL VDD VDD
Cs = Cd
κpCd

1,κp
2R
R = /κ
nu R p
n = fanout
p n
VDD
VDD
VDD VDD nκp Cg
κpCd
κp κp
1,κ
Y 2 Y
A
1 1
1,κ p
1 Rn Cd nCg
where Wn=Wunit => κn=1, Rn=Run τPHL
Wp = κpWunit
κp = µn/ µp = 2 Cd

Rp = Rpu/κp = Rn
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 52
 st
1 Order Delay Model - τPHL
Estimating τPHL
Reff,HL = Rn = Rnu
Reff,LH = Rp = Rpu/κp = Rn
κpCd
VDD
Rp VDD
nκpCg
nκpCg κpCd
κpCd
Y
Y
Rn/κ
Rnn CndC
κ
nC
κnCg
Cd nCg
Rn
Cload = (1 + κp)(Cd + nCg)
Rp = Rn
τPHL

Cd > PHL ≈0.69C load∗R n =0.69511; p 65C d 1n C g 6 R n

ELMORE DELAY MODEL

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 53
 st
1 Order Delay Model - τPLH
Estimating τPLH

Reff,LH = Rp = Rpu/κp = Rn
κpCd
VDD
Rp = Rn VDD VDD
nκpCg
Rp = Rn κpC
τPLH
κpCd nκpCg
Y
Y κnC
C
nC
κnCg
Cd nC
Rn Cg
Cload = (1 + κp)(Cd + nCg)

Cd > PLH ≈0.69 C load∗R n =0.69511; p 65C d 1n C g 6 R n

> PHL ≈0.69C load∗R n =0.69511; p 65C d 1n C g 6 R n

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 54
 Propagation Delay Model Summary
C load 8V HL C load 5V OH −V 50 %p 6
> PHL ≈ =
Average I avg , HL I avg , HL
Current C load 8 V LH C load 5V 50 % p −V OL 6
Model > PLH ≈ =
I avg , LH I avg , LH

> PHL
Differential
Equation
Model > PLH
C load V DD C load V DD
APPROX: > PHL≈ > PLH ≈ 2
k p 5V DD −∣V T0p∣6
2
k n 5V DD −V T0n 6

1st Order RC > PHL ≈0.69 C load∗R n

Elmore > PLH ≈0.69 C load∗R p
Model

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 55

 CMOS Ring Oscillator

= SYM INV

t
τPHL2 τPHL1 τPHL3
τPLH3 τ τPLH2 PLH1

SYM INV => τPHL = τPLH

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 56
 CMOS Ring Oscillator cont.

SYM INV => τPHL = τPLH = τp

where
1 1
f= =
T 6 >p

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 57

 Estimation of Interconnect Parasitics

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 58

 Estimation of Interconnect Parasitics cont.
cross-
talk

Ideal FF value: FF = 1

FF -> Increase as t/h -> Increase, W/h <- Decrease and W/L Increase
(See plot of FF in Fig. 6.18 of V3 & V4 of Text) Actual(1FF< value:
FF < 200)
1 < FF ≤ 20

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 59

Estimation of Interconnect Parasitics cont.
cross-
talk

Cmf = CoxFt = 30 aF/um2, toxF = 0.6 um and Cpa = 1 to 10 pF

Cmff = PP + FF PP = Cpp F/µm2 * Area

FF = CFF F/µm * Perimeter

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 60

Estimation of Interconnect Parasitics cont.

(PP + FF)
0.3 = m
0.9 = m
0.6 = m
2
0.6 = m C gb =1800 aF / = m
0.3 = m
0.6 = m
0.3 = m
Cm2d 0.6 = m
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 61
 DIGITAL CIRCUIT PATH DELAY

O1
3 4
2
5 O2
1

S1 S2

Delays through logic blocks

Net-related delays
Fanout to other logic blocks
Interconnect (wiring)

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 62

 st
1 Order RC – Segment Delay (Elmore Delay Model)
Step Source
> PLH 1
0 0 t
V1(t)
−t / R1 C 1
V 1 506=0 V 1 5t6=V DD 51−e 6
“1” = VDD V DD −t / R C
V 50%p = =V DD 51−e 6
PLH 1 1

Step Source 2
> PHL 1 −> / R C V DD−V 50 %p 1
0 0 t e PLH 1
= 1
=
V DD 2
V 1 506=V DD

> PLH =ln 526 R1 C 1=0.69 R 1 C 1 (1 -> 50%)

NOTE > D =R 1 C 1 (0 -> 63%) = 1 time constant

ALSO > PHL =ln 526 R 1 C 1=0.69 R 1 C 1

> PLH => PHL =0.69 > D
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 63
 INTERCONNECT DELAY CALCULATIONS
R3
RC Tree Network 3
> PLH Lumped V3(0)
Step Source R2 C3
RC Model 2
1 for a Wire
0 0 t Segment C2 R4 R5
R1 4 5
1 V5(0)
> PHL S V4(0) C4 C5
Step Source V1(0) C1
1 V7(0) R
t R6 R7
0 0 6 7 8 8 V (0)
8

V6(0) C6 C7 C8

1. Lump total wire resistance of each wire segment into single Rj between nodes in network.
2. Lump total capacitance into single node capacitor to GND.
3. Model RC tree Topology:
(a) Single input node “S”;
(b) All Ci between node i and GND;
4. Unique resistive path from source node S to any node k (k ≠ S).

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 64

 INTERCONNECT DELAY CALCULATIONS
RC Tree Network R3
3
R2 C3
Step Source 2
1 C2 R4 R5
0 R1 4 5
1
S C4 C5
C1
R6 R7 R8
6 7 8
C6 C7 C8
Elmore delay at node “i”
N
> PLH =0.69> Di =0.69 ∑ C k R ik where R ik =∑ R j 3 R j :[ path5S 3 i6∩ path 5S 3 k 6]
k =1
st
Rik is the “shared path resistance”
1 Order Time-Constant Model
for the Net @ node “i”.
Elmore delay at node “7”
>D7 = R1 C 11 R 1 C 21 R1 C 31R 1 C 41 R 1 C 5 15 R1 1R 6 6 C 615 R1 1R 6 1 R 7 6 C 7 15 R 1 1R 61 R7 6C 8
R71 R72 R73 R74 R75 R R77 R78
76

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 65

 INTERCONNECT DELAY CALCULATIONS
Elmore delay at node “i”
N
>Di = ∑ C k Rik
k =1

Rik =∑ R j 3 R j :[ path5 S 3 i6∩ path5 S 3 k 6]

Elmore delay at node “5”:

> D5 =?

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 66

 INTERCONNECT DELAY CALCULATIONS
Elmore delay at node “i”
N
>Di = ∑ C k Rik
k =1

Rik =∑ R j 3 R j :[ path 5S 3 i6∩ path 5S 3 k 6]

Elmore delay at node “5” R55

>D5 = R1 C 1 15 R11 R 2 6C 2 15 R11 R2 6C 3 15 R11 R 21 R 4 6 C 4 15 R11 R2 1 R4 1 R5 6C 5
R51 R52 R53 R54 1R 1 C 6 1R 1 C 7 1R 1 C 8
R56 R57 R58
Elmore delay at nodes “1” and “8”
>D1= R1 C 11 R1 C 2 1R1 C 3 1R1 C 4 1 R1 C 51 R1 C 61 R1 C 71R1 C 8

>D8 = R1 C 1 1 R1 C 2 1R1 C 3 1R1 C 4 1 R1 C 5 15 R11 R6 6C 6 15 R11 R6 1 R7 6C 7

15 R1 1R 61R 7 1R 8 6C 8
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 67
 INTERCONNECT DELAY CALCULATIONS
RC Chain or Ladder Network
Wire Length L
R1 R2 R3 RN
1 2 3 N
S O

C1 C2 C3 CN

Elmore delay at node “N”

N N j
> DN =0.69 ∑ C k R Nk =∑ C j ∑ R k
k =1 j=1 k =1

Let the RC Ladder Network be uniform, i.e. Ri = rL/N for all i ≤ N and Cj = cL/N
for all j ≤ N such that
N j 2
cL rL L 2 N 11
> DN =∑ 5 6 ∑ 5 6= 2 5rc12 rc13 rc1...1N rc6=rc L 5 6
j=1 N k =1 N N 2N
rc L 2
For large N, as N 3 ∞ (distributed RC line) > DN 3
2
> PLH =0.69 > DN ≈0.35 r c L 2
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 68
 Practical Interconnect Length Rule-of-Thumb
> PHLinv =0.69C load R n > PLHwire =0.35 r c L 2

rL/N rL/N rL/N rL/N

S
cL/N cL/N cL/N cL/N
Rn, κnC
Rp, κpC

> PLHtotal => PLHinv 1> PLHwire =0.69 C load R n10.35 r c L2

Let the goal be for the layout to enable > PLHtotal ≈> PLHinv

> PLHtotal ≈> PLHinv ⇒> PLHwire ≪> PLHinv

0.35 r c L 2 ≪0.69C load R n

L≪
4
> PLHinv
0.35 r c
=
0.35 r c4
0.69 C load R n

L≤
4
1 > PLHinv
=
10 0.35 r c 10 4
1 0.69 C load R n
0.35 r c

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 69

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 70
 vin, vout
VDD

vin
vout
0

1 T
P avg = ∫0 v 5t 6i 5t 6dt
T
v DSn 5t 6=v out 5t 6 v SDp 5t 6=V DD −v out 5t 6
1 T /2 1 T dt
P avg ≈ ∫0 v DSn 5t 6 i Dn 5t 6 dt1 ∫T /2 v SDp 5t6 i Dp 5t 6 dt
T T
dv out dv out
i Dn 5t 6=−C load i Dp 5t 6=C load
dt dt
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 71
 1 T /2 d v out 1 T d v out
P avg ≈ ∫0 v out 5−C load 6dt 1 ∫T /2 5V DD −v out 65C load 6 dt
T dt T dt
vin, vout
VDD

1 0 1 V
P avg ≈ ∫V −C load v out 5t 6dv out 1 ∫0 C load 5V DD −v out 5t 66 dv out
DD

T DD T
2 v out =0 2 v out =V DD
1 v out 1 v out
.= [−C load ] 1 [C load 5V DD v out − 6]
T 2 v out =V DD T 2 v out =0

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 72

 2 v out =0 2 v out =V DD
1 v out 1 v out
P avg ≈ [−C load ] 1 [C load 5V DD v out − 6]
T 2 v out =V DD T 2 v out =0

1 2
.= C load V DD
T P avg ≈C load V 2DD f
f = operating frequency or switching frequency
Units calculation
2 Q −1
f = F∗V ∗Hz= ∗V 2∗s
2
P avg ≈C load V DD In = A∗V =W
General:
V
C load 3C total
Ctotal = total chip capacitance

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 73

 P avg ≈C load V 2DD f
EXAMPLE: Consider 0.1 µm CMOS chip with a clock rate of 100 MHz, VDD =
2V and an average Cload = 3 fF per gate.
(a). What is the dynamic power dissipation per gate?
(b). If the chip incorporates 200,000 gates, what is the power dissipation for the
chip?
(a).
−15 F 2 6 −1
P avg / gate≈3 x 10 ∗4V ∗100 x 10 s =1.2= W / gate
gate
(b).
P avg = P avg / gate∗200,000 gates≈1.2= W / gate∗2 x 105 gates=0.24 W
PESSIMISTIC -> NOT ALL 200,000 GATES SWITCH AT THE SAME TIME
OR AT 100 MHZ!
P avg ≈C EFF V 2DD f C EFF =9C load
CEFF = effective capacitance -> avg. capacitance switched per cycle at f Hz.
e.g. if α = 0.2, Pavg = 0.24 W -> 48 mW

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 74

 Buffer to Drive Large CLOAD

standard
CMOS
logic on
INV1 Buffer
die CLOAD

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently

large to drive CLOAD with a specified τP.

How do you feel about this design strategy?

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 75

 Buffer to Drive Large CLOAD

standard
CMOS
logic on
INV1 Buffer
die CLOAD

Cin

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently

large to drive CLOAD with a specified τP.

How do you feel about this design strategy?

What happens to Cin as (W/L)n and (W/L)p sufficiently large?
What is the impact on the standard CMOS logic on the die?

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 76

 Super-Buffer to Drive Large CLOAD

standard
CMOS INV1
logic on
die CLOAD

VDD PROBLEM: A minimum sized inverter drives a

large load CLOAD, leading to excessive delay, even
with a large buffer (large W/L).

CLOAD SOLUTION: Insert N inverter stages in cascade

with increasing W/L between INV1 and load
CLOAD. The total delay through N smaller stages
will be less than the delay through a single large
stage driving CLOAD.
VDD
N=3

CLOAD

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 77

 Super-Buffer to Drive Large CLOAD cont.
INV1
Stage-0
CLOAD

NOTE for CMOS INV:

cascade Cd = Cdbn + Cdbp
a -> stage scale factor > 1 Cg = Cgbn + Cgbp
Wni = aiWn0, Lni = Ln0 and Wpi = aiWp0, Lpi = Lp0 for i = 0, 1, 2, ..., N
Stage load capacitances Cloadi are also scaled by a
Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N

when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg
ln 5C LOAD / C g 6 N is rounded up to nearest
CLOAD/Cg = a N+1
=> N = −1 integer value.
ln a
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 78
 Super-Buffer to Drive Large CLOAD cont.

CLOAD

CLOAD

NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay
> PHL 1> PLH C load
> p= =7
2 W
Let τ0 = gate delay for INV1 (with a = 1) in a ring oscillator with load Cload = Cd + Cg
>d0 C load0 /W 0 Cdd1a C g
C Cdd 1a C g
For Stage-0: = = ⇒> p0 =>0
>0 5C Cdd 1C g 6/ W 0 C dd 1C g Cdd 1C g

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 79

 Super-Buffer to Drive Large CLOAD cont.

> p0 C load0 /W 0 Cdd 1a C g CCdd1a C g

For Stage-0: = = ⇒ > p0 =>0
>0 5C Cdd 1C g 6/W 0 orC dd 1C g Cdd 1C g
C
> p1 C load1 /a W 0 5a Cdd 1a 2 C g 6/ a Cd 1a C g
For Stage-1: = = ⇒ > p1=>0 => p0
>0 5C
C dd
1C g 6/W 0 C
C dd
1C g CCdd 1C g

> pN C load1 /a N W 0 5a N C
Cdd 1a N 11 C g 6/a N Cd 1a C g
C
For Stage-N: = = ⇒ > pN =>0 => p0
>0 5C
Cdd1C g 6/ W 0 C dd
1C g C dd
1C g
Cdd 1a C g Choose N and a
TOTAL DELAY >total =5 N 116⋅> p0 =5N 116⋅>0⋅ C
C dd 1C g to minimize τtotal
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 80
 Super-Buffer to Drive Large CLOAD cont.
CCdd 1a C g
>total =5 N 116⋅>0⋅ ln 5C LOAD /C g 6 CCd 1a C g
CCdd 1C g >total = ⋅>0⋅
ln a C dd 1C g
ln 5C LOAD / C g 6
N 11=
ln a Wni = aiWn0 Wpi = aiWp0
TO MINIMIZE τtotal:
d >total C LOAD −1/a CCdd1a C g 1 Cg
=>0 ln 5 6⋅[ 1 ]=0
da Cg 2
5ln a6 C Cdd 1C g ln a CCdd1C g
=0
Cdd
aopt [ln a opt −1]=
Cg
Cd ln a opt =1⇒ a opt =e 1 =2.718
ln 5C /C g 6
Since Cd > Cg, Cd =N0=is onlyLOAD −1 N
an academic is rounded
special up to nearest
case.
integer value.
ln aopt
Since Cd > Cg, then Cd = 0 is only an academic special case.
aaopt ≥ e=2.718
opt 2e=2.718

Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 81

 Super-Buffer to Drive Large CLOAD cont.
EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve
LOAD ≈100
minimum total delay ttotal when CCLOAD = 100 CCgg. Consider the case where
Cd = 2Cg.
Cd = 2Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47
ln 5C LOAD /C g 6
Plot using Excel, MathCad, MatLab. N 11=
ln aopt
4.61
ln 5C LOAD /C g 6
⇒N= −1=2.133 N =3
1.47
a opt =4.35 3.13∗1.47 C LOAD 4∗1.47
=100
e Suitable ≤
Sub-Optimum =365
≤ e Design?
Cg
i Wni/Wn0 Wpi/Wp0
1 (aopt)1 = 4.35 (aopt)1 = 4.35
Cd/Cg = 2 2 (aopt)2 = 18.92 (aopt)2 = 18.92
e
3 (aopt)3 = 82.31 (aopt)3 = 82.31
Cdd rd N+1 with little impact.
3 stageCcan be/Celiminated
=aopt [ln aopt −1] NOTE: LOAD g
= a = 82 for N = 2
Cg
= 358 >> 100 for N = 3
Kenneth R. Laker, University of Pennsylvania, updated 26Feb15 82