Digital Design: Sequential Logic Design - Controllers

Digital Design
Chapter 3:
Sequential Logic Design -- Controllers
Slides to accompany the textbook Digital Design, First Edition,
by Frank Vahid, John Wiley and Sons Publishers, 2007.
http://www.ddvahid.com
Copyright © 2007 Frank Vahid

Instructors of courses requiring Vahid's Digital Design textbook (published by John Wiley and Sons) have permission to modify and use these slides for customary course-related activities,
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Copyright © 2006 1
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3.1
Introduction
• Sequential circuit 1
a 1
– Output depends not just on present inputs (as in 0 Combinational F
combinational circuit), but on past sequence of inputs b digital circuit
• Stores bits, also known as having “state”

– Simple example: a circuit that counts up in binary
• In this chapter, we will: 1
a
– Design a new building block, a flip-flop, that stores 0 Sequential ? F
b digital circuit
one bit
– Combine that block to build multi-bit storage –siaansis Must know
register sequence of
– Describe the sequential behavior using a finite state past inputs to
machine ez know output
– Convert a finite state machine to a controller – a
sequential circuit having a register and combinational
logic
Digital Design
Copyright © 2006 2
Frank Vahid Note: Slides with animation are denoted with a small red "a" near the animated items
3.2
Example Needing Bit Storage

Call Blue light
button Bit
• Flight attendant call button Cancel
button
Storage
– Press call: light turns on

1. Call button pressed – light turns on
• Stays on after button released
– Press cancel: light turns off Call Blue light
button Bit
– Logic gate circuit to implement this? Cancel Storage
a
button
Call Q 2. Call button released – light stays on

Cancel
a
Call Blue light
Doesn’t work. Q=1 when Call=1, but button Bit
doesn’t stay 1 when Call returns to 0 Cancel Storage
button
Need some form of “feedback” in the circuit
3. Cancel button pressed – light turns off
Digital Design
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Frank Vahid
First attempt at Bit Storage
• We need some sort of feedback S Q
– Does circuit on the right do what we want? t
• No: Once Q becomes 1 (when S=1), Q stays 1
forever – no value of S can bring Q back to 0
S 0 S 1 S 1 S 0
0Q S 1 0Q 1Q 1Q 1Q
a
0 0 0 1 1
t t t t t
1
S
0
1
t
0
1
Q
0
Digital Design
Copyright © 2006 4
Frank Vahid
Bit Storage Using an SR Latch
S (set) SR latch
• Does the circuit to the right, with cross-coupled
NOR gates, do what we want?
– Yes! How did someone come up with that circuit?
Maybe just trial and error, a bit of insight... Q
R (reset)
S=0 S=0 S=1 S=0
t t t t Recall…
1 1 0 0 0
0 0 1 1 1
0
1
1 1 0 0 0
0 Q 0 Q 1
Q
1
Q eRcall ...
X
R=1 R=0 R=0 R=0
1
S
0
R1
0 a
t 1
0
1
Q
0
Digital Design
Copyright © 2006 5
Frank Vahid
Example Using SR Latch for Bit Storage
• SR latch can serve as bit Call Blue light
storage in previous example button Bit
Storage
Cancel
of flight-attendant call button button
– Call=1 : sets Q to 1
• Q stays 1 even after Call=0 C all S
– Cancel=1 : resets Q to 0 but ton
Blue lig ht
• But, there’s a problem... Q
Cancel
but ton
R
Digital Design
Copyright © 2006 6
Frank Vahid
Problem with SR Latch
• Problem
– If S=1 and R=1 simultaneously, we don’t know what value Q will take
1
S
0
1
R
0
1
t
0
1
Q
0
1
Q may oscillate. Then, because one path will be t
0
slightly longer than the other, Q will eventually 1
settle to 1 or 0 – but we don’t know which. Q
0
Digital Design
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Frank Vahid
Problem with SR Latch
• Problem not just one of a user pressing two buttons at
same time
• Can also occur even if SR inputs come from a circuit that
supposedly never sets S=1 and R=1 at same time
– But does, due to different delays of different paths
Arbitrary
circuit S SR latch
X
Y R
The longer path from X to R than to S causes SR=11 for

short time – could be long enough to cause oscillation
Digital Design
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Frank Vahid
Solution: Level-Sensitive SR Latch
• Add enable input “C” as shown Level-sensitive SR latch
S
– Only let S and R change when C=0 S1
• Enure circuit in front of SR never sets
SR=11, except briefly due to path delays C
– Change C to 1 only after sufficient time for S
and R to be stable Q
– When C becomes 1, the stable S and R R
R1
value passes through the two AND gates to
the SR latch’s S1 R1 inputs. S
Q’
Level-sensitive SR latch Though SR=11 briefly... C
1 Q
S S R
X S1 0
1 Level-sensitive
R
0
SR latch symbol
C 1 a
Clk C
0
Q 1
S1
R 0
R1
Y 1
R1 0
Digital Design
Copyright © 2006
...S1R1 never = 11
9
Frank Vahid
Clock Signals for a Latch
• How do we know when it’s safe to set C=1?

– Most common solution –make C pulse up/down
• C=0: Safe to change X, Y Level-sensitive SR latch
• C=1: Must not change X, Y X
S
S1
• We’ll see how to ensure that later
– Clock signal -- Pulsing signal used to enable C
Clk
latches
Q
• Because it ticks like a clock
R
– Sequential circuit whose storage components all Y
R1
use clock signals: synchronous circuit
• Most common type
• Asynchronous circuits – important topic, but left for
advanced course
Digital Design
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Frank Vahid
Clocks
• Clock period: time interval between pulses

– Above signal: period = 20 ns Freq Period
100 GHz 0.01 ns
• Clock cycle: one such time interval 10 GHz 0.1 ns
– Above signal shows 3.5 clock cycles 1 GHz 1 ns
• Clock frequency: 1/period 100 MHz 10 ns
10 MHz 100 ns
– Above signal: frequency = 1 / 20 ns = 50 MHz
• 1 Hz = 1/s
Digital Design
Frank Vahid
Level-Sensitive D Latch
• SR latch requires careful design to D latch
D
ensure SR=11 never occurs S
• D latch relieves designer of that C

burden
Q
– Inserted inverter ensures R always R
opposite of S
1
D
0
D Q’
1
C C Q
0
1
S D latch symbol
0
1
R
0
1
Q
0
Digital Design
Frank Vahid
Problem with Level-Sensitive D Latch
• D latch still has problem (as does SR latch)
– When C=1, through how many latches will a signal travel?
– Depends on for how long C=1
• Clk_A -- signal may travel through multiple latches
• Clk_B -- signal may travel through fewer latches
– Hard to pick C that is just the right length
• Can we design bit storage that only stores a value on the rising edge of
a clock signal?
rising edges
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Clk
C1 C2 C3 C4
Clk
Clk_A Clk_B
Digital Design
Frank Vahid
D Flip-Flop
• Flip-flop: Bit storage that stores on clock edge, not level rising edges
• One design -- master-servant Clk
– Two latches, output of first goes to input of second, master

latch has inverted clock signal Note:
– So master loaded when C=0, then servant when C=1 Hundreds of
different flip-
– When C changes from 0 to 1, master disabled, servant flop designs
loaded with value that was at D just before C changed -- i.e., exist
value at D during rising edge of C
D flip-flop
D latch D latch
D Q’
Dm Qm Ds Qs’
Q
Cm Cs Qs
master servant
Clk
Digital Design
Frank Vahid
D Flip-Flop
D Q’ D Q’ Internal design: Just

The triangle invert servant clock
means clock Q Q rather than master
input, edge
triggered
Symbol for rising-edge Symbol for falling-edge
triggered D flip-flop triggered D flip-flop
rising edges falling edges

Clk Clk
Digital Design
Frank Vahid
D Flip-Flop
• Solves problem of not knowing through how many latches a signal
travels when C=1
– In figure below, signal travels through exactly one flip-flop, for Clk_A or
Clk_B
– Why? Because on rising edge of Clk, all four flip-flops are loaded
simultaneously -- then all four no longer pay attention to their input, until the
next rising edge. Doesn’t matter how long Clk is 1.
Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 Tw each
inside
fli
p ol
-flop aflip-flop
Two latches inside
eachtches
Clk
Clk_A Clk_B
Digital Design
Frank Vahid
D Latch vs. D Flip-Flop
• Latch is level-sensitive: Stores D when C=1
• Flip-flop is edge triggered: Stores D when C changes from
0 to 1
– Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is
redundant
– Two types of flip-flops -- rising or falling edge triggered.
• Comparing behavior of latch and flip-flop:
Digital Design
Frank Vahid
Flight-Attendant Call Button Using D Flip-Flop
• D flip-flop will store bit Call
Flight Blue
button
• Inputs are Call, Cancel, and present value Cancel
attendant
call-button
light
of D flip-flop, Q button system
• Truth table shown below
Preserve value: if Circuit derived from truth table,

Q=0, make D=0; if using Chapter 2 combinational
Q=1, make D=1 logic design process
Cancel -- make Call Call

but ton D Q’
Blue
D=0 light
Cancel Cancel
but ton
Clk Q
Call -- make D=1 Q
Let’s give priority

to Call -- make
D=1
Digital Design
Frank Vahid
Bit Storage Summary
SR latch Level-sensitive SR latch D latch D flip-flop
S (set) S D
S1 S D latch D latch
D Q’
Dm Qm Ds Qs’
C C Q
Cm Cs Qs
Q Q Q master servant
R
R1 R Clk
R (reset)
Feature: S=1 sets Q Feature: S and R only have Feature: SR can’t be 11 if D is Feature: Only loads D value
to 1, R=1 resets Q to effect when C=1. We can stable before and while C=1, present at rising clock edge, so
0. Problem: SR=11 design outside circuit so and will be 11 for only a brief values can’t propagate to other
yield undefined Q. SR=11 never happens when glitch even if D changes while flip-flops during same clock cycle.
C=1. Problem: avoiding C=1. Problem: C=1 too long Tradeoff: uses more gates
SR=11 can be a burden. propagates new values internally than D latch, and
through too many latches: requires more external gates than
too short may not enable a SR – but gate count is less of an
store. issue today.
• We considered increasingly better bit storage until we

arrived at the robust D flip-flop bit storage
Digital Design
Frank Vahid
Basic Register
• Typically, we store multi-bit items
– e.g., storing a 4-bit binary number
• Register: multiple flip-flops sharing clock signal
– From this point, we’ll use registers for bit storage
• No need to think of latches or flip-flops
• But now you know what’s inside a register
I3 I2 I1 I0
4-bit register
D D D D I3 I2 I1 I0
Q Q Q Q reg(4)
clk Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Digital Design
Frank Vahid
Example Using Registers: Temperature Display
• Temperature history display
– Sensor outputs temperature as 5-bit binary number
– Timer pulses C every hour
– Record temperature on each pulse, display last three recorded values
Present 1 hour ago 2 hours ago

Display Display Display
x4 a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
er x3
tu
ar x2
TemperatureHistoryStorage
x1
sensor x0
empe
t
timer
C
(In practice, we would actually avoid connecting the timer output
C to a clock input, instead only connecting an oscillator output to a clock input.)
Digital Design
Frank Vahid
Example Using Registers: Temperature Display
• Use three 5-bit registers
a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0
I4 Q4 I4 Q4 I4 Q4
x4
I3 Q3 I3 Q3 I3 Q3
x3
I2 Q2 I2 Q2 I2 Q2
x2
I1 Q1 I1 Q1 I1 Q1
x1
I0 Q0 I0 Q0 I0 Q0
x0
Ra Rb Rc
C
TemperatureHistoryStorage
x4...x0 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27
Ra 0 18 21 24 25 26 27
Rb 0 0 18 21 24 25 26
Digital Design Rc 0 0 0 18 21 24 25
Frank Vahid
3.3
Finite-State Machines (FSMs) and Controllers

• Want sequential circuit with b Controller
laser
particular behavior over time x
clk
• Example: Laser timer
– Push button: x=1 for 3 clock cycles patient
– How? Let’s try three flip-flops

• b=1 gets stored in first D flip-flop
• Then 2nd flip-flop on next cycle,
then 3rd flip-flop on next
• OR the three flip-flop outputs, so x b
D Q D Q D Q
should be 1 for three cycles
clk
x
Digital Design
Frank Vahid
Need a Better Way to Design Sequential Circuits
• Trial and error is not a good design method
– Will we be able to “guess” a circuit that works for other desired
behavior?
• How about counting up from 1 to 9? Pulsing an output for 1 cycle
every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit
input?
– And, a circuit built by guessing may have undesired behavior
• Laser timer: What if press button again while x=1? x then stays one
another 3 cycles. Is that what we want?
• Combinational circuit design process had two important
things
1. A formal way to describe desired circuit behavior
• Boolean equation, or truth table
2. A well-defined process to convert that behavior to a circuit
• We need those things for sequence circuit design
Digital Design
Frank Vahid
Describing Behavior of Sequential Circuit: FSM
• Finite-State Machine (FSM) Outputs: x
clk^
– A way to describe desired x=0 x=1
behavior of sequential circuit
Off On
• Akin to Boolean equations for
combinational behavior
clk^
– List states, and transitions
among states
• Example: Make x change
toggle (0 to 1, or 1 to 0) every
clock cycle
• Two states: “Off” (x=0), and
“On” (x=1)
• Transition from Off to On, or
On to Off, on rising clock edge
• Arrow with no starting state
points to initial state (when
circuit first starts)
Digital Design
Frank Vahid
FSM Example: 0,1,1,1,repeat
• Want 0, 1, 1, 1, 0, 1, 1, 1, ... Outputs: x
– Each value for one clock cycle x=0 clk ^ x=1 clk ^ x=1 clk ^ x=1
• Can describe as FSM Off On1 On2 On3
– Four states
clk ^
– Transition on rising clock
edge to next state
clk
State Off On1 On2 On3 Off On1 On2 On3 Off
Outputs:
x
Digital Design
Frank Vahid
Extend FSM to Three-Cycles High Laser Timer
Inputs: b; Outputs: x
• Four states x=0
clk ^
• Wait in “Off” state while b is Off b’*clk^
0 (b’)
b*clk ^
• When b is 1 (and rising x=1 clk ^ x=1 clk ^ x=1
clock edge), transition to On1 On2 On3
On1
– Sets x=1
– On next two clock edges,
transition to On2, then On3,
which also set x=1
• So x=1 for three cycles after
button pressed
Digital Design
Frank Vahid
FSM Simplification: Rising Clock Edges Implicit
Inputs: b; Outputs: x
• Showing rising clock on every x=0
clk ^
transition: cluttered Off b’*clk^
– Make implicit -- assume every
edge has rising clock, even if not b*clk ^
x=1 clk ^ x=1 clk ^ x=1
shown
On1 On2 On3
– What if we wanted a transition
without a rising edge
• We don’t consider such Inputs: b; Outputs: x
asynchronous FSMs -- less x=0
common, and advanced topic
Off b’
• Only consider synchronous
a
FSMs -- rising edge on every b
transition x=1 x=1 x=1
On1 On2 On3
Note: Transition with no associated condition thus
Digital Design transistions to next state on next clock cycle
Frank Vahid
FSM Definition
• FSM consists of Inputs: b; Outputs: x
– Set of states x=0
• Ex: {Off, On1, On2, On3} Off b’

– Set of inputs, set of outputs b
• Ex: Inputs: {x}, Outputs: {b} x=1 x=1 x=1
– Initial state On1 On2 On3
• Ex: “Off”
– Set of transitions We often draw FSM graphically,
• Describes next states known as state diagram
• Ex: Has 5 transitions
Can also use table (state table), or
– Set of actions
textual languages
• Sets outputs while in states
• Ex: x=0, x=1, x=1, and x=1
Digital Design
Frank Vahid
FSM Example: Secure Car Key
• Many new car keys include
tiny computer chip
– When car starts, car’s
computer (under engine hood)
requests identifier from key
Inputs: a; Outputs: r
– Key transmits identifier
• If not, computer shuts off car Wait
r=0
• FSM a a’
– Wait until computer requests K1 K2 K3 K4

ID (a=1)
r=1 r=1 r=0 r=1
– Transmit ID (in this case,
1101)
Digital Design
Frank Vahid
FSM Example: Secure Car Key (cont.)
• Nice feature of FSM
Wait
– Can evaluate output behavior r=0 a’
a
for different input sequence
K1 K2 K3 K4
– Timing diagrams show states
r=1 r=1 r=0 r=1
and output values for different
input waveforms
Q: Determine states and r value for
given input waveform:
clk clk
Inputs Inputs
a
a
State Wait Wait K1 K2 K3 K4 Wait Wait State Wait Wait K1 K2 K3 K4 Wait K1
Outputs Output a
r r
Digital Design
Frank Vahid
FSM Example: Code Detector
• Unlock door (u=1) only when Start
s
u
buttons pressed in sequence: r Door
Red Code
– start, then red, blue, green, red a Green
g detector lock
• Input from each button: s, r, g, b Blue b
a
– Also, output a indicates that
some colored button pressed
Inputs: s,r,g,b,a;
• FSM Outputs: u
– Wait for start (s=1) in “Wait” Wait
u=0 s s’
– Once started (“Start”) ar’ ab’ ag’ ar’
a
• If see red, go to “Red1”
Start a’
• Then, if see blue, go to “Blue”
u=0
• Then, if see green, go to ar
“Green” ab ag ar
Red1 Blue Green Red2
• Then, if see red, go to “Red2” a’ a’ a’
– In that state, open the door u=0 u=0 u=0 u=1
(u=1) Q: Can you trick this FSM to open the door,
• Wrong button at any step, return without knowing the code?
to “Wait”, without opening door a
A: Yes, hold all buttons simultaneously
Digital Design
Frank Vahid
Improve FSM for Code Detector
Inputs: s,r,g,b,a;
Outputs: u
Wait
u=0 s s’ ar’ ab’ ag’ ar’ a
Start
a’
u=0
ar
ab ag ar
Red1 Blue Green Red2
a’ a’ a’
u=0 u=0 u=0 u=1 Note: small problem still
remains; we’ll discuss later
• New transition conditions detect if wrong button pressed, returns to “Wait”

• FSM provides formal, concrete means to accurately define desired behavior
Digital Design
Frank Vahid
Standard Controller Architecture
• How implement FSM as sequential Inputs: b; Outputs: x
circuit? x=0
– Use standard architecture Off b’
• State register -- to store the present
state b
• Combinational logic -- to compute x=1 x=1 x=1
outputs, and next state On1 On2 On3
• For laser timer FSM
– 2-bit state register, can represent four
states
– Input b, output x outpu
outputs
inputs
b x
FSM
FSM
FSM
– Known as controller Combinational n1
logic
outputs
inputs
O
FSM
I FSM n0
Combinational
logic s1 s0
S clk State register
a m
m-bit m
clk
state register
Digital Design N
Copyright © 2006 General version 34
Frank Vahid
3.4
Controller Design
• Five step controller design process
Digital Design
Frank Vahid
Controller Design: Laser Timer Example
• Step 1: Capture the FSM Inputs: b; Outputs: x
x=0
– Already done 00
Off b’
• Step 2: Create architecture a
b
– 2-bit state register (for 4 states) x=1 x=1 x=1
01 On1 10 On2 11 On3
– Input b, output x
– Next state signals n1, n0
• Step 3: Encode the states output
outputs
inputs
b x
FSM
FSM
FSM
Combinational n1
– Any encoding with each state logic
unique will work n0
a
s1 s0
clk State register
Digital Design
Frank Vahid
Controller Design: Laser Timer Example (cont)
• Step 4: Create state table Inputs: b; Outputs: x
x=0
00
Off b’
a
b
x=1 x=1 x=1
01 On1 10 On2 11 On3
outputs
inputs
FSM
FSM
b x
Combinational n1
logic
n0
s1 s0
clk State register
Digital Design
Frank Vahid
• Step 5: Implement
outputs
inputs
FSM
FSM
b x
combinational logic Combinational n1
logic
n0
a
s1 s0
clk State register
x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1)
n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’
Digital Design
Frank Vahid
• Step 5: Implement b
Combinational Logic
x FSM out
outputs
inputs
combinational logic (cont)
FSM
FSM
b x
Combinational n1
FSM inputs
logic n1 a
n0
s1 s0
clk State register
n0
s1 s0
clk State register
x = s1 + s0
n1 = s1’s0 + s1s0’
n0 = s1’s0’b + s1s0’
Digital Design
Frank Vahid
Understanding the Controller’s Behavior
x=0 x=0 x=0
00 b’ 00 b’ 00 b’
Off Off Off
b b b
x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1 x=1
01 On1 10 On2 11 On3 01 On1 10 On2 11 On3 01 On1 10 On2 11 On3
b x b x b x
0 0 0
0 0 0 1 0 0 1 1 1
0 0 1
n1 n1 n1
0 0 1
0 0 0 a
0 1 0
n0 n0 n0
0 1 0
0 0 0
s1 s0 s1 s0 s1 s0
clk clk clk
0 0 0 0 0 1
0 0 0 1 1 0
clk state=00 state=00 state=01
Inputs:
b
Outputs:
x
Digital Design
Frank Vahid
Controller Example:
Button Press Synchronizer
Button press
bi synchronizer
bo
controller
• Want simple sequential circuit that converts button press to

single cycle duration, regardless of length of time that
button actually pressed
– We assumed such an ideal button press signal in earlier example,
like the button in the laser timer controller
Digital Design
Frank Vahid
Controller Example:
Button Press Synchronizer (cont)
outputs
inputs
bi bo Step 2: Create architecture
FSM
FSM
FSM inputs: bi; FSM outputs: bo
Combinational
bi’ logic n1
bi
bi’ bi’ n0
A bi B bi C s1 s0 n1 = s1’s0bi + s1s0bi a
n0 = s1’s0’bi
bo=0 bo=1 bo=0 State register bo = s1’s0bi’ + s1’s0bi = s1s0
clk
Combinational logic
Step 1: FSM bo
outp
bi
FSM
n1
FSM inputs: bi; FSM outputs: bo
bi’ n0
bi
bi’
00 bi 01 bi 10 bi’
s1 s0
bo=0 bo=1 bo=0
State register
clk
Step 3: Encode states
Step 4: State table Step 5: Create
combinational circuit
Digital Design
Frank Vahid
Step 5: Create combinational circuit
Controller Example: Sequence Generator
• Want generate sequence 0001, 0011, 1100, 1000, (repeat)
– Each value for one clock cycle
– Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor”
w
Inputs: none; Outputs: w,x,y,z x Inputs: none; Outputs: w,x,y,z
y
wxyz=0001 wxyz=1000 Combinational z wxyz=0001 wxyz=1000
logic
A D n1 A D
n0 00 11
s1 s0
State register 01 10
B C clk B C
wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100
Step 1: Create FSM Step 2: Create architecture Step 3: Encode states
w
w = s1
x = s1s0’
x
FSM outpu
y
y = s1’s0
z
z = s1’
a
n1 = s1 xor s0
n0 = s0’
n0 n1
s1 s0
clk State register
Digital Design Step 4: Create state table
Copyright © 2006 Step 5: Create combinational circuit 43
Frank Vahid
Controller Example: Secure Car Key
• (from earlier example)
Wait
r=0 a a’
Step 1
a
K1 K2 K3 K4
r=1 r=1 r=0 r=1
a r
outputs
Combinational FSM
FSM
Step 2
n2
inputs logic
n1
n0
s2 s1 s0
clk State register
000
r=0 a’
a
Step 3
001 010 011 100

r=1 r=1 r=0 r=1
Digital Design
We’ll omit Step 5 Step 4
Frank Vahid
Example: Seq. Circuit to FSM (Reverse Engineering)
What does this y=s1’ a
A B
circuit do? z = s1s0’ states

n1=(s1 xor s0)x
x y FSM outputs
n0=(s1’*s0’)x
D C
z Outputs:y, z
FSM inputs
A B states
n1 yz=10 yz=10
with
D C outputs
n0 yz=00 yz=01
s1 s0
Inputs: x; Outputs:y, z
State register
clk x
x’ A B yz=10
yz=10 x’ x
Work backwards D x’ C yz=01
yz=00
Pick any state names you want x
states with
outputs and
Digital Design transitions
Frank Vahid
Common Pitfalls Regarding Transition Properties
a
• Only one condition should b

ab=11 –
be true next state? a
– For all transitions leaving a

state
a
– Else, which one? a
• One condition must be true a’b

what if
a’b
– For all transitions leaving a ab=00?
state
a’b’
– Else, where go?
a
a’b
Digital Design
Frank Vahid
Verifying Correct Transition Properties
• Can verify using Boolean algebra Answer:
a * a’b
– Only one condition true: AND of each condition pair (for = (a * a’) * b
transitions leaving a state) should equal 0  proves pair =0*b
can never simultaneously be true =0 a
OK!
– One condition true: OR of all conditions of transitions
leaving a state) should equal 1  proves at least one a + a’b
= a*(1+b) + a’b
condition must be true = a + ab + a’b
– Example = a + (a+a’)b
a =a+b
Fails! Might not
be 1 (i.e., a=0,
a’b b=0)
Q: For shown transitions, prove whether:

* Only one condition true (AND of each pair is always 0)
* One condition true (OR of all transitions is always 1)
Digital Design
Frank Vahid
Evidence that Pitfall is Common
• Recall code detector FSM
– We “fixed” a problem with the Wait
u=0 s s’ a
transition conditions
– Do the transitions obey the two Start
required transition properties? u=0ar a’
• Consider transitions of state ab ag ar
Start, and the “only one true” Red1 Blue Green Red2
a’ a’ a’
property u=0 u=0 u=0 u=1
ar * a’ a’ * a(r’+b+g) ar * a(r’+b+g) Intuitively: press red and blue
= (a*a’)r = 0*r = (a’*a)*(r’+b+g) = 0*(r’+b+g) buttons at same time: conditions
= (a*a)*r*(r’+b+g) = a*r*(r’+b+g) ar, and a(r’+b+g) will both be
=0 =0 = arr’+arb+arg true. Which one should be
taken?
= 0 + arb+arg
= arb + arg Q: How to solve? a
= ar(b+g) A: ar should be arb’g’

Fails! Means that two of Start’s (likewise for ab, ag, ar)
transitions could be true Note: As evidence the pitfall is common,
Digital Design we admit the mistake was not intentional.
Copyright © 2006 A reviewer of the book caught it. 48
Frank Vahid
Simplifying Notations
a=0 a=0
• FSMs b=1 b=0 a
c=0 c=1
– Assume unassigned output clk a
implicitly assigned 0
• Sequential circuits
– Assume unconnected clock b=1 c=1
inputs connected to same
external clock
a
Digital Design
Frank Vahid
3.5
More on Flip-Flops and Controllers

• Other flip-flop types
– SR flip-flop: like SR latch, but edge triggered
– JK flip-flop: like SR (SJ, RK)
• But when JK=11, toggles
• 10, 01
– T flip-flop: JK with inputs tied together
• Toggles on every rising clock edge
– Previously utilized to minimize logic outside flip-flop
• Today, minimizing logic to such extent is not as important
• D flip-flops are thus by far the most common
Digital Design
Frank Vahid
Non-Ideal Flip-Flop Behavior
• Can’t change flip-flop input too close to clock
edge
– Setup time: time that D must be stable before edge
• Else, stable value not present at internal latch
– Hold time: time that D must be held stable after
edge
• Else, new value doesn’t have time to loop around
and stabilize in internal latch
Setup time violation
Leads to oscillation!
Digital Design
Frank Vahid
Metastability
• Violating setup/hold time can lead to bad
situation known as metastable state
– Metastable state: Any flip-flop state other
than stable 1 or 0
• Eventually settles to one or other, but we
don’t know which
– For internal circuits, we can make sure
observe setup time
– But what if input comes from external
(asynchronous) source, e.g., button
press?
• Partial solution
– Insert synchronizer flip-flop for
asynchronous input a
• Special flip-flop with very small setup/hold
time
– Doesn’t completely prevent metastability
Digital Design
Frank Vahid
Metastability
• One flip-flop doesn’t completely solve problem
• How about adding more synchronizer flip-flops?
– Helps, but just decreases probability of metastability
• So how solve completely?
– Can’t! May be unsettling to new designers. But we just can’t guarantee a
design that won’t ever be metastable. We can just minimize the mean time
between failure (MTBF) -- a number often given along with a circuit
Probability of flip-flop being metastable is…

very
very very incredibly
low low low low
ai
synchronizers
Digital Design
Frank Vahid
Flip-Flop Set and Reset Inputs
• Some flip-flops have D Q’ D Q’ D
AR
Q’
additional inputs Q
Q Q
– Synchronous reset: clears Q to 0 AR AS
R
on next clock edge
– Synchronous set: sets Q to 1 on
next clock edge
– Asynchronous reset: clear Q to 0
immediately (not dependent on
clock edge)
• Example timing diagram shown
– Asynchronous set: set Q to 1
immediately
Digital Design
Frank Vahid
Initial State of a Controller
• All our FSMs had initial state Inputs: x; Outputs: b
x=0
– But our sequential circuit designs
Off b’
did not
b
– Can accomplish using flip-flops x=1 x=1 x=1
with reset/set inputs On1 On2 On3
• Shown circuit initializes flip-flops to
01 b x
Combinational
– Designer must ensure reset input n1
logic
is 1 during power up of circuit n0
s1 s0
• By electronic circuit design State register
clk
D Q’ D Q’
Q Q
R S
reset
Digital Design
Frank Vahid
Glitching
• Glitch: Temporary values on outputs that appear soon after
input changes, before stable new output values
• Designer must determine whether glitching outputs may
pose a problem
– If so, may consider adding flip-flops to outputs
• Delays output by one clock cycle, but may be OK
Digital Design
Frank Vahid
Active Low Inputs
• We’ve assumed input action

occur when input is 1
D Q’
– Some inputs are instead active
when input is 0 -- “active low”
Q
– Shown with inversion bubble R
– So to reset the shown flip-flop,
set R=0. Else, keep R=1.
Digital Design
Frank Vahid
Chapter Summary
• Sequential circuits
– Have state
• Created robust bit-storage device: D flip-flop
– Put several together to build register, which we used to hold state
• Defined FSM formal model to describe sequential behavior
– Using solid mathematical models -- Boolean equations for
combinational circuit, and FSMs for sequential circuits -- is very
important.
• Defined 5-step process to convert FSM to sequential circuit
– Controller
• So now we know how to build the class of sequential
circuits known as controllers
Digital Design
Frank Vahid

Digital Design: Sequential Logic Design - Controllers

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Digital Design

Copyright © 2007 Frank Vahid

• Stores bits, also known as having “state”

Example Needing Bit Storage

– Press call: light turns on

Call Q 2. Call button released – light stays on

R=1 R=0 R=0 R=0

The longer path from X to R than to S causes SR=11 for

• How do we know when it’s safe to set C=1?

• Clock period: time interval between pulses

• D latch relieves designer of that C

– Two latches, output of first goes to input of second, master

D Q’ D Q’ Internal design: Just

rising edges falling edges

of D flip-flop, Q button system

• Truth table shown below

Preserve value: if Circuit derived from truth table,

Cancel -- make Call Call

Let’s give priority

• We considered increasingly better bit storage until we

Present 1 hour ago 2 hours ago

Finite-State Machines (FSMs) and Controllers

– How? Let’s try three flip-flops

• Can describe as FSM Off On1 On2 On3

clock edge), transition to On1 On2 On3

• Ex: {Off, On1, On2, On3} Off b’

– Wait until computer requests K1 K2 K3 K4

• New transition conditions detect if wrong button pressed, returns to “Wait”

clk State register

x = s1 + s0 (note from the table that x=1 if s1 = 1 or s0 = 1)

n1 = s1’s0b’ + s1’s0b + s1s0’b’ + s1s0’b

n0 = s1’s0’b + s1s0’b’ + s1s0’b

clk State register

clk state=00 state=00 state=01

• Want simple sequential circuit that converts button press to

001 010 011 100

circuit do? z = s1s0’ states

• Only one condition should b

– For all transitions leaving a

• One condition must be true a’b

Q: For shown transitions, prove whether:

= ar(b+g) A: ar should be arb’g’

More on Flip-Flops and Controllers

Probability of flip-flop being metastable is…

• We’ve assumed input action

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