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SA555 - SE555
Features
■ Low turn-off time
■ Maximum operating frequency greater than
500 kHz
■ Timing from microseconds to hours N
■ Operates in both astable and monostable DIP8
modes (Plastic package)
■ Output can source or sink up to 200 mA
■ Adjustable duty cycle
■ TTL compatible
■ Temperature stability of 0.005% per °C D
SO8
(Plastic micropackage)
Description
The NE555, SA555, and SE555 monolithic timing
circuits are highly stable controllers capable of
Pin connections
producing accurate time delays or oscillation. In
(top view)
the time delay mode of operation, the time is
precisely controlled by one external resistor and
capacitor. For a stable operation as an oscillator,
the free running frequency and the duty cycle are 1 8
both accurately controlled with two external
resistors and one capacitor. 2 7
1 Schematic diagrams
VCC+
5kΩ
COMP
DISCHARGE
THRESHOLD
CONTROL VOLTAGE R
FLIP-FLOP
5kΩ Q
COMP OUT
TRIGGER
S
INHIBIT/
RESET
5kΩ
RESET S
Supply voltage
VCC NE555 4.5 to 16 V
SA555 4.5 to 16
SE555 4.5 to 18
Vth, Vtrig,
Maximum input voltage VCC V
Vcl, Vreset
IOUT Output current (sink and source) ±200 mA
Operating free air temperature range
NE555 0 to 70
Toper °C
SA555 -40 to 105
SE555 -55 to 125
3 Electrical characteristics
Figure 3. Minimum pulse width required for Figure 4. Supply current versus supply
triggering voltage
Figure 5. Delay time versus temperature Figure 6. Low output voltage versus output
sink current
Figure 7. Low output voltage versus output Figure 8. Low output voltage versus output
sink current sink current
Figure 9. High output voltage drop versus Figure 10. Delay time versus supply voltage
output
4 Application information
VCC = 5 to 15V
Reset
R1
4 8
Trigger 2 7
NE555 6 C1
Control Voltage
Output 3 5
1 0.01μF
The circuit triggers on a negative-going input signal when the level reaches 1/3 VCC. Once
triggered, the circuit remains in this state until the set time has elapsed, even if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R1C1 and
is easily determined by Figure 14.
Note that because the charge rate and the threshold level of the comparator are both
directly proportional to supply voltage, the timing interval is independent of supply. Applying
a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2)
during the timing cycle discharges the external capacitor and causes the cycle to start over.
The timing cycle now starts on the positive edge of the reset pulse. During the time the reset
pulse is applied, the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 2, the flip-flop is set, releasing the short-
circuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time constant t = R1C1. When the voltage across
the capacitor equals 2/3 VCC, the comparator resets the flip-flop which then discharges the
capacitor rapidly and drives the output to its LOW state.
Figure 13 shows the actual waveforms generated in this mode of operation.
When Reset is not used, it should be tied high to avoid any possibility of unwanted
triggering.
t = 0.1 ms / div
INPUT = 2.0V/div
C
(μF)
10
Ω
1k
1.0
1=
k
R
10
Ω
0k
10
0.1
1M
Ω
M
10
0.01
0.001
10 100 1.0 10 100 10 (t d )
μs μs ms ms ms s
VCC = 5 to 15V
R1
4 8
Output 3 7
NE555 R2
Control
Voltage
5 6
0.01μF
1 2 C1
t = 0.5 ms / div
C
(μF)
10 1k
10 Ω
1.0 kΩ
R 10
1 0k
+ 1M Ω
0.1 R2 Ω
=
10
M
0.01 Ω
0.001
0.1 1 10 100 1k 10k f o (Hz)
VCC
RA
4 8
Trigger 2 7
NE555 6
Modulation
Input
Output 3 5
C
1
VCC
RE R1
4 8
Trigger 2 7
2N4250
or equiv.
NE555 6
C
Output 3 5 R2
0.01μF
1
VCC = 5 V
Time:
20 µs/DIV Top trace: input 3 V/DIV
R1 + 47 kΩ Middle trace: output 5 V/DIV
R2 = 100 kΩ Bottom trace: output 5 V/DIV
RE = 2.7 kΩ Bottom trace: capacitor voltage 1 V/DIV
C = 0.01 µF
VCC
VCC
RA
51kΩ
4 8
RB
2 7
22kΩ
NE555 6
Out 3 5 0.01μF
C
1 0.01μF
Note that this circuit will not oscillate if RB is greater than 1/2 RA because the junction of RA
and RB cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.
5 Package information
A 5.33 0.210
A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b 0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c 0.20 0.25 0.36 0.008 0.010 0.014
D 9.02 9.27 10.16 0.355 0.365 0.400
E 7.62 7.87 8.26 0.300 0.310 0.325
E1 6.10 6.35 7.11 0.240 0.250 0.280
e 2.54 0.100
eA 7.62 0.300
eB 10.92 0.430
L 2.92 3.30 3.81 0.115 0.130 0.150
A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.010
D 4.80 4.90 5.00 0.189 0.193 0.197
E 5.80 6.00 6.20 0.228 0.236 0.244
E1 3.80 3.90 4.00 0.150 0.154 0.157
e 1.27 0.050
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
L1 1.04 0.040
k 0 8° 1° 8°
ccc 0.10 0.004
6 Ordering information
7 Revision history
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