Académique Documents
Professionnel Documents
Culture Documents
TOPSwitch-HX Family
®
Enhanced EcoSmart , Integrated Off-Line Switcher with
Advanced Feature Set and Extended Power Range
Product Highlights
+
Lower System Cost, Higher Design Flexibility AC DC
• Multi-mode operation maximizes efficiency at all loads IN OUT
-
• No heatsink required up to 35 W using P, G and M packages
with universal input voltage and up to 48 W at 230 VAC
• Output overvoltage protection (OVP) is user programmable for
D V
latching/non-latching shutdown with fast AC reset
• Allows both primary and secondary sensing CONTROL
TOPSwitch-HX C
• Line undervoltage (UV) detection prevents turn-off glitches
• Line overvoltage (OV) shutdown extends line surge limit S X F
• Accurate programmable current limit
• Optimized line feed-forward for line ripple rejection
• 132 kHz frequency (Y package) reduces transformer and power PI-4510-100206
supply size Figure 1. Typical Flyback Application.
• Half frequency option in Y package for video applications
• Tight I2f parameter tolerance reduces system cost
• Maximizes MOSFET and transformer power delivery • Energy efficient over entire load range
• Minimizes overload power, reducing cost of transformer, • No-load consumption <200 mW at 265 VAC
primary clamp and secondary components • Standby power for 1 W input
• Frequency jittering reduces EMI filter cost • >600 mW output at 110 VAC input
• Improved auto-restart delivers <3% of maximum power in short • >500 mW output at 265 VAC input
circuit and open loop fault conditions
• Accurate hysteretic thermal shutdown function automatically Description
recovers without requiring a reset
• Fully integrated soft-start for minimum start-up stress TOPSwitch-HX cost effectively incorporates a 700 V power
• Pin-out simplifies heatsinking to the PCB for P, G and M packages MOSFET, high voltage switched current source, PWM control,
• Extended creepage between DRAIN and all other pins improves oscillator, thermal shutdown circuit, fault protection and other
field reliability control circuitry onto a monolithic device.
• Heatsink is connected to SOURCE for low EMI
®
EcoSmart – Energy Efficient
VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
÷ 16
ON/OFF
+
SHUTDOWN/
AUTO-RESTART CURRENT LIMIT
VBG + VT COMPARATOR
SOURCE (S)
PI-4508-082907
VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
÷ 16
ON/OFF
+
SHUTDOWN/
EXTERNAL AUTO-RESTART CURRENT LIMIT
CURRENT VBG + VT COMPARATOR
LIMIT (X)
VOLTAGE STOP LOGIC HYSTERETIC
MONITOR (V) THERMAL SOURCE (S)
1V
SHUTDOWN
CONTROLLED
TURN-ON
STOP SOFT GATE DRIVER
V OVP OV/ START
UV
LINE OSCILLATOR DMAX
DCMAX DCMAX
SENSE WITH JITTER
CLOCK
F REDUCTION S Q
LEADING
R EDGE
BLANKING
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)
SOURCE (S)
PI-4643-082907
2
Rev. A www.powerint.com
09/07
TOP254-258
VC
0
CONTROL (C) DRAIN (D)
ZC INTERNAL
1 SUPPLY
SHUNT REGULATOR/ -
ERROR AMPLIFIER + +
SOFT START
- 5.8 V
4.8 V -
+ 5.8 V
INTERNAL UV KPS(UPPER) -
IFB COMPARATOR
+
VI (LIMIT)
CURRENT
LIMIT
ADJUST KPS(LOWER) -
÷ 16
ON/OFF
+
SHUTDOWN/
EXTERNAL AUTO-RESTART CURRENT LIMIT
CURRENT VBG + VT COMPARATOR
LIMIT (X)
VOLTAGE STOP LOGIC HYSTERETIC
MONITOR (V) THERMAL SOURCE (S)
1V
SHUTDOWN
CONTROLLED
TURN-ON
STOP SOFT GATE DRIVER
V OVP OV/ START
UV
LINE OSCILLATOR DMAX
DCMAX DCMAX
SENSE WITH JITTER
CLOCK
66k/132k
F REDUCTION S Q
LEADING
R EDGE
FREQUENCY BLANKING
(F)
F REDUCTION
SOFT START
IFB PWM OFF
KPS(UPPER) IPS(UPPER)
KPS(LOWER) IPS(LOWER)
SOURCE (S)
PI-4511-082907
3
www.powerint.com Rev. A
09/07
TOP254-258
PI-4711-061507
voltage current source. Internal current limit sense point for
drain current. + VUV = IUV × RLS
VOV = IOV × RLS
CONTROL (C) Pin: For RLS = 4 M7
Error amplifier and feedback current input pin for duty cycle RLS 4 M7
VUV = 100 VDC
control. Internal shunt regulator connection to provide internal VOV = 450 VDC
bias current during normal operation. It is also used as the DC DCMAX@100 VDC = 75%
connection point for the supply bypass and auto-restart/ Input D V DCMAX@375 VDC = 41%
Voltage CONTROL
compensation capacitor. C
For RIL = 12 k7
EXTERNAL CURRENT LIMIT (X) Pin (Y & M package only): ILIMIT = 63%
S X
Input pin for external current limit adjustment and remote
ON/OFF. A connection to SOURCE pin disables all functions RIL See Figure 50b for
12 k7 other resistor values
on this pin. - (RIL) to select different
ILIMIT values.
VOLTAGE MONITOR (V) Pin (Y & M package only):
Input for OV, UV, line feed forward with DCMAX reduction, output Figure 4. Y/M Package Line Sense and Externally Set Current Limit.
overvoltage protection (OVP), remote ON/OFF and device reset.
A connection to the Source pin disables all functions on this pin.
M Package
Y Package
V 1 10 S
X 2 9 S
+
C 3 8 S For RIL = 12 k7
S ILIMIT = 63%
7
D 5 6 S For RIL = 19 k7
ILIMIT = 40%
Tab Internally
Connected to DC
P and G Package See Figure 50b for other
SOURCE Pin Input
resistor values (RIL) to
Voltage
M S select different ILIMIT values.
1 8 D M
C 2 7 S CONTROL
RIL C
6 S 12345 7
VXCS F D - S
D 4 5 S
PI-4644-041107 PI-4713-061507
Figure 3. Pin Configuration (Top View). Figure 6. P/G Package Externally Set Current Limit.
4
Rev. A www.powerint.com
09/07
TOP254-258
components: Variable
Frequency Mode
66 Mode
1. A fully integrated 17 ms soft-start significantly reduces or
eliminates output overshoot in most applications by sweeping Jitter Multi-Cycle
Modulation
both current limit and frequency from low to high to limit the
peak currents and voltages during start-up. 30
2. A maximum duty cycle (DCMAX) of 78% allows smaller input
storage capacitor, lower input voltage requirement and/or
ICD1 IB IC01 IC02 IC03 ICOFF CONTROL
higher power capability. Current
3. Multi-mode operation optimizes and improves the power PI-4645-041107
supply efficiency over the entire load range while maintaining Figure 7. Control Pin Characteristics (Multi-Mode Operation).
good cross regulation in multi-output supplies.
4. Switching frequency of 132 kHz reduces the transformer size
with no noticeable impact on EMI. reduction. In this mode, the value of the resistor determines the
5. Frequency jittering reduces EMI in the full frequency mode at OV/UV thresholds and the DCMAX is reduced linearly with a dual
high load condition. slope to further improve the line ripple rejection. In addition, it
6. Hysteretic over-temperature shutdown ensures automatic also provides another threshold to implement the latched and
recovery from thermal fault. Large hysteresis prevents circuit hysteretic output overvoltage protection (OVP). The pin can
board overheating. also be used as a remote ON/OFF using the IUV threshold.
7. Packages with omitted pins and lead forming provide large
drain creepage distance. The EXTERNAL CURRENT LIMIT (X) pin is usually used to
8. Reduction of the auto-restart duty cycle and frequency to reduce the current limit externally to a value close to the
improve the protection of the power supply and load during operating peak current, by connecting the pin to SOURCE
open loop fault, short circuit, or loss of regulation. through a resistor. This pin can also be used as a remote
9. Tighter tolerances on I2f power coefficient, current limit ON/OFF input.
reduction, PWM gain and thermal shutdown threshold.
For the P and G package the VOLTAGE-MONITOR and
The VOLTAGE-MONITOR (V) pin is usually used for line sensing EXTERNAL CURRENT LIMIT pin functions are combined on
by connecting a 4 MΩ resistor from this pin to the rectified DC one MULTI-FUNCTION (M) pin. However, some of the functions
high voltage bus to implement line overvoltage (OV), under- become mutually exclusive.
voltage (UV) and dual-slope line feed-forward with DCMAX
5
www.powerint.com Rev. A
09/07
TOP254-258
7 kHz to reduce the effect of switching noise in the chip supply Maximum Duty Cycle
current generated by the MOSFET gate driver. The maximum duty cycle, DCMAX is set at a default maximum
value of 78% (typical). However, by connecting the VOLTAGE-
To optimize power supply efficiency, four different control MONITOR or MULTI-FUNCTION pin (depending on the
modes are implemented. At maximum load, the modulator package) to the rectified DC high voltage bus through a resistor
operates in full frequency PWM mode, as load decreases, the with appropriate value (4 MΩ typical), the maximum duty cycle
modulator automatically transitions, first to variable frequency can be made to decrease from 78% to 40% (typical) when input
PWM mode, then to low frequency PWM mode. At light load, line voltage increases from 88 V to 380 V, with dual gain slopes.
the control operation switches from PWM control to multi-cycle-
modulation control, and the modulator operates in multi-cycle- Error Amplifier
modulation mode. Although different modes operate differently, The shunt regulator can also perform the function of an error
to make transitions between modes smooth, the simple amplifier in primary side feedback applications. The shunt
relationship between duty cycle and excess CONTROL pin regulator voltage is accurately derived from a temperature-
current shown in Figure 7 is maintained through all three PWM compensated bandgap reference. The CONTROL pin dynamic
modes. Please see the following sections for the details of the impedance ZC sets the gain of the error amplifier. The
operation of each mode and the transitions between modes. CONTROL pin clamps external circuit signals to the VC voltage
level. The CONTROL pin current in excess of the supply
Full Frequency PWM mode: The PWM modulator enters full current is separated by the shunt regulator and becomes the
frequency PWM mode when the CONTROL pin current (IC) feedback current Ifb for the pulse width modulator.
reaches IB. In this mode, the average switching frequency is
kept constant at fOSC (66 kHz for P, G and M packages, pin On-Chip Current Limit with External Programmability
selectable 132 kHz or 66 kHz for Y package). Duty cycle is The cycle-by-cycle peak drain current limit circuit uses the
reduced from DCMAX through the reduction of the on-time when output MOSFET ON-resistance as a sense resistor. A current
IC is increased beyond IB. This operation is identical to the PWM limit comparator compares the output MOSFET on-state drain
control of all other TOPSwitch families. TOPSwitch-HX only to source voltage, VDS(ON) with a threshold voltage. High drain
operates in this mode if the cycle-by-cycle peak drain current current causes VDS(ON) to exceed the threshold voltage and turns
stays above kPS(UPPER)*ILIMIT(set), where kPS(UPPER) is 55% (typical) the output MOSFET off until the start of the next clock cycle.
and ILIMIT(set) is the current limit externally set via the X or M pin. The current limit comparator threshold voltage is temperature
compensated to minimize the variation of the current limit due
Variable Frequency PWM mode: When peak drain current is to temperature related changes in RDS(ON) of the output MOSFET.
lowered to kPS(UPPER)* ILIMIT(set) as a result of power supply load The default current limit of TOPSwitch-HX is preset internally.
reduction, the PWM modulator initiates the transition to variable However, with a resistor connected between EXTERNAL
frequency PWM mode, and gradually turns off frequency jitter. CURRENT LIMIT (X) pin (Y and M packages) or MULTI-
In this mode, peak drain current is held constant at kPS(UPPER)* FUNCTION (M) pin (P and G package) and SOURCE pin,
ILIMIT(set) while switching frequency drops from the initial full current limit can be programmed externally to a lower level
frequency of fOSC (132 kHz or 66 kHz) towards the minimum between 30% and 100% of the default current limit. By setting
frequency of fMCM(MIN) (30 kHz typical). Duty cycle reduction is current limit low, a larger TOPSwitch-HX than necessary for the
accomplished by extending the off-time. power required can be used to take advantage of the lower
RDS(ON) for higher efficiency/smaller heat sinking requirements.
Low Frequency PWM mode: When switching frequency TOPSwitch-HX current limit reduction initial tolerance through
reaches fMCM(MIN) (30 kHz typical), the PWM modulator starts to the X pin (or M pin) has been improved significantly compare
transition to low frequency mode. In this mode, switching with previous TOPSwitch-GX. With a second resistor
frequency is held constant at fMCM(MIN) and duty cycle is reduced, connected between the EXTERNAL CURRENT LIMIT (X) pin
similar to the full frequency PWM mode, through the reduction (Y and M packages) or MULTI-FUNCTION (M) pin (P and G
of the on-time. Peak drain current decreases from the initial package) and the rectified DC high voltage bus, the current limit
value of kPS(UPPER)* ILIMIT(set) towards the minimum value of is reduced with increasing line voltage, allowing a true power
kPS(LOWER)*ILIMIT(set), where kPS(LOWER) is 25% (typical) and ILIMIT(set) is limiting operation against line variation to be implemented.
the current limit externally set via the X or M pin. When using an RCD clamp, this power limiting technique
reduces maximum clamp voltage at high line. This allows for
Multi-Cycle-Modulation mode: When peak drain current is higher reflected voltage designs as well as reducing clamp
lowered to kPS(LOWER)*ILIMIT(set), the modulator transitions to multi- dissipation.
cycle-modulation mode. In this mode, at each turn-on, the
modulator enables output switching for a period of TMCM(MIN) at The leading edge blanking circuit inhibits the current limit
the switching frequency of fMCM(MIN) (4 or 5 consecutive pulses at comparator for a short time after the output MOSFET is turned
30 kHz) with the peak drain current of kPS(LOWER)*ILIMIT(set), and on. The leading edge blanking time has been set so that, if a
stays off until the CONTROL pin current falls below IC(OFF). This power supply is designed properly, current spikes caused by
mode of operation, not only keeps peak drain current low, but primary-side capacitances and secondary-side rectifier reverse
also minimizes harmonic frequencies between 6 kHz and recovery time should not cause premature termination of the
30 kHz. By avoiding transformer resonant frequency this way, switching pulse.
all potential transformer audible noises are greatly supressed.
7
www.powerint.com Rev. A
09/07
TOP254-258
~
~
~
~
VUV
~
~
~
~
~
~
VLINE
0V
S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S14 S13 S12 S0 S15 S15 5.8 V
~
~
~
~
~
~
VC 4.8 V
0V
~
~
~
~
VDRAIN
~
~
0V
VOUT
~
~
~
~
~
~
0V
1 2 3 2 4
Note: S0 through S15 are the output states of the auto-restart counter PI-4531-121206
Figure 9. Typical Waveforms for (1) Power Up (2) Normal Operation (3) Auto-Restart (4) Power Down.
The current limit is lower for a short period after the leading TOPSwitch-HX output will be forced into off state. Unlike with
edge blanking time. This is due to dynamic characteristics of TOPSwitch-GX, however, when the line voltage is back to
the MOSFET. During startup and fault conditions the controller normal with a small amount of hysteresis provided on the OV
prevents excessive drain currents by reducing the switching threshold to prevent noise triggering, the state machine sets to
frequency. S13 and forces TOPSwitch-HX to go through the entire auto-
restart sequence before attempting to switch again. The ratio
Line Undervoltage Detection (UV) of OV and UV thresholds is preset at 4.5 as can be seen in
At power up, UV keeps TOPSwitch-HX off until the input line Figure 10. When the MOSFET is off, the rectified DC high
voltage reaches the under-voltage threshold. At power down, voltage surge capability is increased to the voltage rating of the
UV prevents auto-restart attempts after the output goes out of MOSFET (700 V), due to the absence of the reflected voltage
regulation. This eliminates power down glitches caused by slow and leakage spikes on the drain. The OV feature can be
discharge of the large input storage capacitor present in disabled independent of the UV feature.
applications such as standby supplies. A single resistor
connected from the VOLTAGE-MONITOR pin (Y and M In order to reduce the no-load input power of TOPSwitch-HX
packages) or MULTI-FUNCTION pin (P and G packages) to the designs the V-pin (or M-pin for P Package) operates at very low
rectified DC high voltage bus sets UV threshold during power currents. This requires careful layout considerations when
up. Once the power supply is successfully turned on, the UV designing the PCB to avoid noise coupling. Traces and
threshold is lowered to 44% of the initial UV threshold to allow components connected to the V-pin should not be adjacent to
extended input voltage operating range (UV low threshold). If any traces carrying switching currents. These include the drain,
the UV low threshold is reached during operation without the clamp network, bias winding return or power traces from other
power supply losing regulation, the device will turn off and stay converters. If the line sensing features are used then the sense
off until UV (high threshold) has been reached again. If the resistors must be placed within 10 mm of the V-pin to minimize
power supply loses regulation before reaching the UV low the V pin node area. The DC bus should then be routed to the
threshold, the device will enter auto-restart. At the end of each line sense resistors. Note that external capacitance must not
auto-restart cycle (S15), the UV comparator is enabled. If the be connected to the V-pin as this may cause misoperaton of the
UV high threshold is not exceeded the MOSFET will be disabled V pin related functions.
during the next cycle (see Figure 9). The UV feature can be
disabled independent of the OV feature. Hysteretic or Latching Output Overvoltage Protection (OVP)
The detection of the hysteretic or latching output overvoltage
Line Overvoltage Shutdown (OV) protection (OVP) is through the trigger of the line overvoltage
The same resistor used for UV also sets an overvoltage threshold. The V-pin or M-pin voltage will drop by 0.5 V, and
threshold, which, once exceeded, will force TOPSwitch-HX to the controller measures the external attached impedance right
stop switching instantaneously (after completion of the current after this voltage drops. If IV or IM exceeds IOV(LS) (336 μA typical)
switching cycle). If this condition lasts for at least 100 μs, the longer than 100 μs, TOPSwitch-HX will latch into a permanent
8
Rev. A www.powerint.com
09/07
TOP254-258
off state for the latching OVP. It only can be reset if V V or VM same CONTROL pin current, higher line voltage results in smaller
goes below 1 V or VC goes below the power-up-reset threshold operating duty cycle. As an added feature, the maximum duty
(VC(RESET)) and then back to normal. cycle DCMAX is also reduced from 78% (typical) at a voltage slightly
lower than the UV threshold to 30% (typical) at the OV threshold.
If IV or IM does not exceed IOV(LS) or exceeds no longer than DCMAX of 36% at high line was chosen to ensure that the power
100 μs, TOPSwitch-HX will initiate the line overvoltage and the capability of the TOPSwitch-HX is not restricted by this feature
hysteretic OVP. Their behavior will be identical to the line under normal operation. TOPSwitch-HX provides a better fit to the
overvoltage shutdown (OV) that had been described in detail in ideal feed-forward by using two reduction slopes: -1% per μA for all
the previous section. bus voltage less than 192 V (typical for 4 MΩ line impedance) and
-0.25% per μA for all bus voltage more than 192 V. This dual
Line Feed-Forward with DCMAX Reduction slope line feed-forward improves the line ripple rejection
The same resistor used for UV and OV also implements line voltage significantly compared with the TOPSwitch-GX.
feed-forward, which minimizes output line ripple and reduces
power supply output sensitivity to line transients. Note that for the Remote ON/OFF
Table 2. VOLTAGE MONITOR (V) Pin and EXTERNAL CURRENT LIMIT (X) Pin Configuration Options.
9
www.powerint.com Rev. A
09/07
TOP254-258
M Pin
X Pin V Pin
Current
Limit
DCMAX (78%)
Maximum
Duty Cycle
VBG
Pin Voltage
I
-250 -200 -150 -100 -50 0 25 50 75 100 125 336
X and V Pins (Y and M Packages) and M Pin (P and G Packages) Current (μA)
Note: This figure provides idealized functional characteristics with typical performance values. Please refer to the parametric
table and typical performance characteristics sections of the data sheet for measured data. For a detailed description of
each functional pin operation refer to the Functional Description section of the data sheet.
PI-4646-041107
Figure 10. MULTI-FUNCTION (P and G package). VOLTAGE MONITOR and EXTERNAL CURRENT LIMIT (Y and M package) Pin Characteristics.
10
Rev. A www.powerint.com
09/07
TOP254-258
TOPSwitch-HX can be turned on or off by controlling the regulation changes from shunt mode to the hysteretic auto-
current into the VOLTAGE-MONITOR pin or out from the restart mode as described in CONTROL pin operation section.
EXTERNAL CURRENT LIMIT pin (Y and M packages) and into When the fault condition is removed, the power supply output
or out from the MULTI-FUNCTION pin (P and G package, see becomes regulated, VC regulation returns to shunt mode, and
Figure 10). In addition, the VOLTAGE-MONITOR pin has a 1 V normal operation of the power supply resumes.
threshold comparator connected at its input. This voltage
threshold can also be used to perform remote ON/OFF control. Hysteretic Over-Temperature Protection
Temperature protection is provided by a precision analog circuit
When a signal is received at the VOLTAGE-MONITOR pin or the that turns the output MOSFET off when the junction
EXTERNAL CURRENT LIMIT pin (Y and M packages) or the temperature exceeds the thermal shutdown temperature
MULTI-FUNCTION pin (P and G package) to disable the output (142 °C typical). When the junction temperature cools to below
through any of the pin functions such as OV, UV and remote the hysteretic temperature, normal operation resumes providing
ON/OFF, TOPSwitch-HX always completes its current switching automatic recovery. A large hysteresis of 75 °C (typical) is
cycle before the output is forced off. provided to prevent overheating of the PC board due to a
continuous fault condition. VC is regulated in hysteretic mode
As seen above, the remote ON/OFF feature can also be used as and a 4.8 V to 5.8 V (typical) triangular waveform is present on
a standby or power switch to turn off the TOPSwitch-HX and the CONTROL pin while in thermal shutdown.
keep it in a very low power consumption state for indefinitely
long periods. If the TOPSwitch-HX is held in remote off state for Bandgap Reference
long enough time to allow the CONTROL pin to discharge to the All critical TOPSwitch-HX internal voltages are derived from a
internal supply undervoltage threshold of 4.8 V (approximately temperature-compensated bandgap reference. This voltage
32 ms for a 47 μF CONTROL pin capacitance), the CONTROL reference is used to generate all other internal current
pin goes into the hysteretic mode of regulation. In this mode, references, which are trimmed to accurately set the switching
the CONTROL pin goes through alternate charge and discharge frequency, MOSFET gate drive current, current limit, and the
cycles between 4.8 V and 5.8 V (see CONTROL pin operation line OV/UV/OVP thresholds. TOPSwitch-HX has improved
section above) and runs entirely off the high voltage DC input, circuitry to maintain all of the above critical parameters within
but with very low power consumption (160 mW typical at very tight absolute and temperature tolerances.
230 VAC with M or X pins open). When the TOPSwitch-HX is
remotely turned on after entering this mode, it will initiate a High-Voltage Bias Current Source
normal start-up sequence with soft-start the next time the This high-voltage current source biases TOPSwitch-HX from the
CONTROL pin reaches 5.8 V. In the worst case, the delay from DRAIN pin and charges the CONTROL pin external capacitance
remote on to start-up can be equal to the full discharge/charge during start-up or hysteretic operation. Hysteretic operation
cycle time of the CONTROL pin, which is approximately 125 ms occurs during auto-restart, remote OFF and over-temperature
for a 47 μF CONTROL pin capacitor. This reduced shutdown. In this mode of operation, the current source is
consumption remote off mode can eliminate expensive and switched on and off with an effective duty cycle of
unreliable in-line mechanical switches. It also allows for approximately 35%. This duty cycle is determined by the ratio
microprocessor controlled turn-on and turn-off sequences that of CONTROL pin charge (IC) and discharge currents (ICD1 and
may be required in certain applications such as inkjet and laser ICD2). This current source is turned off during normal operation
printers. when the output MOSFET is switching. The effect of the
current source switching will be seen on the DRAIN voltage
Soft-Start waveform as small disturbances and is normal.
The 17 ms soft-start sweeps the peak Drain current and
switching frequency linearly from minimum to maximum value
by operating through the low frequency PWM mode and the
variable frequency mode before entering the full frequency
mode. In addition to start-up, soft-start is also activated at
each restart attempt during auto-restart and when restarting
after being in hysteretic regulation of CONTROL pin voltage (VC),
due to remote OFF or thermal shutdown conditions. This
effectively minimizes current and voltage stresses on the output
MOSFET, the clamp circuit and the output rectifier during start-
up. This feature also helps minimize output overshoot and
prevents saturation of the transformer during start-up.
Shutdown/Auto-Restart
To minimize TOPSwitch-HX power dissipation under fault
conditions, the shutdown/auto-restart circuit turns the power
supply on and off at an auto-restart duty cycle of typically 2% if
an out of regulation condition persists. Loss of regulation
interrupts the external current into the CONTROL pin. VC
11
www.powerint.com Rev. A
09/07
TOP254-258
Y and M Package
CONTROL (C)
TOPSwitch-HX
240 MA
400 MA
PI-4714-061207
Figure 11a. VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pin Input Simplified Schematic.
P and G Package
CONTROL (C)
TOPSwitch-HX
240 MA
VREF
(Positive Current Sense - Undervoltage,
Overvoltage, Maximum Duty Cycle Reduction,
Output Overvoltage Protection)
400 MA
PI-4715-061207
12
Rev. A www.powerint.com
09/07
TOP254-258
+ +
DC D DC D
Input Input
Voltage CONTROL Voltage CONTROL
C C
S F S F
- -
PI-2654-071700 PI-2655-071700
Figure 12. Full Frequency Operation (132 kHz). Figure 13. Half Frequency Operation (66 kHz).
13
www.powerint.com Rev. A
09/07
TOP254-258
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
For RLS = 4 M7
S S S S S VXCS F D RLS 4 M7 VUV = 97 VDC
VOV = 445 VDC
DC DC
Input Input DCMAX@100 VDC = 75%
D S C
Voltage Voltage DCMAX@375 VDC = 41%
D V D V
C S D
CONTROL CONTROL
C C
S X F S
- -
PI-4716-061207 PI-4717-092107
Figure 14. Three Terminal Operation (VOLTAGE MONITOR and EXTERNAL Figure 15. Line-Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
CURRENT LIMIT Features Disabled. FREQUENCY Pin Tied to
SOURCE or CONTROL Pin).
S S
- -
PI-4718-092107 PI-4719-092107
Figure 16. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Figure 17. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
Latched Output Overvoltage Protection. Unlatched Output Overvoltage Protection.
+ +
4 M7 VUV = RLS × IUV 4 M7 VOV = IOV × RLS
DC DC
Input 40 k7 Input 55 k7
Voltage Voltage
1N4148
D V D V
CONTROL CONTROL
C C
6.2 V
S S
- -
PI-4720-092107 PI-4721-092107
Figure 18. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 19. Line-Sensing for Overvoltage Only (Undervoltage Disabled). Maximum
Duty Cycle Reduced at Low Line and Further Reduction with
Increasing Line Voltage.
14
Rev. A www.powerint.com
09/07
TOP254-258
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
S X S X
RIL RIL
6 k7
- -
PI-4722-092107 PI-4723-092107
Figure 20. External Set Current Limit. Figure 21. Current Limit Reduction with Line Voltage.
For RIL = 12 k7
DC ILIMIT = 61%
DC
Input D D
Input For RIL = 19 k7
Voltage CONTROL Voltage CONTROL ILIMIT = 37%
C C
S X S X
QR ON/OFF RIL
47 K7 QR ON/OFF
- - 16 k7
PI-2625-040501 PI-4724-092107
Figure 22. Active-on (Fail Safe) Remote ON/OFF. Figure 23. Active-on Remote ON/OFF with Externally Set Current Limit.
PI-4726-092107
VUV = IUV × RLS VUV = IUV x RLS
+ VOV = IOV × RLS + VOV = IOV x RLS
Figure 24. Active-on Remote ON/OFF with LINE-SENSE and EXTERNAL Figure 25. Line Sensing and Externally Set Current Limit.
CURRENT LIMIT.
15
www.powerint.com Rev. A
09/07
TOP254-258
Typical Uses of VOLTAGE MONITOR (V) and EXTERNAL CURRENT LIMIT (X) Pins
For RLS = 4 M7
RLS 4 M7 VUV = 97 VDC
VOV = 445 VDC
DC
Sense Output Voltage
Input
Voltage DCMAX @ 100 VDC = 75%
DCMAX @ 375 VDC = 41%
D V
Reset 10 k7 CONTROL
QR C
S
-
PI-4756-092107
+ +
VUV = IUV × RLS
VOV = IOV × RLS
D C
M
For RLS = 4 M7
RLS 4 M7
VUV = 97 VDC
S S S S VOV = 445 VDC
DC DC
Input Input
Voltage Voltage DCMAX @ 100 VDC = 75%
DCMAX @ 375 VDC = 41%
D M D M
D S C
CONTROL CONTROL
C C
S S
- -
PI-4727-061207 PI-4728-092107
Figure 27. Three Terminal Operation (MULTI-FUNCTION Features Disabled). Figure 28. Line Sensing for Undervoltage, Overvoltage and Line Feed-Forward.
S S
- -
PI-4729-092107 PI-4730-092107
Figure 29. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and Figure 30. Line Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
Latched Output Overvoltage Protection. Unlatched Output Overvoltage Protection.
16
Rev. A www.powerint.com
09/07
TOP254-258
+ +
4 M7 VUV = RLS × IUV VOV = IOV × RLS
4 M7
For Values Shown For Values Shown
RLS VUV = 98 VDC RLS VOV = 451 VDC
DC DC
Input 40 k7 Input 55 k7
Voltage Voltage 1N4148
D M D M
CONTROL CONTROL
C C
6.2 V
S S
- -
PI-4731-092107 PI-4732-092107
Figure 31. Line Sensing for Undervoltage Only (Overvoltage Disabled). Figure 32. Line Sensing for Overvoltage Only (Undervoltage Disabled). Maximum
Duty Cycle Reduced at Low Line and Further Reduction with
Increasing Line Voltage.
+ +
For RIL = 12 k7 ILIMIT = 100% @ 100 VDC
ILIMIT = 61% ILIMIT = 53% @ 300 VDC
RLS 2.5 M7
For RIL = 19 k7
ILIMIT = 37%
DC DC
Input See Figures 50b for other Input
Voltage resistor values (RIL) to Voltage
select different ILIMIT values.
D M D M
CONTROL RIL 6 k7 CONTROL
RIL C C
S S
- -
PI-4733-092107 PI-4734-092107
Figure 33. Externally Set Current Limit (Not Normally Required – See M Pin Figure 34. Current Limit Reduction with Line Voltage (Not Normally Required –
Operation Description). See M Pin Operation Description).
+ +
QR can be an optocoupler QR can be an optocoupler
output or can be replaced output or can be replaced
by a manual switch. by a manual switch.
For RIL = 12 k7
DC DC ILIMIT = 61%
Input Input
Voltage Voltage For RIL = 19 k7
D M D M ILIMIT = 37%
RIL
CONTROL CONTROL
QR C C
ON/OFF ON/OFF QR
47 k7 S 16 k7 S
- -
PI-2519-040501 PI-4735-092107
Figure 35. Active-on (Fail Safe) Remote ON/OFF. Figure 36. Active-on Remote ON/OFF with Externally Set Current Limit
(see M Pin Operation Description).
17
www.powerint.com Rev. A
09/07
TOP254-258
+ QR can be an optocoupler
+ VUV = IUV × RLS
output or can be replaced VOV = IOV × RLS
by a manual switch.
For RLS = 4 M7
RLS 4 M7 VUV = 97 VDC
VOV = 445 VDC
ON/OFF QR DC
DC 7 k7 Sense Output Voltage
Input Input
Voltage Voltage DCMAX @ 100 VDC = 75%
RMC 24 k7 RMC = 2RIL DCMAX @ 375 VDC = 41%
D M D M
CONTROL Reset 10 k7 CONTROL
RIL 12 k7 C QR C
S S
- -
PI-4736-060607 PI-4757-092107
Figure 37. Active-off Remote ON/OFF with Externally Set Current Limit Figure 38. Line-Sensing for Undervoltage, Overvoltage, Line Feed-Forward and
(see M Pin Operation Description). Latched Output Overvoltage Protection with Device Reset.
18
Rev. A www.powerint.com
09/07
TOP254-258
Application Examples winding. Zener VR2 will break down and current will flow into
the “M” pin of the TOPSwitch initiating a hysteretic over voltage
A High Efficiency, 35 W, Dual Output - Universal Input protection with automatic restart attempts. Resistor R5 will limit
Power Supply the current into the M pin to < 336 μA thus setting hysteretic
The circuit in Figure 39 takes advantage of several of the OVP. If latching OVP is desired the value of R5 can be reduced
TOPSwitch-HX features to reduce system cost and power to 20 Ω.
supply size and to improve efficiency. This design delivers 35
W total continuous output power from a 90 VAC to 265 VAC The output voltage is controlled using the amplifier TL431.
input at an ambient of 50 ºC in an open frame configuration. A Diode D9, capacitor C20 and resistor R16 form the soft finish
nominal efficiency of 84% at full load is achieved using circuit. At start, capacitor C23 is discharged. As the output
TOP258P. With a DIP-8 package this design provides 35 W voltage starts rising, current flows through the optocoupler diode
continuous output power using only the copper area on the inside U2A, resistor R13 and diode D9 to charge capacitor C20.
circuit board underneath the part as a heat sink. The different This provides feedback to the circuit on the primary side. The
operating modes of the TOPSwitch-HX provide significant current in the optocoupler diode U2A gradually decreases as the
improvement in the no-load, standby, and light load capacitor C20 becomes charged and the control amplifier IC U3
performance of the power supply as compared to the previous becomes operational. This ensures that the output voltage
generations of the TOPSwitch. increases gradually and settles to the final value without any
overshoot. Resistor R16 ensures that the capacitor C20 is
Resistor R3 and R4 provide line sensing, setting UV at 100 VDC maintained charged at all times after startup, which effectively
and OV at 450 VDC. isolates C20 from the feedback circuit after startup. Capacitor
C20 discharges when the supply shuts down.
Diode D5 together with resistors R6, R7, capacitor C6 and TVS
VR1 form a clamp network that limits the Drain voltage of the Resistor R20, R21 and R18 form a voltage divider network. The
TOPSwitch after the integrated MOSFET turns off. TVS VR1 output of this divider network is primarily dependent on the
provides a defined maximum clamp voltage and typically only divider circuit formed using R20 and R21 and will vary to some
conducts during fault conditions such as overload. This allows extent for changes in voltage at the 15 V output due to the
the RCD clamp (R6, R7, C6 and D5) to be sized for normal connection of resistor R18 to the output of the divider network.
operation thereby maximizing efficiency at light load. Resistor R19 and Zener VR3 improve cross regulation in case
Should the feedback circuit fail, output of the power supply may only the 5 V output is loaded which results in the 15 V output
exceed regulation limits. This increased voltage at output will operating at the higher end of the specification.
also result in an increased voltage at the output of the bias
C6 C7 C12
3.9 nF 2.2 nF R11 470 pF
1 kV 250 VAC 33 7 100 V
19
www.powerint.com Rev. A
09/07
TOP254-258
20
Rev. A www.powerint.com
09/07
TOP254-258
A High Efficiency, 20 W continuous – 80 W Peak, Universal TOPSwitch-HX and R20, C9, R22 and VR5. Should the bias
Input Power Supply winding output voltage across C13 rise due to output overload
or an open loop fault (opto coupler failure) then VR5 conducts
The circuit shown in Figure 41 takes advantage of several of triggering the latching shutdown. To prevent false triggering due
TOPSwitch-HX features to reduce system cost, power supply to short duration overload a delay is provided by R20, R22 and
size and improve power supply efficiency while delivering C9.
significant peak power for a short duration. This design delivers
20 W at 32 V from an 85 VAC to 265 VAC input. A nominal To reset the supply following a latching shutdown the V pin must
efficiency of 82% at full load is achieved using TOP258MN. The fall below the reset threshold. To prevent the long reset delay
M-package part has an optimized current limit to enable design associated with the input capacitor discharging, a fast AC reset
of power supplies capable of delivering high power for a short circuit is used. The AC input is rectified and filtered by D13 and
duration. C30. While the AC supply is present Q3 is on and Q1 is off
allowing normal device operation. However when AC is
Resistor R12 sets the current limit of the part. Resistors R11 removed Q1 pulls down the V pin and resets the latch. The
and R14 provide line feed forward information that reduces the supply will then return to normal operation when AC is again
current limit with increasing DC bus voltage thereby maintaining applied.
a constant overload power level with increasing line voltage.
Resistors R1 and R2 implement the line under-voltage and Transistor Q2 provides an additional lower UV threshold to the
over-voltage function and also provide feed forward level programmed via R1, R2 and the V pin. At low input AC
compensation for reducing line frequency ripple at the output. voltage Q2 turns off allowing the X pin to float and thereby
The over voltage feature inhibits TOPSwitch-HX switching disabling switching.
during a line surge extending the high voltage withstand to 700
V without device damage. A simple feedback circuit automatically regulates the output
voltage. Zener VR3 sets the output voltage together with the
The snubber circuit comprising of VR7, R17, R25, C5 and D2 voltage drop across series resistor R8, which sets the DC gain of
limit the maximum Drain voltage and dissipates energy stored in the circuit. Resistor R10 and C28 provide a phase boost to
the leakage inductance of transformer T1. This clamp improve loop bandwidth.
configuration maximizes energy efficiency by preventing C5
from discharging below the value of VR7 during the lower Diodes D6 and D7 are low loss Schottky rectifiers and capacitor
frequency operating modes of TOPSwitch-HX. Resistor R25 C20 is the output filter capacitor. Inductor L3 is a common
damps high frequency ringing for reduced EMI. mode inductor to limit radiated EMI when long output cables
are used and the output return is connected to safety earth
A combined output overvoltage and over power protection ground. Example applications where this occurs include PC
circuit is provided via the latching shutdown feature of peripherals such as inkjet printers.
C8 R19 C26
1 nF 68 7 100 pF
250 VAC 0.5 W 1 kV
C20 C31 32 V
330 MF 22 MF
50 V L2 50 V L3 625 mA, 2.5 APK
1 10
3.3 MH
D6-D7
D8 D9 VR7 2 STPS3150 RTN
R25 9
1N4007 1N4007 BZY97C150
C3 100 7 47 MH
120 MF 150 V 5
400 V C29
to R11
3
NC
C13
10 MF 220 nF
R1 C10
RT1 2 M7 3.6 M7 R17 C5 50 V 50 V
D11 D10 1 nF
1N4007 1N4007 10 7 1 k7 10 nF 4 250 VAC
0.5 W 1 kV
T1 D5
EF25 LL4148 R10
56 7 R8
L1 1.5 k7
5.3 mH D2
R2 R14 FR107 C28
D13 2 M7 3.6 M7 330 nF
1N4007 50 V
R23 R24 VR3
1N5255B
1 M7 1 M7 28 V
U2A
VR5 R20 PC817D
R3 1N5250B C9
R22 1 MF 130 k7
2 M7 20 V
C1 D V 2 M7 100 V
F1 R21
220 nF 3.15 A CONTROL R9
275 VAC 1 M7 2 k7
R4 0.125 W
2 M7
C
90 - 264 PI-4833-092007
VAC S X
R15
1 k7 R6
R12 TOPSwitch-HX
Q1 U4 C6 6.8 7
7.5 k7 100 nF
C30 2N3904 1% TOP258MN
50 V
100 nF
400 V Q2
Q3 C7
2N3904
2N3904 47 MF
R26 16 V
68 k7 R18
39 k7
21
www.powerint.com Rev. A
09/07
TOP254-258
savings in the transformer and other power components. The output diode is selected for peak inverse voltage, output
current, and thermal conditions in the application (including
TOPSwitch-HX Design Considerations heat sinking, air circulation, etc.). The higher DCMAX of
TOPSwitch-HX, along with an appropriate transformer turns
Power Table ratio, can allow the use of a 80 V Schottky diode for higher
The data sheet power table (Table 1) represents the maximum efficiency on output voltages as high as 15 V (see Figure 39).
practical continuous output power based on the following
conditions: Bias Winding Capacitor
1. 12 V output. Due to the low frequency operation at no-load a 10 μF bias
2. Schottky or high efficiency output diode. winding capacitor is recommended.
3. 135 V reflected voltage (VOR) and efficiency estimates.
4. A 100 VDC minimum for 85-265 VAC and 250 VDC mini- Soft-Start
mum for 230 VAC. Generally, a power supply experiences maximum stress at
5. Sufficient heat sinking to keep device temperature ≤100 °C. start-up before the feedback loop achieves regulation. For a
6. Power levels shown in the power table for the M/P package period of 17 ms, the on-chip soft-start linearly increases the
device assume 6.45 cm2 of 610 g/m2 copper heat sink area drain peak current and switching frequency from their low
in an enclosed adapter, or 19.4 cm2 in an open frame. starting values to their respective maximum values. This
causes the output voltage to rise in an orderly manner, allowing
The provided peak power depends on the current limit for the time for the feedback loop to take control of the duty cycle.
respective device. This reduces the stress on the TOPSwitch-HX MOSFET, clamp
circuit and output diode(s), and helps prevent transformer
TOPSwitch-HX Selection saturation during start-up. Also, soft-start limits the amount of
Selecting the optimum TOPSwitch-HX depends upon required output voltage overshoot and, in many applications, eliminates
maximum output power, efficiency, heat sinking constraints, the need for a soft-finish capacitor.
system requirements and cost goals. With the option to
externally reduce current limit, a M package or Y package EMI
TOPSwitch-HX may be used for lower power applications The frequency jitter feature modulates the switching frequency
where higher efficiency is needed or minimal heat sinking is over a narrow band as a means to reduce conducted EMI
available. peaks associated with the harmonics of the fundamental
switching frequency. This is particularly beneficial for average
Input Capacitor detection mode. As can be seen in Figure 42, the benefits of
The input capacitor must be chosen to provide the minimum jitter increase with the order of the switching harmonic due to
DC voltage required for the TOPSwitch-HX converter to an increase in frequency deviation. The TOP258P, G and M
maintain regulation at the lowest specified input voltage and operate at a nominal switching frequency of 66 kHz. The
maximum output power. Since TOPSwitch-HX has a high FREQUENCY pin of TOP258Y offers a switching frequency
DCMAX limit, it is possible to use a smaller input capacitor. For option of 132 kHz or 66 kHz. In applications that require heavy
TOPSwitch-HX, a capacitance of 2 μF per watt is possible for snubber on the drain node for reducing high frequency radiated
universal input with an appropriately designed transformer. noise (for example, video noise sensitive applications such as
VCRs, DVDs, monitors, TVs, etc.), operating at 66 kHz will
Primary Clamp and Output Reflected Voltage VOR reduce snubber loss resulting in better efficiency. Also, in
A primary clamp is necessary to limit the peak TOPSwitch-HX applications where transformer size is not a concern, use of the
drain to source voltage. A Zener clamp requires few parts and 66 kHz option will provide lower EMI and higher efficiency. Note
takes up little board space. For good efficiency, the clamp that the second harmonic of 66 kHz is still below 150 kHz,
Zener should be selected to be at least 1.5 times the output above which the conducted EMI specifications get much tighter.
reflected voltage VOR, as this keeps the leakage spike For 10 W or below, it is possible to use a simple inductor in
conduction time short. When using a Zener clamp in a place of a more costly AC input common mode choke to meet
universal input application, a VOR of less than 135 V is worldwide conducted EMI limits.
recommended to allow for the absolute tolerances and
temperature variations of the Zener. This will ensure efficient Transformer Design
operation of the clamp circuit and will also keep the maximum It is recommended that the transformer be designed for
drain voltage below the rated breakdown voltage of the maximum operating flux density of 3000 Gauss and a peak flux
TOPSwitch-HX MOSFET. A high VOR is required to take full density of 4200 Gauss at maximum current limit. The turns
advantage of the wider DCMAX of TOPSwitch-HX. An RCD ratio should be chosen for a reflected voltage (VOR) no greater
clamp provides tighter clamp voltage tolerance than a Zener than 135 V when using a Zener clamp, or 150 V (max) when
clamp and allows a VOR as high as 150 V. RCD clamp using an RCD clamp with current limit reduction with line
dissipation can be minimized by reducing the external current voltage (overload protection). For designs where operating
limit as a function of input line voltage (see Figures 21 and 34). current is significantly lower than the default current limit, it is
The RCD clamp is more cost effective than the Zener clamp but recommended to use an externally set current limit close to the
requires more careful design (see Quick Design Checklist). operating peak current to reduce peak flux density and peak
power (see Figures 20 and 33). In most applications, the tighter
Output Diode current limit tolerance, higher switching frequency and soft-start
23
www.powerint.com Rev. A
09/07
TOP254-258
PI-2576-010600
70 returning surge currents from the bias winding directly to the
input filter capacitor. The CONTROL pin bypass capacitor
60 should be located as close as possible to the SOURCE and
Amplitude (dBMV)
24
Rev. A www.powerint.com
09/07
TOP254-258
Isolation Barrier
VR1
Capacitor Output
Rectifier
D1
J1
D3 Output Filter
+ Transformer C7 Capacitor
S D
HV S
U1
- C1 S C
L1
S M
JP1
C3 C4
R8 C5
C8
R1 R2
D2 J2
R14
R13
R6
R11
R7
JP2 U3
R8 R10
Maximize hatched copper C9
areas ( ) for optimum U2
VR2
heat sinking R12
DC
- +
Out PI-4753-070307
Isolation Barrier
C2
Y1-
Optional PCB slot for external Capacitor
heatsink in contact with R6 C6 T1
SOURCE pins
Input Filter R5 R12 Output
VR1
Capacitor Rectifier
J1 D1
+ D3 Output Filter
HV Transformer C7 Capacitor
-
S D
S
S U1 C L1
C1 S X
S V
JP1
R7 C4
C5 C9 R13
R8
C3 R14
D2 C8
R1 R2 U3
R9
R10
R4 R15
R11
R3 JP2 J2
VR2 R16
Maximize hatched copper U2
areas ( ) for optimum R17
heat sinking
- DC +
Out PI-4752-070307
25
www.powerint.com Rev. A
09/07
TOP254-258
Isolation Barrier
C2
Y1-
R4 Capacitor
C6 T1
Input Filter R3
VR1
Capacitor R12 Output
C10 Rectifier
D1
J1 Output Filter
+ Transformer
D3 Capacitor
HV HS1
U1 D
- S C7
F
C L1
C1 V
X
JP1
C4
R7 R10
R13
R1 R2 C5 C9
D2 U3
R8
C8
R14
JP2
R16
R11
R3 R4 J2
R9
R15
U2
R17
VR2 R12
- DC +
Out
PI-4751-070307
clamp network, bias winding return or power traces from other temperature specifications are not exceeded for
converters. If the line sensing features are used then the sense TOPSwitch-HX, transformer, output diodes and output
resistors must be placed within 10 mm of the V-pin to minimize capacitors. Enough thermal margin should be allowed for
the V pin node area. The DC bus should then be routed to the the part-to-part variation of the RDS(ON) of TOPSwitch-HX, as
line sense resistors. Note that external capacitance must not specified in the data sheet. The margin required can either
be connected to the V-pin as this may cause misoperaton of the be calculated from the tolerances or it can be accounted for
V pin related functions. by connecting an external resistance in series with the DRAIN
pin and attached to the same heat sink, having a resistance
As with any power supply design, all TOPSwitch-HX designs value that is equal to the difference between the measured
should be verified on the bench to make sure that components RDS(ON) of the device under test and the worst case maximum
specifications are not exceeded under worst-case conditions. specification.
The following minimum set of tests is strongly recommended:
Design Tools
1. Maximum drain voltage – Verify that peak VDS does not
exceed 675 V at highest input voltage and maximum Up-to-date information on design tools can be found at the
overload output power. Maximum overload output power Power Integrations website: www.powerint.com
occurs when the output is overloaded to a level just before
the power supply goes into auto-restart (loss of regulation).
2. Maximum drain current – At maximum ambient temperature,
maximum input voltage and maximum output load, verify
drain current waveforms at start-up for any signs of trans-
former saturation and excessive leading edge current spikes.
TOPSwitch-HX has a leading edge blanking time of 220 ns
to prevent premature termination of the ON-cycle. Verify that
the leading edge current spike is below the allowed current
limit envelope (see Figure 48) for the drain current waveform
at the end of the 220 ns blanking period.
3. Thermal check – At maximum output power, minimum input
voltage and maximum ambient temperature; verify that
26
Rev. A www.powerint.com
09/07
TOP254-258
DRAIN Peak Voltage .................................................................. -0.3 V to 700 V Operating Junction Temperature................................... -40 °C to 150 °C
DRAIN Peak Current: TOP254 ................................................................ 2.08 A Lead Temperature(1) ......................................................................................260 °C
DRAIN Peak Current: TOP255 .................................................................2.72 A
DRAIN Peak Current: TOP256 ................................................................ 4.08 A Notes:
DRAIN Peak Current: TOP257 ................................................................ 5.44 A 1. 1/16 in. from case for 5 seconds.
DRAIN Peak Current: TOP258 ................................................................ 6.88 A 2. Maximum ratings specified may be applied one at a time
CONTROL Voltage ............................................................................-0.3 V to 9 V without causing permanent damage to the product. Exposure
CONTROL Current ...................................................................................... 100 mA to Absolute Maximum Rating conditions for extended periods
VOLTAGE MONITOR Pin Voltage .............................................-0.3 V to 9 V of time may affect product reliability.
CURRENT LIMIT Pin Voltage .................................................-0.3 V to 4.5 V
MULTI-FUNCTION Pin Voltage .................................................-0.3 V to 9 V
FREQUENCY Pin Voltage ........................................................... -0.3 V to 9 V
Storage Temperature ............................................................-65 °C to 150 °C
Thermal Impedance
Thermal Impedance: Y Package: Notes:
(θJA) .................................................................. 80 °C/W(1) 1. Free standing with no heatsink.
(θJC) ............................................... .....................2 °C/W(2) 2. Measured at the back surface of tab.
P, G and M Packages: 3. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
(θJA) .........................................70 °C/W(3); 60 °C/W(4) 4. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(θJC) ............................................... .................. 11 °C/W(5) 5. Measured on the SOURCE pin close to plastic interface.
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol Min Typ Max Units
See Figure 49
(Unless Otherwise Specified)
Control Functions
FREQUENCY Pin
119 132 145
Connected to SOURCE
Switching Frequency
in Full Frequency fOSC TJ = 25 °C FREQUENCY Pin kHz
Mode (average) Connected to CONTROL 59.5 66 72.5
M/P/G Package
Frequency Jitter
fM 250 Hz
Modulation Rate
IV ≤ IV(DC) or IM ≤ IM(DC) or
75 78 83
VV, VM = 0 V
Maximum Duty Cycle DCMAX IC = ICD1 %
IV or IM = 95 μA 30
PWM Gain
See Note A -0.01 %/mA/°C
Temperature Drift
27
www.powerint.com Rev. A
09/07
TOP254-258
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
28
Rev. A www.powerint.com
09/07
TOP254-258
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Multi-Function (M), Voltage Monitor (V) and External Current Limit (X) Inputs
VV(TH) or
V or M Pin Reset Voltage TJ = 25 °C 0.8 1.0 1.6 V
VM(TH)
Remote ON/OFF Threshold -35 -27 -20
Negative Threshold
IREM (N) TJ = 25 °C μA
Current and Hysteresis
(M or X Pin) Hysteresis 5
X, V or M Pin
0.6 1.0
Remote OFF DRAIN Floating
ID(RMT) VDRAIN = 150 V mA
Supply Current V or M Pin Shorted to
1.0 1.6
CONTROL
From Remote ON to Drain 66 kHz 3.0
Remote ON Delay tR(ON) Turn-On μs
See Note B 132 kHz 1.5
29
www.powerint.com Rev. A
09/07
TOP254-258
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
Circuit Protection
TOP254PN/GN
di/dt = 105 mA/μs 0.93 1.00 1.07
TJ = 25 °C
TOP254MN
di/dt = 135 mA/μs 1.209 1.30 1.391
TJ = 25 °C
TOP254YN
di/dt = 270 mA/μs 1.209 1.30 1.391
TJ = 25 °C
TOP255PN/GN
di/dt = 120 mA/μs 1.069 1.15 1.231
TJ = 25 °C
TOP255MN
di/dt = 175 mA/μs 1.581 1.70 1.819
TJ = 25 °C
TOP255YN
di/dt = 350 mA/μs 1.581 1.70 1.819
TJ = 25 °C
TOP256PN/GN
di/dt = 140 mA/μs 1.255 1.35 1.445
TJ = 25 °C
Self Protection
TOP256MN
Current Limit ILIMIT di/dt = 210 mA/μs 1.953 2.10 2.247 A
TJ = 25 °C
(See Note C)
TOP256YN
di/dt = 530 mA/μs 2.371 2.55 2.729
TJ = 25 °C
TOP257PN/GN
di/dt = 155 mA/μs 1.395 1.50 1.605
TJ = 25 °C
TOP257MN
di/dt = 265 mA/μs 2.371 2.55 2.729
TJ = 25 °C
TOP257YN
di/dt = 705 mA/μs 3.162 3.40 3.638
TJ = 25 °C
TOP258PN/GN
di/dt = 170 mA/μs 1.534 1.65 1.766
TJ = 25 °C
TOP258MN
di/dt = 310 mA/μs 2.790 3.00 3.210
TJ = 25 °C
TOP258YN
di/dt = 890 mA/μs 3.999 4.30 4.601
TJ = 25 °C
0.70 ×
Initial Current Limit IINIT See Note B A
ILIMIT(MIN)
30
Rev. A www.powerint.com
09/07
TOP254-258
Conditions
Parameter Symbol SOURCE = 0 V; TJ = -40 to 125 °C Min Typ Max Units
(Unless Otherwise Specified)
31
www.powerint.com Rev. A
09/07
TOP254-258
NOTES:
A. For specifications with negative values, a negative temperature coefficient corresponds to an increase in
magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in
magnitude with increasing temperature.
C. For externally adjusted current limit values, please refer to Figures 50a and 50b (Current Limit vs. External Current Limit Resis-
tance) in the Typical Performance Characteristics section. The tolerance specified is only valid at full current limit.
D. I2f calculation is based on typical values of ILIMIT and fOSC, i.e. ILIMIT(TYP)2 × fOSC(66K, TYP) , where fOSC(66K, TYP) = 66 kHz / 132 kHz depending
on package / F pin connection. See fOSC specification for detail.
E. The TOPSwitch-HX will start up at 18 VDC Drain voltage. The capacitance of electrolytic capacitors drops significantly at tempera-
tures below 0 °C. For reliable start up at 18 V in sub zero temperatures, designers must ensure that circuit capacitors meet
recommended capacitance values.
32
Rev. A www.powerint.com
09/07
TOP254-258
HV
90% 90%
DRAIN
VOLTAGE
10%
0V
PI-2039-033001
Figure 47. CONTROL Pin I-V Characteristic. Figure 48. Drain Current Operating Envelope.
33
www.powerint.com Rev. A
09/07
TOP254-258
PI-4754-082907
1.1 1.1
1 1
Maximum
0.9 0.9
Normalized Current Limit
0.8 0.8
0.7 0.7
Typical
Normalized di/dt
0.6 0.6
0.5 0.5
Minimum
0.4 0.4
0.3 0.3
Notes:
1. Maximum and Minimum levels are
0.2 based on characterization; 0.2
O O
2. T J = 0 C to 125 C
0.1 0.1
0 0
-200 -150 -100 -50 0
IX or IM ( μA )
PI-4755-082907
1.1 1.1
Notes:
1 1. Maximum and Minimum levels are 1
based on characterization;
0.9 2. T J = 0 OC to 125 OC; 0.9
3. Includes the variation of X or M pin
0.8 voltage 0.8
Normalized Current Limit
Maximum
0.7 0.7
0.6 0.6
Normalized di/dt
Typical
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
Minimum
0.1 0.1
0 0
0 5 10 15 20 25 30 35 40 45
RIL ( kΩ )
Figure 50b. Normalized Current Limit vs. External Current Limit Resistance.
34
Rev. A www.powerint.com
09/07
TOP254-258
1.1 1.2
PI-4759-061407
PI-176B-033001
1.0
(Normalized to 25 oC)
(Normalized to 25 oC)
Output Frequency
Breakdown Voltage
0.8
1.0 0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC) Junction Temperature (oC)
Figure 51. Breakdown Voltage vs. Temperature. Figure 52. Frequency vs. Temperature.
1.2 1.2
PI-4760-061407
PI-4739-061507
1.0 1.0
(Normalized to 25 °C)
(Normalized to 25 oC)
Current Limit
Current Limit
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
1.2 1.2
PI-4762-061407
PI-4761-061407
Under-Voltage Threshold
Overvoltage Threshold
1.0 1.0
(Normalized to 25 oC)
(Normalized to 25 oC)
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC) Junction Temperature (oC)
Figure 55. Overvoltage Threshold vs. Temperature. Figure 56. Undervoltage Threshold vs. Temperature.
35
www.powerint.com Rev. A
09/07
TOP254-258
PI-4740-060607
PI-4741-061407
VX = 1.354 - 1147.5 × |IX| 1.759 × 106 ×
5 1.2
4 0.8
3.5 0.6
3 0.4
2.5 0.2
2 0
0 100 200 300 400 500 200 -150 -100 -50 0
VOLTAGE-MONITOR Pin Current (MA) EXTERNAL CURRENT LIMIT Pin Current (MA)
Figure 57a. LINE-SENSE Pin Voltage vs. Current. Figure 57b. EXTERNAL CURRENT LIMIT Pin Voltage vs. Current.
6 1.6
PI-4742-061207
MULTI-FUNCTION Pin Voltage (V)
PI-4743-061407
MULTI-FUNCTION Pin Voltage (V)
VM = 1.354 - 1147.5 × |IM| 1.759 × 106 ×
1.4 (IM)2 with -180 MA IM -25 MA
5
1.2
4
1.0
3 0.8
2 0.6
0 0
-200 -100 0 100 200 300 400 500 -200 -150 -100 -50 0
MULTI-FUNCTION Pin Current (MA) MULTI-FUNCTION Pin Current (MA)
Figure 58a. MULTI-FUNCTION Pin Voltage vs. Current. Figure 58b. MULTI-FUNCTION Pin Voltage vs. Current (Expanded).
1.2 1.2
PI-4764-061407
PI-4763-061407
1.0 1.0
(Normalized to 25 oC)
(Normalized to 25 oC)
CONTROL Current
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC) Junction Temperature (oC)
Figure 59. Control Current Out at 0% Duty Cycle vs. Temperature. Figure 60. Maximum Duty Cycle Reduction Onset Threshold
Current vs. Temperature.
36
Rev. A www.powerint.com
09/07
TOP254-258
5 1
PI-4748-061207
PI-4744-061207
VC = 5 V
0
3
-0.5
Scaling Factors:
TOP258 1.00
2 TOP257 0.85 -1
TOP256 0.61
TOP255 0.42
-1.5
TOP254 0.32
1
TCASE = 25 oC -2
TCASE = 100 oC
0 -2.5
0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100
DRAIN Voltage (V) DRAIN Pin Voltage (V)
Figure 61. Output Characteristics. Figure 62. IC vs. DRAIN Voltage.
10000 500
PI-4750-061407
PI-4749-061207
300
200
100
P/M-Package
100
10 0
0 100 200 300 400 500 600 0 100 200 300 400 500 600 700
Drain Voltage (V) DRAIN Voltage (V)
Figure 63. COSS vs. DRAIN Voltage. Figure 64. DRAIN Capacitance Power.
Remote OFF DRAIN Supply Current
1.2
PI-4745-061407
1.0
(Normalized to 25 oC)
0.8
0.6
0.4
0.2
0
-50 -25 0 25 50 75 100 125 150
Junction Temperature (oC)
Figure 65. Remote OFF DRAIN Supply Current vs. Temperature.
37
www.powerint.com Rev. A
09/07
TOP254-258
TO-220-7C
.165 (4.19)
.185 (4.70)
.390 (9.91) .045 (1.14)
.146 (3.71) .420 (10.67) .055 (1.40)
.156 (3.96)
.108 (2.74) REF
+ .234 (5.94)
.261 (6.63)
PI-2644-122004
38
Rev. A www.powerint.com
09/07
TOP254-258
DIP-8C
⊕D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1
5. Minimum metal to metal spacing at the package body for
.367 (9.32) the omitted lead location is .137 inch (3.48 mm).
-D- 6. Lead width measured at package body.
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
-T-
SEATING .008 (.20)
PLANE .120 (3.05) .015 (.38)
.140 (3.56)
SDIP-10C
Notes:
10 6
-E- 1. Package dimensions conform to JEDEC specification
MS-019.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
3. Dimensions shown do not include mold flash or other
.240 (6.10) protrusions. Mold flash or protrusions shall not exceed
.260 (6.60) .006 (.15) on any side.
4. D, E and F are reference datums.
5. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
1 5
.125 (3.18)
.200 (5.08) Max
.145 (3.68)
-F-
SEATING .008 (.20)
PLANE
.120 (3.05) .015 (.38)
.020 (.51) Min
.140 (3.56)
39
www.powerint.com Rev. A
09/07
TOP254-258
SMD-8C
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
.086 protrusions. Mold flash or
.186 protrusions shall not exceed
.372 (9.45) .006 (.15) on any side.
.240 (6.10)
.388 (9.86) .286 .420 3. Pin locations start with Pin 1,
.260 (6.60)
⊕ E S .010 (.25) and continue counter-clock-
wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
Pin 1 Pin 1 for the omitted lead location
.137 (3.48) is .137 inch (3.48 mm).
MINIMUM Solder Pad Dimensions 5. Lead width measured at
.100 (2.54) (BSC)
package body.
6. D and E are referenced
.367 (9.32) datums on the package
-D-
.387 (9.83) body.
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0°- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-013106
40
Rev. A www.powerint.com
09/07
TOP254-258
Notes
41
www.powerint.com Rev. A
09/07
Revision Notes Date
A Initial Release 09/07
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be
covered by one or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power
Integrations. A complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its
customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET,
PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
©2007, Power Integrations, Inc.